ROHM BD8163EFV Technical data

A

Power Supply ICs for TFT-LCD Panels

5V Input Multi-channel System Power Supply ICs

BD8163EFV

●Description

The BD8163EFV is a system power supply IC for TFT panels. A 1-chip IC providing a total of four voltages required for TFT panels, i.e., logic voltage, sauce voltage, gate high-level, and gate low-level voltage, thus constructing a TFT panel power supply with minimal components required.

●Features

1) Operates in an operating voltage range as low as 2.1 V to 6. 0 V.

2) Incorporates a step-up DC/DC converter.

3) Incorporates a 2.5 V regulator.

4) Incorporates positive and negative-side charge pumps.

5) Switching frequency of 1100 kHz

6) DC/DC converter feedback voltage of 1.24 V ± 1%

7) Incorporates a gate shading function

8) Under-voltage lockout protection circuit

9) Thermal shutdown circuit

10) Overcurrent protection circuit

11) HTSSOP-B24 package

●Applications

Liquid crystal TV, PC monitor, and TFT-LCD panel

●Absolute maximum ratings (Ta = 25℃)

Parameter Symbol Ratings Unit

No.10035EAT13

Power supply voltage VCC 7 V

Vo1 voltage Vo1 19 V

Vo2 voltage Vo2 32 V

SW voltage Vsw 19 V

Maximum junction temperature Tjmax 150 ℃

Power dissipation Pd 1100* mW

Operating temperature range Topr -40 to 125 ℃

Storage temperature range Tstg -55 to 150 ℃

* Reduced by 4.7 mW/℃ over 25℃, when mounted on a glass epoxy board. (70 mm  70 mm  1.6 mm).

●Recommended Operating Ranges

Ratings

Parameter Symbol

Min. Max.

Power supply voltage VCC 2.1 6 V

Vo1 voltage Vo1 8 18 V

Vo2 voltage Vsw — 18 V

SW Current Isw — 1.8 A

Vo2 Current Vo2 — 30 V

Unit

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●Electrical Characteristics (Unless otherwise specified, VCC = 5 V; Vo1 = 15 V; Vo2 = 25 V; Ta = 25℃)

1 DC/DC Converter Block

Limits

Parameter Symbol

Unit Conditions

Min. Typ. Max.

[Soft start]

Source current Iso 6 10 14 μA Vss = 0.5 V

Sinking current Isi 0.1 0.2 1.0 mA Vss = 0.5 V, VDD = 1.65 V

[Error amp]

Technical Note

Input bias current 1 I

Feedback voltage 1 V

— 0.1 0.5 μA

FB1

1.227 1.240 1.253 V Buffer

FB1

Voltage gain AV — 200 — V/V *

Sinking current IoI 25 50 100 μA VFB = 1.5 V VCOMP = 0.5 V

Source current Ioo -100 -50 -25 μA VFB = 1.0 V VCOMP = 0.5 V

[SW]

ON resistance N-channel R

Leak current N-channel I

Maximum duty cycle D

50 200 600 mΩ *

ON_N

— — 10 μA Vsw = 18 V

LEAKN

75 85 95 %

MAX

[Overcurrent protection]

Saw current limit Insw 2 3 — A *

2. Regulator controller

Limits

Parameter Symbol

Unit Conditions

Min. Typ. Max.

[Error amp]

VDD voltage VDD 2.4 2.5 2.6 V

Maximum base current I

Line regulation RegI — 10 30 mV Vcc = 4.5 V to 5.5 V

Load regulation RegL — 10 50 mV Io = 10 mA to 100 mA

[Under-voltage lockout protection]

Off threshold voltage V

On threshold voltage V

 This product is not designed for protection against radioactive rays. * Design guarantee (No total shipment inspection is made.)

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2 7 15 mA

BMAX

1.7 1.8 1.9 V

ROFF

1.6 1.7 1.8 V

RON

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3. Charge pump

Parameter Symbol

[Error amp]

Technical Note

Limits

Unit Conditions

Min. Typ. Max.

Input bias current 2 I

Input bias current 3 I

Feedback voltage 2 V

Feedback voltage 3 V

— 0.1 0.5 μA

FB2

— 0.1 0.5 μA

FB3

1.183 1.240 1.307 V

FB2

0.15 0.2 0.25 V

FB3

[Delay start block]

Source current I

Sinking current I

3 5 7 μA VDLS = 0.5V

DSO

0.1 0.5 1.0 mA VDLS = 0.5V

DSI

Startup voltage VST 0.45 0.60 0.75 V

[Switch]

ON resistance N-channel R

ON resistance P-channel R

0.5 2 4 Ω Io = 10 mA *

ON_NC

0.5 4 8 Ω Io = -10 mA *

ON_PC

[Diode]

Voltage of diode Vf

600 710 800

mV Io = 10 mA

[Gate shading block]

ON resistance N-channel R

ON resistance P-channel R

Leak current N-channel I

Leak current P-channel I

LEAK_NG

LEAK_PG

2 10 20 Ω Io = 10 mA *

ON_NGS

2 10 20 Ω Io = -10 mA *

ON_PGS

S — — 10 μA

High voltage IGH VDD × 0.7 VDD — V

Low voltage IGL — 0 VDD × 0.3 V

Input current IIG 8 16.5 30 μA IG = 3.3 V

 This product is not designed for protection against radioactive rays. * Design guarantee (No total shipment inspection is made.)

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4. Overall

Parameter Symbol

[Reference block]

Technical Note

Limits

Unit Conditions

Min. Typ. Max.

Reference voltage V

Drive current I

1.215 1.240 1.265 V

REF

— 23 — mA VREF = 0 V

REF

Load regulation ∆V — 1 10 mV IREF = -1 mA

[Oscillator]

Oscillating frequency Fosc 0.94 1.1 1.265 MHz

[Oscillator]

DET 1 On threshold voltage V

DET 1 Off threshold voltage V

DET 2 On threshold voltage V

DET 2 Off threshold voltage V

DET 3 On threshold voltage V

1.7 1.8 1.9 V

DON1

1.6 1.7 1.8 V

DOFF1

1.02 1.12 1.22 V

DON2

0.90 1.00 1.10 V

DOFF2

0.25 0.30 0.35 V

DON3

DET 3 Off threshold voltage V

DET 4 On threshold voltage V

DET 4 Off threshold voltage V

0.35 0.41 0.47 V

DOFF3

1.02 1.12 1.22 V

DON4

0.90 1.00 1.10 V

DOFF4

[Device]

Average circuit current Icc 0.5 2 5 mA No switching

 This product is not designed for protection against radioactive rays.

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●Reference Data (Unless otherwise specified, Ta = 25℃)

1

0.8

0.6

0.4

0.2

SUPPLY CURRENT : ICC[mA] .

0

01.5 34.56

Fig. 1 Total Supply Current 1

125℃

25℃

-40℃

SUPPLY VOLTAGE : VCC [V]

10

8

6

4

2

SUPPLY CURRENT : IDD[mA] .

0

01.534.56

SUPPLY VOLTAGE : VD D[V]

Fig. 2 Total Supply Current 2

1.6

1.2

0.8

0.4

REF VO LTAGE : VREF [V]

0.4

REF VO LTAGE : VREF [V]

0

01.534.56

SUPPLY VOLT AGE : VCC[ V]

Fig. 4 Internal

Reference Line Regulation

12

10

8

6

0

0 5 10 15 20 25 30

REF CURRENT : IREF[mA]

Reference Load Regulation

2

1.5

1

4

2

DLS SOURCE CURRENT : IDLS[µA] .

0

01.534.56

SUPPLY VOLT AGE : VD D[V]

Fig. 7 DLS Source Current

0.5

0

SWITCHHING FREQUENCY : f [MHz] .

-50 - 25 0 25 50 75 100 125

-40

AMBIEN T T EMPER ATU RE : T a[

Fig. 8 Switching Frequency

200

160

120

80

40

SW VOLTAGE : VSW [V] .

0

0 0.2 0.4 0.6 0.8 1

SW CURRENT : ISW [A]

Fig. 10 SW On Resistance

200

160

120

80

40

OUTPUT VOLTAGE : Vcp[mV].

0

0 20 40 60

INPUT CURRENT : Icp[mA]

Fig. 11 Charge Pump

125℃

Fig. 5 Internal

Temperature

N channel

P channel

On Voltage

25℃

-40℃

80

Technical Note

1.26

1.25

1.24

1.23

REF VO LTAGE : VREF [V]

1.22

-50 - 25 0 25 50 75 100 125

AMBIENT TEM PERATU RE : Ta[℃]

Fig. 3 Internal Reference

Temperature

12

10

8

6

4

2

SS SOURCE CURRENT : ISS[µA] .

0

01.5 34.56

SUPPLY VOLT AGE : VDD[V]

Fig. 6 SS Source Current

5

4

3

2

VDD VOLTAGE : VDD[V]

1

0

0246810

]

℃

GS VOLTAGE : Vgs[V]

100

BASE CURRENT : IBASE[mA]

Fig. 9 REG Current Capacity

1

0.8

0.6

N channel

0.4

0.2

0

20

GS CURRENT : Igs[mA]

P channel

40 60 80 100

Fig. 12 Gate Shading

On Voltage

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●Reference Data (Unless otherwise specified, Ta = 25℃)

15

10

5

OUT PUT VOLT AGE : VD D [V ]

0

01.534.56

SUPPLY VOLT AGE : VCC [ V]

Fig. 13 Vo1 Line Regulation

5

4

3

2

1

OUTPU T VOLTAGE : VDD[V]

0

0 0.4 0.8 1.2 1.6 2

OUTPUT CURRENT : IDD[mA]

Fig. 14 VDD Load Regulation

14

13

12

13V

12V

100

95

90

11

OUT PUT VOLT AGE : VO1[V]

10

0 100 200 300 400 500 600 700

Fig. 16 Vo1 Load Regulation

10.8V

OUTPUT CURRENT : IO[mA]

EFFICIENCY [ % ]

85

80

0 150 300 450 600

OUTPUT CURRENT : IO1[mA]

Fig. 17 Efficiency vs Output Current

1600

1200

23.8

23.7

800

23.6

400

MAXIMUM CURRENT : IoMAX[mA] .

0

1.5 3 4.5 6

SUPPLY VOLT AGE : VCC[ V]

23.5

OUT PUT VOLT AGE : VO2[V]

23.4 10 11.5 13 14.5 16

INPU T VOLTAGE : Vo1[v]

Fig. 19 Power Supply Voltage vs

Max. Output Current Capacity

Fig. 20 Vo2 Line Regulation Fig. 21 Vo2 Load Regulation

-6

-6.1

-6.2

-6.3

OUT PUT VOLT AGE : VO3[V]

-6.4 10 11 12 13 14 15

INPU T VOLTAGE : VO 1[V]

Fig. 22 Negative-side Charge

Pump Line Regulation

-6.3

OUT PUT VOLT AGE : VO1[V]

-6.4 0 50 100 150 200

OUTPUT C UR RENT : IO[mA]

Fig. 23 Negative-side Charge

Pump Load Regulation

10.8V 12V 13V

Technical Note

12.5

12.4

12.3

12.2

12.1

12.0

11.9

11.8

Vo1 VOLT AGE : VO 1[V]

11.7

11.6

11.5 23 456

SUPPLY VOLT AGE : VCC[ V]

Fig. 15 Vo1 Line Regulation

100

90

80

EFFICIENCY [ % ]

70

60

2.5 3 3. 5 4 4. 5 5 5.5 6

SUPPLY VOLT AGE : VCC[ V]

Fig. 18 Efficiency vs Power

Supply Voltage

24

23.8

23.6

23.4

23.2

OUT PUT VOLTAGE : VO2[V]

23

0 50 100 150

OUTPUT CURRENT : IO2[mA]

IG

VO2GS

Fig. 24 Gate Shading

Output Waveform

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●Block Diagram

0.1µF

5.1k

1000pF

0.1µF

Ω

REF

COMP

DLS

Vcc

1µF

Technical Note

VREF

DET2

VCC

Regulator

Control

10µF

Step-up

Controller

Charge

Pump

Control 1

DET4

VDD

4.7µF

VCC

Vo1

Gate

Shading

Controller

Charge

Pump

Control 2

DET1

1.8V

VDD=2.5V

VCC 5V

SS

TSD

UVLO

Step-up

Controller

IG

BASE

Fig. 25 Block Diagram

PGND

DET4

PGND

Vo1

10µF

SW

Vo1

DET3

GND

DET2

1.1V

0.3V

GND

Vo1

1.1V

FB1

Vo2

C2H

C2L

C1H

C1L

FB2

Vo2GS

GSOUT

C3

0.1µF

FB3

10µF

0.1µF

160k

15kΩ

1µF

R

1µF

Ω

270k

Ω

16kΩ

0.01µF

91k

18kΩ

Vo1=14.5V (18V MAX)

Vo2 23.5V (30V MAX)

Vo2GS

Vo3=-5V

Ω

REF

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