ROHM BD8153EFV Technical data
Power Supply IC Series for TFT-LCD Panels
5V Input Multi-channel
System Power Supply IC
BD8153EFV
●Description
The BD8153EFV is a system power supply IC for TFT panels.A 1-chip IC providing a total of four voltages required for TFT
panels, i.e., logic voltage, sauce voltage, gate high-level, and gate low-level voltage, thus constructing a TFT panel power
supply with minimal components required.
●Features (BD8153EFV)
1) Operates in an operating voltage range as low as 2.1 V to 6. 0 V.
2) Incorporates a step-up DC/DC converter.
3) Incorporates a 3.3-V regulator.
4) Incorporates positive and negative-side charge pumps.
5) Switching frequency of 1100 kHz
6) DC/DC converter feedback voltage of 1.24 V ± 1%
7) Incorporates a gate shading function
8) Under-voltage lockout protection circuit
9) Thermal shutdown circuit
10) Overcurrent protection circuit
11) HTSSOP-B24 package
●Applications
Liquid crystal TV, PC monitor, and TFT-LCD panel
●Absolute maximum ratings (Ta = 25°C)
Parameter Symbol Limit Unit
Power supply voltage VCC 7 V
Vo1 voltage Vo1 19 V
Vo2 voltage Vo2 32 V
SW voltage Vsw 19 V
Maximum junction temperature Tjmax 150 °C
Power dissipation Pd 1100* mW
Operating temperature range Topr -40 to 125 °C
Storage temperature range Tstg -55 to 150 °C
* Reduced by 4.7 mW/°C over 25°C, when mounted on a glass epoxy board.
(70 mm 70 mm 1.6 mm).
●Recommended Operating Ranges
Parameter Symbol
Power supply voltage VCC 2.1 6 V
Vo1 voltage Vo1 8 18 V
SW voltage Vsw — 18 V
SW Current Isw — 1.8 A
Vo2 voltage Vo2 — 30 V
Limit
MIN MAX
Unit
No.09035JBT09
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1/17
2009.07 - Rev.B
BD8153EFV
●Electrical Characteristics (Unless otherwise specified, VCC = 5 V; Vo1 = 15 V; Vo2 = 25 V; Ta = 25°C)
1 DC/DC Converter Block
Parameter Symbol
[Soft start]
Source current Iso 6 10 14 μA Vss = 0.5 V
Sinking current Isi 0.1 0.2 1.0 mA Vss = 0.5 V,VDD = 1.65 V
[Error amp]
Input bias current 1 IFB1 — 0.1 0.5 μA
Feedback voltage 1 VFB1 1.227 1.240 1.253 V Buffer
Voltage gain AV — 200 — V/V *
Sinking current IoI 25 50 100 μA VFB = 1.5 V VCOMP = 0.5 V
Source current Ioo -100 -50 -25 μA VFB = 1.0 V VCOMP = 0.5 V
[SW]
ON resistance N-channel RON_N 50 200 600 mΩ *
Leak current N-channel ILEAKN — — 10 μA Vsw = 18 V
Maximum duty cycle DMAX 75 85 95 %
[Overcurrent protection]
Saw current limit Insw 2 3 — A *
2. Regulator controller
Parameter Symbol
[Error amp]
VDD voltage VDD 3.2 3.3 3.4 V
Maximum base current IBMAX 4 7 11 mA
Line regulation RegI — 10 30 mV VCC = 4.5 V to 5.5 V
Load regulation RegL — 10 50 mV Io = 10 mA to 100 mA
[Under-voltage lockout protection]
Off threshold voltage VROFF 1.7 1.8 1.9 V
On threshold voltage VRON 1.6 1.7 1.8 V
This product is not designed for protection against radio active rays.
* Design guarantee (No total shipment inspection is made.)
Min. Typ. Max.
Min. Typ. Max.
Limit
Limit
Unit Conditions
Unit Conditions
Technical Note
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2/17
2009.07 - Rev.B
BD8153EFV
●Electrical Characteristics (Unless otherwise specified, VCC = 5 V; Vo1 = 15 V; Vo2 = 25 V; Ta = 25°C)
3.Charge pump
Parameter Symbol
[Error amp]
Input bias current 2 IFB2 — 0.1 0.5 μA
Input bias current 3 IFB3 — 0.1 0.5 μA
Feedback voltage 2 VFB2 1.183 1.240 1.307 V
Feedback voltage 3 VFB3 0.15 0.2 0.25 V
[Delay start block]
Source current IDSO 3 5 7 μA VDLS = 0.5V
Sinking current IDSI 0.1
Startup voltage VST 0.45 0.60 0.75 V
[Switch]
ON resistance N-channel RON_NC 0.5 2 4 Ω Io = 10 mA *
ON resistance P-channel RON_PC 0.5 4 8 Ω Io = -10 mA *
[Diode]
Voltage of diode Vf 600 710 800 mV Io = 10 mA
[Gate shading block]
ON resistance N-channel RON_NGS 2 10 20 Ω Io = 10 mA *
ON resistance P-channel RON_PGS 2 10 20 Ω Io = -10 mA *
Leak current N-channel ILEAK_NGS — — 10 μA
Leak current P-channel ILEAK_PGS — — 10 μA
High voltage IGH VDD × 0.7 VDD — V
Low voltage IGL — 0 VDD × 0.3 V
Input current IIG 8 16.5 30 μA IG = 3.3 V
4.Overall
Parameter Symbol
[Reference block]
Reference voltage VREF 1.215 1.240 1.265 V
Drive current IREF — 23 — mA VREF = 0 V
Load regulation ∆V — 1 10 mV IREF = -1 mA
[Oscillator]
Oscillating frequency Fosc 0.94 1.1 1.265 MHz
[Oscillator]
DET 1 On threshold voltage VDON1 1.7 1.8 1.9 V
DET 1 Off threshold voltage VDOFF1 1.6 1.7 1.8 V
DET 2 On threshold voltage VDON2 1.02 1.12 1.22 V
DET 2 Off threshold voltage VDOFF2 0.90 1.00 1.10 V
DET 3 On threshold voltage VDON3 0.25 0.30 0.35 V
DET 3 Off threshold voltage VDOFF3 0.35 0.41 0.47 V
DET 4 On threshold voltage VDON4 1.02 1.12 1.22 V
DET 4 Off threshold voltage VDOFF4 0.90 1.00 1.10 V
[Device]
Average circuit current Icc 0.5 2 5 mA No switching
This product is not designed for protection against radio active rays.
* Design guarantee (No total shipment inspection is made.)
Min. Typ. Max.
Min. Typ. Max.
Limit
0.5
Limit
Unit Conditions
1.0 mA VDLS = 0.5V
Unit Conditions
Technical Note
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3/17
2009.07 - Rev.B
BD8153EFV
]
.
Technical Note
● Reference Data (Unless otherwise specified, Ta = 25°C)
1
0.8
0.6
0.4
125℃
25℃
0.2
SUPPLY CURRENT : ICC[mA]
0
0 1.5 3 4.5 6
Fig. 1 Total Supply Current 1
-40℃
SUPPLY VOLT AGE : VC C [V]
1.6
1.2
0.8
10
8
6
25
4
2
SUPPLY CURRENT : IDD[mA]
0
01.534.56
SUPPLY VOLTAGE : VD D[V]
125℃
℃
-40
Fig. 2 Total Supply Current 2
1.6
1.2
0.8
1.26
1.25
1.24
1.23
℃
REF VOLTAGE : VREF[V
1.22
- 50 - 25 0 25 50 75 100 125
AMBIEN T TEMPERATURE : T a[℃]
Fig. 3 Internal Reference
Temperature
12
10
8
6
0.4
REF VOLTAGE : VREF [V]
0.4
REF VOLTAGE : VREF [V]
0
01.534.56
SUPPLY VOLT AGE : VC C[V]
Fig. 4 Internal
Reference Line Regulation
12
10
8
6
4
2
DLS SOURCE CURRENT : IDLS[μA]
0
01.5 34.56
SUPPLY VOLT AGE : VD D[V]
Fig. 7 DLS Source Current
200
160
120
80
SW VOLTAGE : VSW [V]
40
0
0 0.2 0.4 0.6 0.8 1
SW CURR ENT : ISW [A]
0
0 5 10 15 20 25 30
REF CURRENT : IREF[mA]
Fig. 5 Internal
Reference Load Regulation
2
1.5
1
0.5
SWITC HHING FR EQUENCY : f [MH z]
0
-50 - 25 0 25 50 75 100 125
-40
AMBIEN T TEM PERAT URE : Ta[℃]
Fig. 8 Switching Frequency
Temperature
200
160
120
80
40
OUTPUT VOLTAGE : Vcp[mV].
0
0 20 40 60 80 100
N channel
P channel
INPUT CURRENT : Icp[mA]
Fig. 10 SW On Resistance
Fig. 11 Charge Pump
On Voltage
4
2
SS SOURCE CURRENT : ISS[μA]
0
01.534.56
SUPPLY VOLT AGE : VDD[V]
Fig. 6 SS Source Current
5
4
3
2
VDD VOLTAGE : VDD [V]
1
0
024 6810
BASE CURRENT : IBASE[mA]
Fig. 9 REG Current Capacity
1
0.8
0.6
N channel
0.4
GS VOLTAGE : Vgs[V]
0.2
0
20 40 60 80 100
0
GS CURRENT : Igs[mA]
P channel
Fig. 12 Gate Shading
On Voltage
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© 2009 ROHM Co., Ltd. All rights reserved.
4/17
2009.07 - Rev.B
BD8153EFV
●Reference Data (Unless otherwise specified, Ta = 25°C)
15
10
5
OUTPU T VOLTAGE : VDD [V]
0
0 1.5 3 4.5 6
SUPPLY VOLT AGE : VCC [V]
Fig. 13 Vo1 Line Regulation
5
4
3
2
1
OUT PUT VOLTAGE : VDD [V]
0
00.40.81.21.62
OUTPUT CURRENT : IDD[mA]
Fig. 14 VDD Load Regulation
14
13
12
13V
12V
11
OUT PUT VOLTAGE : VO1[V]
10
0 100 200 300 400 500 600 700
Fig. 16 Vo1 Load Regulation
10.8V
OUTPUT CURRENT : IO[mA]
100
95
90
EFFICIENCY [ % ]
85
80
0 150 300 450 600
OUTPUT CURRENT : IO1[mA]
Fig. 17 Efficiency vs Output Current
1600
23.8
1200
800
23.7
23.6
400
MAXIMUM CURRENT : IoMAX[mA]
0
1.534.56
SUPPLY VOLT AGE : VC C[V]
23.5
OUT PUT VOLTAGE : VO2[V]
23.4
10 11.5 13 14.5 16
INPU T VOLTAGE : Vo1[v]
Fig. 19 Power Supply Voltage vs
Max. Output Current Capacity
Fig. 20 Vo2 Line Regulation
-6
-6
-6.1
-6.1
-6.2
-6.2
-6.3
OUT PUT VOLTAGE : VO3[V]
-6.4
10 11 12 13 14 15
INPU T VOLTAGE : VO1[V]
Fig. 22 Negative-side Charge
Pump Line Regulation
-6.3
OUT PUT VOLTAGE : VO1[V]
-6.4
0 50 100 150 200
OUTPUT CURRENT : IO[mA]
Fig. 23 Negative-side Charge
Pump Load Regulation
10.8V 12V 13V
Technical Note
12.5
12.4
12.3
12.2
12.1
12.0
11.9
11.8
Vo1 VOLTAGE : VO1[V]
11.7
11.6
11.5
23 456
SUPPLY VOLT AGE : VC C[V]
Fig. 15 Vo1 Line Regulation
100
90
80
EFF ICIEN CY [ % ]
70
60
2.5 3 3.5 4 4.5 5 5.5 6
SUPPLY VOLT AGE : VCC[V]
Fig. 18 Efficiency vs Power
Supply Voltage
24
23.8
23.6
23.4
23.2
OUT PUT VOLTAGE : VO2[V]
23
0 50 100 150
OUTPUT CURRENT : IO2[mA]
Fig. 21 Vo2 Load Regulation
IG
VO2GS
Fig. 24 Gate Shading
Output Waveform
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5/17
2009.07 - Rev.B
BD8153EFV
(
)
)
p
Technical Note
●Pin Assignments Diagram ●Block Diagram
GND
VDD
BASE
VCC
DLS
COMP
FB1
SS
PGND
SW
IG
FB2
REF
FB3
GND
C3
Vo1
C1H
C1L
C2L
C2H
GSOUT
Vo2GS
Vo2
0.1uF
0.1uF
1000
0.1uF
5.1k
SS
REF
COMP
Ω
F
DLS
IG
Vcc
1uF
VCC
5V
BASE
TSD
UVLO
Start-up
Controller
DET2
Regulator
VCC
VREF
10uF
Control 1
DET4
Step-up
Controller
Charge
Pump
1.8V
VDD
4.7uF
VCC
Gate
Shading
Controller
Vo1
Charge
Pump
Control 2
＋－
VDD=3.3V
DET1
10uF
SW
PGND
Vo1
＋－
DET4
PGND
Vo1
DET2
＋－
1.1V
Vo1
DET3
＋－
GND
GND
10uF
FB1
1.1V
Vo2
C2H
0.1uF
C2L
C1H
0.1uF
C1
L
FB2
Vo2G
GSOUT
C3
0.1uF
FB3
0.3V
160kΩ
15kΩ
1uF
R
1uF
Vo1=14.5V (18V MAX
Vo2 23.5V
270k
Ω
16kΩ
0.01uF
91k
Ω
18k
Ω
Fig. 25 Pin Arrangements and Block Diagram
●Pin Assignments and Function
PIN
NO.
Pin
name
Function
PIN
NO.
Pin
name
Function
1 GND Ground pin 13 Vo2 Positive-side charge pump output
2 VDD LDO feedback input pin 14 Vo2GS Gate shading source output pin
3 BASE LDO base drive output pin 15 GSOUT Gate shading sink output pin
4 VCC Power supply input pin 16 C2H Flying capacitor connection pin
5 DLS Capacity connection pin for delay start 17 C2L Flying capacitor connection pin
6 COMP DC/DC difference amplifier output 18 C1L Flying capacitor connection pin
7 FB1 DC/DC feedback input 19 C1H Flying capacitor connection pin
8 SS Soft start capacitor connection pin 20 Vo1 Negative-side charge pump power supply input pin
9 PGND Ground pin 21 C3 Negative-side charge pump driver output
10 SW Switch output 22 GND Ground pin
11 IG Gate shading input 23 FB3 Negative-side charge pump feedback input
12 FB2 Positive-side charge pump feedback input 24 REF Internal standard output pin
30V MAX
Vo2G
Vo3=-5V
REF
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6/17
2009.07 - Rev.B
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