ROHM BD8143MUV Technical data

Power Supply IC Series for TFT LCD Panels

High-precision
Gamma Correction IC with built-in DAC

BD8143MUV

●Description

This gamma correction voltage generation IC feature built-in DACs and provide a 1chip solution with setting control via serial
communications, a high-precision 10-bitDAC, and Buffer Amp (12ch).

●Features

1) 1chip design means fewer components

2) Built-in 10bit DAC

3) DAC output Buffer AMP (12ch)

4) Amp input select (CTL)

5) 3-line serial interface control

6) Thermal shut down

7) Power ON Reset Circuit

8) VQFN032V5050 Package

●Applications

These ICs can be used with TFT LCD Panels used by Large-Screen and High-Definition LCD TVs.

●Absolute maximum ratings (Ta=25℃)

Parameter Symbol Limit Unit

Power Supply Voltage 1 DVCC 7 V

Power Supply Voltage 2 VCC 20 V

REFIN Voltage REF 20 V

Amplifier Drive Current Io 30 *

Junction Temperature Tjmax 150 ℃

Power Dissipation Pd 2440 *2 mW
Operating Temperature Range Topr -40～+105 ℃
Storage Temperature Range Tstg -55～+150 ℃

*1 Pd, should not be exceeded.
*2 Reduced by 19.52mW/°C over 25°C, when mounted on a glass epoxy board.
(4-layer 74.2×74.2×1.6mm).

●Operating Condition (Ta=-40℃～105℃)

Parameter Symbol

Power Supply Voltage 1 DVCC 2.3 5.5 V

Power Supply Voltage 2 VCC 8 18 V

REFIN Voltage REF 8 18 V

AMP0 Drive Current IOA -40 - mA
AMP1～10 Drive Current IOB -20 20 mA

AMP11 Drive Current IOC - 40 mA

Serial CLK Frequency fCLK - 5 MHz

OSC Frequency FOSC - 200 kHz

MIN MAX

1

mA

Limit

Unit

No.09035EBT08

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1/10

2009.07 - Rev.B

BD8143MUV

●Electrical Characteristics (Unless otherwise specified, Ta=25℃,DVCC=3.3V,VCC=15V)

Parameter Symbol

〔REFIN〕

Sink Current Iref 90 200 µA REF=10V

〔γCORRECTION AMP〕

Source Drive Current (AMP0) IooA -60 mA DAC=7V,OUT0=13V
Source Drive Current (AMP1～10) IooB -30 mA DAC=3.5V,OUT1～10=0V
Source Drive Current (AMP11) IooC -10 mA DAC=0.5V,OUT11=0V
Sink Drive Current (AMP0) IoiA 10 mA DAC=7V,OUT0=15V
Sink Drive Current (AMP1～10) IoiB 30 mA DAC=3.5V,OUT1～10=15V
Sink Drive Current (AMP11) IoiC 60 mA DAC=0.5V,OUT11=2V
Load regulation (OUT0) ⊿V-A 10 mV Io=0mA～-35mA, OUTx=6V
Load regulation (OUT1～10) ⊿V-B 10 mV Io=-15mA～15mA, OUTx=6V
Load regulation (OUT11) ⊿V-C 10 mV Io=0mA～35mA, OUTx=6V
Slew Rate SR 3 V/µs
OUT Voltage High (OUT0) VOH-A VCC-0.4 VCC-0.15 - V Io=-35mA
OUT Voltage High (OUT1～10) VOH-B VCC-0.75 - V Io=-15mA
OUT Voltage High (OUT11) VOH-C VCC-0.75 - V Io=-15mA
OUT Voltage Low (OUT0) VOL-A - 0.75 V Io=15mA
OUT Voltage Low (OUT1～10) VOL-B - 0.75 V Io=15mA
OUT Voltage Low (OUT11) VOL-C - 0.1 0.2 V Io=35mA

〔DAC〕

Resolution Coding Res 10 Bit

Non-Linear Error (INL) LE -2 - 2 LSB

Differential Error (DNL) DLE -2 - 2 LSB

〔OSC〕

OSC Frequency fosc - 100 - kHz Internal oscillator mode

〔CONTROL SIGNAL〕

Sink Current Ictl 16.5 µA VIN=3.3V
Threshold Voltage VTH DVCC×0.2 DVCC×0.8 V

〔CONTROL〕

OUT0 Voltage Vpre0 -

OUT1 Voltage Vpre1 -

OUT2 Voltage Vpre2 -

OUT3 Voltage Vpre3 -

OUT4 Voltage Vpre4 -

OUT5 Voltage Vpre5 -

OUT6 Voltage Vpre6 -

OUT7 Voltage Vpre7 -

OUT8 Voltage Vpre8 -

OUT9 Voltage Vpre9 -

OUT10 Voltage Vpre10 -

OUT11 Voltage Vpre11 -

〔WHOLE DEVICE〕

VDAC Detection Voltage Vdet 2.6 3.2 3.6 V
Circuit Current ICC 5 mA CTL=”LOW”

This product is not designed for protection against radio active rays.

MIN TYP MAX

Limit

REFIN

X 12/13

REFIN

X 11/13

REFIN

X 10/13

REFIN
X 9/13
REFIN

X 813
REFIN
X 7/13
REFIN
X 6/13
REFIN
X 5/13
REFIN
X 4/13
REFIN
X 3/13
REFIN
X 2/13
REFIN
X 1/13

Unit Conditions

Error with ideal straight Range
00A～3F5
Error with ideal amount of

Increase in 1LSB Range
00A～3F5

- V CTL=”LOW”

- V CTL=”LOW”

- V CTL=”LOW”

- V CTL=”LOW”

- V CTL=”LOW”

- V CTL=”LOW”

- V CTL=”LOW”

- V CTL=”LOW”

- V CTL=”LOW”

- V CTL=”LOW”

- V CTL=”LOW”

- V CTL=”LOW”

Technical Note

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2/10

2009.07 - Rev.B

K

C

8

A

5

C

N

C

C

0

9

BD8143MUV

●Pin No ●Block Diagram

OUT

OUT1

OUT11

VC

REFI

VDA

DACGND

N.

OUT

OUT7

24 23 22 21 19 17 18 20

25

26

27

28

29

30

31

32

1 2 3 4 6 8 7 5

SDIN

LATCH

OUT6

CL

GND AGND

SDOUT

OUT3

OUT4

OUT

16

OUT2

15

OUT1

14

OUT0

13

VCC

N.C

12

CTL

11

10

N.C

OS C

9

CT

DVC

N.C

GND

LATCH

DATA

CLK

SDOUT

VDD

VCC REFIN

VDD

VREF

CT

Power

ON

Reset

Serial

DACGND GND OSC AGND AGND

VDAC

VCC

VCC

R

R

I/F

VDD

OSC

UVLO

VDAC

REG

TSD

Refresh
Control

Fig.1 Pin No. & Block Diagram

●Pin NO. & Function Table

PIN
No.

Pin

Name

Function

PIN
No.

Pin

Name

1 LATCH LATCH signal input 17 OUT3 Gamma 3 output

2 SDIN DATA signal input 18 OUT4 Gamma 4 output

3 CLK CLK signal input 19 OUT5 Gamma 5 output

4 SDOUT DATA signal output 20 AGND Ground for Buffer AMP

5 DVCC Digital Power Supply 21 AGND Ground for Buffer AMP

6 CT Capacitor connection for Power on Reset 22 OUT6 Gamma 6 output

7 GND Ground 23 OUT7 Gamma 7 output

8 N.C - 24 OUT8 Gamma 8 output

9 OSC DAC Synchronized clock inout 25 OUT9 Gamma 9 output

10 N.C - 26 OUT10 Gamma 10 output

11 CTL Output control signal input 27 OUT11 Gamma 11 output

12 N.C - 28 VCC Power Supply for Buffer AMP

13 VCC Power Supply for Buffer AMP 29 REFIN DAC reference input

14 OUT0 Gamma 0 output 30 VDAC DAC Voltage output

15 OUT1 Gamma 1 output 31 DACGND Ground for DAC

16 OUT2 Gamma 2 output 32 N.C -

Technical Note

VDAC

REGISTER0

REGISTER1

REGISTER2

REGISTER3

REGISTER4

REGISTER5

REGISTER6

REGISTER7

REGISTER8

REGISTER9

REGISTER10

REGISTER11

REGISTER12

Function

DAC

Control

VCC

AMP0

x2

OUT0

AMP1

OUT1

x2

AMP2

x2

OUT2

AMP3

x2

OUT3

AMP4

OUT4

x2

AMP5

x2

OUT5

AMP6

OUT6

x2

AMP7

x2

OUT7

AMP8

OUT8

x2

AMP9

OUT9

x2

AMP10

x2

OUT10

AMP11

OUT11

x2

CTL

CTL

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© 2009 ROHM Co., Ltd. All rights reserved.

3/10

2009.07 - Rev.B

BD8143MUV

●Block Operation
・REG

REG amplifiers the voltage applied to REFIN by 0.5x and output it to the VDAC pin. Connect a 1µF phase compensation
capacitor to the VDAC pin.

・DAC Control

DAC Control convents the 10-bit digital signal read to the register to a voltage.

・Amp

Amp amplifiers the voltage output from DAC Control by 2x. Input includes sample & hold function, refreshed by OSC.

・OSC

The OSC generates the frequency that determines the Amp's refresh time.
External input can be selected using serial input.

・Power On Reset

When the digital power supply DVCC is activated, each IC generates a reset signal to initialize the serial interface, registers.
Adding a 1,000 pF capacitor to the CT pin ensures that reset operation can be performed reliably, without regard to the
speed with which the power supply starts up.

・VREF

This block generates the internal reference voltage.

・TSD(Thermal Shut Down)

The TSD circuit turns output off when the chip temperature reaches or exceeds approximately 175°C(TYP) in order to
prevent thermal destruction or thermal runaway. When the chip returns to a specified temperature, the circuit resets.
The TSD circuit is designed only to protect the IC itself. Application thermal design should ensure operation of the IC
below the thermal shutdown junction temperature of approximately 150°C(TYP).

・CTL

CTL signal can select Amp input. If CTL=”L”, each output voltage is fixed at REFIN voltage divided 13th equality.
IF CTL=”H”, each Amp input connect DAC output, and each output comply with each register.

・Register

A serial signal (consisting of 10-bit gamma correction voltage values) input using the serial interface is held for each
register address. Data is initialized by the reset signal generated during a power-on reset.

・Serial I/F

The serial interface uses a 3-line serial data format (LATCH, CLK, SDIN). It is used to set gamma correction voltages,
specify register addresses, and select OSC I/O.

Technical Note

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© 2009 ROHM Co., Ltd. All rights reserved.

4/10

2009.07 - Rev.B