High-precision
Gamma Correction IC with built-in DAC
BD8143MUV
●Description
This gamma correction voltage generation IC feature built-in DACs and provide a 1chip solution with setting control via serial
communications, a high-precision 10-bitDAC, and Buffer Amp (12ch).
●Features
1) 1chip design means fewer components
2) Built-in 10bit DAC
3) DAC output Buffer AMP (12ch)
4) Amp input select (CTL)
5) 3-line serial interface control
6) Thermal shut down
7) Power ON Reset Circuit
8) VQFN032V5050 Package
●Applications
These ICs can be used with TFT LCD Panels used by Large-Screen and High-Definition LCD TVs.
●Absolute maximum ratings (Ta=25℃)
Parameter Symbol Limit Unit
Power Supply Voltage 1 DVCC 7 V
Power Supply Voltage 2 VCC 20 V
REFIN Voltage REF 20 V
Amplifier Drive Current Io 30 *
Junction Temperature Tjmax 150 ℃
Power Dissipation Pd 2440 *2 mW
Operating Temperature Range Topr -40~+105 ℃
Storage Temperature Range Tstg -55~+150 ℃
*1 Pd, should not be exceeded.
*2 Reduced by 19.52mW/°C over 25°C, when mounted on a glass epoxy board.
(4-layer 74.2×74.2×1.6mm).
●Operating Condition (Ta=-40℃~105℃)
Parameter Symbol
Power Supply Voltage 1 DVCC 2.3 5.5 V
Power Supply Voltage 2 VCC 8 18 V
REFIN Voltage REF 8 18 V
AMP0 Drive Current IOA -40 - mA
AMP1~10 Drive Current IOB -20 20 mA
Source Drive Current (AMP0) IooA -60 mA DAC=7V,OUT0=13V
Source Drive Current (AMP1~10) IooB -30 mA DAC=3.5V,OUT1~10=0V
Source Drive Current (AMP11) IooC -10 mA DAC=0.5V,OUT11=0V
Sink Drive Current (AMP0) IoiA 10 mA DAC=7V,OUT0=15V
Sink Drive Current (AMP1~10) IoiB 30 mA DAC=3.5V,OUT1~10=15V
Sink Drive Current (AMP11) IoiC 60 mA DAC=0.5V,OUT11=2V
Load regulation (OUT0) ⊿V-A 10 mV Io=0mA~-35mA, OUTx=6V
Load regulation (OUT1~10) ⊿V-B 10 mV Io=-15mA~15mA, OUTx=6V
Load regulation (OUT11) ⊿V-C 10 mV Io=0mA~35mA, OUTx=6V
Slew Rate SR 3 V/µs
OUT Voltage High (OUT0) VOH-A VCC-0.4VCC-0.15- V Io=-35mA
OUT Voltage High (OUT1~10) VOH-B VCC-0.75- V Io=-15mA
OUT Voltage High (OUT11) VOH-C VCC-0.75- V Io=-15mA
OUT Voltage Low (OUT0) VOL-A - 0.75 V Io=15mA
OUT Voltage Low (OUT1~10) VOL-B - 0.75 V Io=15mA
OUT Voltage Low (OUT11) VOL-C - 0.1 0.2 V Io=35mA
〔DAC〕
Resolution Coding Res 10 Bit
Non-Linear Error (INL) LE -2 - 2 LSB
Differential Error (DNL) DLE -2 - 2 LSB
〔OSC〕
OSC Frequency fosc - 100 - kHz Internal oscillator mode
〔CONTROL SIGNAL〕
Sink Current Ictl 16.5 µA VIN=3.3V
Threshold Voltage VTH DVCC×0.2 DVCC×0.8V
〔CONTROL〕
OUT0 Voltage Vpre0 -
OUT1 Voltage Vpre1 -
OUT2 Voltage Vpre2 -
OUT3 Voltage Vpre3 -
OUT4 Voltage Vpre4 -
OUT5 Voltage Vpre5 -
OUT6 Voltage Vpre6 -
OUT7 Voltage Vpre7 -
OUT8 Voltage Vpre8 -
OUT9 Voltage Vpre9 -
OUT10 Voltage Vpre10 -
OUT11 Voltage Vpre11 -
〔WHOLE DEVICE〕
VDAC Detection Voltage Vdet 2.6 3.2 3.6 V
Circuit Current ICC 5 mA CTL=”LOW”
This product is not designed for protection against radio active rays.
MIN TYP MAX
Limit
REFIN
X 12/13
REFIN
X 11/13
REFIN
X 10/13
REFIN
X 9/13
REFIN
X 813
REFIN
X 7/13
REFIN
X 6/13
REFIN
X 5/13
REFIN
X 4/13
REFIN
X 3/13
REFIN
X 2/13
REFIN
X 1/13
UnitConditions
Error with ideal straight Range
00A~3F5
Error with ideal amount of
REG amplifiers the voltage applied to REFIN by 0.5x and output it to the VDAC pin. Connect a 1µF phase compensation
capacitor to the VDAC pin.
・DAC Control
DAC Control convents the 10-bit digital signal read to the register to a voltage.
・Amp
Amp amplifiers the voltage output from DAC Control by 2x. Input includes sample & hold function, refreshed by OSC.
・OSC
The OSC generates the frequency that determines the Amp's refresh time.
External input can be selected using serial input.
・Power On Reset
When the digital power supply DVCC is activated, each IC generates a reset signal to initialize the serial interface, registers.
Adding a 1,000 pF capacitor to the CT pin ensures that reset operation can be performed reliably, without regard to the
speed with which the power supply starts up.
・VREF
This block generates the internal reference voltage.
・TSD(Thermal Shut Down)
The TSD circuit turns output off when the chip temperature reaches or exceeds approximately 175°C(TYP) in order to
prevent thermal destruction or thermal runaway. When the chip returns to a specified temperature, the circuit resets.
The TSD circuit is designed only to protect the IC itself. Application thermal design should ensure operation of the IC
below the thermal shutdown junction temperature of approximately 150°C(TYP).
・CTL
CTL signal can select Amp input. If CTL=”L”, each output voltage is fixed at REFIN voltage divided 13th equality.
IF CTL=”H”, each Amp input connect DAC output, and each output comply with each register.
・Register
A serial signal (consisting of 10-bit gamma correction voltage values) input using the serial interface is held for each
register address. Data is initialized by the reset signal generated during a power-on reset.
・Serial I/F
The serial interface uses a 3-line serial data format (LATCH, CLK, SDIN). It is used to set gamma correction voltages,
specify register addresses, and select OSC I/O.
The serial data control block is composed of Shift-Register, DAC Register and DAC circuit.
The DAC register memorizes data from the serial interface (LATCH, CLK and SDIN).
The DAC circuit makes control voltage from the register output and it outputs to the each block. The DAC register value turns
back the preset value when Power Supply starts up.
Then, beginning 1bit of SDIN is always 0, because it is for test. Next 1bit switches OSC mode.
If input 0, OSC mode is internal mode (the frequency is 100kHz). If input 1, it is external one that require external clock.
LATCH
CLK
SDIN
CLOCK
CONTROL
SERIAL DATA CONTROL BLOCK
d13
d14
d15
d16
d12
Shift Register
d11
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
OUT0~12
Register
10bit
ADDRESS
DECORDE
5bit
OSC
MODE
1bit
TEST
MODE
1bit
DAC
Fig.2 SERIAL BLOCK
①TIMING OF SERIAL COMMUNICATION
The 17 bits Serial data from SDIN terminal is loaded to Shift-Register at the rise edge of CLK, and these data is loaded to
DAC Register at the rise edge of LATCH.
If serial data period is less than 17 bits while LATCH state is LOW, the serial data is not memorized. If serial data period is
more than 17 bits while LATCH state is LOW, last 17 bits are effective.
LATCH
CLK
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10
SDIN
TIMING OF SERIAL COMMUNICATION
d1
1
d12
d14 d15
d16
d13
Fig.3 TIMING OF SERIAL COMMUNICATION
②SERIAL DATA
The composition of SERIAL DATA INPUT(SDIN)
First →→ Last
LATCH Set up time tLC 0.1 - - us
SDIN Set up time tSC 0.1 - - us
CLK “H” time tWH 0.1 - - us
CLK “L” time tWL 0.1 - - us
LATCH hold time tCL 0.1 - - us
LATCH “H” time tLA 0.6 - - us
●Setting γ-Correction
Formula (1) shows the relationship between γ output voltage (OUT0~OUT11) and DAC digital value.
Output Voltage(OUT0~OUT11)=({(DAC digital value +1)/1024}×(REFIN/2)‐10mV)×2.0025 ・・・(1)
●Power Supply Sequence
Digital power supply DVCC must be supplied earlier than VCC for the prevent of wrong behavior.
The serial data must be input after cancellation of “Power on Reset”.
When turn off power supply, VCC must be done earlier than DVCC.
VCC
REFIN
DVCC
LATCH
CLK
SDIN
・・・
・・・
・・・
・・・
tDS
・・・
・・・
tSV
・・・
tVcc
・・・
tVR
・・・
・・・
・・・
・・・
tVD
tRV
Fig.5 Power Supply Sequence
●Power Supply Sequence Standard Value
Parameter Symbol
Min. Typ. Max.
LIMIT
Unit Condition
Timing of serial data input tDS 100 - - μs Cct=1000pF
Data writing time for register depend on frequency of CLK. Below formula shows data writing time for all registers.
(Because data writing time for a register is needed at 17bit data + LATCH “H” time.)
18 CLK × ×12ch [µs]
f
CLK
1
[MHz]
●Refresh time of Amp input
Each Amp input have sample & hold function refreshed by OSC frequency (fosc).
Below formula shows refresh cycle.
×12ch [µs]
f
OSC
1
[kHz]
When internal OSC mode, f
=100kHz (Typ).
OSC
●Function of selecting Amp input
This IC can select Amp input by CTL signal. If CTL=”L”, Amp input is connected to resistance division of REFIN voltage.
IF CTL=”H”, connected to DAC output. When VCC(REFIN) supplies with CTL=”L”, it is possible to start up without opposite
Voltage of each output. Then, if the CTL signal changes “H” after 1ms and over since VCC(REFIN) supplied and data send
finished, start up sequence should be below Fig.
(*Amp input is connected to DAC output not only by CTL=”H”, but also DATA=1010100000(2A0h) sended to Register 12.
Also in this case, please send DATA=1010100000(2A0h) to Register 12 after 1ms and over since VCC(REFIN) supplied
And output data send finished, at this time CTL=”L”.)
REFIN
VCC
Preset value
CTL
VDAC
VCC
DAC
Control
x2
OUT
DAC value
CTL
Preset value DAC value
Fig.6 Selecting Amp input block diagram Fig.7 Start up sequence
1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may
result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such
damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special
mode where the absolute maximum ratings may be exceeded is anticipated.
2) GND potential
Ensure a minimum GND pin potential in all operating conditions.
3) Setting of heat
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4) Pin short and mistake fitting
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in
damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the
presence of a foreign object may result in damage to the IC.
5) Actions in strong magnetic field
Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction.
6) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure,
and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process.
7) Ground wiring patterns
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the
GND wiring patterns of any external components.
8) Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of
parasitic elements. For example, when the resistors and transistors are connected to the pins as shown in below Fig.9, a
parasitic diode or a transistor operates by inverting the pin voltage and GND voltage. The formation of parasitic elements
as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation
of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these
reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements
such as by the application of voltages lower than the GND (P substrate) voltage to input and output pins.
(Pin A)
NN
P
Fig.9 Example of a Simple Monolithic IC Architecture
Resistor
N
P
GND
~
~
P+P+
Parasitic elements
Pin B
P+
NN
Parasitic elements
Transistor (NPN)
C
B
E
~
~
N
P
N
P substrate
GND
Pin B
C
B
~
~
E
GND
P+
Pin A
GND
Parasitic
elements
Parasitic
elements
~
~
GND
9) Overcurrent protection circuits
An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC damage
that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and
unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or
transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capacity has negative
characteristics to temperatures.
10) Thermal shutdown circuit (TSD)
This IC incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within the
specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power
dissipation limits, the attendant rise in the chip's junction temperature Tj will trigger the TSD circuit to turn off all output power
elements. The circuit automatically resets once the junction temperature Tj drops.Operation of the TSD circuit presumes that
the IC's absolute maximum ratings have been exceeded. Application designs should never make use of the TSD circuit.
11) Testing on application boards
At the time of inspection of the inst
allation boards, when the capacitor is connected to the pin with low impedance, be sure
to discharge electricity per process because it may load stresses to the IC. Always turn the IC's power supply off before
connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as
an antistatic measure, and use similar caution when transporting or storing the IC.
12) Push Current
This IC may rush current momentary by power supply order or delay, use caution about power supply coupling capacitor,
width or routing of VCC ,GND patterns
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Examples of application circuits, circuit constants and any other information contained herein
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