●Description
High voltage operable CMOS Op- A m p BD7561/BD7541 family and BD7562/BD7542 family Integrate one or two independent
input-output fullswing Op-amps and phase compesation capacitorson a single chip.
Especially, characteristics are wide operati ng vol t age range o f +5[V]~+14.5[V](single power supply),low supply current and little
input bias current.
Supply Voltage VDD-VSS+15.5 V
Differential Input Voltage
(*1)
Vid VDD-VSS V
Input Common-mode Voltage Range Vicm (VSS-0.3)~(VDD+0.3) V
Operating Temperature Topr -40~+85 -40~+105 ℃
Storage Temperature Tstg -55~+125 ℃
Maximum Junction Temperature Tjmax +125 ℃
Note: Absolute maximum rating item indicates the condition which must not be exceeded.
Application of voltage in excess of absolute maximum rating or use out absoluted maximum rated temperature environment may cause deterioration of characteristics.
(*1) The voltage difference between inverting input and non-inverting input is the differential input voltage.
Then input terminal voltage is set to more then VSS.
●Electric Characteristics
○BD7561
Input Offset Voltage
Input Offset Current
Input Bias Current
Supply Current
High Level Output Voltage VOH 25℃ VDD-0.1- - VRL=10[kΩ]
Low Level Output Voltage
family (Unless otherwise specified VDD=+12[V], VSS=0[V], Ta=25[℃])
Parameter Symbol
(*2)(*4)
Vio
(*2)
Iio 25℃ - 1 - pA-
(*2)
Ib 25℃ - 1 - pA-
T emperature
range
25℃ - 1 9
Full range- - 10
25℃ - 370 550
(*4)
IDD
Full range- - 600
25℃ - 440 650
Full range- - 700
VOL 25℃ - - VSS+0.1VRL=10[kΩ]
Guaranteed limit
BD7561G,BD7561SG
Min. Typ. Max.
UnitCondition
mV VDD=5~14.5[V],VOUT=VDD/2
RL=∞ All Op-Amps
AV=0[dB],VDD=5[V],VIN=2.5[V]
μA
RL=∞ All Op-Amps
AV=0[dB],VDD=12[V],VIN=6.0[V]
Large Single Voltage Gain AV 25℃ 70 95 - dB RL=10[kΩ]
Input Common-mode Voltage Range Vicm 25℃ 0 - 12 VVDD-VSS=12[V]
Common-mode Rejection Ratio CMRR 25℃ 45 60 - dBPower Supply Rejection Ratio PSRR 25℃ 60 80 - dBOutput Source Current
Output Sink Current
(*3)
IOH 25℃ 3 8 - mA VDD-0.4[V]
(*3)
IOL 25℃ 4 14 - mA VSS+0.4[V]
Slew Rate SR 25℃ - 0.9 - V/μs CL=25[pF]
Gain Bandwidth Product FT 25℃ - 1.0 - MHz CL=25[pF], AV=40[dB]
Phase Margin θ 25℃ - 50° - - CL=25[pF], AV=40[dB]
Total Harmonic Distortion THD 25℃ - 0.05 - %VOUT=1[Vp-p],f=1[kHz]
(*2) Absolute value
(*3) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.
When the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.
(*4) Full range:BD7561:Ta=-40[℃]~+85[℃] BD7561S:Ta=-40[℃]~+105[℃]
○BD7562 family (Unless otherwise specified VDD=+12[V], VSS=0[V], Ta=25[℃])
Guaranteed limit
Parameter Symbol
T emperature
range
BD7562F/FVM
BD7562SF/FVM
UnitCondition
Min. Typ. Max.
Input Offset Voltage
Input Offset Current
Input Bias Current
Supply Current
High Level Output Voltage VOH 25℃ VDD-0.1- - VRL=10[kΩ]
Low Level Output Voltage
(*2)(*4)
Vio
(*2)
Iio 25℃ - 1 - pA-
(*2)
Ib 25℃ - 1 - pA-
(*4)
IDD
VOL 25℃ - - VSS+0.1VRL=10[kΩ]
25℃ - 1 9
Full range- - 10
25℃ - 750 1300
Full range- - 1500
25℃ - 900 1400
Full range- - 1600
mV VDD=5~14.5[V],VOUT=VDD/2
RL=∞ All Op-Amps
AV=0[dB],VDD=5[V],VIN=2.5[V]
μA
RL=∞ All Op-Amps
AV=0[dB],VDD=12[V],VIN=6.0[V]
Large Single Voltage Gain AV 25℃ 70 95 - dB RL=10[kΩ]
Input Common-mode Voltage Range Vicm 25℃ 0 - 12 VVDD-VSS=12[V]
Common-mode Rejection Ratio CMRR 25℃ 45 60 - dBPower Supply Rejection Ratio PSRR 25℃ 60 80 - dBOutput Source Current
Output Sink Current
(*3)
IOH 25℃ 3 8 - mA VDD-0.4[V]
(*3)
IOL 25℃ 4 14 - mA VSS+0.4[V]
Slew Rate SR 25℃ - 0.9 - V/μs CL=25[pF]
Gain Bandwidth Product FT 25℃ - 1.0 - MHz CL=25[pF], AV=40[dB]
Phase Margin θ 25℃ - 50° - - CL=25[pF], AV=40[dB]
Total Harmonic Distortion THD 25℃ - 0.05 - %VOUT=1[Vp-p],f=1[kHz]
(*2) Absolute value
(*3) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.
When the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.
(*4) Full range: BD7562:Ta=-40[℃]~+85[℃] BD7562S:Ta=-40[℃]~+105[℃]
○BD7541 family (Unless otherwise specified VDD=+12[V], VSS=0[V], Ta=25[℃])
Parameter Symbol
Input Offset Voltage
Input Offset Current
Input Bias Current
(*5)(*7)
Vio
(*5)
Iio 25℃ - 1 - pA-
T emperature
range
25℃ - 1 9
Full range- - 10
Ib 25℃ - 1 - pA-
25℃ - 170 300
Supply Current
(*7)
IDD
Full range- - 400
25℃ - 180 320
Full range- - 420
High Level Output Voltage VOH 25℃ VDD-0.1- - VRL=10[kΩ]
Low Level Output Voltage
VOL 25℃ - - VSS+0.1VRL=10[kΩ]
Guaranteed limit
BD7541G,BD7541SG
Min. Typ. Max.
UnitCondition
mV VDD=5~14.5[V],VOUT=VDD/2
RL=∞ All Op-Amps
AV=0[dB],VDD=5[V],VIN=2.5[V]
μA
RL=∞ All Op-Amps
AV=0[dB],VDD=12[V],VIN=6.0[V]
Large Single Voltage Gain AV 25℃ 70 95 - dB RL=10[kΩ]
Input Common-mode Volt age Range Vicm 25℃ 0 - 12 VVDD-VSS=12[V]
Common-mode Rejection Ratio CMRR 25℃ 45 60 - dBPower Supply Rejection Ratio PSRR 25℃ 60 80 - dBOutput Source Current
Output Sink Current
(*6)
IOH 25℃ 2 4 - mA VDD-0.4[V]
(*6)
IOL 25℃ 3 7 - mA VSS+0.4[V]
Slew Rate SR 25℃ - 0.3 - V/μs CL=25[pF]
Gain Bandwidth Product FT 25℃ - 0.6 - MHz CL=25[pF], AV=40[dB]
Phase Margin θ 25℃ - 50° - - CL=25[pF], AV=40[dB]
Total Harmonic Distortion THD 25℃ - 1 9 %VOUT=1[Vp-p],f=1[kHz]
(*5) Absolute value
(*6) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.
When the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.
(*7) Full range:BD7541:Ta=-40[℃]~+85[℃] BD7541S:Ta=-40[℃]~+105[℃]
○BD7542 family (Unless otherwise specified VDD=+12[V], VSS=0[V], Ta=25[℃])
Guaranteed limit
Parameter Symbol
T emperature
range
BD7542 F/FVM
BD7542S F/FVM
UnitCondition
Min. Typ. Max.
Input Offset Voltage
Input Offset Current
Input Bias Current
Supply Current
High Level Output Voltage VOH 25℃ VDD-0.1- - VRL=10[kΩ]
Low Level Output Voltage
(*5)(*7)
Vio
(*5)
Iio 25℃ - 1 - pA-
(*7)
IDD
Ib 25℃ - 1 - pA-
VOL 25℃ - - VSS+0.1VRL=10[kΩ]
25℃ - 1 9
Full range- - 10
25℃ - 340 650
Full range- - 850
25℃ - 400 780
Full range- - 900
mV VDD=5~14.5[V],VOUT=VDD/2
RL=∞ All Op-Amps
AV=0[dB],VDD=5[V],VIN=2.5[V]
μA
RL=∞ All Op-Amps
AV=0[dB],VDD=12[V],VIN=6.0[V]
Large Single Voltage Gain AV 25℃ 70 95 - dB RL=10[kΩ]
Input Common-mode Volt age Range Vicm 25℃ 0 - 12 VVDD-VSS=12[V]
Common-mode Rejection Ratio CMRR 25℃ 45 60 - dBPower Supply Rejection Ratio PSRR 25℃ 60 80 - dBOutput Source Current
Output Sink Current
(*6)
IOH 25℃ 2 4 - mA VDD-0.4[V]
(*6)
IOL 25℃ 3 7 - mA VSS+0.4[V]
Slew Rate SR 25℃ - 0.3 - V/μs CL=25[pF]
Gain Bandwidth Product FT 25℃ - 0.6 - MHz CL=25[pF], AV=40[dB]
Phase Margin θ 25℃ - 50° - - CL=25[pF], AV=40[dB]
Total Harmonic Distortion THD 25℃ - 0.05 - %VOUT=1[Vp-p],f=1[kHz]
(*5) Absolute value
(*6) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.
When the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.
(*7) Full range:BD7542:Ta=-40[℃]~+85[℃] BD7542S:Ta=-40[℃]~+105[℃]
Supply Current OFF OFFONOFFONOFF OFFOFF OFF OFF OFF OFF
Maximum Output Voltage RL=10 [kΩ] OFF ONOFFOFFONOFFOFFON OFF OFF ONOFF
Output Current OFF ONOFF OFFONOFF OFF OFF OFF ON OFF OFF
Slew Rate OFF OFFONOFF OFF OFFONOFF ON OFF OFFON
Maximum Frequency ON OFF OFFONONOFF OFF OFF ON OFF OFFON
●Description of electrical characteristics
Described here are the terms of electric characteristics used in this technical note. Items and symbols used are also shown.
Note that item name and symbol and their meaning may differ from those on another manufacture’s document or general document.
1. Absolute maximum ratings
Absolute maximum rating item indicates the condition which must not be exce eded. Application of voltage in excess of absolute
maximum rating or use out of absolute maximum rated temperature environment may cause deterioration of characteristics.
1.1 Power supply voltage (VDD/VSS)
Indicates the maximum voltage that can be applied between the positive power supply terminal and negative power supply
terminalwithout deterioration or destruction of characteristics of internal circuit.
1.2 Differential input voltage (Vid)
Indicates the maximum voltage that can be applied between non-inverting terminal and inverting terminal without
deterioration and destruction of characteristics of IC.
1.3 Input common-mode voltage range (Vicm)
Indicates the maximum voltage that can be applied to non-inverting terminal and inverting terminal without deterioration or
destruction of characteristics. Input common-mode voltage range of the maximum ratings not assure normal operation of
IC. When normal Operation of IC is desired, the input common-mode voltage of characteristics item must be followed.
1.4 Power dissipation (Pd)
Indicates the power that can be consumed by specified mounte d board at the ambient temperature 25℃( normal temperature).
As for package product, Pd is determined by the temperature that can be permitted by IC chip in the package(maximum
junction temperature)and thermal resistance of the package.
2. Electrical characteristics item
2.1 Input offset voltage (Vio)
Indicates the voltage difference between non-inverting terminal and inverting terminal. It can be translated into the input
voltage difference required for setting the output voltage at 0 [V].
2.2 Input offset current (Iio)
Indicates the difference of input bias current between non-inverting terminal and inverting terminal.
2.3 Input bias current (Ib)
Indicates the current that flows into or out of the input terminal. It is defined by the average of input bias current at
non-inverting terminal and input bias current at inverting terminal.
2.4 Circuit current (ICC)
Indicates the IC current that flows under specified conditions and no-load steady status.
2.5 High level output voltage / Low level output voltage(VOH/VOL)
Indicates the voltage range that can be output by the IC under specified load condition. It is typically divided into high-level
output voltage and low-level output voltage. High-level output voltage indicates the upper limit of output voltage. Low-level
output voltage indicates the lower limit.
2.6 Large signal voltage gain (AV)
Indicates the amplifying rate (gain) of output voltage against the voltage difference between non-inverting terminal and
inverting terminal.It is normally the amplifying rate (gain) with reference to DC voltage.
Av = (Output voltage fluctuation) / (Input offset fluctuation)
2.7 Input common-mode voltage range (Vicm)
Indicates the input voltage range where IC operates normally.
2.8 Common-mode rejection ratio (CMRR)
Indicates the ratio of fluctuation of input offset voltage when in-phase input voltage is changed. It is normally the fluctuation of DC.
CMRR =(Change of Input common-mode voltage)/(Input offset fluctuation)
2.9 Power supply rejection ratio (PSRR)
Indicates the ratio of fluctuation of input offset voltage when supply voltage is changed. It is normally the fluctuation of DC.
PSRR=(Change of power supply voltage)/(Input offset fluctuation)
2.10 Ch
annel separation(CS)
Indicates the fluctuation of input offset voltage or that of output voltage with reference to the change of output voltage of
driven channel.
2.11 Slew rate (SR)
Indicates the time fluctuation ratio of voltage output when step input signal is applied.
2.12 Unity gain frequency (ft)
Indicates a frequency where the voltage gain of Op-Amp is 1.
2.13 Total harmonic distortion + Noise (THD+N)
Indicates the fluctuation of input offset voltage or that of output voltage with reference to the change of output voltage
of driven channel.
2.14 Input referred noise voltage (Vn)
Indicates a noise voltage generated inside the operational amplifier equivalent by ideal voltage source connected in series
with input terminal.
●Derating curve
Power dissipation (total loss) indicates the power that can be consumed by IC at Ta=25℃(normal temperature).
IC is heatedwhen it consumed power, and the temperature of IC ship becomes higher than ambient temperature.
The temperature that can be accepted by IC chip depends on circuit configuration, manufacturing process, and consumable
power is limited. Power dissipation is determined by the temperature allowed in IC chip (maximum junction temperature) and
thermal resistance of pa ckage (heat di ssip a tion cap abi lity ).
The maximum junction temperature is typically equal to the maximum value in the storage package (heat dissipation capability).
The maximum junction temperature is typically equal to the maximum value in the storage temperatur e range.
Heat generated by consumed power of IC radiates from the mold resin or lead frame of the package.
The parameter which indicates this heat dissip ation cap ability (hardness of heat release) is calle d thermal resistance, represented
by the symbol θj-a[℃/W]. The temperature of IC inside the package can be estimated by this thermal resistance.
Fig.98 (a) shows the model of thermal resistance of the package. Thermal resistance θja, ambient temperature Ta, junction
temperature Tj, and power dissipation Pd can be calculated by the equation below :
θja = (Tj-Ta) / Pd [℃/W] ・・・・・ (Ⅰ)
Derating curve in Fig.98 (b) indicates power that can be consumed by IC with reference to ambient temperature.
Power that can be consumed by IC begins to attenuate at certain ambient temperature. This gradient iis determined by
thermal resistance θja.
Thermal resistance θja depends on chip size, power consumption, package, ambient temperature, package condition, wind
velocity, etc even when the same of package is used.
Thermal reduction curve indicates a reference value measured at a specified condition. Fig99(c)-(f) show a derating curve
for an example of BU7561family, BU7562family, 7541family, 7542family.
Power dissipation of LSI [W]
θja = (Tj-Ta) / Pd [℃/W]
Ta[℃]
Ambient temperature Ta [℃]
周囲温度
パッケージ表面温度
Package surface temperature [℃]
Ta[℃]
LSI
の消費電力
P2
P1
Pd(max)
[W]
θja1
θja2 <θja1
θja2
Tj(max)
0
25125
Ambient temperature Ta [℃]
周囲温度
Ta[℃]
(b) Derating curve
7515010050
BD7561/BD7541
Tj(max)
消費電力
Tj[℃]
P[W]
Fig. 98. Thermal resistance and derating
Chip surface temp er ature Tj [℃]
Power dissipation P [W]
When using the unit above Ta=25[℃], subtract the value above per degree[℃]. Permissible dissipation is the value
when FR4 glass epoxy board 70[mm]×70[mm]×1.6[mm] (cooper foil area below 3[%]) is mounted.
Absolute maximum ratings are the values which indicate the limits,within which the given voltage range can be safely
charged to the terminal.However, it does not guarantee the circuit operation.
2) Applied voltage to the input terminal
For normal circuit operation of voltage comparator, please input voltage for its input terminal within input common mode
voltage VDD+0.3[V].Then, regardless of power supply voltage,VSS-0.3[V] can be applied to inputterminals without
deterioration or destruction of its characteristics.
3) Operating power supply (split power supply/single power supply)
The voltage comparator operates if a given level of voltage is applied bet ween VDD and VSS. Therefore, the operational
amplifier can be operated under single power supply or split power supply.
4) Power dissipation (Pd)
If the IC is used under excessive power dissipation. An increase in the chip temperatur e will cause deterioration of the
radical characteristics of IC. For example, reduction of current capability. Take consideration of the effective power
dissipation andthermal design with a sufficient margin. Pd is reference to the provided power dissipation curve.
5) Short circuits between pins and incorrect mounting
Short circuits between pins and incorrect mounting when mounting the IC on a printed circuits board, take notice of the
direction and positioning of the IC.If IC is mounted erroneously, It may be dama ged. Also, when a foreign object is inserted
between output, between output and VDD terminal or VSS terminal which causes short circuit, the IC may be damaged.
6) Using under strong electromagnetic field
Be careful when using the IC under strong electromagnetic field because it may malfunction.
7) Usage of IC
When stress is applied to the IC through warp of the printed circuit board, The characteristics may fluctuate due to the
piezo effect. Be careful of the warp of the printed circuit board.
8) Testing IC on the set board
When testing IC on the set board, in cases where the capacitor is connected to the low impedance,make sure to discharge
per fabrication because there is a possibility that IC may be damaged by stress.
When removing IC from the set board, it is essential to cut supply voltage.As a countermeasure against the static
electricity, observe proper grounding during fabrication processand take due care when carrying and storage it.
9) The IC destruction caused by capacitive load
The transistors in circuits may be damaged when VDD terminal and VSS terminal is shorted with the charged output
terminal capacitor. When IC is used as a operational amplifier or as an application circuit,where oscillation is not activated
by an output capacitor, the output capacitor must be kept below 0.1[μF] in order to prevent the damage mentioned above.
10) Decupling capacitor
Insert the deculing capacitance between VDD and VSS, for stable operation of operational amplifier.
11) Latch up
Be careful of input vltage that exceed the VDD and VSS. When CMOS device have sometimes occur latch up operation.
And protect the IC from abnormaly noise.
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