Rohm BD71837MWV Design Manual

No. 60AP001E Rev.001

No. 61AN002E Rev.001

May.2018

2017.4

Application Note

2.7V to 5.5V

BD71837MWV

BUCK1 0.9V / 3.6A

i.MX 8M Quad

i.MX 8M QuadLite

i.MX 8M Dual

LDO1 3.3V / 10mA

Power Mux Switch

1.8V/3.3V / 150mA

LPDDR4 Memory

SD Card

USB /

Li-Ion Battery

BUCK2 1.0V / 4.0A BUCK3 1.0V / 2.1A BUCK4 1.0V / 1.0A

LDO2 0.9V / 10mA

LDO7 3.3V / 150mA

BUCK6 3.3V / 3.0A

LDO3 1.8V / 150mA LDO5 1.8V / 300mA

BUCK7 1.8V / 1.5A

LDO4 0.9V / 250mA

LDO6 0.9V / 300mA BUCK5 1.0V / 2.5A BUCK8 1.1V / 3.0A

I2C (slave)

Power Mode

Control Signals

Power

Sequencing

Controller

Die temp

UVLO

32.768kHz Crystal Oscillator Driver

Interrupt

VR Fault

Power On Key

Detection

Power On Key

Figure 1.1 The system power map

Figure 1.2 The package image

Power Management IC designed for “NXP

i.MX 8M Quad”

BD71837MWV Platform Design Guide

1. Introduction

BD71837MWV is a Power Management Integrated Circuit (PMIC) available in 68-QFN package and dedicated to the application powered by 5V input. PMIC includes eight Buck convertors, seven LDOs, one internal load switch and crystal oscillator driver for RTC clock. These functions are designed to support the specific power requirements from NXP i.MX 8M platform to achieve the required performance for cost-sensitive applications. The below figure is the outline of the power map between PMIC and i.MX 8M SoC, showing that all voltage rails required by SoC are satisfied. “BD71837MWV Platform Design Guide” provides the guideline for designing PCB including recommendatio n for the PCB layer stack up, the components placement and the PCB routings.

To reduce the risk that comes from PCB layout or parts placement, the guideline is strongly recommended to be applied to the PCB design.

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Application Note

BD71837MWV Platform Design Guide

No. 61AN002E Rev.001

May.2018

1. Introduction ................................................................................................................................................................................ 1

2. Revision History ......................................................................................................................................................................... 4

3. Features ..................................................................................................................................................................................... 5

3.1. Terminologies ...................................................................................................................................................................... 5

3.2. Reference Documents ........................................................................................................................................................ 5

3.3. PMIC futures ....................................................................................................................................................................... 6

4. General Design Considerations ................................................................................................................................................. 7

4.1. Package Dimension of BD71837MWV ............................................................................................................................... 7

4.2. Pin Configuration ................................................................................................................................................................ 8

4.3. General Stack-up Recommendations ................................................................................................................................. 9

4.4. 6-layer Board Stack-up ....................................................................................................................................................... 9

4.5. Via Guidelines ................................................................................................................................................................... 10

4.6. Placement of PTHs underneath the exposed pad.............................................................................................................. 11

4.7. Outline for PCB layout ...................................................................................................................................................... 12

5. Platform Power Delivery Guidelines ......................................................................................................................................... 18

5.1. Platform Power Delivery ................................................................................................................................................... 18

5.2. General Layout Guideline ................................................................................................................................................. 20

5.2.1. Overall Component Placement .................................................................................................................................. 20

5.2.2. Large Current Loop .................................................................................................................................................... 21

5.2.3. Power GND ................................................................................................................................................................ 22

5.2.4. VSYS (Power supply for BD71837MWV analog circuit) ............................................................................................ 22

5.2.5. Other Signal Pattern Precautions .............................................................................................................................. 22

5.2.6. Feedback Sense Lines .............................................................................................................................................. 22

5.2.7. AGND layout .............................................................................................................................................................. 23

5.3. BUCK Convertors ............................................................................................................................................................. 24

5.3.1. BUCK1 (VDD_SoC) ................................................................................................................................................... 24

5.3.1.1. Schematic Example ............................................................................................................................................... 24

5.3.1.2. Schematic checklist ................................................................................................................................................ 24

5.3.1.3. Parts placement for each decoupling capacitor ...................................................................................................... 25

5.3.2. BUCK2 (VDD_ARM) .................................................................................................................................................. 25

5.3.2.1. Schematic Example ............................................................................................................................................... 25

5.3.2.2. Schematic checklist ................................................................................................................................................ 26

5.3.2.3. Layout Example ..................................................................................................................................................... 26

5.3.3. BUCK3 (VDD_GPU) .................................................................................................................................................. 27

5.3.3.1. Schematic Example ............................................................................................................................................... 27

5.3.3.2. Schematic Checklist ............................................................................................................................................... 27

5.3.3.3. Layout Example ..................................................................................................................................................... 28

5.3.4. BUCK4 (VDD_VPU) .................................................................................................................................................. 29

5.3.4.1. Schematic Example ............................................................................................................................................... 29

5.3.4.2. Schematic Checklist ............................................................................................................................................... 29

5.3.4.3. Layout Example ..................................................................................................................................................... 30

5.3.5. BUCK5 (VDD_DRAM) ............................................................................................................................................... 30

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5.3.5.1. Schematic Example ............................................................................................................................................... 30

5.3.5.2. Schematic Checklist ............................................................................................................................................... 31

5.3.5.3. Layout Example ..................................................................................................................................................... 32

5.3.6. BUCK6 (NVCC_3P3) ................................................................................................................................................. 32

5.3.6.1. Schematic Example ............................................................................................................................................... 32

5.3.6.2. Schematic Checklist ............................................................................................................................................... 33

5.3.6.3. Layout Example ..................................................................................................................................................... 33

5.3.7. BUCK7 (NVCC_1V8) ................................................................................................................................................. 34

5.3.7.1. Schematic Example ............................................................................................................................................... 34

5.3.7.2. Schematic Checklist ............................................................................................................................................... 34

5.3.7.3. Layout Example ..................................................................................................................................................... 35

5.3.8. BUCK8 (NVCC_DRAM) ............................................................................................................................................. 36

5.3.8.1. Schematic Example ............................................................................................................................................... 36

5.3.8.2. Schematic Checklist ............................................................................................................................................... 36

5.3.8.3. Layout Example ..................................................................................................................................................... 37

5.4. LDOs ................................................................................................................................................................................. 38

5.4.1. LDO1 (NVCC_SNVS) ................................................................................................................................................ 38

5.4.2. LDO2 (VDD_SNVS) ................................................................................................................................................... 38

5.4.3. LDO3 (VDDA_1P8/VDDA_DRAM) ............................................................................................................................ 38

5.4.4. LDO4 (VDDA_0P9) .................................................................................................................................................... 38

5.4.5. LDO5 (1P8_PHY) ...................................................................................................................................................... 38

5.4.6. LDO6 (0P9_PHY) ...................................................................................................................................................... 38

5.4.7. LDO7 (3P3_PHY) ...................................................................................................................................................... 38

5.4.8. Schematic Examples ................................................................................................................................................. 39

5.4.8.1. Schematic Checklist ............................................................................................................................................... 39

5.5. Load SW ........................................................................................................................................................................... 41

5.5.1. MUXSW (NVCC_SD2)............................................................................................................................................... 41

5.5.1.1. Schematic Examples .............................................................................................................................................. 41

5.5.1.2. Schematic Checklist ............................................................................................................................................... 41

5.6. Crystal Oscillator Driver .................................................................................................................................................... 42

5.6.1. XIN / XOUT / C32K_OUT .......................................................................................................................................... 42

5.6.1.1. Schematic Examples .............................................................................................................................................. 42

5.6.1.2. Schematic Checklist ............................................................................................................................................... 42

5.6.1.3. Layout Example ..................................................................................................................................................... 43

5.7. Interfaces .......................................................................................................................................................................... 44

5.7.1. I2C ................................................................................................ ............................................................................. 44

5.7.2. System Control – Reset, Power, and Control Signals ................................................................................................ 45

5.7.3. MISC .......................................................................................................................................................................... 46

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Application Note

BD71837MWV Platform Design Guide

No. 61AN002E Rev.001

May.2018

Revision Number

Description

Revision Date

001

Initial release

May. 1st, 2018

2. Revision History

Table 2.1 Revision History

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Application Note

BD71837MWV Platform Design Guide

No. 61AN002E Rev.001

May.2018

Term

Definition

BOM

Bill Of Materials

PMIC

Power Management Integrated Circuit

FET

Field Effect Transistor

I2C

Inter-Integrated Circuit

IRQ

Interrupt ReQuest

LDO

Low Drop-Out Regulator

OCP

Over Current Protection

OVP

Over Voltage Protection

SoC

System-On-a-Chip

Document

BD71837MWV Datasheet Rev.001.pdf

BD71837MWV Reference Schematic Rev.001.pdf

BD71837MWV Reference BOM Rev001.xlsx

BD71837MWV Reference Layout Rev.001.brd

BD71837MWV Schematic Checklist Rev001.xlsx

3. Features

3.1. Terminologies

3.2. Reference Documents

Table 3.1 Acronyms, Conventions and Terminologies

Table 3.2 Reference Documents

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3.3. PMIC futures

BD71837MWV supply the power required by SoC and peripheral devices for NXP i.MX 8M platform. Once PMIC powered up, it can be controlled by I2C interface to determine the internal register settings. The followings explain the features incorporated in the IC.

Voltage Rails

■ 8ch low power consumption Buck Convertors with Integrated BUCK FETs

 Buck1: 0.7V – 1.3V / 10mV step (DVS), I  Buck2: 0.7V – 1.3V / 10mV step (DVS), I  Buck3: 0.7V – 1.3V / 10mV step (DVS), I  Buck4: 0.7V – 1.3V / 10mV step (DVS), I  Buck5: 0.7V – 1.35V / 8 steps, I  Buck6: 3.0V – 3.3V / 100mV step, I  Buck7: 1.6V – 2.0V / 8 steps, I  Buck8: 0.8V – 1.4V / 10mV step, I

OMAX

= 2.5A

OMAX

= 1.5A

OMAX

= 3.0A

= 3.6A = 4.0A

= 2.1A = 1.0A

■ 7ch LDO Regulator

 LDO1: 3.0V – 3.3V / 1.6V – 1.9V, I  LDO2: 0.9V / 0.8V, I  LDO3: 1.8V – 3.3V, I  LDO4: 0.9V – 1.8V, I  LDO5: 1.8V – 3.3V, I  LDO6: 0.9V – 1.8V, I  LDO7: 1.8V – 3.3V, I

OMAX

= 10mA

= 300mA = 250mA = 300mA = 300mA = 150mA

OMAX

= 10mA

■ 1ch Internal General Switch

 Mux Switch: 1.8V/3.3V, I

OMAX

= 150mA

Serial Interface

 I2C interface provides access to configuration registers.

Crystal Oscillator Driver

 32.768kHz Crystal Oscillator Driver is included.

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Application Note

BD71837MWV Platform Design Guide

No. 61AN002E Rev.001

May.2018

BD7 1837

ROHM

LOT Number

Part Number Marking

4. General Design Considerations

This chapter provides general PCB design guidelines such as BD71837MWV general parts placement.

4.1. Package Dimension of BD71837MWV

Figure 4.1 The package dimension of BD71837MWV

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May.2018

LDO4_FB

LDO4_VOUT

VSYS2

WDOG_B

RTC_RESET_B

BUCK8_FB

BUCK8_VIN

BUCK8_VIN BUCK8_LX

BUCK8_LX

BUCK7_LX

BUCK7_VIN BUCK7_FB

IRQ_B

POR_B

C32K_OUT

DVDD

(**)EXP-PAD

LDO3_FB

VIN_3P3

LDO3_VOUT

VSYS3

BUCK4_FB

BUCK4_VIN

BUCK4_LX

BUCK3_LX

BUCK3_VIN

BUCK3_FB

AGND

INTLDO1P5

LDO7_VOUT

VSYS1

XIN

XOUT

454443424140515049484746SDA33SCL32PMIC_ON_REQ

PMIC_STBY_REQ

3938373635

BUCK1_LX

BUCK2_LX

BUCK1_FB

BUCK1_VIN

BUCK2_FB

PWRON_B

LDO1_VOUT

BUCK2_LX

BUCK2_VIN

LDO2_VOUT

12345678151617111213145591056

BUCK6_VIN

BUCK6_LX

LDO5_VOUT

(*)EXP-PAD

(PGND)

1Pin Mark

VIN_1P8_2

MUXSW_VOUT

BUCK6_FB

(**)EXP-PAD

MUXSW_VOUT

BUCK5_VIN

BUCK5_FB

BUCK6_LX

BUCK5_LX

VIN_1P8_1

LDO6_VOUT

SD_VSELECT

4.2. Pin Configuration

The pin configuration of BD71837MWV is designed and it will result in the effective routings between PMIC and SoC, memory device and other components.

Note: (*) EXP-PAD is the power GND for PMIC so it should be soldered to GND plane.

(**) EXP-PAD assigned to 4 corners are also the same potentials with (*) EXP-PAD.

Figure 4.2 BD71837MWV pin configuration

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Application Note

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Figure 4.3 6-layers PCB stack-up

4.3. General Stack-up Recommendations

Type-3 and 6 layers PCB technology are used for BD71837MWV ROHM’s EVM. The following general stack-up is strongly recommended to be applied to all the routings on the PCB.

 Surface plane layers are recommended to apply 1.9 Mils thick copper.  Internal plane layers are recommended to apply 1.2 Mils thick copper.  It is recommended I2C signals to have the reference versus solid planes over the length of their routing and not to

cross plane splits. Ground should be the ideal reference.

 The extra area in each layers should be filled with as much ground or other power rails as possible.

There should not be any large free areas with no metal for each layer because of the improvement for heat dissipation. Large metal area also reduces stray resistance and inductance.

4.4. 6-layer Board Stack-up

BD71837MWV ROHM’s EVM uses Type 3 PCB technology and Figure 4.3 shows the 6-layer PCB stack-up.

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Application Note

BD71837MWV Platform Design Guide

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May.2018

Via type

Hole size

Pad size

Anti-Pad size

Plated through-hole (PTH)

12 mils

24 mils

32 mils

Hole size

Pad size

Anti-Pad size

Figure 4.4 The image of PTH vias

4.5. Via Guidelines

This section explains proper via-drill, pad, and anti-pad size.

Note: Improper drill, pad, and anti-pad size may cause some troubles on the PCB cost, reliability, manufacturability, and electrical characteristics.

Type-3 PCB technology employs plated through-hole (PTH) vias for breakout routing. The dimension of PTH vias may vary as necessary. Table 2.1 shows the recommended via dimension used for the breakout areas of BD71837MWV. Figure 4.4 shows the image of PTH vias.

Table 4.1 Dimension example for PTH

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500μm or more

Current

flow

Exposed pad

Figure 4.5 The clearance between PTH and the exposed pad

4.6. Placement of PTHs underneath the exposed pad

When the distance between the edge of metal mask of the exposed pad and PTH is close, the solder may get on the resist then the PTH and exposed pad of BD71837MWV will be shorted. To avoid the soldering issue, it is highly recommended to keep the positons of PTHs away from the edge of the exposed pad by 500μm or more, and PTHs should be placed not to disrupt the current flows between each GND of the output capacitors and the exposed pad.

Note The spaces for the current flows between GNDs of each output capacitor and exposed pad for PMIC PGND should be ensured. So it is recommended that the numbers of PTHs disturbing the current flows should be secured.

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BUCK8

BUCK5

BUCK1

MUXSW

BUCK7

BUCK2

BUCK3

BUCK4

BUCK6

i.MX 8M

Top layer is used as power trace for each VR.

It’s better to secure the power traces with enough width to

relief the effect of the parasitic impedance.

Figure 4.6 BD71837MWV Reference Board Outline (Top Layer)

4.7. Outline for PCB layout

For understanding the outline of ROHM’s reference layout, the layout data for Layer 1(Top Layer) to 6 (Bottom layer) are shown in Figure 4.6 to Figure 4.11. The layout is designed, supposing the position of the SoC as Figure 4.6. (1st pin of SoC is positioned at lower right.)

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May.2018

GND

Layer 2 is used as power GND. It’s better to secure the wide plane for large switching currents. The parasitic impedance between PGND and each capacitor should be as low as possible.

Figure 4.7 BD71837MWV Reference Board Outline (Layer 2)

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May.2018

VSYS

Layer 3 is used as VSYS power (Input for each VR).

It’s better to secure the wide plane for large input currents

which happens between input source and input capacitors.

Figure 4.8 BD71837MWV Reference Board Outline (Layer 3)

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Layer 4 is used as power traces for each VR.

It’s better to secure the enough width to relief the effect of

the parasitic impedance.

Figure 4.9 BD71837MWV Reference Board Outline (Layer 4)

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Rohm BD71837MWV Design Manual

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