Power Management IC Series for Automotive Body Control
Antenna Driver
BD6934FV
●Description
This 1ch half-bridje pre-driver for 125kHZ drive with a built-in oscillation circuit is equipped the driving current adjustment
function.
●Features
1)Pre-driver for driving MOS-FET
2)4MHz ceramic resonator or external pulse are available
3)Driving current adjustment function (Dependence on power supply voltage)
4)Stand-by current 0μA(typ.)
5)Built-in the resistance between Gate to Source of FET
6)Built-in FET synchro on protect
7)Built-in thermal shutdown
8)Built-in under voltage lockout protection(UVLO)
●Applications
Usable in driving low frequency , the likes of TPMS and smart entry system.
●Absolute Maximum Ratings(Ta=25℃)
Parameter Symbol Rating Unit
Supply voltage Vcc1,Vcc2 12 V
Power dissipation Pd 562 * mW
Operating temperature range T
Storage temperature range T
Junction temperature T
*Reduced by 4.496mW/℃,when mounted on a glass epoxy board (70mm×70mm×1.6mm)
●Operating range
Supply voltage Vcc1,Vcc2 3.5~8 V
RP,RN voltage Vrp,Vrn VCC2 V
XOUT,RT,CT voltage Vxout,Vrt,Vct VCC1 V
Input voltage VIN -0.3~VCC1 V
*This product described in this specification isn’t judged whether it applies to COCOM regulations.
It should not be exported without authorization from the appropriate government.
*This product is not designed for protection against radioactive rays.
Status of this document
*
The Japanese version of this document is the formal specification.
A customer may use this translation version only for a reference to help reading the formal version.
If there are any differences in translation version of this document, formal version takes priority.
1 OUTN Nch FET GATE connection
2 N.C. N.C.
3 OUTP Pch FET GATE connection
4 RP For pull-up resistance of Pch FET Gate
5 VCC2 Power VCC terminal
6 VCC1 Signal VCC terminal
7 N.C. N.C.
8 RN For pull – down resistance of Nch FET Gate
9 XIN Resonator connection
10 XOUT Resonator connection
11 CT Capacitor connection for triangular wave generation
12 RT Capacitor connection for triangular wave generation
13 SEL Input terminal for mode selection(Resonator mode:L,External pulse mode:H)
14 IN Input terminal (Stand-by:L, Enable:H)
15 GND Signal GND terminal
16 PGND Power GND terminal
●Operating explanation
Driving current adjustment function.
This IC control the duty of output pulse in response to supply voltage(Vcc).
This function is allowed to control driving current and adjust the arrival range of radio frequency. The relationship
between supply voltage(Vcc) and output(OUTN) is as shown in the following figure.
This data is typical , refer to the electrical characteristics in regard to variation.
Duty
(%)
49
Technical Note
External FET
Connect PchMOS to OUTP and Nch MOS to OUTN
Vds>VCC, Vgs>VCC, Allowable current > Output current
There is a possibility that upper and lower FET turn on at the same time. It is recommended to use 1000pF or smaller
at input capacitor of external FET. However , these characteristics change in the layout pattern and parts variation and
so on. Make evaluations with using board in mass production.
Oscillation precision and condition
The oscillation precision depends on the condition of ceramic resonator. This IC is evaluated with the ceramic
resonator (Product No.CSTCR4M00G55B-R0) of MURATA manufacturing. In the range of Vcc 2.2~2.7V, this IC
stops its oscillation without disenabling the ceramic resonator.
OPERATING NOTES
●
1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result
in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such
damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a specialmode
where the absolute maximum ratings may be exceeded is anticipated.
2) GND potential
Ensure a minimum GND pin potential in all operating conditions.
3) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4) Pin short and mistake mounting
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improp er mounting may result
in damage to the IC. Shorts between output pins and the power supply and GND pins caused by the presence of a foreign
object may result in damage to the IC. Ensure a minimum GND pin potential in all operating conditions.
5) Actions in strong magnetic field
Keep in mind that the IC may malfunction in strong magnetic fields.
6) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance su bjects the IC to
stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting
it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure, and use similar caution when transporting or storing the IC.
7) This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a
variety of parasitic elements. For example, when the resistors and transistors are connected to the pins as sho wn in the
following figure,
The P/N junction functions as a parasitic diode when GND > Pin A for the resistor or GND > Pin B for the transistor(NPN).
Similarly, when GND > Pin B for the transistor (NPN), the parasitic diode described above combines with the N layer of
other adjacent elements to operate as a parasitic NPN transistor.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable
result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as
IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will
trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (P substrate) voltage
to input pins. Keep in mind that the IC may malfunction in strong magnetic fields.
(Pin A)
P+
N
P
Resistor
N
P
GND
P+
N
Parasitic elements
(Pin B)
Parasitic elements
or Transistors
C
P+
N
B
E
N
P
N
P substrate
GND
(Pin B)
C
B
E
GND
N
(Pin A)
Parasitic elements or
Parasitic elements
8) Ground patterns
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing
a single ground point at the application's reference point s o that the pattern wiring resistance and voltage variations c aused
by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern
of any external parts, either.
9) Thermal shutdown circuit (TSD)
This IC incorporates a built-in TSD circuit for the protection from thermal destruction. T he IC should be used within the
specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power
dissipation limits, the attendant rise in the junction temperature (Tj) will trigger the TSD circuit to turn off all output po wer
elements. The circuit automatically resets once the junction temperature (Tj) drops. Operation of the TSD circuit presumes
that the IC's absolute maximum ratings have been exceeded. Application designs should never make use of the TSD
circuit.
10) External parts
Driving current adjustment function in use low accuracy parts (Especially, RT terminal connection resistance, CT terminal
connection capacitor and resonator ) may malfunction.
The external parts use highly accuracy, and be careful additional impedance and capacitor for wiring pattern.
11)RP, RN terminal
The resistance is built in between OUTP and RP, and OUTN and RN to turn off external MOS - FET in stand - by.
Please wire with RP=VCC2 and RN =PGND.
Improper wiring may result in damage for the penetration current.
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