ROHM BD64550EFV Technical data

A
Motor Drivers for Printers
BD64550EFV
No.10016EAT03
Description
This is 1-chip system motor driver integrating 2-channel H-bridge driver, step-down switching regulator with built-in power DMOS, series regulator and reset output.
Features
1) Low-on resistance output H-bridge driver (2-channel)
2) Constant-current chopping drive H-bridge driver
3) Switching regulator with built-in P-channel power DMOS FET
4) Soft start function: 23.6 ms (Typ.)
5) Reset release timer: 80 ms (Typ.)
6) 16 bit serial interface
7) Logic input interface (serial/parallel changeable)
8) Ultra thin type high heat dissipation HTSSOP-B40 package
9) Overcurrent protection in H-bridge driver block
10) Input voltage low voltage protection in H-bridge driver block
11) Overcurrent protection in switching regulator block
12) Output overvoltage protection in switching regulator block
13) Output low voltage protection in switching regulator block
14) Thermal shutdown
Applications
Inkjet printer, photo printer, etc.
Absolute Maximum Ratings (Ta=25℃)
Parameter Symbol Ratings Unit
VM applied voltage
Logic input voltage
RIN applied voltage
RNF voltage
Power dissipation
Operating temperature range
Storage temperature range
Junction temperature
Motor driver output current (peak 500 ns)
Motor driver output current (DC)
Switching regulator output current (DC)
Series regulator output current (DC)
* Reduced by 12.8 mW/ over 25 , when mounted on a glass epoxy board (70 mm x 70 mm x 1.6 mm). ** Must not exceed Pd or ASO.
I
omax
I
VM
V
V
Pd
T
T
T
(peak)
omax
I
omax
I
omax
V
L
RIN
RNF
OPR
STG
jmax
(DC)
40 V
-0.4 ~ 5.5 V
5.5 V
0.5 V
1600* mW
-25 ~ +85
-55 ~ +150 150
8.0 A
2.5** A
0.5 A
0.25 A
Operating Conditions
Parameter Symbol Limit Unit
VM operating power supply voltage range VM 7 ~ 36 V
SCLK max. operating frequency F
Switching regulator output voltage range V
20 MHz
SCLK
3 ~ 5 V
swreg
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© 2010 ROHM Co., Ltd. All rights reserved.
1/16
2010.06 - Rev.
BD64550EFV
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Technical Note
Electrical Characteristics (Unless otherwise specified,Ta=25℃,VM=24V)
Parameter Symbol
Min. Typ. Max.
Limit
Unit Conditions
Overall
VM current 1 I
VM current 2 I
- - 8 mA VM=7V
VM1
- - 12 mA VM=24V
VM2
H-bridge 1
Output on resistance (source side)) R
Output on resistance (sinking side) R
Output leak current I
Built-in diode forward direction voltage (source side)
Built-in diode forward direction voltage (sinking side)
- 0.6 0.78 Ω Io=1A
ONH1
- 0.4 0.52 Ω Io=1A
ONL1
0 - 10 µA VM=36V
LEAK1
V
FH1
V
0.6 0.9 1.2 V Io=1A
FL1
0.6 0.9 1.2 V Io=1A
H-bridge 2
Output on resistance (source side) R
Output on resistance (sinking side) R
Output leak current I
Built-in diode forward direction voltage (source side)
Built-in diode forward direction voltage (sinking side)
- 0.7 0.91 Ω Io=1A
ONH2
- 0.5 0.65 Ω Io=1A
ONL2
0 - 10 µA VM=36V
LEAK2
V
FH2
V
0.6 0.9 1.2 V Io=1A
FL2
0.6 0.9 1.2 V Io=1A
Current control
VREF voltage range V
VREF pin outflow current I
RNF pin outflow current I
RNFS pin outflow current I
VREF-RNFS offset voltage V
0.8 - 3.5 V
REF
- 0 1 µA
REF
5 15 30 µA
RNF
- 0 1 µA
RNFS
OFFSET
-15 0 15 mV VREF=2V
Control logic
High input voltage V
Low input voltage V
2.0 - 5.5 V
INH
0 - 0.8 V
INL
Input current IIN 21 33 45 µA Input voltage=3.3V
Switching power source
DSEN threshold voltage V
Output on resistance R
Leak current I
DUTY_MAX value D
SWBIAS
SWON
SWLEAK
MAX
0.873 0.9 0.927 V
- 0.8 1.04 Ω At Io=250mA
0 - 10 µA VM=36V
- 92 - %
Clock frequency FSW 130 200 270 kHz
DSEN pin outflow current I
- 0 1 µA
DSEN
Series power source
Output voltage V
Leak current I
1.425 1.5 1.575 V At Io=70mA
SOUT
0 - 10 µA
SLEAK
RESET pin
Output voltage V
Leak current I
High VM threshold voltage V
Low VM threshold voltage V
High motor UVLO voltage V
Low motor UVLO voltage V
Reset delay time T
0 - 0.2 V I
RSTL
RSTLEAK
MPORH
MPORL
13.5 15 16.5 V Off motor only
MMTH
12.5 14 15.5 V
MMTL
50 80 110 ms
POR
0 - 10 µA
6.3 6.5 6.7 V VM at power on
5.9 6.1 6.3 V VM at power off
DRAIN
=1mA
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© 2010 ROHM Co., Ltd. All rights reserved.
2/16
2010.06 - Rev.
BD64550EFV
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]
5
Technical Note
Reference Data
6
25℃
85℃
8.00
1.2
4
2
Ci rcui t current :Ic c[m A]
-25℃
6.00
4.00
CLK8M [MHz]
2.00
0.8
Vref [V]
0.4
0
0 8 16 24 32
Supply voltag e :VM[ V]
0.00
-25 0 25 50 75
Temper ature [℃ ]
0.0
-25 0 25 50 75 Temper atur e (℃)
Fig.1 VM Current Fig.2 Internal Reference Clock
1.4
1.2
1.0
0.8
85
25
0.6
0.4
Output H voltage :VO H[V ]
0.2
0.0 0 400 800 1200 1600 2000
Supply curr ent :Io[mA]
-25
Fig.4 OUT1 High Output Voltage
(source side)
(VM=24V)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
Output L v oltage :VOL[V]
0.2
0.1
0.0 0 400 800 1200 1600 2000
25
Supply cur rent :Io[mA]
85
-25
Fig.5 OUT1 Low Output Voltage
(sinking side)
Fig.3 Temperature dependence of
Internal Standard Voltage (VM=24V)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
Output H voltage :VOH[ V]
0.2
0.0 0 400 800 1200 1600 2000
Supply curr ent :Io[mA]
85
25
-25
Fig.6 OUT2 High Output Voltage
(source side)
1.4
1.2
1.0
0.8
0.6
0.4
Output L v olt age :VOL[V]
0.2
0.0 0 400 800 1200 1600 2000
Supply cur rent :Io[ mA]
85
25
Fig.7 OUT2 Low Output Voltage
(sinking side)
-25
500
400
85
300
200
Swout vol tage :R sw[m V
100
0
0 100 200 300 400 500
Supply cur rent :Io[ mA]
2
-25
Fig.8 Switching Regulator High Output
Voltage
100
80
60
40
Output effect:[%]
20
0
0 100 200 300 400 500
Output current :[mA]
VM= 7V
VM =24V
Fig.9 Switching Regulator Efficiency
(Ta=25)
2.0
1.8
1.6
1.4
Rout v oltage:[V]
1.2
1.0 0 50 100 150 200 250
Supply cur rent :[mA]
Fig.10 Series Regulator Load Regulation
(VM=24V, Ta=25℃)
4
3
2
1
Swout vol tage :SV[ mV]
0
02468
Supply v oltage :VM[V]
-25
25
85
Fig.11 Reset Output
(Pull up to switching regulator at 10kΩ)
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© 2010 ROHM Co., Ltd. All rights reserved.
3/16
2010.06 - Rev.
BD64550EFV
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A
A
Technical Note
Block Diagram, Application Circuit Diagram, and Pin Function
0.2
(0.04~0.35)
Same as RNF1
STROBE(DC1E
From VDCDCOUT
(0.1µF~2.2µF)
VM2
VM2
OUT2P
OUT2M
RNF2
RNF2
RNF2S VREF2
SELECT
DC2P
SCLK(DC1P)
DC2E
SDAT
GND
RIN
ROUT
1µF
VM1
1/10
8
9
7
2
3
4 5
20
31
28
40
21
10
12
18
VM1
OUT1P
OUT1M
RNF1
RNF1
RNF1S VREF1
VM3
RESET
PGND
DGND
VM4
SWOUT
220µH
100µF
DSEN
0.2 (0.04~0.35)
300µF (220µF~470µF)
VDCDCOUT
2.7k
4700pF
1k
32
33
39
34
37
38
36
1/10
19
22
24
27
Selector
23
25
)
26
29
16
14
Pre
driver
CONTROL LOGIC
Serial
Control
BG BG
Pre
driver
POWER
MONITOR
RESET
BGTSD UVLOOSC
DRIVER REG
Be sure to use VM1,VM2.VM3 and VM4 by short-circuit.
0.2Ω(0.04Ω~0.35Ω) Io1=(VREF1/10)(1/RNF1S) See P.9.
N.C.
1
OUT1M
2
RNF1
3
RNF1
4
RNF1S
5
N.C.
6
OUT1P
7
8
VM1
VM1
9
VM4
10
N.C.
11
SWOUT
12
N.C.
13
ROUT
14
N.C.
15
RIN
16
N.C.
17
DSEN
18
VREF2
19
VREF1
20
The figure on the left-hand side shows optimum recommended values. See P.10 for setting.
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Fig.12 Block Diagram and Application Circuit Diagram Fig.13 Pin Assignment Diagram
No.
Pin
name
Function No.
Pin
name
Function
1 NC Non Connection 21 DGND Digital GND
2 OUT1M H-bridge output pin 1M 22 SELECT Input pin select pin
3 RNF1 Output current detection pin 1 23 DC2E H-bridge 2 side enable input pin
4 RNF1 Output current detection pin 1 24 DC2P H-bridge 2 side phase pin
5 RNF1S Output current detection input pin
6 NC Non Connection
25 STROBE
Serial port strobe input pin / H-bridge 1 side enable pin
7 OUT1P H-bridge output pin 1P 26 SDATA Serial port data input pin
8 VM1 Motor power supply pin
9 VM1 Motor power supply pin
27 SCLK
Serial port clock input pin / H-bridge 1 side phase input pin
10 VM4 Switching regulator power supply pin 28 RESET Reset signal output pin
11 NC Non Connection 29 AGND ANALOG GND
12 SWOUT Switching regulator output pin 30 NC Non Connection
13 NC Non Connection 31 VM3 Power supply pin
14 ROUT Series regulator output pin 32 VM2 Motor power supply pin
15 NC Non Connection 33 VM2 Motor power supply pin
16 RIN Series regulator power supply pin 34 OUT2M H-bridge output pin 2M
17 NC Non Connection 35 NC Non Connection
18 DSEN Switching regulator voltage sense pin 36 RNF2S Output current detection input pin
19 VREF2 Reference voltage input pin 37 RNF2 Output current detection pin 2
20 VREF1 Reference voltage input pin 38 RNF2 Output current detection pin 2
39 OUT2P H-bridge output pin 2P
40 PGND POWER GND
* Precaution regarding VM pin If you use VM1, VM2, VM3 and VM4 not by short-circuit, they may be destroyed. Be sure to use them by short-circuit. And be sure to set up a bypass capacitor (220µF to 470µF) closer to VM3 pin as much as possible.
PGND
OUT2P
RNF2
RNF2
RNF2S
N.C.
OUT2M
VM2
VM2
VM3
N.C.
AGND
RESET
SCLK
SDATA
STROBE
DC2P
DC2E
SELECT
DGND
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4/16
2010.06 - Rev.
BD64550EFV
A
Pin selection function
Either serial control or external PWM control can be selected for motor control type with SELECT pin (pin 22).
SELECT Output state
L Serial input mode
H External PWM control mode
STROBE/DC1E(25pin)
SDATA(26pin)
SCLK/DC1P(27pin)
DC2P(24pin)
DC2E(23pin)
ENA PHA
Internal shift register
SEL
SEL
Serial
SEL
Serial
SEL
Serial
SELECT(22pin)
Fig.14 Serial Input Block Diagram
The input/output logic at SELECT = H is as follows.
DC1E/DC2E Output state
L Open
H ACTIVE
DC1P/DC2P OUTP OUTM
L SINK SOURCE
H SOURCE SINK
Procedure of DC motor drive by external PWM control
1) Serial setting Set the serial by SELECT pin = L. (WORD_S and WORD_D setting)
WORD_S (see P.7) is a drive parameter for setting OFF_TIME, BLANK TIME etc. WORD_D (see P.7) is for drive setting to set drive mode of each H-bridge.
When setting WORD_D (see P.7), make sure that ENABLE signal (ENABLE_1ENABLE_2) of serial bit is L. If ENABLE signal is H, the motor may operate. Input of DC2P pin can be either H or L.
2) External PWM drive mode switch Set external PWM drive mode by SELECT pin = H. Switch by DC1E (STROBE)/CD2E pin = L when switching SELECT pin.
3) Drive PHASE, ENABLE pin input signal (DC1E/DC1P/DC2E/DC2P) drives in external PWM mode.
Technical Note
OUTPUT
Control
Logic
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© 2010 ROHM Co., Ltd. All rights reserved.
5/16
2010.06 - Rev.
BD64550EFV
A
A
Technical Note
Serial interface
16-bit 3-linear type serial interface (SDATA (pin 26), SCLK (pin 27), STROBE (pin 25)) is provided to set the operation and the value of current limit. Data are sent to the internal shift register by falling edge of SCLK pin in the area L of STROBE pin. Data of shift register are written in an appropriate address of internal memory of 2*15 bits by rising edge of STROBE pin according to address data of D15.The input order of serial data is from D0 to D15.
Address data
D15 Word select
0 WORD_S
1 WORD_D
Memory data allocation
BIT WORD_S Default WORD_D Default
D0 Rohm_Reserve[2] 0 Rohm_Reserve[11] 0
D1 Rohm_Reserve[1] 0 Rohm_Reserve[10] 0
D2 Rohm_Reserve[0] 0 Rohm_Reserve[9] 0
D3 OFF TIME_2[2] 0 Rohm_Reserve[8] 0
D4 OFF TIME_2[1] 0 Rohm_Reserve[7] 0
D5 OFF TIME_2[0] 0 Rohm_Reserve[6] 0
D6 BLANK TIME_2[1] 0 Rohm_Reserve[5] 0
D7 BLANK TIME_2[0] 0 Rohm_Reserve[4] 0
D8 OFF TIME_1[2] 0 Rohm_Reserve[3] 0
D9 OFF TIME_1[1] 0 PWM_MODE_2 0
D10 OFF TIME_1[0] 0 S_PHASE_2 0
D11 BLANK TIME_1[1] 0 S_ENABLE_2 0
D12 BLANK TIME_1[0] 0 PWM_MODE_1 0
D13 MASK SELECT 0 S_PHASE_1 0
D14 SWOFF 0 S_ENABLE_1 0
The timing of serial report writing is shown in the right figure. And the minimum timing of each is as follows:
ASDATA setup time・・・・・・・・・・・・・・・・・・・ 10nsec BSDATA hold time・・・・・・・・・・・・・・・・・・・・ 10nsec CSetup STROBE to SCLK falling edge・・ 50nsec DSCLK low pulse width・・・・・・・・・・・・・・・・ 25nsec ESCLK High pulse width・・・・・・・・・・・・・・・ 25nsec FSetup SCLK falling edge to STROBE・・・ 25nsec GSTROBE pulse width・・・・・・・・・・・・・・・・ 50nsec HSetup RESET to SCLK Rising・・・・・・・・・ 50µsec
H
RESET
STROBE
SCLK
B
D0
D1
D15
CGF E D
RESET signal is an internal RESET signal and generated inside IC at the same timing of external RESET output. STROBE, SCLK and SDATA signals are input signals through external ASIC.
Fig.15 Serial Signal Input Timing
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6/16
2010.06 - Rev.
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