ROHM BD6095GUL Technical data

A

LED Drivers for LCD Backlights

Mulitifunction Backlight LED Driver
for Small LCD Panels (Charge Pump Type)

BD6095GUL,BD6095GU

●Description

BD6095GUL/BD6095GU is “Intelligent LED Driver” that is the most suitable for the cellular phone.
It has many functions that are needed to "the upper side" of the cellular phone.
It has ALC function, that is “Low Power Consumption System” realized.
It has “Contents Adaptive Interface” (External PWM control), that is “Low Power Consumption System” realized.
It adopts the very thin CSP package that is the most suitable for the slim phone.

●Features

1) Total 5LEDs driver for LCD Backlight
It can set maximum 25.6mA /ch by 128steps (Current DAC) for LCD Display.
3LEDs(LED1~LED3) are same controlled.
Another 2LEDs(LED4~5) can be independent controlled. (Enable and Current setting)
2LEDs(LED4~5) can be attributed to “Main Group”.
“Main Group” can be controlled by Auto Luminous Control (ALC) system.
“Main Group” can be controlled by external PWM signal.

2) 1LED driver for Flash/Torch
It can set maximum 120mA for Flash LED Driver.
It has Flash mode and Torch mode, there can be changed by external pin or register.

3) Auto Luminous Control (ALC)
Main backlight can be controlled by ambient brightness.
Photo Diode, Photo Transistor, Photo IC(Linear/Logarithm) can be connected.
Bias source for ambient light sensor, gain and offset adjustment are built in.
LED driver current as ambient level can be customized.

4) 2ch Series Regulator (LDO)
It has selectable output voltage by the register.
LDO1,LDO2 : Iomax=150mA

5) Charge Pump DC/DC for LED driver
It has x1/x1.33/x1.5/x2 mode that will be selected automatically.
Soft start
Over voltage protection (Auto-return type)
Over current protection (Auto-return type)

6) Thermal shutdown (Auto-return type)

7) I2C BUS FS mode (max 400kHz)

8) VCSP50L3 (3.75mm

9) VCSP85H3 (3.75mm

*This chip is not designed to protect itself against radioactive rays.
*This material may be changed on its way to designing.
*This material is not the official specification.

●Absolute Maximum Ratings (Ta=25 oC)

functions

2

, 0.55mmt max) Small and thin CSP package (BD6095GUL)

2

, 1.0mmt max) Small and thin CSP package (BD6095GU)

No.11040EAT31

Parameter Symbol Ratings Unit

Maximum voltage VMAX 7 V

Power Dissipation Pd 1500 mW

Operating Temperature Range Topr -35 ~ +85

Storage Temperature Range Tstg -55 ~ +150

note)Power dissipation deleting is 12.0mW/ oC, when it’s used in over 25 oC. (It’s deleting is on the board that is ROHM’s standard)

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Technical Note

●Operating conditions (VBAT≥VIO, Ta=-35~85 oC)

Parameter Symbol Ratrings Unit

VBAT input voltage VBAT 2.7~5.5 V

VIO pin voltage VIO 1.65~3.3 V

●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VIO=1.8V)

Parameter Symbol

Min. Typ. Max.

Limits

Unit Condition

【Circuit Current】

VBAT Circuit current 1 IBAT1 - 0.1 1.0 μA RESETB=0V, VIO=0V

VBAT Circuit current 2 IBAT2 - 0.5 3.0 μA RESETB=0V, VIO=1.8V

VBAT Circuit current 3 IBAT3 - 90 150 μA

VBAT Circuit current 4 IBAT4 - 61 65 mA

VBAT Circuit current 5 IBAT5 - 83 94 mA

VBAT Circuit current 6 IBAT6 - 93 104 mA

VBAT Circuit current 7 IBAT7 - 124 136 mA

VBAT Circuit current 8 IBAT8 - 0.25 1.0 mA

LDO1=LDO2=ON, I
Other blocks=OFF
DC/DC x1mode, I

LED

VBAT=3.7V, LED Vf=3.0V
DC/DC x1.33mode, I
VBAT=3.1V, LED Vf=3.0V
DC/DC x1.5mode, I
VBAT=2.9V, LED Vf=3.5V
DC/DC x2mode, I

LED

VBAT=3.2V, LED Vf=4.0V
Onl

ALC block ON
ADCYC=0.5s setting
Except sensor current

【LED Driver】

LED current Step (Setup) ILEDSTP1 128 Step LED1~5

LED current Step (At slope) ILEDSTP2 256 Step LED1~5

LED current Step (Flash) ILEDSTPFL 32 Step LEDFL

White LED Maximum setup current IMAXWLED - 25.6 - mA LED1~5

Flash LED Maximum setup current IMAXFLED - 120 - mA LEDFL

LED1~5 current accuracy IWLED -7% 15 +7% mA I

Flash LED current accuracy IFLED -7% 60 +7% mA I

=15mA setting at VLED=1.0V

LED

=60mA setting at VLED=1.0V

LED

LED current Matching ILEDMT - - 4 % Between LED1~5 at VLED=1.0V

LED OFF Leak current ILKLED - - 1.0 μA VLED=4.5V

【DC/DC（Charge Pump)】

Maximum Output voltage VoCP 4.65 5.1 5.55 V

Current Load IOUT - - 250 mA VBAT≥3.2V, VOUT=4V

Oscillator frequency fosc 0.8 1.0 1.2 MHz
Over Voltage Protection detect

voltage

OVP - - 6.0 V

Short Circuit current limit Ilim - 125 250 mA VOUT=0V

【I2C Input (SDA, SCL)】

LOW level input voltage VIL -0.3 -

HIGH level input voltage VIH

Hysteresis of Schmitt trigger input Vhys

LOW level output voltage
(SDA) at 3mA sink current

Input current each I/O pin lin -3 - 3 μA Input voltage = 0.1×VIO~0.9×VIO

VOL 0 - 0.3 V

0.75 ×
VIO

0.05 ×
VIO

0.25 ×
VIO

VBAT

­+0.3

V

V

- - V

【RESETB】

LOW level input voltage VIL -0.3 -

HIGH level input voltage VIH

0.75 ×
VIO

0.25 ×
VIO

VBAT

­+0.3

V

V

Input current each I/O pin Iin -3 - 3 μA Input voltage = 0.1×VIO~0.9×VIO

=0mA

LDO

=60mA

=60mA

LED

=60mA

LED

=60mA

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●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VIO=1.8V)

Parameter Symbol

【Regulator (LDO1)】

Output voltage Vo1

Output Current Io1 - - 150 mA Vo=1.8V

Dropout Voltage Vsat1 - 0.05 0.1 V VBAT=2.5V, Io=50mA, Vo=2.8V

Load stability ΔVo11 - 10 60 mV Io=1~150mA, Vo=1.8V

Input voltage stability ΔVo12 - 10 60 mV VBAT=3.4~4.5V, Io=50mA, Vo=1.8V

Ripple Rejection Ratio RR1 - 65 - dB

Short circuit current limit Ilim1 - 200 400 mA Vo=0V

Discharge resister at OFF ROFF1 - 1.0 1.5 kΩ

【Regulator (LDO2)】

Output voltage Vo2

Output Current Io2 - - 150 mA Vo=2.5V

Dropout Voltage Vsat2 - 0.05 0.1 V VBAT=2.5V, Io=50mA, Vo=2.8V

Load stability Δvo21 - 10 60 mV Io=1~150mA, Vo=2.5V

Input voltage stability Δvo22 - 10 60 mV VBAT=3.4~4.5V, Io=50mA, Vo=2.5V

Ripple Rejection Ratio RR2 - 65 - dB

Short circuit current limit Ilim2 - 200 400 mA Vo=0V

Discharge resister at OFF ROFF2 - 1.0 1.5 kΩ

Min. Typ. Max.

1.164 1.20 1.236 V Io=50mA

1.261 1.30 1.339 V Io=50mA

1.455 1.50 1.545 V Io=50mA

1.552 1.60 1.648 V Io=50mA

1.746 1.80 1.854 V Io=50mA <Initial Voltage>

2.134 2.20 2.266 V Io=50mA

2.328 2.40 2.472 V Io=50mA

2.425 2.50 2.575 V Io=50mA

2.522 2.60 2.678 V Io=50mA

2.619 2.70 2.781 V Io=50mA

2.716 2.80 2.884 V Io=50mA

2.813 2.90 2.987 V Io=50mA

2.910 3.00 3.090 V Io=50mA

3.007 3.10 3.193 V Io=50mA

3.104 3.20 3.296 V Io=50mA

3.201 3.30 3.399 V Io=50mA

1.164 1.20 1.236 V Io=50mA

1.261 1.30 1.339 V Io=50mA

1.455 1.50 1.545 V Io=50mA

1.552 1.60 1.648 V Io=50mA

1.746 1.80 1.854 V Io=50mA

2.134 2.20 2.266 V Io=50mA

2.328 2.40 2.472 V Io=50mA

2.425 2.50 2.575 V Io=50mA <Initial Voltage>

2.522 2.60 2.678 V Io=50mA

2.619 2.70 2.781 V Io=50mA

2.716 2.80 2.884 V Io=50mA

2.813 2.90 2.987 V Io=50mA

2.910 3.00 3.090 V Io=50mA

3.007 3.10 3.193 V Io=50mA

3.104 3.20 3.296 V Io=50mA

3.201 3.30 3.399 V Io=50mA

Limits

Unit Condition

f=100Hz, Vin=200mVp-p, Vo=1.2V
Io=50mA, BW=20Hz~20kHz

f=100Hz, Vin=200mVp-p, Vo=1.2V
Io=50mA, BW=20Hz~20kHz

Technical Note

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●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VIO=1.8V)

Parameter Symbol

【Sensor Interface】

SBIAS Output voltage VoS

SBIAS Output current IoS - - 30 mA Vo=3.0V

Min. Typ. Max.

2.850 3.0 3.150 V Io=200μA <Initial Voltage>

2.470 2.6 2.730 V Io=200μA

Limits

Unit Condition

Technical Note

SSENS Input range VISS 0 -

SBIAS Discharge resister at
OFF

ADC resolution ADRES 8 bit

ADC non-linearity error ADINL -3 - +3 LSB

ADC differential non-linearity
error

SSENS Input impedance RSSENS 1 - - MΩ

【WPWMIN】

L level input voltage VILA -0.3 - 0.3 V

H level input voltage VIHA 1.4 -

Input current IinA - 3.6 10 μA Vin=1.8V

PWM input minimum High
pulse width

【GC1, GC2】

L level output voltage VOLS - - 0.2 V IOL=1mA

H level output voltage VOHS

【FLASHCNT】

ROFFS - 1.0 1.5 kΩ

ADDNL -1 - +1 LSB

PWpwm 80 - - μs

VoS

-0.2

VoS x

255/256

VBAT

+0.3

- - V IOH=1mA

V

V

L level input voltage VILF -0.3 - 0.3 V

H level input voltage VIHF 1.4 -

Input current IinF - 3.6 10 μA Vin=1.8V

VBAT

+0.3

V

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●Block Diagram / Application Circuit example

1μF (6.3V)

1μF (6.3V)

Technical Note

1μF (6.3V)

VBAT

VBATCP

VBAT1

VBATLDO

10µF

VIO

RESETB

SCL

SD

WPWMIN

FLASHCNT

Charge Pump
Mode Control

I/O

IREF

Level

Shift

C1P

C1N

C2P

C2N

C3N

Charge Pump

x1 / x1.33 / x1.5 / x2

OVP

LED terminal voltage feedback

2

I

C interface

Digital Control

To L ED1 ~ 5
LEDFL

TSD

C3P

VOUT

2.2μF

(6.3V)

LED1

LED2

LED3

Back Light

LED4

LED5

LEDFL

Flash

BH1600FVC

SBIAS

SSENS

GC1

GC2

SGND

1μF

VREF

Sensor

I/F

LED

control

ALC

T3

T1

T2

CPGND

LEDGND

LDO1

Vo selectable

Io=150mA

LDO2

Vo selectable

Io=150mA

T4

(Open)

(Open)

LDO1O

1μF

LDO2O

1μF

Fig.1 Block Diagram / Application Circuit example

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●Pin Arrangement ［Bottom View］

Technical Note

F

E

D

C

B

A

T4 LDO1O SSENS VBAT1 SBIAS T3

VBATLDO LDO2O GC2 GC1 SGND VIO

WPWMIN LED1 FLASHCNT SDA SCL C1N

LED3 LED2 RESETB C1P C2N

LED4 LED5 LEDGND VOUT VBATCP C2P

T1 LEDFL CPGND C3N C3P T2

Total: 35 balls

1 2 3 4 5 6

Index

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●Package

●BD6095GUL

VCSP50L3
SIZE : 3.75mm
A ball pitch : 0.5mm
Height : 0.55mm max

Technical Note

BD6095

Lot No.

( Unit : mm )

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●BD6095GU

VCSP85H3
SIZE : 3.75mm
A ball pitch : 0.5mm
Height : 1.0mm max

Technical Note

D6095

Lot No.

( Unit : mm )

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●Pin Functions

ESD Diode

No Ball No. Pin Name I/O

1 B5 VBATCP - - GND Power supply for charge pump A
2 F4 VBAT1 - - GND Power supply A
3 E1 VBATLDO - - GND Power supply for LDO A
4 A1 T1 I VBAT GND Test Input Pin (short to Ground) S
5 A6 T2 I VBAT GND Test Input Pin (short to Ground) S
6 F6 T3 O VBAT GND Test Output Pin (Open) M
7 F1 T4 O VBAT GND Test Output Pin (Open) N
8 E6 VIO - VBAT GND Power supply for I/O and Digital C

9 C4 RESETB I VBAT GND Reset input (L: reset, H: reset cancel) H
10 D4 SDA I/O VBAT GND I2C data input / output I
11 D5 SCL I VBAT GND I2C clock input H
12 A3 CPGND - VBAT - Ground B
13 B3 LEDGND - VBAT - Ground B
14 D6 C1N I/O VBAT GND Charge Pump capacitor is connected F
15 C5 C1P I/O - GND Charge Pump capacitor is connected G
16 C6 C2N I/O VBAT GND Charge Pump capacitor is connected F
17 B6 C2P I/O - GND Charge Pump capacitor is connected G
18 A4 C3N I/O VBAT GND Charge Pump capacitor is connected F
19 A5 C3P I/O - GND Charge Pump capacitor is connected G
20 B4 VOUT O - GND Charge Pump output pin A
21 F2 LDO1O O VBAT GND LDO1 output pin Q
22 E2 LDO2O O VBAT GND LDO2 output pin Q
23 D2 LED1 I - GND LED cathode connection 1 E
24 C2 LED2 I - GND LED cathode connection 2 E
25 C1 LED3 I - GND LED cathode connection 3 E
26 B1 LED4 I - GND LED cathode connection 4 E
27 B2 LED5 I - GND LED cathode connection 5 E
28 A2 LEDFL I - GND LED cathode connection for Flash E
29 F5 SBIAS O VBAT GND Bias output for the Ambient Light Sensor Q
30 F3 SSENS I VBAT GND Ambient Light Sensor input N
31 E4 GC1 O VBAT GND Ambient Light Sensor gain control output 1 X
32 E3 GC2 O VBAT GND Ambient Light Sensor gain control output 2 X
33 E5 SGND - VBAT - Ground B
34 D1 WPWMIN I VBAT GND External PWM input for Back Light L
35 D3 FLASHCNT I VBAT GND External enable for Flash L

※ The LED terminal that isn't used is to short-circuit to the ground. But, the setup of a register concerned with LED that isn't used is prohibited.

Total: 35 Pin

For

Power

For

Ground

Functions

Technical Note

Equivalent

Circuit

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●Equivalent Circuit

A VBATB E

C

VBAT

Technical Note

VBAT F G

J

N VBAT VBAT

VIO VBAT

VBAT

K

O

VIOVIO

VBAT

H VIO VBAT I

P

VBAT VBAT

VIOVBAT

VBATVBATL

M

Q

VBAT VBAT

R

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VBAT VBAT

S VIO VBAT

VBATVBAT

T

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Technical Note

●I2C BUS format

The writing/reading operation is based on the I2C slave standard.

・Slave address

A7 A6 A5 A4 A3 A2 A1 R/W

1 1 1 0 1 1 0 1/0

・Bit Transfer

SCL transfers 1-bit data during H. SCL cannot change signal of SDA during H at the time of bit transfer. If SDA changes
while SCL is H, START conditions or STOP conditions will occur and it will be interpreted as a control signal.

SDA

SCL

SDA a state of stability

Data are effective

SDA

：

It can change

・START and STOP condition

When SDA and SCL are H, data is not transferred on the I

2

C- bus. This condition indicates, if SDA changes from H to L
while SCL has been H, it will become START (S) conditions, and an access start, if SDA changes from L to H while SCL
has been H, it will become STOP (P) conditions and an access end.

SDA

SCL

S P

START condition

STOP condition

・Acknowledge

It transfers data 8 bits each after the occurrence of START condition. A transmitter opens SDA after transfer 8bits data, and
a receiver returns the acknowledge signal by setting SDA to L.

DATA OUTPUT
BY TRANSMITTER

DATA OUTPUT
BY RECEIVER

SCL

START condition

S

12 89

not acknowledge

acknowledge

clock pulse for
acknowledgement

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A A

A

A

A7 A6 A5A4A3A2A1A

A

A

A

A

A

A

A

A A

A

A

A6A5A4A3A2A1A

A

A

A

A

Technical Note

・Writing protocol

A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The 3rd
byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register address is
carried out automatically. However, when a register address turns into the last address, it is set to 00h by the next
transmission. After the transmission end, the increment of the address is carried out.

*1 *1

D7D6 D5 D4 D3 D2 D1D0 D7 D6 D5 D4 D3 D2 D1 D0

X X X X X X X

S

R/W=0(write)

from master to slave

from slave to master

register addressslave address

00

DATA

register address

increment

=acknowledge(SDA LOW)

=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
*1: Write Timing

DATA

register address

・Reading protocol

It reads from the next byte after writing a slave address and R/W bit. The register to read considers as the following address
accessed at the end, and the data of the address that carried out the increment is read after it. If an address turns into the
last address, the next byte will read out 00h. After the transmission end, the increment of the address is carried out.

X X X X X X X

R/W=1(read)

from master to slave

from slave to master

P

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

DATA

register address

increment

=acknowledge(SDA LOW)

=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition

DATA slave address

register address

increment

1 S

・Multiple reading protocols

After specifying an internal address, it reads by repeated START condition and changing the data transfer direction. The
data of the address that carried out the increment is read after it. If an address turns into the last address, the next byte will
read out 00h. After the transmission end, the increment of the address is carried out.

P

increment

S

slave address

R/W=0(write)

from master to slave

from slave to master

0

7

register address

D7 D6 D5 D4 D3D2D1D0 D7D6 D5 D4 D3 D2 D1 D0

DATA DATA

register address

increment

Sr 1

0X X X X X X X

X X X X X X X

slave address

=acknowledge(SDA LOW)

=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
Sr=repeated START condition

R/W=1(read)

P

register address

increment

As for reading protocol and multiple reading protocols, please do A(not acknowledge) after doing the final reading operation.
It stops with read when ending by A(acknowledge), and SDA stops in the state of Low when the reading data of that time is

0. However, this state returns usually when SCL is moved, data is read, and A(not acknowledge) is done.

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S

●Timing diagram

SDA

LOW

t

CL

SU;DAT

t

Technical Note

BUF

t

t

HD;STA

HD;STA

t

HD;DAT

S Sr P

t

t HIGH

●Electrical Characteristics(Unless otherwise specified, Ta=25

Parameter Symbol

2

【I

C BUS format】

SU;STA

t

o

C, VBAT=3.6V, VIO=1.8V)

Standard-mode Fast-mode

Min. Typ. Max. Min. Typ. Max.

t SU;STO

S

Unit

SCL clock frequency fSCL 0 - 100 0 - 400 kHz

LOW period of the SCL clock tLOW 4.7 - - 1.3 - - μs

HIGH period of the SCL clock tHIGH 4.0 - - 0.6 - - μs

Hold time (repeated) START condition
After this period, the first clock is generated

t

HD;STA 4.0 - - 0.6 - - μs

Set-up time for a repeated START condition tSU;STA 4.7 - - 0.6 - - μs

Data hold time tHD;DAT 0 - 3.45 0 - 0.9 μs

Data set-up time tSU;DAT 250 - - 100 - - ns

Set-up time for STOP condition tSU;STO 4.0 - - 0.6 - - μs

Bus free time between a STOP
and START condition

t

BUF 4.7 - - 1.3 - - μs

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