ROHM BD60910GU Technical data

LED Drivers for LCD Backlights

White backlight LED Drivers
for Small to Medium LCD Panels
(Switching Regulator Type)

BD60910GU

●Description

BD60910GU is maximum 8LED(minimum 4LED) serial LED driver with ALC (Auto Luminous Control) function.
Best match for mobile application that needs long battery life.

●Features

1) Boost DC/DC for LED back lighting
Drives maximum 8 to minimum 4 serial LEDs.
Integrated high voltage switching transistor
Soft start function.
Over voltage protection (Detect voltage is controllable)
Over current protection (2nd side)
VOUT short to GND protection
VOUT open protection.

2) Constant current driver for LED back lighting
Current step can be set in 7bit(0.2mA 128steps), and 8bit(0.1mA 256steps) in sloping.
Rise and fall time of sloping are set independently.
Iout max = 25.6mA
PWM brightness control by external input.

3) Auto Luminous Control (ALC)
Periodic ambient detection reduces sensor consumption current.
LED brightness can be controlled by 16steps ambient brightness level.
LED current for each ambient level is freely customizable.
SBIAS for sensor bias is integrated. (3.0V or 2.6V)
Photo Diode, Photo Transistor, Photo IC(Linear/ Logarithm) can be connected.
Automatic gain control built-in, so BH1600FVC can be connected directly.

4) Thermal shutdown (Auto-return type)

2

5) I

6) VCSP85H3(3.00mm

●Absolute Maximum Ratings (Ta=25

C BUS FS mode（max 400kHz）Write/Read

Parameter Symbol Ratings Unit Pins

x 3.00mm) Small Size CSP package

℃)

No.11040EBT30

Maximum voltage 1 VMAX1 7 V except for VLED VOUT, SW

Maximum voltage 2 VMAX2 15 V VLED

Maximum voltage 3 VMAX3 40 V VOUT, SW

Power Dissipation Pd 1250 *1 mW
Operating Temperature Range Topr -40 ~ +85 ℃
Storage Temperature Range Tstg -55 ~ +150 ℃

*1) Power dissipation deleting is 10mW/ ℃, when it’s used in over 25 ℃. It’s deleting is on the board that is ROHM’s standard.
Dissipation by LSI should not exceed tolerance level of Pd.

●Operating conditions (VBATVIO, Ta=-40~85

Parameter Symbol Ratings Unit

VBAT input voltage VBAT 2.7~5.5 V

VIO pin voltage VIO 1.65~3.3 V

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℃)

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2011.07 - Rev.B

BD60910GU

●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VIO=1.8V)

Parameter Symbol

【Circuit Current】

VBAT Circuit current 1 IBAT1 - 0.1 1.0 A RESETB=0V, VIO=0V

VBAT Circuit current 2 IBAT2 - 0.5 3.0 A RESETB=0V, VIO=1.8V

Min. Typ. Max.

Limits

Unit Condition

Technical Note

VBAT Circuit current 3 IBAT3 - 3.5 5.0 mA

VBAT Circuit current 4 IBAT4 - 0.4 1.0 mA

【LED Driver】

LED current Step (Setup) ILEDSTP1 128 Step

LED current Step (At slope) ILEDSTP2 256 Step

LED Maximum current IMAXWLED - 25.6 - mA

LED current accuracy IWLED -7% 15 +7% mA I

【DC/DC】

VLED pin feedback voltage Vfb - 0.3 - V

Over current protection OCP - 650 - mA

Oscillator frequency fosc 0.8 1.0 1.2 MHz

OVP1 30 31 32 V

Over Voltage Protection detect
voltage

OVP2 - 27 - V
OVP3 - 24 - V
OVP4 - 21 - V
OVP5 - 18 - V

LED=ON, ILED=15mA setting
Vo=24V

Only ALC block ON
ADCYC=0.52s setting
Except sensor current

=15mA setting

LED

Maximum Duty Mduty 92.5 - - %

VOUT open protection OVO - 0.7 1.4 V

●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VIO=1.8V)

Parameter Symbol

【I2C Input (SDA, SCL)】

LOW level input voltage VIL -0.3 -

HIGH level input voltage VIH

Hysteresis of Schmitt trigger
input

LOW level output voltage
(SDA) at 3mA sink current

Input current each I/O pin lin -3 - 3 A Input voltage = 0.1×VIO~0.9×VIO

【RESETB】

LOW level input voltage VIL -0.3 -

HIGH level input voltage VIH

Input current each I/O pin Iin -3 - 3 A Input voltage = 0.1×VIO~0.9×VIO

Vhys

VOL 0 - 0.3 V

Min. Typ. Max.

0.75 ×
VIO

0.05 ×
VIO

0.75 ×
VIO

Limits

0.25 ×
VIO

VBAT

­+0.3

- - V

0.25 ×
VIO

VBAT

­+0.3

Unit Condition

V

V

V

V

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2/30

2011.07 - Rev.B

BD60910GU

●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VIO=1.8V)

Parameter Symbol

【ALC】

SBIAS Output voltage VoS

SBIAS Output current IoS - - 30 mA Vo=3.0V

Min. Typ. Max.

2.850 3.0 3.150 V Io=200A <Initial value>

2.470 2.6 2.730 V Io=200A

Limits

Unit Condition

Technical Note

SSENS Input range VISS 0 -

SBIAS Discharge resister at
OFF

ADC resolution ADRES 8 bit

ADC non-linearity error ADINL -3 - +3 LSB

ADC differential non-linearity
error

SSENS Input impedance RSSENS 1 - - M

【WPWMIN】

L level input voltage VILA -0.3 - 0.3 V

H level input voltage VIHA 1.4 -

Input current IinA - 3.6 10 A Vin=1.8V

PWM input minimum High
pulse width

【GC1, GC2】

L level output voltage VOLS - - 0.2 V IOL=1mA

H level output voltage VOHS

ROFFS - 1.0 1.5 k

ADDNL -1 - +1 LSB

PWpwm 50 - - s

VoS

-0.2

VoS x

255/256

VBAT

+0.3

- - V IOH=1mA

V

V

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3/30

2011.07 - Rev.B

BD60910GU

A

( )

( )

( )

●Block Diagram / Application Circuit example

VBAT

VBAT1

VBAT2

10µF

VIO

RESETB

SCL

SD

I/O

Level

Shift

WPWMIN

Photo IC

GC1

GC2

BH1600FVC

VDD

GND

IOUT

*

5.6k

SBIAS

SSENS

SGND

1F

Sensor

I/F

GC2

GC1

* The example when using BH1600FVC and assuming brightness range
10(lx)-50000(lx) by the panel of 20% transmissivity

Fig.1 Block Diagram / Application Circuit example

22H

2

C interface

I

Digital Control

ALC

RB520S-40

SW

DC/DC

External PWM

TSD

IREF

1F(50V)

T1

OCP

T2

GNDP

VREF

(Open)

T3

(Open)

GNDPS

OVP

Feed Back

T4

Technical Note

VOUT

VLED

LEDGND

GND1

GND2

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4/30

2011.07 - Rev.B

BD60910GU

●Pin Arrangement [Bottom View］

●Pin Functions

T4 GND2 GNDP SW T3

E

VIO SCL RESETB GNDPS VBAT2

D

GND1 SDA VOUT GC2 SGND

C

index

WPWMIN

B

T1 VBAT1 LEDGND VLED T2

A

GC1 SBIAS SSENS

12345

Fig.2 Pin Arrangement

Technical Note

No Ball No. Pin Name I/O

1 A2 VBAT1 - - GND Power supply A
2 D5 VBAT2 - - GND Power supply A

3 D1 VIO - VBAT GND Power supply for I/O C

4 C1 GND1 - VBAT - Ground B

5 E2 GND2 - VBAT - Ground B

6 A3 LEDGND - VBAT - Ground B

7 E3 GNDP - VBAT - Ground B

8 D4 GNDPS - VBAT - Ground B

9 C5 SGND - VBAT - Ground B

10 D3 RESETB I VBAT GND Reset input (L: reset, H: reset cancel) H

11 C2 SDA I/O VBAT GND I2C data input / output I

12 D2 SCL I VBAT GND I2C clock input H
13 B1 WPWMIN I VBAT GND External PWM input L

14 E4 SW O - GND DC/DC Switching port A

15 C3 VOUT O - GND DC/DC output voltage monitor A

16 A4 VLED I - GND LED cathode connection E

17 B4 SBIAS O VBAT GND Bias output for the Ambient Light Sensor Q

18 B5 SSENS I VBAT GND Ambient Light Sensor input N
19 B3 GC1 O VBAT GND Ambient Light Sensor gain control output 1 X
20 C4 GC2 O VBAT GND Ambient Light Sensor gain control output 2 X
21 A1 T1 I VBAT GND Test Input Pin (short to Ground) S
22 A5 T2 O VBAT GND Test Output Pin (Open) M
23 E5 T3 O VBAT GND Test Output Pin (Open) N

24 E1 T4 I VBAT GND Test Input Pin (short to Ground) S

ESD Diode

For Power For Ground

Functions

Equivalent

Circuit

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5/30

2011.07 - Rev.B

BD60910GU

●Equivalent Circuit

A VBATB E

C

VBAT

Technical Note

H VIOVBAT I

N

VIO VBAT

VBAT

Q

VBAT VBAT

VBATVBATL

S

VBATVBAT

M

X

VoS VBAT

VBAT

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2011.07 - Rev.B

BD60910GU

Technical Note

●I2C BUS format

The writing/reading operation is based on the I

2

C slave standard.

・ Slave address

A7 A6 A5 A4 A3 A2 A1 R/W

1 1 1 0 1 1 0 1/0

・ Bit Transfer

SCL transfers 1-bit data during H. SCL cannot change signal of SDA during H at the time of bit transfer. If SDA changes
while SCL is H, START conditions or STOP conditions will occur and it will be interpreted as a control signal.

SDA

SCL

SDA a state of stability

Data are effective

SDA

：

It can change

・ START and STOP condition

When SDA and SCL are H, data is not transferred on the I

2

C- bus. This condition indicates, if SDA changes from H to L
while SCL has been H, it will become START (S) conditions, and an access start, if SDA changes from L to H while SCL
has been H, it will become STOP (P) conditions and an access end.

SDA

SCL

S P

START condition

STOP condition

・ Acknowledge

It transfers data 8 bits each after the occurrence of START condition. A transmitter opens SDA after transfer 8bits data, and
a receiver returns the acknowledge signal by setting SDA to L.

DATA OUTPUT
BY TRANSMITTER

DATA OUTPUT
BY RECEIVER

SCL

START condition

S

12 89

not acknowledge

acknowledge

clock pulse for
acknowledgement

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7/30

2011.07 - Rev.B

BD60910GU

A A

A

A

A7 A6 A5A4A3A2A1A

A

A

A

A

A

A

A

A A

A

A

A6A5A4A3A2A1A

A

A

A

A

Technical Note

・Writing protocol

A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The 3rd
byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register address
is carried out automatically. However, when a register address turns into the last address, it is set to 00h by the next
transmission. After the transmission end, the increment of the address is carried out.

*1 *1

D7D6 D5 D4 D3 D2 D1D0 D7 D6 D5 D4 D3 D2 D1 D0

X X X X X X X

S

R/W=0(write)

from master to slave

from slave to master

register addressslave address

00

DATA

register address

increment

=acknowledge(SDA LOW)

=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
*1: Write Timing

DATA

register address

・Reading protocol

It reads from the next byte after writing a slave address and R/W bit. The register to read considers as the following
address accessed at the end, and the data of the address that carried out the increment is read after it. If an address
turns into the last address, the next byte will read out 00h. After the transmission end, the increment of the address is
carried out.

X X X X X X X

R/W=1(read)

from master to slave

from slave to master

P

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

DATA

register address

increment

=acknowledge(SDA LOW)

=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition

DATA slave address

register address

increment

1 S

・Multiple reading protocols

After specifying an internal address, it reads by repeated START condition and changing the data transfer direction. The
data of the address that carried out the increment is read after it. If an address turns into the last address, the next byte
will read out 00h. After the transmission end, the increment of the address is carried out.

P

increment

S

slave address

R/W=0(write)

from master to slave

from slave to master

0

7

register address

D7 D6 D5 D4 D3D2D1D0 D7 D6 D5 D4 D3 D2 D1D0

DATA DATA

register address

increment

Sr 1

0X X X X X X X

X X X X X X X

slave address

=acknowledge(SDA LOW)

=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
Sr=repeated START condition

R/W=1(read)

P

register address

increment

As for reading protocol and multiple reading protocols, please do A (not acknowledge) after doing the final reading
operation. It stops with read when ending by A(acknowledge), and SDA stops in the state of Low when the reading data
of that time is 0. However, this state returns usually when SCL is moved, data is read, and A (not acknowledge) is done.

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2011.07 - Rev.B

BD60910GU

S

●Timing diagram

SDA

CL

t

LOW

t

SU;DAT

HD;STA

t

Technical Note

t BUF

t SU;STO

S

SU;STA

t

HD;STA

t

HD;DAT

t

S Sr P

HIGH

t

●Electrical Characteristics(Unless otherwise specified, Ta=25 ℃, VBAT=3.6V, VIO=1.8V)

Standard-mode Fast-mode

Parameter Symbol

Unit

Min. Typ. Max. Min. Typ. Max.

2

【I

C BUS format】

SCL clock frequency fSCL 0 - 100 0 - 400 kHz

LOW period of the SCL clock tLOW 4.7 - - 1.3 - - s

HIGH period of the SCL clock tHIGH 4.0 - - 0.6 - - s

Hold time (repeated) START condition
After this period, the first clock is generated

Set-up time for a repeated START
condition

tHD;STA 4.0 - - 0.6 - - s

t

SU;STA 4.7 - - 0.6 - - s

Data hold time tHD;DAT 0 - 3.45 0 - 0.9 s

Data set-up time tSU;DAT 250 - - 100 - - ns

Set-up time for STOP condition tSU;STO 4.0 - - 0.6 - - s

Bus free time between a STOP
and START condition

BUF 4.7 - - 1.3 - - s

t

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9/30

2011.07 - Rev.B

BD60910GU

●Register List

Input "0” for "-".

Address W/R

Technical Note

Register data

Function

D7 D6 D5 D4 D3 D2 D1 D0

00h W - - - - - - - SFTRST

01h R/W - VOVP(2) VOVP(1) VOVP(0) WPWMEN ALCEN LEDMD LEDEN LED, ALC, OVP Control

02h - - - - - - - - - -

03h R/W - ILED(6) ILED(5) ILED(4) ILED(3) ILED(2) ILED(1) ILED(0)

04h - - - - - - - - - -

05h - - - - - - - - - -

06h - - - - - - - - - -

07h - - - - - - - - - -

08h W THL(3) THL(2) THL(1) THL(0) TLH(3) TLH(2) TLH(1) TLH(0) LED Current transition

09h - - - - - - - - - -

0Ah - - - - - - - - - -

0Bh R/W ADCYC(1) ADCYC(0) GAIN(1) GAIN(0) STYPE VSB MDCIR SBIASON ALC mode setting

0Ch - - - - - - - - - -

0Dh R - - - - AMB(3) AMB(2) AMB(1) AMB(0) Ambient level output

0Eh W - IU0(6) IU0(5) IU0(4) IU0(3) IU0(2) IU0(1) IU0(0) LED Current at Ambient level 0h

0Fh W - IU1(6) IU1(5) IU1(4) IU1(3) IU1(2) IU1(1) IU1(0) LED Current at Ambient level 1h

10h W - IU2(6) IU2(5) IU2(4) IU2(3) IU2(2) IU2(1) IU2(0) LED Current at Ambient level 2h

Software Reset

LED Current Setting
at non-ALC mode

11h W - IU3(6) IU3(5) IU3(4) IU3(3) IU3(2) IU3(1) IU3(0) LED Current at Ambient level 3h

12h W - IU4(6) IU4(5) IU4(4) IU4(3) IU4(2) IU4(1) IU4(0) LED Current at Ambient level 4h

13h W - IU5(6) IU5(5) IU5(4) IU5(3) IU5(2) IU5(1) IU5(0) LED Current at Ambient level 5h

14h W - IU6(6) IU6(5) IU6(4) IU6(3) IU6(2) IU6(1) IU6(0) LED Current at Ambient level 6h

15h W - IU7(6) IU7(5) IU7(4) IU7(3) IU7(2) IU7(1) IU7(0) LED Current at Ambient level 7h

16h W - IU8(6) IU8(5) IU8(4) IU8(3) IU8(2) IU8(1) IU8(0) LED Current at Ambient level 8h

17h W - IU9(6) IU9(5) IU9(4) IU9(3) IU9(2) IU9(1) IU9(0) LED Current at Ambient level 9h

18h W - IUA(6) IUA(5) IUA(4) IUA(3) IUA(2) IUA(1) IUA(0) LED Current at Ambient level Ah

19h W - IUB(6) IUB(5) IUB(4) IUB(3) IUB(2) IUB(1) IUB(0) LED Current at Ambient level Bh

1Ah W - IUC(6) IUC(5) IUC(4) IUC(3) IUC(2) IUC(1) IUC(0) LED Current at Ambient level Ch

1Bh W - IUD(6) IUD(5) IUD(4) IUD(3) IUD(2) IUD(1) IUD(0) LED Current at Ambient level Dh

1Ch W - IUE(6) IUE(5) IUE(4) IUE(3) IUE(2) IUE(1) IUE(0) LED Current at Ambient level Eh

1Dh W - IUF(6) IUF(5) IUF(4) IUF(3) IUF(2) IUF(1) IUF(0) LED Current at Ambient level Fh

Prohibit to accessing the address that isn’t mentioned.
The timing indicated by explanation of registers, is a value in case built-in OSC has Typ. frequency.(1MHz)

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10/30

2011.07 - Rev.B