ROHM BD6083GUL Technical data

A

LED Drivers for LCD BackLights

Multifunction Backlight LED Driver
for Small LCD Panels (Charge Pump Type)

BD6083GUL

●Description

BD6083GUL is “Intelligent LED Driver” that is the most suitable for the cellular phone.
It has 3 - 6LED driver and output variable LDO4ch for LCD Backlight.
It has ALC function that is “Low Power Consumption System” realized.
It can be developed widely from the high End model to the Low End model.
As it has charge pump circuit for DCDC, it is no need to use coils, and it contributes to small space.
VCSP50L3 (3.15mm x 3.15mm 0.5mm pitch)
It adopts the very thin CSP package that is the most suitable for the slim phone.

●Features

1) Total 3 - 6LEDs driver for LCD Backlight
・It has 4LEDs (it can select 4LED or 3LED) for exclusire use of Main and 2LEDs which can chose independent
control or a main allotment by resister setting.
・Main Group” can be controlled by Auto Luminous Control (ALC) system.
“Main Group” can be controlled by external PWM signal.
・ON/ Off and a setup of LED current are possible at the time of the independent control by the independence.

2) Ambient Light sensor interface
・Incorporates various functions such as a sensor bias adjustment function, an ADC with an average filter, a gainoffset
adjustment function and an LOG conversion function so that options can be increased for illumination intensity
sensors (Photo Diode, Photo Transistor, Photo IC (Linear/LOG)).
・Incorporates an auto gain switching function for suppressing an illumination intensity sensor current
at high illumination intensity and improving sensitivity at low illumination intensity
・Capable of customizing an LED current value according to a table setting.
・Slope control loading and an independent control change are possible.

3) Charge Pump DC/DC for LED driver
・It has x1/x1.5/ x2 mode that will be selected automatically.
・The most suitable voltage up magnification is controlled automatically by LED port voltage.
・Soft start

4) 4ch Series Regulator (LDO)
・It has selectable output voltage by the register.(16 steps)
LDO1, LDO2, LDO3, LDO4: Iomax=150mA

5) Thermal shutdown

2

6) I

●Absolute Maximum Ratings (Ta=25

Maximum Voltage VMAX 7 V

Power Dissipation Pd 1280
Operating Temperature Range Topr -30 ~ +85 ℃
Storage Temperature Range Tstg -55 ~ +150 ℃

●Operating Conditions (VBAT≥VIO, Ta=-30~85

VBAT Input Voltage VBAT 2.7 ~ 5.5 V

VIO Pin Voltage VIO 1.65 ~ 3.3 V

C BUS FS mode (max 400 kHz) Compatibility

(Note) Power dissipation deleting is 10.24mW/ ℃ , when it’s used in over 25 ℃.
(It’s deleting is on the board that is ROHM’s standard)

functions、Over voltage protection (Auto-return type),Over current protection (Auto-return type) loading

℃)

Parameter Symbol Ratings Unit

(Note)

mW

℃)

Parameter Symbol Limits Unit

No.10040EAT16

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●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VBAT=3.6V, VIO=1.8V)

Parameter Symbol

Min. Typ. Max.

Limits

Unit Conditions

【Circuit Current】

VBAT Circuit Current 1 IBAT1 - 0.1 3.0 μA RESETB=0V, VIO= 0V

VBAT Circuit Current 2 IBAT2 - 0.5 3.0 μA RESETB=0V, VIO=1.8V

Technical Note

VBAT Circuit Current 3 IBAT3 - 61 65 mA

VBAT Circuit Current 4 IBAT4 - 92 102 mA

VBAT Circuit Current 5 IBAT5 - 123 140 mA

DC/DC x1 mode, Io=60mA
VBAT=4.0V

DC/DC x1.5 mode, Io=60mA
VBAT=3.6V

DC/DC x2 mode, Io=60mA
VBAT=2.7V

ALC Operating

VBAT Circuit Current 6 IBAT6 - 0.25 1.0 mA

ALCEN=1, AD cycle=0.5s setting
Except sensor current

VBAT Circuit Current 7 IBAT7 - 90 150 μA LDO1,2=ON, I

VBAT Circuit Current 8 IBAT8 - 90 150 μA LDO3,4=ON, I

【LED Driver】

LED Current Step (Setup) ILEDSTP1 128 Step LED1~6

LED Current Step (At slope) ILEDSTP2 256 Step LED1~6

LED Maximum Setup Current IMAXWLED - 25.6 - mA LED1~6

LED Current Accuracy IWLED -7% 15 +7% mA I

LED Current Matching ILEDMT - - 4 %

=15mA setting, VLED=1.0V

LED

Between LED1~6 at VLED=1.0V,
ILED=15mA

LED OFF Leak Current ILKLED - - 1.0 μA VLED=4.5V

LDO

LDO

=0mA

=0mA

【DC/DC(Charge Pump)】

Output Voltage VoCP - Vf+0.2 Vf+0.25 V Vf is forward direction of LED

Drive Ability IOUT - - 150 mA VBAT≥3.2V, VOUT=3.9V

Switching Frequency fosc 0.8 1.0 1.2 MHz

Over Voltage Protection
Detect Voltage

Over Current Protection
Detect Current

OVP - 5.6 - V

OCP - 250 375 mA VOUT=0V

【Sensor Interface】

SBIAS
Output Voltage

SBIAS
Maximum Output Current

SBIAS
Discharge Resister at OFF

SSENS Input Range VISS 0 -

VoS 2.85 3.0 3.15 V Io=200µA

IomaxS 30 - - mA

ROFFS - 1.0 1.5 kΩ

VoS×

255/256

V

ADC Resolution ADRES 8 bit

ADC Integral Calculus
Non-linearity

ADC Differential Calculus
Non-linearity

ADINL -3 - +3 LSB

ADDNL -1 - +1 LSB

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●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VBAT=3.6V, VIO=1.8V)

Parameter Symbol

【Regulator (LDO1)】

Output Voltage Vo1

Output Current Io1 - - 150 mA Vo=1.8V

Dropout Voltage Vsat1 - 0.2 0.3 V VBAT=2.5V, Io=150mA, Vo=2.8V

Load Stability ΔVo11 - 10 60 mV Io=1~150mA, Vo=1.8V

Input Voltage Stability ΔVo12 - 10 60 mV VBAT=3.4~4.5V, Io=50mA, Vo=1.8V

Ripple Rejection Ratio RR1 - 65 - dB

Short Circuit Current Limit Ilim1 - 200 400 mA Vo=0V

Discharge Resister at OFF ROFF1 - 1.0 1.5 kΩ

【Regulator (LDO2)】

Output Voltage Vo2

Output Current Io2 - - 150 mA Vo=2.5V

Dropout Voltage Vsat2 - 0.2 0.3 V VBAT=2.5V, Io=150mA, Vo=2.8V

Load Stability Δvo21 - 10 60 mV Io=1~150mA, Vo=2.5V

Input Voltage Stability Δvo22 - 10 60 mV VBAT=3.4~4.5V, Io=50mA, Vo=2.5V

Ripple Rejection Ratio RR2 - 65 - dB

Short Circuit Current Limit Ilim2 - 200 400 mA Vo=0V

Discharge Resister at OFF ROFF2 - 1.0 1.5 kΩ

Min. Typ. Max.

1.164 1.20 1.236 V Io=50mA

1.261 1.30 1.339 V Io=50mA

1.455 1.50 1.545 V Io=50mA

1.552 1.60 1.648 V Io=50mA

1.746 1.80 1.854 V Io=50mA <Initial Voltage>

2.134 2.20 2.266 V Io=50mA

2.328 2.40 2.472 V Io=50mA

2.425 2.50 2.575 V Io=50mA

2.522 2.60 2.678 V Io=50mA

2.619 2.70 2.781 V Io=50mA

2.716 2.80 2.884 V Io=50mA

2.813 2.90 2.987 V Io=50mA

2.910 3.00 3.090 V Io=50mA

3.007 3.10 3.193 V Io=50mA

3.104 3.20 3.296 V Io=50mA

3.201 3.30 3.399 V Io=50mA

1.164 1.20 1.236 V Io=50mA

1.261 1.30 1.339 V Io=50mA

1.455 1.50 1.545 V Io=50mA

1.552 1.60 1.648 V Io=50mA

1.746 1.80 1.854 V Io=50mA

2.134 2.20 2.266 V Io=50mA

2.328 2.40 2.472 V Io=50mA

2.425 2.50 2.575 V Io=50mA <Initial Voltage>

2.522 2.60 2.678 V Io=50mA

2.619 2.70 2.781 V Io=50mA

2.716 2.80 2.884 V Io=50mA

2.813 2.90 2.987 V Io=50mA

2.910 3.00 3.090 V Io=50mA

3.007 3.10 3.193 V Io=50mA

3.104 3.20 3.296 V Io=50mA

3.201 3.30 3.399 V Io=50mA

Limits

Unit Condition

f=100Hz, Vin=200mVp-p, Vo=1.2V
Io=50mA, BW=20Hz~20kHz

f=100Hz, Vin=200mVp-p, Vo=1.2V
Io=50mA, BW=20Hz~20kHz

Technical Note

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●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VBAT=3.6V, VIO=1.8V)

Parameter Symbol

【Regulator (LDO3)】

Output Voltage Vo3

Output Current Io3 - - 150 mA Vo=1.8V

Dropout Voltage Vsat3 - 0.2 0.3 V VBAT=2.5V, Io=150mA, Vo=2.8V

Load Stability ΔVo31 - 10 60 mV Io=1~150mA, Vo=1.8V

Input Voltage Stability ΔVo32 - 10 60 mV VBAT=3.4~4.5V, Io=50mA, Vo=1.8V

Ripple Rejection Ratio RR3 - 65 - dB

Short Circuit Current Limit Ilim3 - 200 400 mA Vo=0V

Discharge Resister at OFF ROFF3 - 1.0 1.5 kΩ

【Regulator (LDO4)】

Output Voltage Vo4

Output Current Io4 - - 150 mA Vo=2.8V

Dropout Voltage Vsat4 - 0.2 0.3 V VBAT=2.5V, Io=150mA, Vo=2.8V

Load Stability ΔVo41 - 10 60 mV Io=1~150mA, Vo=2.8V

Input Voltage Stability ΔVo42 - 10 60 mV VBAT=3.4~4.5V, Io=50mA, Vo=2.8V

Ripple Rejection Ratio RR4 - 65 - dB

Short Circuit Current Limit Ilim4 - 200 400 mA Vo=0V

Discharge Resister at OFF ROFF4 - 1.0 1.5 kΩ

Min. Typ. Max.

1.164 1.20 1.236 V Io=50mA

1.261 1.30 1.339 V Io=50mA

1.455 1.50 1.545 V Io=50mA

1.552 1.60 1.648 V Io=50mA

1.746 1.80 1.854 V Io=50mA <Initial Voltage>

2.134 2.20 2.266 V Io=50mA

2.328 2.40 2.472 V Io=50mA

2.425 2.50 2.575 V Io=50mA

2.522 2.60 2.678 V Io=50mA

2.619 2.70 2.781 V Io=50mA

2.716 2.80 2.884 V Io=50mA

2.813 2.90 2.987 V Io=50mA

2.910 3.00 3.090 V Io=50mA

3.007 3.10 3.193 V Io=50mA

3.104 3.20 3.296 V Io=50mA

3.201 3.30 3.399 V Io=50mA

1.164 1.20 1.236 V Io=50mA

1.261 1.30 1.339 V Io=50mA

1.455 1.50 1.545 V Io=50mA

1.552 1.60 1.648 V Io=50mA

1.746 1.80 1.854 V Io=50mA

2.134 2.20 2.266 V Io=50mA

2.328 2.40 2.472 V Io=50mA

2.425 2.50 2.575 V Io=50mA

2.522 2.60 2.678 V Io=50mA

2.619 2.70 2.781 V Io=50mA

2.716 2.80 2.884 V Io=50mA <Initial Voltage>

2.813 2.90 2.987 V Io=50mA

2.910 3.00 3.090 V Io=50mA

3.007 3.10 3.193 V Io=50mA

3.104 3.20 3.296 V Io=50mA

3.201 3.30 3.399 V Io=50mA

Limits

Unit Condition

f=100Hz, Vin=200mVp-p, Vo=1.2V
Io=50mA, BW=20Hz~20kHz

f=100Hz, Vin=200mVp-p, Vo=1.2V
Io=50mA, BW=20Hz~20kHz

Technical Note

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Technical Note

●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VBAT=3.6V, VIO=1.8V)

Parameter Symbol

Min. Typ. Max.

Limits

Unit Condition

【SDA, SCL】 (I2C Interface)

L Level Input Voltage VILI -0.3 - 0.25 ×VIO V

H Level Input Voltage VIHI 0.75 ×VIO - VBAT+0.3 V

Hysteresis of
Schmitt trigger Input

VhysI 0.05 ×VIO - - V

L Level Output Voltage VOLI 0 - 0.3 V SDA Pin, IOL=3 mA

Input Current linI - - 1 μA Input Voltage= 0.1×VIO ~ 0.9×VIO

【RESETB】 (CMOS Input Pin)

L Level Input Voltage VILR -0.3 - 0.25 ×VIO V

H Level Input Voltage VIHR 0.75 ×VIO - VBAT+0.3 V

Input Current IinR - - 1 μA Input Voltage = 0.1×VIO ~ 0.9×VIO

【WPWMIN】 (NMOS Input Pin)

L Level Input Voltage VILA -0.3 - 0.3 V

H Level Input Voltage VIHA 1.4 - VBAT+0.3 V

Input Current IinA - 3.6 10 μA Input Voltage = 1.8V

PWM Input Minimum
High Pulse Width

PWmin 250 - - μs WPWMIN Pin

【GC1, GC2】 (Sensor Gain Control CMOS Output Pin)

L Level Output Voltage VOLS - - 0.2 V IOL=1mA

H Level Output Voltage VOHS VoS-0.2 - - V IOH=1mA

●Power Dissipation (On the ROHM’s standard board)

1.6

1.4

1280mW

1.2

W)

（

1.0

0.8

0.6

0.4

Power Dissipation Pd

0.2

0.0
0 25 50 75 100 125 150

Ta(℃)

Information of the ROHM’s standard board

Material: glass-epoxy
Size : 50mm×58mm×1.75mm(8

th

layer)

Wiring pattern figure Refer to after page.

Fig.1 Power Dissipation

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●Block Diagram / Application Circuit Example 1

6LED + ALC +PWM

1μF/10V

Technical Note

1μF/10V

C2N

OVP

C2P

TSD

CPGND

C6B5

A5

VOUT

D6

1μF/10V

LED1

A2

LED2

B1

LED3

B2

LED4

C2

LED5

D1

LED6

D2

LEDGND

C1

6LED
Main Back Light

IREF

LDO1

Vo Selectable

VREF

A3

GND1

Io=150mA

LDO2

Vo Selectable

Io=150mA

LDO3

Vo Selectable

Io=150mA

LDO4

Vo Selectable

Io=150mA

LDO1O

E6

LDO2O

E5

LDO3O

E4

LDO4O

E3

1μF/6.3V

1μF/6.3V

1μF/6.3V

1μF/6.3V

From CPU

From LCM

VIO Voltage

<ALS>

GC1

BH1621FVC

GC2

VBAT

GND

VBATCP

2.2µF/10V

RESETB

WPWMIN

SBIAS

VCC

1μF/6.3V

IOUT

VBAT1

VBAT2

VIO

SCL

SD

SSENS

SGND

GC2

GC1

C1P

C1N

A4

C5

B6

F4

F5

Charge Pump
Mode Control

D5

B4

C4

Level

D4

B3

F3

E1

F2

D3

E2

I/O

Sensor

I/F

Shift

A6 F1

T2

Charge Pump

x1 / x1.5 / x2

I2C interface

Digital Control

LED

control

(ALC)

A1 F6

T4

T3

T1

(Open)

(Open)

LED terminal voltage feedback

Fig.2 Block Diagram / Application Circuit Example 1

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●Block Diagram / Application Circuit Example 2

5LED + ALC +PWM

1μF/10V

Technical Note

1μF/10V

From CPU

From LCM

VIO Voltage

<ALS>

GC1

BH1621FVC

GC2

VBAT

GND

VBATCP

2.2µF/10V

RESETB

WPWMIN

SBIAS

VCC

1μF/6.3V

IOUT

VBAT1

VBAT2

VIO

SCL

SD

SSENS

SGND

GC2

GC1

C2N

OVP

C2P

TSD

CPGND

C6B5

A5

VOUT

D6

1μF/10V

LED1

A2

LED2

B1

LED3

B2

LED4

C2

LED5

D1

LED6

D2

LEDGND

C1

5LED
Main Back Light

IREF

LDO1

Vo Selectable

VREF

A3

GND1

Io=150mA

LDO2

Vo Selectable

Io=150mA

LDO3

Vo Selectable

Io=150mA

LDO4

Vo Selectable

Io=150mA

LDO1O

E6

LDO2O

E5

LDO3O

E4

LDO4O

E3

1μF/6.3V

1μF/6.3V

1μF/6.3V

1μF/6.3V

C1P

C1N

A4

C5

B6

F4

F5

Charge Pump
Mode Control

D5

B4

C4

Level

D4

B3

F3

E1

F2

D3

E2

I/O

Sensor

I/F

Shift

A6 F1

T2

Charge Pump

x1 / x1.5 / x2

I2C interface

Digital Control

LED

control

(ALC)

A1 F6

T4

T3

T1

(Open)

(Open)

LED terminal voltage feedback

Fig.3 Block Diagram / Application Circuit Example 2

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●Block Diagram / Application Circuit Example 3

4LED + 2LED + ALC +PWM

1μF/10V

Technical Note

1μF/10V

C2N

OVP

C2P

TSD

CPGND

C6B5

A5

VOUT

D6

1μF/10V

LED1

A2

LED2

B1

LED3

B2

LED4

C2

LED5

D1

LED6

D2

LEDGND

C1

6LED
Main Back Light

2LED
Sub Back Light
or
Key Back Light

IREF

LDO1

Vo Selectable

VREF

A3

GND1

Io=150mA

LDO2

Vo Selectable

Io=150mA

LDO3

Vo Selectable

Io=150mA

LDO4

Vo Selectable

Io=150mA

LDO1O

E6

LDO2O

E5

LDO3O

E4

LDO4O

E3

1μF/6.3V

1μF/6.3V

1μF/6.3V

1μF/6.3V

From CPU

From LCM

VIO Voltage

<ALS>

GC1

BH1621FVC

GC2

VBAT

GND

VBATCP

2.2µF/10V

RESETB

WPWMIN

SBIAS

VCC

1μF/6.3V

IOUT

VBAT1

VBAT2

VIO

SCL

SD

SSENS

SGND

GC2

GC1

C1P

C1N

A4

C5

B6

F4

F5

Charge Pump
Mode Control

D5

B4

C4

Level

D4

B3

F3

E1

F2

D3

E2

I/O

Sensor

I/F

Shift

A6 F1

T2

Charge Pump

x1 / x1.5 / x2

I2C interface

Digital Control

LED

control

(ALC)

A1 F6

T4

T3

T1

(Open)

(Open)

LED terminal voltage feedback

Fig.4 Block Diagram / Application Circuit Example 3

.

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BD6083GUL

●Pin Arrangement ［Bottom View］

F T4 SGND SBIAS VBAT1 VBAT2 T3

E SSENS GC1 LDO4O LDO3O LDO2O LDO1O

D LED5 LED6 GC2 SDA VIO VOUT

Technical Note

index

C LEDGND LED4

B LED2 LED3 WPWMIN RESETB C2N VBATCP

A T1 LED1 GND1 C1N CPGND T2

1 2 3 4 5 6

Total 35 Ball

SCL C1P C2P

Fig.5 Pin Arrangement

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●Package Outline

VCSP50L3 CSP small package
SIZE : 3.15mm x 3.15mm (A difference in public:X,Y Both ±0.05mm)
Height : 0.55mm max
A ball pitch : 0.5 mm

Fig.6 Package Outline

Technical Note

(Unit : mm)

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BD6083GUL

●Pin Functions

No Ball No. Pin Name I/O

1 B6 VBATCP - - GND Battery is connected A

2 F4 VBAT1 - - GND Battery is connected A

3 F5 VBAT2 - - GND Battery is connected A

4 A1 T1 O VBAT GND Test Output Pin(Open) N

5 A6 T2 I VBAT GND Test Input Pin (short to Ground) S

6 F6 T3 O VBAT GND Test Output Pin(Open) M

7 F1 T4 I VBAT GND Test Input Pin (short to Ground) S

8 D5 VIO - VBAT GND I/O Power supply is connected C

9 B4 RESETB I VBAT GND Reset input (L: reset, H: reset cancel) H

10 D4 SDA I/O VBAT GND I2C data input / output I

11 C4 SCL I VBAT GND I2C clock input H

12 A5 CPGND - VBAT - Ground B

13 A3 GND1 - VBAT - Ground B

14 C1 LEDGND - VBAT - Ground B

15 A4 C1N I/O VBAT GND Charge Pump capacitor is connected F

16 C5 C1P I/O - GND Charge Pump capacitor is connected G

17 B5 C2N I/O VBAT GND Charge Pump capacitor is connected F

18 C6 C2P I/O - GND Charge Pump capacitor is connected G

19 D6 VOUT O - GND Charge Pump output pin A

20 A2 LED1 I - GND LED is connected 1 for LCD Back Light E

21 B1 LED2 I - GND LED is connected 2 for LCD Back Light E

22 B2 LED3 I - GND LED is connected 3 for LCD Back Light E

23 C2 LED4 I - GND LED is connected 4 for LCD Back Light E

24 D1 LED5 I - GND LED is connected 5 for LCD Back Light E

25 D2 LED6 I - GND LED is connected 6 for LCD Back Light E

26 F3 SBIAS O VBAT GND Bias output for the Ambient Light Sensor Q

27 E1 SSENS I VBAT GND Ambient Light Sensor input N

28 E2 GC1 O VBAT GND Ambient Light Sensor gain control output 1 X

29 D3 GC2 O VBAT GND Ambient Light Sensor gain control output 2 X

30 F2 SGND - VBAT - Ground B

31 B3 WPWMIN I VBAT GND External PWM input for Back Light * L

32 E6 LDO1O O VBAT GND LDO1 output pin Q

33 E5 LDO2O O VBAT GND LDO2 output pin Q

34 E4 LDO3O O VBAT GND LDO3 output pin Q

35 E3 LDO4O O VBAT GND LDO4 output pin Q

* A setup of a register is separately necessary to make it effective.

ESD Diode

For Power For Ground

Functions

Technical Note

Equivalent

Circuit

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BD6083GUL

●Equivalent Circuit

A VBATB E

C

VBAT

Technical Note

F

VBAT

J

Q

VBAT VBAT

G

VIO VBAT

R

VBATVBAT L

VBATVBAT

H

M

VBAT VBAT

S

VIOVBAT

VBATVBAT

I

N

U

VIO VBAT

VBAT

VBAT VBAT V

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VBAT W

VIO

Fig.7 Equivalent Circuit

X

VoS VBAT

12/45

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VIO VBAT

2010.07 - Rev.

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BD6083GUL

Technical Note

●I2C BUS Format

The writing/reading operation is based on the I

2

C slave standard.

・Slave address

A7 A6 A5 A4 A3 A2 A1 R/W

1 1 1 0 1 1 0 1/0

・Bit Transfer

SCL transfers 1-bit data during H. SCL cannot change signal of SDA during H at the time of bit transfer. If SDA changes
while SCL is H, START conditions or STOP conditions will occur and it will be interpreted as a control signal.

SDA

SCL

SDA a state of stability

Data are effective

SDA

：

It can change

Fig.8

・START and STOP condition

When SDA and SCL are H, data is not transferred on the I

2

C- bus. This condition indicates, if SDA changes from H to L
while SCL has been H, it will become START (S) conditions, and an access start, if SDA changes from L to H while SCL
has been H, it will become STOP (P) conditions and an access end.

SDA

SCL

S P

START condition

STOP condition

Fig.9

・Acknowledge

It transfers data 8 bits each after the occurrence of START condition. A transmitter opens SDA after transfer 8bits data, and
a receiver returns the acknowledge signal by setting SDA to L.

DATA OUTPUT
BY TRANSMITTER

DATA OUTPUT
BY RECEIVER

SCL

START condition

S

12 89

not acknowledge

acknowledge

clock pulse for
acknowledgement

Fig.10

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A

BD6083GUL

AAA

A

A

A

A

A

A

A2A1A

A

A

A

A

A

A

A

A A

A

A

A6A5A4A3A2A1A

A

A

A

A

Technical Note

・Writing protocol

A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The 3rd
byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register address is
carried out automatically. However, when a register address turns into the last address, it is set to 00h by the next
transmission. After the transmission end, the increment of the address is carried out.

*1 *1

X X X X X X X

S

7

6

R/W=0(write)

from master to slave

from slave to master

register addressslave address

5

4

3

D7D6 D5 D4 D3D2 D1 D0 D7 D6D5 D4 D3 D2 D1 D0

00

DATA

register address

increment

=acknowledge(SDA LOW)

=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
*1: Write Timing

DATA

register address

increment

P

Fig.11

・Reading protocol

It reads from the next byte after writing a slave address and R/W bit. The register to read considers as the following
address accessed at the end, and the data of the address that carried out the increment is read after it. If an address turns
into the last address, the next byte will read out 00h. After the transmission end, the increment of the address is carried
out.

X X X X X X X

R/W=1(read)

from master to slave

from slave to master

P

DATA

register address

increment

=acknowledge(SDA LOW)

=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition

DATA slave address

register address

increment

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

1 S

Fig.12

・Multiple reading protocols

After specifying an internal address, it reads by repeated START condition and changing the data transfer direction. The
data of the address that carried out the increment is read after it. If an address turns into the last address, the next byte will
read out 00h. After the transmission end, the increment of the address is carried out.

S

slave address

R/W=0(write)

from master to slave

from slave to master

0

7

register address

D7 D6 D5 D4 D3D2D1D0 D7 D6 D5 D4 D3 D2 D1D0

DATA DATA

register address

increment

Sr 1

0X X X X X X X

X X X X X X X

slave address

=acknowledge(SDA LOW)

=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
Sr=repeated START condition

R/W=1(read)

P

register address

increment

Fig.13

As for reading protocol and multiple reading protocols, please do A(not acknowledge) after doing the final reading
operation. It stops with read when ending by A(acknowledge), and SDA stops in the state of Low when the reading data of
that time is 0. However, this state returns usually when SCL is moved, data is read, and A (not acknowledge) is done.

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