ROHM’s BD48xxx and BD49xxx series are highly
accurate, low current consumption reset IC series. The
line up includes BD48xxx devices with N channel open
drain output and BD49xxx devices with CMOS output.
The devices are available for specific detection voltages
ranging from 2.3V to 6.0V in increments of 0.1V.
●Features
High accuracy detection
Ultra-low current consumption
Two output types (Nch open drain and CMOS output)
Wide Operating temperature range
Very small and low height package
Package SSOP5 is similar to SOT-23-5 (JEDEC)
Package SSOP3 is similar to SOT-23-3 (JEDEC)
●Ty pical A pplication Circuit
Datasheet
●Key Specifications
Detection voltage: 2.3V to 6.0V (Typ.),
0.1V steps
High accuracy detection voltage: ±1.0%
Ultra-low current consumption: 0.9A (Typ.)
Operating temperature range: -40°C to +105°C
●Package
SSOP5: 2.90mm x 2.80mm x 1.15mm
SSOP3: 2.90mm x 2.80mm x 1.15mm
VSOF5: 1.60 mm x 1.60mm x 0.60mm
●Applications
Circuits using microcontrollers or logic circuits that
require a reset.
DD1
V
○Product structure:Silicon monolithic integrated circuit ○This product is not designed protection against radioactive rays.
*1 Use above Ta=25°C results in a 5.4mW loss per degree.
*2 Use above Ta=25°C results in a 2.1mW loss per degree.
*3 When a ROHM standard circuit board (70mm×70mm×1.6mm glass epoxy board) is mounted.
●Electrical Characteristics (Unless Otherwise Specified Ta=-40 to 105°C)
For both the open drain type (Fig.12) and the CMOS output type (Fig.13), the detection and release voltages are used as
threshold voltages. When the voltage applied to the V
pins reaches the applicable threshold voltage, the V
DD
OUT
voltage switches from either “High” to “Low” or from “Low” to “High”. Please refer to the Timing Waveform and Electrical
Characteristics for information on hysteresis.
or another
DD
Because the BD48xxx series uses an open drain output type, it is possible to connect a pull-up resistor to V
power supply [The output “High” voltage (V
R1
Vref
R2
R3
) in this case becomes VDD or the voltage of the other power supply].
OUT
Q1
V
DD
R
L
V
OUT
GND
Vref
R1
R2
R3
Q2
Q1
Fig.12 (BD48xxx series Internal Block Diagram) Fig.13 (BD49xxx series Internal Block Diagram)
Reference Data
Examples of Leading (t
Part Number t
) and Falling (t
PLH
) Output
PHL
(s) t
PLH
PHL
(s)
BD48x45 39.5 87.8
BD49x45 32.4 52.4
V
=4.3VÆ5.1V VDD=5.1VÆ4.3V
DD
*This data is for reference only.
The figures will vary with the application, so please confirm actual operating conditions before use.
Timing Waveform
Example: the following shows the relationship between the input voltages VDD and the output voltage V
input power supply voltage V
is made to sweep up and sweep down (the circuits are those in Fig.12 and 13).
DD
when the
OUT
1
When the power supply is turned on, the output is unsettled from
VDD
VDET+ΔVDET
V
OUT
0V
VOH
VOL
VDET
VOPL
tPHL
tPLH
tPHL
①
②
③ ④
Fig.14 Timing Waveform
⑤
tPLH
after over the operating limit voltage (V
possible that the reset signal is not valid when the rise time of V
DET
PHL
+ V
.
but less than the reset release
OPL
), the output voltages will switch to Low.
DET
faster than t
2
When VDD is greater than V
voltage (V
3
If VDD exceeds the reset release voltage (V
V
switches from L to H.
OUT
4
If VDD drops below the detection voltage (V
supply is powered down or when there is a power supply fluctuation,
switches to L (with a delay of t
V
OUT
5
The potential difference between the detection voltage and the
PHL
release voltage is known as the hysteresis width (V
system is designed such that the output does not flip-flop with power
).
OPL
) until t
DET
. Therefore it is
PHL
+ V
DET
) when the power
supply fluctuations within this hysteresis width, preventing
malfunctions due to noise.
Examples of a common power supply detection reset circuit.
DD1
V
L
R
BD48xxx
C
L
capacitor is for
(
noise filtering
R
ST
Micro
controller
)
Fig.15 Open Drain Output Type
DD1
V
BD49xxx
C
capacitor is for
(
filtering
ST
R
L
)
GND
Fig.16 CMOS Output Type
DD2
V
GND
Micro
controller
Datasheet
Application examples of BD48xxx series (Open Drain
output type) and BD49xxx series (CMOS output type) are
shown below.
CASE1: the power supply of the microcontroller (V
differs from the power supply of the reset detection (V
Use an open drain output type (BD48xxx) device with a
load resistance R
CASE2: the power supply of the microcontroller (V
same as the power supply of the reset detection (V
Use a CMOS output type (BD49xxx) device or an open
drain device with a pull up resistor between output and
VDD1.
When a capacitance C
the V
pin (the reset signal input terminal of the
OUT
microcontroller), please take into account the waveform of
the rise and fall of the output voltage (V
The Electrical characteristics were measured using
Absolute Maximum Ratings are those values beyond which the life of a device may be destroyed. We cannot be defined the
failure mode, such as short mode or open mode. Therefore a physical security countermeasure, like fuse, is to be given when
a specific mode to be beyond absolute maximum ratings is considered.
2 . GND potential
GND terminal should be a lowest voltage potential every state.
Please make sure all pins, which are over ground even if, include transient feature.
3 . Electrical Characteristics
Be sure to check the electrical characteristics that are one the tentative specification will be changed by temperature, supply
voltage, and external circuit.
4 . Bypass Capacitor for Noise Rejection
Please put into the capacitor of 1F or more between V
pin and GND, and the capacitor of about 1000pF between V
DD
OUT
and GND, to reject noise. If extremely big capacitor is used, transient response might be late. Please confirm sufficiently for the
point.
5 . Short Circuit between Terminal and Soldering
Don’t short-circuit between Output pin and V
pin, Output pin and GND pin, or VDD pin and GND pin. When soldering the IC
DD
on circuit board, please be unusually cautious about the orientation and the position of the IC. When the orientation is
mistaken the IC may be destroyed.
6 . Electromagnetic Field
Mal-function may happen when the device is used in the strong electromagnetic field.
7 . The V
line inpedance might cause oscillation because of the detection current.
DD
8. A V
-GND capacitor (as close connection as possible) should be used in high VDD line impedance condition.
DD
9 . Lower than the mininum input voltage makes the V
OUT high impedance, and it must be VDD in pull up (VDD) condition.
10. This IC has extremely high impedance terminals. Small leak current due to the uncleanness of PCB surface might cause
unexpected operations. Application values in these conditions should be selected carefully. If the leakage is assumed
between the V
terminal and the GND terminal, the pull-up resistor should be less than 1/10 of the assumed leakage
OUT
resistance.
11. External parameters
The recommended parameter range for R
is 10k to 1M. There are many factors (board layout, etc) that can affect
L
characteristics. Please verify and confirm using practical applications.
12. Power on reset operation
Please note that the power on reset output varies with the V
rise up time. Please verify the actual operation.
DD
13. Precautions for board inspection
Connecting low-impedance capacitors to run inspections with the board may produce stress on the IC. Therefore, be certain
to use proper discharge procedure before each process of the test operation.
To prevent electrostatic accumulation and discharge in the assembly process, thoroughly ground yourself and any
equipment that could sustain ESD damage, and continue observing ESD-prevention procedures in all handing, transfer and
storage operations. Before attempting to connect components to the test setup, make certain that the power supply is OFF.
Likewise, be sure the power supply is OFF before removing any component connected to the test setup.
14. When the power supply, is turned on because of in certain cases, momentary Rash-current flow into the IC at the logic
unsettled, the couple capacitance, GND pattern of width and leading line must be considered.
pin
Status of this document
The Japanese version of this document is formal specification. A customer may use this translation version only for a reference
to help reading the formal version.
If there are any differences in translation version of this document formal version takes priority.
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