Rohde&Schwarz R&S®EGTSL - Enhanced Generic Test Software Library User Manual
R&S®EGTSL
Enhanced Generic Test Software
Library
User Manual
(;[YXZ)
1143414042
Version 16
This Software Description is valid for the following software versions.
●
R&S®GTSL version 3.00 and higher versions
●
R&S®EGTSL version 3.00 and higher versions
© 2021 Rohde & Schwarz GmbH & Co. KG
Mühldorfstr. 15, 81671 München, Germany
Phone: +49 89 41 29 - 0
Email: info@rohde-schwarz.com
Internet: www.rohde-schwarz.com
Subject to change – data without tolerance limits is not binding.
R&S® is a registered trademark of Rohde & Schwarz GmbH & Co. KG.
Trade names are trademarks of the owners.
1143.4140.42 | Version 16 | R&S®EGTSL
The following abbreviations are used throughout this manual: R&S®EGTSL is abbreviated as R&S EGTSL.
R&S®EGTSL
Contents
Contents
1 General..................................................................................................15
1.1 User Information......................................................................................................... 15
1.2 Reference Documents................................................................................................ 15
1.3 Explanation of Symbols............................................................................................. 15
2 Software Installation............................................................................16
2.1 General.........................................................................................................................16
2.2 Installation................................................................................................................... 16
2.3 File Structure............................................................................................................... 16
3 Functional Description........................................................................ 19
3.1 General.........................................................................................................................19
3.2 ICT Test Library........................................................................................................... 20
3.2.1 General......................................................................................................................... 20
3.2.2 Entries in PHYSICAL.INI...............................................................................................21
3.2.3 Entries in APPLICATION.INI......................................................................................... 22
3.2.4 Functions.......................................................................................................................24
3.3 R&S EGTSL Loader.....................................................................................................25
3.4 R&S EGTSL user interface (R&S EGTSL IDE).......................................................... 25
3.5 Automatic Test Generator ATG..................................................................................27
3.6 ICT Correction Data.................................................................................................... 27
3.7 Hardware for in-circuit test........................................................................................ 27
4 Getting Started..................................................................................... 28
4.1 General.........................................................................................................................28
4.2 Development Process for an In-circuit Test............................................................. 28
4.3 Preparation of the Circuit Documentation................................................................28
4.3.1 Example Circuit............................................................................................................. 29
4.3.2 Preparation of the Circuit Description........................................................................... 29
4.3.2.1 Entry of the Resistors....................................................................................................30
4.3.2.2 Entry of Capacitors........................................................................................................30
4.3.2.3 Entry of the Transistor...................................................................................................32
4.4 Preparing the ICT program.........................................................................................33
3User Manual 1143.4140.42 ─ 16
R&S®EGTSL
5.4.1 Positioning of the Subwindows..................................................................................... 39
5.4.2 Program Subwindow..................................................................................................... 40
5.4.2.1 Context Menu................................................................................................................41
5.4.3 Report Subwindow........................................................................................................ 42
5.4.3.1 Context Menu................................................................................................................42
Contents
4.5 Adapter Manufacture.................................................................................................. 34
4.6 Commissioning and Debugging................................................................................ 34
5 User Interface (R&S EGTSL IDE)........................................................ 37
5.1 General.........................................................................................................................37
5.2 Menu Structure............................................................................................................38
5.3 Main Screen................................................................................................................. 39
5.4 Subwindow.................................................................................................................. 39
5.4.4 Test Properties Subwindow...........................................................................................43
5.4.5 Results Subwindow.......................................................................................................43
5.4.5.1 Context Menu................................................................................................................43
5.4.5.2 Results Tbl.................................................................................................................... 44
5.4.5.3 Results Gfx....................................................................................................................44
5.4.5.4 Results Hist................................................................................................................... 45
5.4.5.5 Results Details.............................................................................................................. 45
5.4.6 Debug Subwindow........................................................................................................ 46
5.5 Test Steps.................................................................................................................... 47
5.5.1 Contact..........................................................................................................................47
5.5.1.1 General......................................................................................................................... 47
5.5.1.2 Results Details.............................................................................................................. 48
5.5.2 Continuity...................................................................................................................... 49
5.5.2.1 General......................................................................................................................... 49
5.5.2.2 Timing............................................................................................................................50
5.5.2.3 Results Details.............................................................................................................. 51
5.5.3 Diode.............................................................................................................................51
5.5.3.1 Limits.............................................................................................................................52
5.5.3.2 Settings......................................................................................................................... 53
5.5.3.3 CNX...............................................................................................................................55
5.5.3.4 Timing............................................................................................................................55
4User Manual 1143.4140.42 ─ 16
R&S®EGTSL
5.5.3.5 Results Details.............................................................................................................. 57
5.5.4 Discharge...................................................................................................................... 57
5.5.4.1 General......................................................................................................................... 58
5.5.4.2 Results Details.............................................................................................................. 58
5.5.5 FET............................................................................................................................... 59
5.5.5.1 Limits.............................................................................................................................59
5.5.5.2 Settings......................................................................................................................... 60
5.5.5.3 Measurement................................................................................................................ 62
5.5.5.4 CNX...............................................................................................................................62
5.5.5.5 Timing............................................................................................................................63
5.5.5.6 Results Details.............................................................................................................. 64
5.5.6 Impedance.................................................................................................................... 65
5.5.6.1 Limits.............................................................................................................................66
Contents
5.5.6.2 Method.......................................................................................................................... 67
5.5.6.3 Settings......................................................................................................................... 69
5.5.6.4 Timing............................................................................................................................71
5.5.6.5 Determination of Measured Value................................................................................. 72
5.5.6.6 Results Details.............................................................................................................. 73
5.5.7 Resistor......................................................................................................................... 75
5.5.7.1 Limits.............................................................................................................................75
5.5.7.2 Method.......................................................................................................................... 76
5.5.7.3 Settings......................................................................................................................... 78
5.5.7.4 Timing............................................................................................................................80
5.5.7.5 Results Details.............................................................................................................. 81
5.5.8 Short..............................................................................................................................82
5.5.8.1 General......................................................................................................................... 82
5.5.8.2 Timing............................................................................................................................84
5.5.8.3 Results Details.............................................................................................................. 84
5.5.9 Transistor...................................................................................................................... 85
5.5.9.1 Limits.............................................................................................................................85
5.5.9.2 Settings......................................................................................................................... 86
5.5.9.3 CNX...............................................................................................................................87
5.5.9.4 Timing............................................................................................................................88
5User Manual 1143.4140.42 ─ 16
R&S®EGTSL
5.5.9.5 Results Details.............................................................................................................. 89
5.5.10 Transistor Beta..............................................................................................................90
5.5.10.1 Limits.............................................................................................................................90
5.5.10.2 Settings......................................................................................................................... 91
5.5.10.3 Measurement................................................................................................................ 93
5.5.10.4 CNX...............................................................................................................................94
5.5.10.5 Timing............................................................................................................................95
5.5.10.6 Results Details.............................................................................................................. 96
5.5.11 Zener Diode.................................................................................................................. 97
5.5.11.1 Limits.............................................................................................................................98
5.5.11.2 Settings......................................................................................................................... 99
5.5.11.3 CNX.............................................................................................................................100
5.5.11.4 Timing..........................................................................................................................101
Contents
5.5.11.5 Results Details............................................................................................................ 102
5.5.12 Explanations................................................................................................................103
5.5.12.1 Timing..........................................................................................................................103
5.5.12.2 Editing Pin Lists...........................................................................................................105
5.5.13 User-defined Test Methods......................................................................................... 107
5.5.13.1 Limits...........................................................................................................................107
5.5.13.2 Settings....................................................................................................................... 108
5.5.13.3 Info.............................................................................................................................. 109
5.5.13.4 Results Details............................................................................................................ 109
5.6 Menu bar Functions.................................................................................................. 110
5.6.1 Main Menu Command <File>...................................................................................... 110
5.6.1.1 Menu Command <Open>............................................................................................110
5.6.1.2 Menu Command <Save>.............................................................................................111
5.6.1.3 Menu Command <Save Copy As>.............................................................................. 111
5.6.1.4 Menu Command <Select>........................................................................................... 111
5.6.1.5 Menu Command <Close>............................................................................................112
5.6.1.6 Menu Command <Program Properties>......................................................................112
5.6.1.7 Menu Command <Limits>........................................................................................... 114
5.6.1.8 Menu Command <Print>............................................................................................. 117
5.6.1.9 Menu Command <Print Setup>...................................................................................117
6User Manual 1143.4140.42 ─ 16
R&S®EGTSL
5.6.1.10 Menu Command <Exit>...............................................................................................118
5.6.2 Main Menu Command <Edit>......................................................................................119
5.6.2.1 Functions.....................................................................................................................119
5.6.2.2 Menu Command <Find>............................................................................................. 120
5.6.2.3 Menu Command <Step Properties>............................................................................121
5.6.2.4 Menu Point <Breakpoints>..........................................................................................124
5.6.3 Main Menu Command <View>....................................................................................125
5.6.4 Main Menu Command <Debug>................................................................................. 125
5.6.5 Main Menu Command <Report>.................................................................................127
5.6.6 Main Menu Command <Help>.................................................................................... 127
5.6.6.1 Menu Command <About EGTSL>.............................................................................. 127
5.7.1 Main Toolbar................................................................................................................128
Contents
5.7 Toolbar Functions..................................................................................................... 128
5.7.2 Debug Toolbar.............................................................................................................130
5.7.3 Toolbar for Insert......................................................................................................... 131
5.7.4 Toolbar for User-defined Tests.................................................................................... 132
5.8 Shortcuts................................................................................................................... 132
6 License Management.........................................................................134
7 Configuration Files............................................................................ 136
7.1 Syntax........................................................................................................................ 136
7.1.1 Naming Conventions...................................................................................................136
7.1.2 [LogicalNames] Section.............................................................................................. 137
7.1.3 [Device] Section.......................................................................................................... 138
7.1.4 [Bench] Section........................................................................................................... 139
7.1.5 [ResourceManager] Section........................................................................................140
7.1.6 [Extlct] Section............................................................................................................ 140
7.2 PHYSICAL.INI............................................................................................................ 140
7.2.1 Example File for PHYSICAL.INI (Example_Physical.ini)............................................ 141
7.2.2 Description of example file PHYSICAL.INI..................................................................141
7.3 APPLICATION.INI.......................................................................................................143
7.3.1 Example File for APPLICATION.INI (Example_Application.ini)...................................143
7.3.2 Description of Example File APPLICATION.INI.......................................................... 144
7User Manual 1143.4140.42 ─ 16
R&S®EGTSL
8.1.1 Terminology, Symbols................................................................................................. 147
8.1.2 Structure of a Metaprogram........................................................................................ 148
8.1.3 Structure of Rule Bodies............................................................................................. 148
8.2.1 Syntax......................................................................................................................... 151
8.2.1.1 Resistor List................................................................................................................ 151
8.2.1.2 Variable Resistor List...................................................................................................152
8.2.1.3 Potentiometer List....................................................................................................... 152
8.2.1.4 Resistor Array List.......................................................................................................153
8.2.1.5 Capacitor List.............................................................................................................. 153
8.2.1.6 Pol. Capacitor List....................................................................................................... 153
Contents
8 Circuit Description.............................................................................147
8.1 Definition of Meta Language.................................................................................... 147
8.2 External File Format (BDL).......................................................................................151
8.2.1.7 Inductor List.................................................................................................................154
8.2.1.8 Diode List.................................................................................................................... 154
8.2.1.9 LED List.......................................................................................................................155
8.2.1.10 Zener Diode List..........................................................................................................155
8.2.1.11 Transistor List..............................................................................................................156
8.2.1.12 Jumper List..................................................................................................................156
8.2.1.13 IC List.......................................................................................................................... 157
8.2.1.14 Connector List............................................................................................................. 157
8.2.1.15 Black Box List..............................................................................................................157
8.2.1.16 Track List.....................................................................................................................158
8.2.1.17 Node List..................................................................................................................... 158
8.2.1.18 Basic Constructs......................................................................................................... 158
8.2.1.19 FET List.......................................................................................................................160
8.2.2 Semantics................................................................................................................... 160
8.2.2.1 General....................................................................................................................... 160
8.2.2.2 Resistor List................................................................................................................ 162
8.2.2.3 Variable Resistor List...................................................................................................163
8.2.2.4 Potentiometer List....................................................................................................... 163
8.2.2.5 Resistor Array List.......................................................................................................164
8.2.2.6 Capacitor List.............................................................................................................. 166
8User Manual 1143.4140.42 ─ 16
R&S®EGTSL
8.2.2.7 Pol. Capacitor List....................................................................................................... 166
8.2.2.8 Inductor List.................................................................................................................167
8.2.2.9 Diode List.................................................................................................................... 168
8.2.2.10 LED List.......................................................................................................................170
8.2.2.11 Zener Diode List..........................................................................................................170
8.2.2.12 Transistor List..............................................................................................................171
8.2.2.13 Jumper List..................................................................................................................172
8.2.2.14 IC List.......................................................................................................................... 173
8.2.2.15 Connector List............................................................................................................. 173
8.2.2.16 Black Box List..............................................................................................................174
8.2.2.17 Track List.....................................................................................................................175
8.2.2.18 Node List..................................................................................................................... 175
8.2.2.19 FET List.......................................................................................................................176
Contents
8.3 Important Additional Information............................................................................ 177
8.3.1 Node List..................................................................................................................... 177
8.3.2 Treatment of Specific Pins.......................................................................................... 177
9 Automatic Test Generation with ATG............................................... 178
9.1 Function..................................................................................................................... 178
9.2 Starting the Automatic Test Generator ATG...........................................................179
9.3 Output Files............................................................................................................... 183
9.3.1 ICT Program................................................................................................................183
9.3.1.1 General....................................................................................................................... 183
9.3.1.2 Layout of the Test Program......................................................................................... 183
9.3.1.3 State of the Automatically Generated Test Program................................................... 183
9.3.1.4 Program Groups Generated........................................................................................184
9.3.1.5 Automatic Determination of the Guard Points in the Analog Test............................... 186
9.3.1.6 Safety Against Destruction of Components During the Test....................................... 186
9.3.1.7 Taking Account of Topological Problems.....................................................................186
9.3.2 ATG Report................................................................................................................. 187
9.3.2.1 Typical Warning Messages......................................................................................... 188
9.3.2.2 Alternative Proposals from the ATG............................................................................ 189
9.3.2.3 Test Coverage Report................................................................................................. 191
9.3.3 Application Layer Configuration File........................................................................... 192
9User Manual 1143.4140.42 ─ 16
R&S®EGTSL
9.3.4 Adapter Manufacture...................................................................................................193
9.3.5 ICC Program............................................................................................................... 194
10.1 Test Hardware............................................................................................................195
10.2 Ground Wiring........................................................................................................... 197
10.3 Contact Test...............................................................................................................197
10.4 Continuity Test.......................................................................................................... 199
10.5 Diode Test.................................................................................................................. 200
10.6 Discharging Capacitors............................................................................................201
10.7 FET Test..................................................................................................................... 202
10.8 Impedance Test......................................................................................................... 203
10.8.1 2- and 4-wire measurement........................................................................................ 204
Contents
10 Test Methods...................................................................................... 195
10.8.2 Guarded Measurement............................................................................................... 205
10.8.3 Correct Phase Impedance Measurement................................................................... 207
10.8.4 System Residuals....................................................................................................... 207
10.8.5 Fixture Residuals........................................................................................................ 208
10.8.6 Measuring Small Capacitors....................................................................................... 208
10.8.7 Measurement of Polarized Capacitors/Electrolytic Capacitors................................... 209
10.9 Resistor Test..............................................................................................................209
10.9.1 2-wire Measurement................................................................................................... 209
10.9.2 4-wire Measurement................................................................................................... 210
10.9.3 Guarded Measurement................................................................................................211
10.10 Short-circuit Test.......................................................................................................213
10.11 Transistor Test...........................................................................................................214
10.12 Transistor Beta..........................................................................................................214
10.13 Zener Diode............................................................................................................... 216
11 Creating Test Programs.....................................................................219
11.1 Program Groups........................................................................................................219
11.2 Variants...................................................................................................................... 220
11.2.1 Use..............................................................................................................................220
11.2.2 Definition..................................................................................................................... 221
11.2.3 Assignment................................................................................................................. 221
11.2.4 Execution.................................................................................................................... 222
10User Manual 1143.4140.42 ─ 16
R&S®EGTSL
11.3 Limit Files.................................................................................................................. 222
11.4 Multiple Panel Testing...............................................................................................222
11.4.1 Example of an Application Layer Configuration File for Multiple Uses........................223
12.1 Overview.................................................................................................................... 226
12.2 Starting and Terminating the Debugger..................................................................226
12.3 Debug Status............................................................................................................. 227
12.4 Using the Debugger.................................................................................................. 228
12.5 Breakpoints............................................................................................................... 230
12.6 Stop Conditions........................................................................................................ 230
12.7 Typical Debugging Procedure..................................................................................230
12.8 Measuring Time Optimization.................................................................................. 231
Contents
12 Debugger............................................................................................ 226
12.9 Interpretation of the Results Sub-window.............................................................. 232
12.9.1 Results Gfx Sub-Window............................................................................................ 232
12.9.2 Results Hist Sub-Window............................................................................................234
13 Running R&S EGTSL IDE..................................................................236
13.1 Starting Using a Function Call from the ICT Test Library..................................... 236
13.1.1 Example...................................................................................................................... 236
13.2 Starting Using the R&S EGTSL Loader...................................................................239
13.2.1 R&S EGTSL Loader, starting...................................................................................... 240
14 Report Format.................................................................................... 243
15 ICT Correction Data........................................................................... 246
15.1 System Residual Compensation............................................................................. 246
15.1.1 Normal Operation........................................................................................................246
15.1.2 Silent Operation.......................................................................................................... 249
15.1.2.1 Parameter................................................................................................................... 249
15.1.2.2 Exit Codes...................................................................................................................249
15.1.2.3 Programming Example................................................................................................250
15.2 Adapter Compensation.............................................................................................251
16 Error Messages.................................................................................. 258
16.1 Compile Errors.......................................................................................................... 258
16.2 Runtime Errors.......................................................................................................... 258
11User Manual 1143.4140.42 ─ 16
R&S®EGTSL
17.1 Overview.................................................................................................................... 261
17.1.1 Objective..................................................................................................................... 261
17.1.2 Functionality................................................................................................................ 261
17.2 Using Extension Libraries........................................................................................261
17.2.1 Configuration...............................................................................................................261
17.2.2 Documentation............................................................................................................ 262
17.2.3 Inserting Test Steps.....................................................................................................262
17.2.4 Grouping Test Steps....................................................................................................263
17.2.5 Running and Debugging Test Steps............................................................................263
17.3 Creating Extension Libraries................................................................................... 264
17.3.1 Overview..................................................................................................................... 264
17.3.1.1 Software Structure...................................................................................................... 264
Contents
17 ICT Extension Libraries.....................................................................261
17.3.1.2 Working Principle........................................................................................................ 264
17.3.1.3 Integrating Hardware Modules.................................................................................... 265
17.3.1.4 File Structure...............................................................................................................265
17.3.2 Sample Projects.......................................................................................................... 265
17.3.2.1 RSSample................................................................................................................... 266
17.3.2.2 RSSamplePSU............................................................................................................266
17.3.2.3 Framework.................................................................................................................. 266
17.3.3 Internal Structure.........................................................................................................267
17.3.3.1 Project Structure......................................................................................................... 267
17.3.3.2 Export Interface...........................................................................................................268
17.3.3.3 Data Structures........................................................................................................... 268
17.3.3.4 Support Functions....................................................................................................... 271
17.3.3.5 Bitmap......................................................................................................................... 271
17.3.4 Description of Function............................................................................................... 272
17.3.4.1 Header Files................................................................................................................272
17.3.4.2 Exported Variables...................................................................................................... 272
17.3.4.3 Local Data Structures..................................................................................................274
17.3.4.4 Configuration Functions.............................................................................................. 278
17.3.4.5 Test-related Functions.................................................................................................280
17.3.4.6 Functions for Displaying Results.................................................................................282
12User Manual 1143.4140.42 ─ 16
R&S®EGTSL
17.3.5 Details of Implementation............................................................................................283
17.3.5.1 Error Handling............................................................................................................. 283
17.3.5.2 Simulation................................................................................................................... 285
17.3.5.3 Tracing........................................................................................................................ 286
17.3.5.4 Locking........................................................................................................................287
17.3.6 R&S EGTSL-internal Hardware Modules....................................................................287
17.3.7 Additional Hardware Modules..................................................................................... 288
17.3.7.1 Configuration of Hardware Modules............................................................................288
17.3.7.2 Co-operative Session Concept................................................................................... 289
17.3.7.3 Setup...........................................................................................................................290
17.3.7.4 Cleanup.......................................................................................................................290
17.3.7.5 Prolog and Epilog........................................................................................................291
17.3.8 Advanced Topics......................................................................................................... 293
Contents
17.3.8.1 Debugging ICT Extension Libraries............................................................................ 293
17.3.8.2 Non-numeric Test Results........................................................................................... 293
17.3.8.3 Time Optimization....................................................................................................... 294
17.3.8.4 Aspects of Compatibility..............................................................................................294
17.3.8.5 Communication between ICT Extension Libraries...................................................... 295
Annex.................................................................................................. 296
A Example 1........................................................................................... 296
A.1 Circuit for Example 1................................................................................................ 296
A.2 BDL File for Example 1............................................................................................. 296
A.3 ICT Report Generated for Example 1...................................................................... 298
A.4 Application Layer Configuration File Generated for Example 1...........................299
B Example 2........................................................................................... 301
B.1 Circuit for Example 2................................................................................................ 301
B.2 BDL File for Example 2............................................................................................. 301
B.3 ICT Report Generated for Example 2...................................................................... 302
B.4 Application Layer Configuration File Generated for Example 2...........................303
13User Manual 1143.4140.42 ─ 16
R&S®EGTSL
Contents
14User Manual 1143.4140.42 ─ 16
R&S®EGTSL
1.1 User Information
1.2 Reference Documents
General
Explanation of Symbols
1 General
This software description applies to the following ROHDE & SCHWARZ products:
R&S TS-LEGT 1143.4140.02 Enhanced R&S GTSL Software
for ICT
R&S TS-LEG2 1166.3992.02 Enhanced R&S GTSL Software
for Basic ICT on R&S TS-PSAM
The Enhanced Generic Test Software Library R&S EGTSL is part of the Generic Test
Software Library R&S GTSL. For this reason, the following documentation is to be
noted in addition to this software description:
●
Software Description Generic Test Software Library R&S GTSL
The related test hardware is required for performing in-circuit tests. The test hardware
is described in the following documentation:
●
User Manual Test System Versatile Platform R&S CompactTSVP TS-PCA3
●
User Manual Test System Versatile Platform R&S PowerTSVP TS-PWA3
●
User Manual Analog Source and Measurement Module R&S TS-PSAM
●
User Manual ICT Extension Module R&S TS-PICT
●
User Manual Matrix Module B R&S TS-PMB
●
Documentation of the test adapter
1.3 Explanation of Symbols
Certain text passages in this software description are specially highlighted. The passages marked in this way have the following significance:
Incorrect measurements
Failure to follow instructions can result in incorrect measurements.
Highlights important details to which special attention must be paid and that make your
work easier.
15User Manual 1143.4140.42 ─ 16
R&S®EGTSL
2.1 General
Software Installation
File Structure
2 Software Installation
Enhanced Generic Test Software Library R&S EGTSL is installed using the installation
routine for the Generic Test Software Library R&S GTSL.
The Generic Test Software Library R&S GTSL can be downloaded from R&S GLORIS
server. After extracting the compressed installation file, the whole contents of the
installation can be found in the target directory. Please read the README.TXT file
before starting the installation by executing the setup.exe file.
To install the Generic Test Software Library R&S GTSL under Windows 10 or Windows
7, the user must be logged in as administrator or as a user with administrator rights.
For additional information on the de-installation of previous versions of the Generic
Test Software Library R&S GTSL or concerning installation, consult the README.TXT
file in the installation package and the chapter “Installation of R&S CompactTSVP and
R&S GTSL” of the “R&S System Manual TSVP”.
2.2 Installation
Refer to the "Installation" chapter of the R&S GTSL user manual.
Make sure that the "Enhanced GTSL" checkbox is marked in the "Select Features" dialog of the setup procedure.
2.3 File Structure
The test libraries supplied by ROHDE & SCHWARZ are stored in fixed directories at
the time of installation. The following directory structure can be found as subdirectories
below the R&S GTSL program files directory which was specified during the installation
process:
16User Manual 1143.4140.42 ─ 16
R&S®EGTSL
Software Installation
File Structure
Figure 2-1: File structure program files
Description of installed R&S GTSL program files directories:
Table 2-1: Program files directories
Directory Contents
GTSL Generic Test Software Library. The root directory for
the R&S GTSL software can have any name.
Bin Contains the test libraries (DLL, LIB) and the help
files (HLP, CHM) belonging to the test libraries.
Develop The subdirectories of the directory Develop contain
generally valid examples for the creation of a highlevel test library, a customer-specific selftest library
and two sample applications that show how to call
R&S GTSL functions and driver functions.
Documentation Contains the various items of documentation in PDF
file format.
EGTSL
●
Correction
EGTSL
●
Extlct
– Framework
– RSSample
– RSSamplePSU
Contains the utility ICTCorrection with which a correction data set can be determined.
The folder …\Framework contains the framework
code for the creation of a user-defined ICT extension library. The folder …\RSSample contains an
example for the creation of a user-defined ICT
extension library with source-code and binaries. The
RSSamplePSU project is similar to the RSSample
project, but uses the R&S TS-PSU module instead
of the R&S TS-PFG module.
EGTSL
●
Templates
Firmware Update This directory contains the firmware update applica-
Contains a template for the preparation of a new
ICT program on the R&S EGTSL user interface
tion with which the firmware of all TSVP Test System Versatile Platform plug-in boards can be updated to a newer version when available.
17User Manual 1143.4140.42 ─ 16
R&S®EGTSL
Software Installation
File Structure
Directory Contents
Include Contains the h-files (include files) needed for the
development of new test libraries.
Operator Interface Contains the run time module for the operator inter-
face of TestStand. A TestStand run time licence is
required.
Sequences Contains the test sequence examples created by
ROHDE & SCHWARZ.
The application data is stored in the following directory structure below the R&S GTSL
application data directory which was specified during the installation process.
Figure 2-2: File structure application data
Description of installed R&S GTSL application data files directories.
Table 2-2: Application data files directories
Directory Contents
Configuration Contains samples of the two configuration files
PHYSICAL.INI and APPLICATION.INI.
EGTSL
●
Atg
EGTSL
●
Correction
IC-Check Contains example configuration data for the IC-
License Contains one or more subdirectories with optional
Contains the files for the execution of the Automatic
Test Generator ATG.
Contains the correction data determined with the
utility ICTCorrection.
Check application.
license key files.
18User Manual 1143.4140.42 ─ 16
R&S®EGTSL
3.1 General
Functional Description
General
3 Functional Description
Figure 3-1: R&S EGTSL Layer Model
The Enhanced Generic Test Software Library RR&S EGTSL R&S EGTSL is part of an
extension to the Generic Test Software Library R&S GTSL. Using R&S EGTSL it is
possible to prepare and perform in-circuit tests. The individual R&S EGTSL software
components are arranged in individual layers exactly like R&S GTSL.
The bottom layer (device driver layer) of the R&S EGTSL contains the device drivers
necessary for the test hardware used. The test hardware is accessed using these
device drivers.
The middle layer (library layer) of the R&S EGTSL contains the ICT test library and the
R&S EGTSL. The ICT test library provides the functions necessary for performing the
in-circuit test. Using the R&S EGTSL runtime library (runtime engine) the internal R&S
EGTSL program processes are run. In this layer further information is passed to the
resource manager library via the two files PHYSICAL.INI and APPLICATION.INI. The
various device drivers from the lowest level are called from this layer.
The top layer (execution layer) contains the test sequences for performing the in-circuit
test. The test sequences call functions from the ICT test library in the middle layer. The
function calls include, e.g.
●
loading ICT programs,
●
running ICT programs,
●
debugging ICT programs and
●
the generation of reports.
19User Manual 1143.4140.42 ─ 16
R&S®EGTSL
Functional Description
ICT Test Library
The calls for the individual functions from the ICT test library can, e.g., be made using
a sequence editor (TestStand) or a dedicated C program.
The top layer (execution layer) also contains the R&S EGTSL Loader and the R&S
EGTSL user interface (R&S EGTSL). The R&S EGTSL user interface (R&S EGTSL) is
opened using the R&S EGTSL either by the R&S EGTSL Loader or a function call from
the ICT test library.
Special test hardware is required for performing in-circuit tests. This hardware and thus
the individual test functions are called using the R&S GTSL/R&S EGTSL-typical functions in the test libraries.
For further information on R&S GTSL see “Software Description Generic Test Software
Library R&S GTSL”
R&S EGTSL includes the following parts and programs:
●
ICT runtime library
●
ICT test library
●
User interface ( IDE )
●
Loader
●
Automatic Test Generator ATG (utility)
●
ICT correction data (utility)
3.2 ICT Test Library
The following section provides a short overview of the test functions available in the
ICT test library.
The individual test functions and their parameters are described in the online help for
the ICT test library. The help files (.HLP) are in the folder ...\GTSL\BIN.
3.2.1 General
Starting with GTSL 3.30, no GTSL license is required.
Name of the dynamic link library (DLL): ICT.DLL
Name of the help file (HLP): ICT.HLP
20User Manual 1143.4140.42 ─ 16
R&S®EGTSL
Functional Description
ICT Test Library
License required R&S TS-LBAS and
R&S TS-LEGT or R&S TS-LEG2
Supported devices: R&S TS-PICT ICT Extension Module
R&S TS-PMB Matrix Module
R&S TS-PSAM Source and Measurement Module
R&S TS-PSU Power Supply / Load Module
R&S TS-PSU12 Power Supply / Load Module 12V
The in-circuit test library offers functions for the in-circuit test using the R&S EGTSL
software and the R&S TS-PSAM, R&S TS-PICT, R&S TS-PSU, R&S TS-PSU12 and
R&S TS-PMB modules.
The functions allow to
●
load, run and debug ICT programs
●
load limit files
●
generate a report
3.2.2 Entries in PHYSICAL.INI
Section [device->...]
Keyword Value Description
Type String Mandatory entry
ResourceDesc String Mandatory entry
pict = R&S TS-PICT ICT Extension Module
pmb = R&S TS-PMB Matrix Module
psam = R&S TS-PSAM Source
and Measurement Module
psu = R&S TS-PSU Power Supply/Load Module
psu12 = R&S TS-PSU12 Power
Supply/Load Module 12V
VISA resource descriptor in the
form
PXI[segment number]::[device
number]::[function]::INSTR
CAN[board]::[controller]::[frame]::
[slot]
21User Manual 1143.4140.42 ─ 16
R&S®EGTSL
Functional Description
ICT Test Library
Keyword Value Description
DriverPrefix String Mandatory entry
Prefix for the IVI driver functions,
without underscore:
R&S TS-PICT : rspict
R&S TS-PMB : rspmb
R&S TS-PSAM : rspsam
R&S TS-PSU: rspsu
R&S TS-PSU12: rspsu
DriverDLL String Mandatory entry
File name of the driver DLL
R&S TS-PICT : rspict.dll
R&S TS-PMB : rspmb.dll
R&S TS-PSAM : rspsam.dll
R&S TS-PSU : rspsu.dll
R&S TS-PSU12 : rspsu.dll
DriverOption String Optional entry
3.2.3 Entries in APPLICATION.INI
Section [bench->...]
Keyword Value Description
ICTDevice1 String Mandatory entry
ICTDevice2 String Optional entry
ICTDevice3 String Optional entry
Option string being passed to the
device driver during the
Driver_Init function. See the
online help file for the appropriate
device driver.
Refers to the device section of the
R&S TS-PSAM
Refers to the device section of the
R&S TS-PICT or R&S TS-PSU /
R&S TS-PSU12
Refers to the device section of the
R&S TS-PICT or R&S TS-PSU /
R&S TS-PSU12
22User Manual 1143.4140.42 ─ 16
R&S®EGTSL
Functional Description
ICT Test Library
Keyword Value Description
ICTCorrResistor2W REAL Optional entry
Unit: Ohm
Bench correction value, that is
taken into account for all 2-wire
resistor test measurements (DCmeasurements). The correction
value is subtracted from the measurement. The result of the subtraction is compared with the limits.
ICTCorrImpedanceRes2W
ICTCorrImpedanceCap2W
ICTCorrImpedanceInd2W
REAL Optional entry
Bench correction value, that is
taken into account for all 2-wire
impedance test resistor measurements (AC-measurements). The
correction value is subtracted
from the measurement. The result
of the subtraction is compared
with the limits.
REAL Optional entry
Bench correction value, that is
taken into account for all 2-wire
impedance test capacitance measurements. The correction value
is subtracted from the measurement. The result of the subtraction
is compared with the limits.
REAL Optional entry
Unit: Henry
Bench correction value, that is
taken into account for all 2-wire
impedance test inductance measurements. The correction value
is subtracted from the measurement. The result of the subtraction
is compared with the limits.
SwitchDevice<i> String Mandatory entry
Refers to a section with switch
devices in PHYSICAL.INI.
<i> stands for a number from
1,2,3,...,n. The numbers must be
assigned in ascending order without gaps.
<i> may be omitted in the case it
is 1.
23User Manual 1143.4140.42 ─ 16
R&S®EGTSL
Functional Description
ICT Test Library
Keyword Value Description
AppChannelTable String Mandatory entry
Refers to a section with defined
channel names in APPLICATION.INI.
Simulation 0 / 1 Mandatory entry
Blocks the simulation of the
entered devices (value = 0). Enables simulation of the entered
devices (value = 1).
Default = 0
Trace 0 / 1 Optional entry
Blocks the tracing function of the
library (value = 0). Enables the
tracing function of the library
(value = 1).
Default = 0
ChannelTableCase Sensitive 0 / 1 Optional entry
The channel names in the channel table are treated case-sensitive (value = 1) or case-insensitive
(value = 0).
Compensation 1 / 0 Optional entry
Section [io_channel->...]
Contains a list of user-specific channel names (or ATG-defined channel names) which
are assigned to the physical device names and to the physical device channel names.
The defined names apply only to the relevant application. For details about channel
name syntax, see "Software Description GTSL", chapter 8.3.4.
Keyword Value Description
<user-defined name> String Physical channel description in
3.2.4 Functions
Enables the fixture compensation
mechanism in the EGTSL/ICT
modules. If this option is set to 0,
the module will not write any compensation info into the outgoing
program file.
Default = 0
the combination <device name>!
<device channel name>
Setup ICT_Setup
Library Version ICT_Lib_Version
EGTSL Runtime Version ICT_Runtime_Version
Program Control
24User Manual 1143.4140.42 ─ 16
R&S®EGTSL
Functional Description
R&S EGTSL user interface (R&S EGTSL IDE)
Load Program ICT_Load_Program
Run Program ICT_Run_Program
Debug Program ICT_Debug_Program
Unload Program ICT_Unload_Program
Report Generation
Write Report to File ICT_Write_Report
Load Detailed Report ICT_Load_Detailed_Report
Get Detailed Report Entry ICT_Get_Detailed_Report_Entry
Get Detailed Report Entry (Extended)
ICT_Get_Detailed_Report_Entry_Ex
Get TestStand Report Entry ICT_Get_TestStand_Report_Entry
Transfer Report to QUOTIS ICT_Transfer_Quotis_Report
Limit Loader
Load Limits ICT_Load_Limits
Error Handling
Get Error Log ICT_Get_Error_Log
Cleanup ICT_Cleanup
3.3 R&S EGTSL Loader
Using the R&S EGTSL Loader the R&S EGTSL user interface (R&S EGTSL IDE ) can
be opened directly. A function call from the ICT test library is not necessary.
The operation of the R&S EGTSL Loader is described in section 13.2.
3.4 R&S EGTSL user interface (R&S EGTSL IDE)
The R&S EGTSL user interface (R&S EGTSL IDE) for editing and debugging an ICT
program is started either using a function from the ICT test library or using the R&S
EGTSL Loader.
25User Manual 1143.4140.42 ─ 16
R&S®EGTSL
Functional Description
R&S EGTSL user interface (R&S EGTSL IDE)
Figure 3-2: R&S EGTSL User interface (R&S EGTSL IDE )
The R&S EGTSL user interface (R&S EGTSL IDE ) provides a wide range of functions
for preparing, editing and debugging an ICT program.
●
Loading ICT programs
●
Editing general ICT program settings
●
Importing and exporting values for limits for all test steps
●
Printing the test report generated
●
Inserting and deleting test steps
●
Editing the test step settings
●
Search functions
●
Setting break points
●
Debugging the ICT program
– Complete execution of the ICT program
– Execution in single steps
– Execution until an error occurs
– Execution of marked test steps
●
Display of the test results (text and graphics)
●
Preparation of a test report
The individual functions of the R&S EGTSL user interface (R&S EGTSL IDE ) are
described in section 5.
26User Manual 1143.4140.42 ─ 16
R&S®EGTSL
3.5 Automatic Test Generator ATG
3.6 ICT Correction Data
Functional Description
Hardware for in-circuit test
Using the Automatic Test Generator ATG utility, a circuit description and the description
of the test hardware available are used to generate an ICT program that will run in the
Enhanced Generic Test Software Library R&S EGTSL. The ICT program generated
can be opened in the R&S EGTSL user interface (R&S EGTSL IDE) and edited.
The individual functions of the Automatic Test Generator ATG are described in section 9.
The test system is calibrated using the ICTCorrection utility. Resistances and capacitances in the system are determined and saved as correction data. Using this data, the
values measured during the in-circuit test are corrected.
The individual functions of the ICTCorrection program are described in section 15.
3.7 Hardware for in-circuit test
To be able to perform an in-circuit test using R&S EGTSL the following test hardware
must be available:
●
Test System Versatile Platform R&S CompactTSVP TS-PCA3
●
Test System Versatile Platform R&S PowerTSVP TS-PWA3 (alternative expansion)
●
R&S TS-PSAM Source and Measurement Module
●
R&S TS-PICT In-Circuit Test Module (alternative expansion for certain test methods)
●
R&S TS-PSU Power Supply/Load Module / R&S TS-PSU12 Power Supply/Load
Module 12V (expansion for zener diode and transistor test methods).
●
R&S TS-PMB Matrix Module B
●
Test adapters developed and built especially for the Unit Under Test (UUT) and the
related test program
The precise composition and number of items of hardware is always dependent on the
specific project and the test methods required.
The individual components of test hardware are described in the related user manuals.
27User Manual 1143.4140.42 ─ 16
R&S®EGTSL
4.1 General
Getting Started
Preparation of the Circuit Documentation
4 Getting Started
This section describes the development process for an in-circuit test in a step-by-step
manner based on a simple example. The individual steps can be followed using these
instructions so that you can rapidly become familiar with the Enhanced Generic Test
Software Library R&S EGTSL.
The example circuit, the related BDL file and the files generated by the Automatic Test
Generator ATG are listed in appendix A. The related files are saved
in ...\GTSL\EGTSL\Example.
4.2 Development Process for an In-circuit Test
Based on the (existing) circuit documents for a unit under test (for the in-circuit test the
unit is generally a circuit board) an ICT program is to be prepared that can test whether
the circuit board is correctly populated. The mechanical-electrical adaptation of the unit
under test to the test system, i.e. building a bed of nails adapter is also included.
The Enhanced Generic Test Software Library R&S EGTSL provides a series of utilities
that enable these tasks to be tackled largely automatically. Based on an example circuit, the features provided by the software will be demonstrated.
To pass from the circuit documentation to the finished ICT program, the following steps
are necessary:
●
Preparation of the circuit documentation
●
Entry of the circuit description
●
Preparation of the test program by the Automatic Test Generator ATG
●
Preparation of the adapter
●
Commissioning and debugging the test program
4.3 Preparation of the Circuit Documentation
In the first step the test points, i.e. the pins on the bed of nails adapter, are entered on
the circuit diagram. As during the in-circuit test, every component is measured separately, it is important that the test system can make contact to every pin on every component. For this purpose, a test nail must be provided at every node of the circuit.
The names of the test points, also called nodes, appear later in the test program. They
must therefore be clear, i.e. either refer to the function in the circuit (like INPUT, OUTPUT) or to a component connected to the node (like TR1.B for the base of transistor
28User Manual 1143.4140.42 ─ 16
R&S®EGTSL
4.3.1 Example Circuit
Getting Started
Preparation of the Circuit Documentation
TR1). Special rules apply for ground and supply voltage. The names of such test points
must always start with GND or VCC respectively, so that the automatic test generator
can detect them as ground and supply voltage and treat them appropriately.
Figure 4-1: Circuit example
Figure 4-1 shows the circuit for a low frequency amplifier stage. The names of the test
points are already entered.
4.3.2 Preparation of the Circuit Description
For further processing in R&S EGTSL the circuit description for the circuit to be tested
must be available as a BDL file (see also section 8.2). There are now various ways you
can prepare the necessary BDL file.
1. Prepare the BDL file (circuit description) manually in a text editor based on the circuit diagram.
2. Transfer the circuit description from a CAD system. Modern CAD systems for the
preparation of electronic circuits provide a feature for exporting the circuit description. Using commercially available conversion software, the exported circuit
description can be converted to the BDL format.
The manual preparation of the circuit description is of course tedious for larger circuits.
Here it is best, if possible, to transfer the data from the CAD system. For the small
example with only eight components, it is however easy to enter the BDL data by hand.
The BDL file is saved in ...\GTSL\EGTSL\Example\Example1.BDL.
29User Manual 1143.4140.42 ─ 16
R&S®EGTSL
4.3.2.1 Entry of the Resistors
Getting Started
Preparation of the Circuit Documentation
BDL example for resistor R1
RESISTOR
NAME 'R1'
PART_ID '1234.5678.90'
VALUE 1.2 MOHM
TOL+ 10% TOL- 10%
I_LIM 100.0 MA
PIN_1 'VCC'
PIN_2 'TR1.B'
ERR_MSG 'Problem with R1'
The following information on a resistor must be entered in the text editor:
NAME Component name
PART_ID Optional component identifier for the component
VALUE Nominal value and unit for the component
TOL+ Positive component tolerance in % (default value 10
%)
TOL- Negative component tolerance in % (default value
10 %)
I_LIMIT Maximum measuring current for determining the
value with unit (default value 100 mA)
PIN_1 Test point 1 for the component
PIN_2 Test point 2 for the component
ERR_MSG Optional error text The text entered here is dis-
played in the report if the component has been
detected as faulty.
For the example circuit, all resistors must be entered in the same manner:
Name Value Pin 1 Pin 2
R1 1.2 MOHM VCC TR1.B
R2 330 KOHM TR1.B GND
R3 40 KOHM VCC TR1.C
R4 10 KOHM TR1.E GND
4.3.2.2 Entry of Capacitors
BDL example for capacitor C1
CAPACITOR
30User Manual 1143.4140.42 ─ 16
Loading...