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R&S®EGTSL
Enhanced Generic Test Software
Library
User Manual
(;[YXZ)
1143414042
Version 16
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This Software Description is valid for the following software versions.
●
R&S®GTSL version 3.00 and higher versions
●
R&S®EGTSL version 3.00 and higher versions
© 2021 Rohde & Schwarz GmbH & Co. KG
Mühldorfstr. 15, 81671 München, Germany
Phone: +49 89 41 29 - 0
Email: info@rohde-schwarz.com
Internet: www.rohde-schwarz.com
Subject to change – data without tolerance limits is not binding.
R&S® is a registered trademark of Rohde & Schwarz GmbH & Co. KG.
Trade names are trademarks of the owners.
1143.4140.42 | Version 16 | R&S®EGTSL
The following abbreviations are used throughout this manual: R&S®EGTSL is abbreviated as R&S EGTSL.
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R&S®EGTSL
Contents
Contents
1 General..................................................................................................15
1.1 User Information......................................................................................................... 15
1.2 Reference Documents................................................................................................ 15
1.3 Explanation of Symbols............................................................................................. 15
2 Software Installation............................................................................16
2.1 General.........................................................................................................................16
2.2 Installation................................................................................................................... 16
2.3 File Structure............................................................................................................... 16
3 Functional Description........................................................................ 19
3.1 General.........................................................................................................................19
3.2 ICT Test Library........................................................................................................... 20
3.2.1 General......................................................................................................................... 20
3.2.2 Entries in PHYSICAL.INI...............................................................................................21
3.2.3 Entries in APPLICATION.INI......................................................................................... 22
3.2.4 Functions.......................................................................................................................24
3.3 R&S EGTSL Loader.....................................................................................................25
3.4 R&S EGTSL user interface (R&S EGTSL IDE).......................................................... 25
3.5 Automatic Test Generator ATG..................................................................................27
3.6 ICT Correction Data.................................................................................................... 27
3.7 Hardware for in-circuit test........................................................................................ 27
4 Getting Started..................................................................................... 28
4.1 General.........................................................................................................................28
4.2 Development Process for an In-circuit Test............................................................. 28
4.3 Preparation of the Circuit Documentation................................................................28
4.3.1 Example Circuit............................................................................................................. 29
4.3.2 Preparation of the Circuit Description........................................................................... 29
4.3.2.1 Entry of the Resistors....................................................................................................30
4.3.2.2 Entry of Capacitors........................................................................................................30
4.3.2.3 Entry of the Transistor...................................................................................................32
4.4 Preparing the ICT program.........................................................................................33
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5.4.1 Positioning of the Subwindows..................................................................................... 39
5.4.2 Program Subwindow..................................................................................................... 40
5.4.2.1 Context Menu................................................................................................................41
5.4.3 Report Subwindow........................................................................................................ 42
5.4.3.1 Context Menu................................................................................................................42
Contents
4.5 Adapter Manufacture.................................................................................................. 34
4.6 Commissioning and Debugging................................................................................ 34
5 User Interface (R&S EGTSL IDE)........................................................ 37
5.1 General.........................................................................................................................37
5.2 Menu Structure............................................................................................................38
5.3 Main Screen................................................................................................................. 39
5.4 Subwindow.................................................................................................................. 39
5.4.4 Test Properties Subwindow...........................................................................................43
5.4.5 Results Subwindow.......................................................................................................43
5.4.5.1 Context Menu................................................................................................................43
5.4.5.2 Results Tbl.................................................................................................................... 44
5.4.5.3 Results Gfx....................................................................................................................44
5.4.5.4 Results Hist................................................................................................................... 45
5.4.5.5 Results Details.............................................................................................................. 45
5.4.6 Debug Subwindow........................................................................................................ 46
5.5 Test Steps.................................................................................................................... 47
5.5.1 Contact..........................................................................................................................47
5.5.1.1 General......................................................................................................................... 47
5.5.1.2 Results Details.............................................................................................................. 48
5.5.2 Continuity...................................................................................................................... 49
5.5.2.1 General......................................................................................................................... 49
5.5.2.2 Timing............................................................................................................................50
5.5.2.3 Results Details.............................................................................................................. 51
5.5.3 Diode.............................................................................................................................51
5.5.3.1 Limits.............................................................................................................................52
5.5.3.2 Settings......................................................................................................................... 53
5.5.3.3 CNX...............................................................................................................................55
5.5.3.4 Timing............................................................................................................................55
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5.5.3.5 Results Details.............................................................................................................. 57
5.5.4 Discharge...................................................................................................................... 57
5.5.4.1 General......................................................................................................................... 58
5.5.4.2 Results Details.............................................................................................................. 58
5.5.5 FET............................................................................................................................... 59
5.5.5.1 Limits.............................................................................................................................59
5.5.5.2 Settings......................................................................................................................... 60
5.5.5.3 Measurement................................................................................................................ 62
5.5.5.4 CNX...............................................................................................................................62
5.5.5.5 Timing............................................................................................................................63
5.5.5.6 Results Details.............................................................................................................. 64
5.5.6 Impedance.................................................................................................................... 65
5.5.6.1 Limits.............................................................................................................................66
Contents
5.5.6.2 Method.......................................................................................................................... 67
5.5.6.3 Settings......................................................................................................................... 69
5.5.6.4 Timing............................................................................................................................71
5.5.6.5 Determination of Measured Value................................................................................. 72
5.5.6.6 Results Details.............................................................................................................. 73
5.5.7 Resistor......................................................................................................................... 75
5.5.7.1 Limits.............................................................................................................................75
5.5.7.2 Method.......................................................................................................................... 76
5.5.7.3 Settings......................................................................................................................... 78
5.5.7.4 Timing............................................................................................................................80
5.5.7.5 Results Details.............................................................................................................. 81
5.5.8 Short..............................................................................................................................82
5.5.8.1 General......................................................................................................................... 82
5.5.8.2 Timing............................................................................................................................84
5.5.8.3 Results Details.............................................................................................................. 84
5.5.9 Transistor...................................................................................................................... 85
5.5.9.1 Limits.............................................................................................................................85
5.5.9.2 Settings......................................................................................................................... 86
5.5.9.3 CNX...............................................................................................................................87
5.5.9.4 Timing............................................................................................................................88
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5.5.9.5 Results Details.............................................................................................................. 89
5.5.10 Transistor Beta..............................................................................................................90
5.5.10.1 Limits.............................................................................................................................90
5.5.10.2 Settings......................................................................................................................... 91
5.5.10.3 Measurement................................................................................................................ 93
5.5.10.4 CNX...............................................................................................................................94
5.5.10.5 Timing............................................................................................................................95
5.5.10.6 Results Details.............................................................................................................. 96
5.5.11 Zener Diode.................................................................................................................. 97
5.5.11.1 Limits.............................................................................................................................98
5.5.11.2 Settings......................................................................................................................... 99
5.5.11.3 CNX.............................................................................................................................100
5.5.11.4 Timing..........................................................................................................................101
Contents
5.5.11.5 Results Details............................................................................................................ 102
5.5.12 Explanations................................................................................................................103
5.5.12.1 Timing..........................................................................................................................103
5.5.12.2 Editing Pin Lists...........................................................................................................105
5.5.13 User-defined Test Methods......................................................................................... 107
5.5.13.1 Limits...........................................................................................................................107
5.5.13.2 Settings....................................................................................................................... 108
5.5.13.3 Info.............................................................................................................................. 109
5.5.13.4 Results Details............................................................................................................ 109
5.6 Menu bar Functions.................................................................................................. 110
5.6.1 Main Menu Command <File>...................................................................................... 110
5.6.1.1 Menu Command <Open>............................................................................................110
5.6.1.2 Menu Command <Save>.............................................................................................111
5.6.1.3 Menu Command <Save Copy As>.............................................................................. 111
5.6.1.4 Menu Command <Select>........................................................................................... 111
5.6.1.5 Menu Command <Close>............................................................................................112
5.6.1.6 Menu Command <Program Properties>......................................................................112
5.6.1.7 Menu Command <Limits>........................................................................................... 114
5.6.1.8 Menu Command <Print>............................................................................................. 117
5.6.1.9 Menu Command <Print Setup>...................................................................................117
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5.6.1.10 Menu Command <Exit>...............................................................................................118
5.6.2 Main Menu Command <Edit>......................................................................................119
5.6.2.1 Functions.....................................................................................................................119
5.6.2.2 Menu Command <Find>............................................................................................. 120
5.6.2.3 Menu Command <Step Properties>............................................................................121
5.6.2.4 Menu Point <Breakpoints>..........................................................................................124
5.6.3 Main Menu Command <View>....................................................................................125
5.6.4 Main Menu Command <Debug>................................................................................. 125
5.6.5 Main Menu Command <Report>.................................................................................127
5.6.6 Main Menu Command <Help>.................................................................................... 127
5.6.6.1 Menu Command <About EGTSL>.............................................................................. 127
5.7.1 Main Toolbar................................................................................................................128
Contents
5.7 Toolbar Functions..................................................................................................... 128
5.7.2 Debug Toolbar.............................................................................................................130
5.7.3 Toolbar for Insert......................................................................................................... 131
5.7.4 Toolbar for User-defined Tests.................................................................................... 132
5.8 Shortcuts................................................................................................................... 132
6 License Management.........................................................................134
7 Configuration Files............................................................................ 136
7.1 Syntax........................................................................................................................ 136
7.1.1 Naming Conventions...................................................................................................136
7.1.2 [LogicalNames] Section.............................................................................................. 137
7.1.3 [Device] Section.......................................................................................................... 138
7.1.4 [Bench] Section........................................................................................................... 139
7.1.5 [ResourceManager] Section........................................................................................140
7.1.6 [Extlct] Section............................................................................................................ 140
7.2 PHYSICAL.INI............................................................................................................ 140
7.2.1 Example File for PHYSICAL.INI (Example_Physical.ini)............................................ 141
7.2.2 Description of example file PHYSICAL.INI..................................................................141
7.3 APPLICATION.INI.......................................................................................................143
7.3.1 Example File for APPLICATION.INI (Example_Application.ini)...................................143
7.3.2 Description of Example File APPLICATION.INI.......................................................... 144
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8.1.1 Terminology, Symbols................................................................................................. 147
8.1.2 Structure of a Metaprogram........................................................................................ 148
8.1.3 Structure of Rule Bodies............................................................................................. 148
8.2.1 Syntax......................................................................................................................... 151
8.2.1.1 Resistor List................................................................................................................ 151
8.2.1.2 Variable Resistor List...................................................................................................152
8.2.1.3 Potentiometer List....................................................................................................... 152
8.2.1.4 Resistor Array List.......................................................................................................153
8.2.1.5 Capacitor List.............................................................................................................. 153
8.2.1.6 Pol. Capacitor List....................................................................................................... 153
Contents
8 Circuit Description.............................................................................147
8.1 Definition of Meta Language.................................................................................... 147
8.2 External File Format (BDL).......................................................................................151
8.2.1.7 Inductor List.................................................................................................................154
8.2.1.8 Diode List.................................................................................................................... 154
8.2.1.9 LED List.......................................................................................................................155
8.2.1.10 Zener Diode List..........................................................................................................155
8.2.1.11 Transistor List..............................................................................................................156
8.2.1.12 Jumper List..................................................................................................................156
8.2.1.13 IC List.......................................................................................................................... 157
8.2.1.14 Connector List............................................................................................................. 157
8.2.1.15 Black Box List..............................................................................................................157
8.2.1.16 Track List.....................................................................................................................158
8.2.1.17 Node List..................................................................................................................... 158
8.2.1.18 Basic Constructs......................................................................................................... 158
8.2.1.19 FET List.......................................................................................................................160
8.2.2 Semantics................................................................................................................... 160
8.2.2.1 General....................................................................................................................... 160
8.2.2.2 Resistor List................................................................................................................ 162
8.2.2.3 Variable Resistor List...................................................................................................163
8.2.2.4 Potentiometer List....................................................................................................... 163
8.2.2.5 Resistor Array List.......................................................................................................164
8.2.2.6 Capacitor List.............................................................................................................. 166
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8.2.2.7 Pol. Capacitor List....................................................................................................... 166
8.2.2.8 Inductor List.................................................................................................................167
8.2.2.9 Diode List.................................................................................................................... 168
8.2.2.10 LED List.......................................................................................................................170
8.2.2.11 Zener Diode List..........................................................................................................170
8.2.2.12 Transistor List..............................................................................................................171
8.2.2.13 Jumper List..................................................................................................................172
8.2.2.14 IC List.......................................................................................................................... 173
8.2.2.15 Connector List............................................................................................................. 173
8.2.2.16 Black Box List..............................................................................................................174
8.2.2.17 Track List.....................................................................................................................175
8.2.2.18 Node List..................................................................................................................... 175
8.2.2.19 FET List.......................................................................................................................176
Contents
8.3 Important Additional Information............................................................................ 177
8.3.1 Node List..................................................................................................................... 177
8.3.2 Treatment of Specific Pins.......................................................................................... 177
9 Automatic Test Generation with ATG............................................... 178
9.1 Function..................................................................................................................... 178
9.2 Starting the Automatic Test Generator ATG...........................................................179
9.3 Output Files............................................................................................................... 183
9.3.1 ICT Program................................................................................................................183
9.3.1.1 General....................................................................................................................... 183
9.3.1.2 Layout of the Test Program......................................................................................... 183
9.3.1.3 State of the Automatically Generated Test Program................................................... 183
9.3.1.4 Program Groups Generated........................................................................................184
9.3.1.5 Automatic Determination of the Guard Points in the Analog Test............................... 186
9.3.1.6 Safety Against Destruction of Components During the Test....................................... 186
9.3.1.7 Taking Account of Topological Problems.....................................................................186
9.3.2 ATG Report................................................................................................................. 187
9.3.2.1 Typical Warning Messages......................................................................................... 188
9.3.2.2 Alternative Proposals from the ATG............................................................................ 189
9.3.2.3 Test Coverage Report................................................................................................. 191
9.3.3 Application Layer Configuration File........................................................................... 192
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9.3.4 Adapter Manufacture...................................................................................................193
9.3.5 ICC Program............................................................................................................... 194
10.1 Test Hardware............................................................................................................195
10.2 Ground Wiring........................................................................................................... 197
10.3 Contact Test...............................................................................................................197
10.4 Continuity Test.......................................................................................................... 199
10.5 Diode Test.................................................................................................................. 200
10.6 Discharging Capacitors............................................................................................201
10.7 FET Test..................................................................................................................... 202
10.8 Impedance Test......................................................................................................... 203
10.8.1 2- and 4-wire measurement........................................................................................ 204
Contents
10 Test Methods...................................................................................... 195
10.8.2 Guarded Measurement............................................................................................... 205
10.8.3 Correct Phase Impedance Measurement................................................................... 207
10.8.4 System Residuals....................................................................................................... 207
10.8.5 Fixture Residuals........................................................................................................ 208
10.8.6 Measuring Small Capacitors....................................................................................... 208
10.8.7 Measurement of Polarized Capacitors/Electrolytic Capacitors................................... 209
10.9 Resistor Test..............................................................................................................209
10.9.1 2-wire Measurement................................................................................................... 209
10.9.2 4-wire Measurement................................................................................................... 210
10.9.3 Guarded Measurement................................................................................................211
10.10 Short-circuit Test.......................................................................................................213
10.11 Transistor Test...........................................................................................................214
10.12 Transistor Beta..........................................................................................................214
10.13 Zener Diode............................................................................................................... 216
11 Creating Test Programs.....................................................................219
11.1 Program Groups........................................................................................................219
11.2 Variants...................................................................................................................... 220
11.2.1 Use..............................................................................................................................220
11.2.2 Definition..................................................................................................................... 221
11.2.3 Assignment................................................................................................................. 221
11.2.4 Execution.................................................................................................................... 222
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11.3 Limit Files.................................................................................................................. 222
11.4 Multiple Panel Testing...............................................................................................222
11.4.1 Example of an Application Layer Configuration File for Multiple Uses........................223
12.1 Overview.................................................................................................................... 226
12.2 Starting and Terminating the Debugger..................................................................226
12.3 Debug Status............................................................................................................. 227
12.4 Using the Debugger.................................................................................................. 228
12.5 Breakpoints............................................................................................................... 230
12.6 Stop Conditions........................................................................................................ 230
12.7 Typical Debugging Procedure..................................................................................230
12.8 Measuring Time Optimization.................................................................................. 231
Contents
12 Debugger............................................................................................ 226
12.9 Interpretation of the Results Sub-window.............................................................. 232
12.9.1 Results Gfx Sub-Window............................................................................................ 232
12.9.2 Results Hist Sub-Window............................................................................................234
13 Running R&S EGTSL IDE..................................................................236
13.1 Starting Using a Function Call from the ICT Test Library..................................... 236
13.1.1 Example...................................................................................................................... 236
13.2 Starting Using the R&S EGTSL Loader...................................................................239
13.2.1 R&S EGTSL Loader, starting...................................................................................... 240
14 Report Format.................................................................................... 243
15 ICT Correction Data........................................................................... 246
15.1 System Residual Compensation............................................................................. 246
15.1.1 Normal Operation........................................................................................................246
15.1.2 Silent Operation.......................................................................................................... 249
15.1.2.1 Parameter................................................................................................................... 249
15.1.2.2 Exit Codes...................................................................................................................249
15.1.2.3 Programming Example................................................................................................250
15.2 Adapter Compensation.............................................................................................251
16 Error Messages.................................................................................. 258
16.1 Compile Errors.......................................................................................................... 258
16.2 Runtime Errors.......................................................................................................... 258
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17.1 Overview.................................................................................................................... 261
17.1.1 Objective..................................................................................................................... 261
17.1.2 Functionality................................................................................................................ 261
17.2 Using Extension Libraries........................................................................................261
17.2.1 Configuration...............................................................................................................261
17.2.2 Documentation............................................................................................................ 262
17.2.3 Inserting Test Steps.....................................................................................................262
17.2.4 Grouping Test Steps....................................................................................................263
17.2.5 Running and Debugging Test Steps............................................................................263
17.3 Creating Extension Libraries................................................................................... 264
17.3.1 Overview..................................................................................................................... 264
17.3.1.1 Software Structure...................................................................................................... 264
Contents
17 ICT Extension Libraries.....................................................................261
17.3.1.2 Working Principle........................................................................................................ 264
17.3.1.3 Integrating Hardware Modules.................................................................................... 265
17.3.1.4 File Structure...............................................................................................................265
17.3.2 Sample Projects.......................................................................................................... 265
17.3.2.1 RSSample................................................................................................................... 266
17.3.2.2 RSSamplePSU............................................................................................................266
17.3.2.3 Framework.................................................................................................................. 266
17.3.3 Internal Structure.........................................................................................................267
17.3.3.1 Project Structure......................................................................................................... 267
17.3.3.2 Export Interface...........................................................................................................268
17.3.3.3 Data Structures........................................................................................................... 268
17.3.3.4 Support Functions....................................................................................................... 271
17.3.3.5 Bitmap......................................................................................................................... 271
17.3.4 Description of Function............................................................................................... 272
17.3.4.1 Header Files................................................................................................................272
17.3.4.2 Exported Variables...................................................................................................... 272
17.3.4.3 Local Data Structures..................................................................................................274
17.3.4.4 Configuration Functions.............................................................................................. 278
17.3.4.5 Test-related Functions.................................................................................................280
17.3.4.6 Functions for Displaying Results.................................................................................282
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17.3.5 Details of Implementation............................................................................................283
17.3.5.1 Error Handling............................................................................................................. 283
17.3.5.2 Simulation................................................................................................................... 285
17.3.5.3 Tracing........................................................................................................................ 286
17.3.5.4 Locking........................................................................................................................287
17.3.6 R&S EGTSL-internal Hardware Modules....................................................................287
17.3.7 Additional Hardware Modules..................................................................................... 288
17.3.7.1 Configuration of Hardware Modules............................................................................288
17.3.7.2 Co-operative Session Concept................................................................................... 289
17.3.7.3 Setup...........................................................................................................................290
17.3.7.4 Cleanup.......................................................................................................................290
17.3.7.5 Prolog and Epilog........................................................................................................291
17.3.8 Advanced Topics......................................................................................................... 293
Contents
17.3.8.1 Debugging ICT Extension Libraries............................................................................ 293
17.3.8.2 Non-numeric Test Results........................................................................................... 293
17.3.8.3 Time Optimization....................................................................................................... 294
17.3.8.4 Aspects of Compatibility..............................................................................................294
17.3.8.5 Communication between ICT Extension Libraries...................................................... 295
Annex.................................................................................................. 296
A Example 1........................................................................................... 296
A.1 Circuit for Example 1................................................................................................ 296
A.2 BDL File for Example 1............................................................................................. 296
A.3 ICT Report Generated for Example 1...................................................................... 298
A.4 Application Layer Configuration File Generated for Example 1...........................299
B Example 2........................................................................................... 301
B.1 Circuit for Example 2................................................................................................ 301
B.2 BDL File for Example 2............................................................................................. 301
B.3 ICT Report Generated for Example 2...................................................................... 302
B.4 Application Layer Configuration File Generated for Example 2...........................303
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Contents
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1.1 User Information
1.2 Reference Documents
General
Explanation of Symbols
1 General
This software description applies to the following ROHDE & SCHWARZ products:
R&S TS-LEGT 1143.4140.02 Enhanced R&S GTSL Software
for ICT
R&S TS-LEG2 1166.3992.02 Enhanced R&S GTSL Software
for Basic ICT on R&S TS-PSAM
The Enhanced Generic Test Software Library R&S EGTSL is part of the Generic Test
Software Library R&S GTSL. For this reason, the following documentation is to be
noted in addition to this software description:
●
Software Description Generic Test Software Library R&S GTSL
The related test hardware is required for performing in-circuit tests. The test hardware
is described in the following documentation:
●
User Manual Test System Versatile Platform R&S CompactTSVP TS-PCA3
●
User Manual Test System Versatile Platform R&S PowerTSVP TS-PWA3
●
User Manual Analog Source and Measurement Module R&S TS-PSAM
●
User Manual ICT Extension Module R&S TS-PICT
●
User Manual Matrix Module B R&S TS-PMB
●
Documentation of the test adapter
1.3 Explanation of Symbols
Certain text passages in this software description are specially highlighted. The passages marked in this way have the following significance:
Incorrect measurements
Failure to follow instructions can result in incorrect measurements.
Highlights important details to which special attention must be paid and that make your
work easier.
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2.1 General
Software Installation
File Structure
2 Software Installation
Enhanced Generic Test Software Library R&S EGTSL is installed using the installation
routine for the Generic Test Software Library R&S GTSL.
The Generic Test Software Library R&S GTSL can be downloaded from R&S GLORIS
server. After extracting the compressed installation file, the whole contents of the
installation can be found in the target directory. Please read the README.TXT file
before starting the installation by executing the setup.exe file.
To install the Generic Test Software Library R&S GTSL under Windows 10 or Windows
7, the user must be logged in as administrator or as a user with administrator rights.
For additional information on the de-installation of previous versions of the Generic
Test Software Library R&S GTSL or concerning installation, consult the README.TXT
file in the installation package and the chapter “Installation of R&S CompactTSVP and
R&S GTSL” of the “R&S System Manual TSVP”.
2.2 Installation
Refer to the "Installation" chapter of the R&S GTSL user manual.
Make sure that the "Enhanced GTSL" checkbox is marked in the "Select Features" dialog of the setup procedure.
2.3 File Structure
The test libraries supplied by ROHDE & SCHWARZ are stored in fixed directories at
the time of installation. The following directory structure can be found as subdirectories
below the R&S GTSL program files directory which was specified during the installation
process:
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R&S®EGTSL
Software Installation
File Structure
Figure 2-1: File structure program files
Description of installed R&S GTSL program files directories:
Table 2-1: Program files directories
Directory Contents
GTSL Generic Test Software Library. The root directory for
the R&S GTSL software can have any name.
Bin Contains the test libraries (DLL, LIB) and the help
files (HLP, CHM) belonging to the test libraries.
Develop The subdirectories of the directory Develop contain
generally valid examples for the creation of a highlevel test library, a customer-specific selftest library
and two sample applications that show how to call
R&S GTSL functions and driver functions.
Documentation Contains the various items of documentation in PDF
file format.
EGTSL
●
Correction
EGTSL
●
Extlct
– Framework
– RSSample
– RSSamplePSU
Contains the utility ICTCorrection with which a correction data set can be determined.
The folder …\Framework contains the framework
code for the creation of a user-defined ICT extension library. The folder …\RSSample contains an
example for the creation of a user-defined ICT
extension library with source-code and binaries. The
RSSamplePSU project is similar to the RSSample
project, but uses the R&S TS-PSU module instead
of the R&S TS-PFG module.
EGTSL
●
Templates
Firmware Update This directory contains the firmware update applica-
Contains a template for the preparation of a new
ICT program on the R&S EGTSL user interface
tion with which the firmware of all TSVP Test System Versatile Platform plug-in boards can be updated to a newer version when available.
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Software Installation
File Structure
Directory Contents
Include Contains the h-files (include files) needed for the
development of new test libraries.
Operator Interface Contains the run time module for the operator inter-
face of TestStand. A TestStand run time licence is
required.
Sequences Contains the test sequence examples created by
ROHDE & SCHWARZ.
The application data is stored in the following directory structure below the R&S GTSL
application data directory which was specified during the installation process.
Figure 2-2: File structure application data
Description of installed R&S GTSL application data files directories.
Table 2-2: Application data files directories
Directory Contents
Configuration Contains samples of the two configuration files
PHYSICAL.INI and APPLICATION.INI.
EGTSL
●
Atg
EGTSL
●
Correction
IC-Check Contains example configuration data for the IC-
License Contains one or more subdirectories with optional
Contains the files for the execution of the Automatic
Test Generator ATG.
Contains the correction data determined with the
utility ICTCorrection.
Check application.
license key files.
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R&S®EGTSL
3.1 General
Functional Description
General
3 Functional Description
Figure 3-1: R&S EGTSL Layer Model
The Enhanced Generic Test Software Library RR&S EGTSL R&S EGTSL is part of an
extension to the Generic Test Software Library R&S GTSL. Using R&S EGTSL it is
possible to prepare and perform in-circuit tests. The individual R&S EGTSL software
components are arranged in individual layers exactly like R&S GTSL.
The bottom layer (device driver layer) of the R&S EGTSL contains the device drivers
necessary for the test hardware used. The test hardware is accessed using these
device drivers.
The middle layer (library layer) of the R&S EGTSL contains the ICT test library and the
R&S EGTSL. The ICT test library provides the functions necessary for performing the
in-circuit test. Using the R&S EGTSL runtime library (runtime engine) the internal R&S
EGTSL program processes are run. In this layer further information is passed to the
resource manager library via the two files PHYSICAL.INI and APPLICATION.INI. The
various device drivers from the lowest level are called from this layer.
The top layer (execution layer) contains the test sequences for performing the in-circuit
test. The test sequences call functions from the ICT test library in the middle layer. The
function calls include, e.g.
●
loading ICT programs,
●
running ICT programs,
●
debugging ICT programs and
●
the generation of reports.
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R&S®EGTSL
Functional Description
ICT Test Library
The calls for the individual functions from the ICT test library can, e.g., be made using
a sequence editor (TestStand) or a dedicated C program.
The top layer (execution layer) also contains the R&S EGTSL Loader and the R&S
EGTSL user interface (R&S EGTSL). The R&S EGTSL user interface (R&S EGTSL) is
opened using the R&S EGTSL either by the R&S EGTSL Loader or a function call from
the ICT test library.
Special test hardware is required for performing in-circuit tests. This hardware and thus
the individual test functions are called using the R&S GTSL/R&S EGTSL-typical functions in the test libraries.
For further information on R&S GTSL see “Software Description Generic Test Software
Library R&S GTSL”
R&S EGTSL includes the following parts and programs:
●
ICT runtime library
●
ICT test library
●
User interface ( IDE )
●
Loader
●
Automatic Test Generator ATG (utility)
●
ICT correction data (utility)
3.2 ICT Test Library
The following section provides a short overview of the test functions available in the
ICT test library.
The individual test functions and their parameters are described in the online help for
the ICT test library. The help files (.HLP) are in the folder ...\GTSL\BIN.
3.2.1 General
Starting with GTSL 3.30, no GTSL license is required.
Name of the dynamic link library (DLL): ICT.DLL
Name of the help file (HLP): ICT.HLP
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R&S®EGTSL
Functional Description
ICT Test Library
License required R&S TS-LBAS and
R&S TS-LEGT or R&S TS-LEG2
Supported devices: R&S TS-PICT ICT Extension Module
R&S TS-PMB Matrix Module
R&S TS-PSAM Source and Measurement Module
R&S TS-PSU Power Supply / Load Module
R&S TS-PSU12 Power Supply / Load Module 12V
The in-circuit test library offers functions for the in-circuit test using the R&S EGTSL
software and the R&S TS-PSAM, R&S TS-PICT, R&S TS-PSU, R&S TS-PSU12 and
R&S TS-PMB modules.
The functions allow to
●
load, run and debug ICT programs
●
load limit files
●
generate a report
3.2.2 Entries in PHYSICAL.INI
Section [device->...]
Keyword Value Description
Type String Mandatory entry
ResourceDesc String Mandatory entry
pict = R&S TS-PICT ICT Extension Module
pmb = R&S TS-PMB Matrix Module
psam = R&S TS-PSAM Source
and Measurement Module
psu = R&S TS-PSU Power Supply/Load Module
psu12 = R&S TS-PSU12 Power
Supply/Load Module 12V
VISA resource descriptor in the
form
PXI[segment number]::[device
number]::[function]::INSTR
CAN[board]::[controller]::[frame]::
[slot]
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Functional Description
ICT Test Library
Keyword Value Description
DriverPrefix String Mandatory entry
Prefix for the IVI driver functions,
without underscore:
R&S TS-PICT : rspict
R&S TS-PMB : rspmb
R&S TS-PSAM : rspsam
R&S TS-PSU: rspsu
R&S TS-PSU12: rspsu
DriverDLL String Mandatory entry
File name of the driver DLL
R&S TS-PICT : rspict.dll
R&S TS-PMB : rspmb.dll
R&S TS-PSAM : rspsam.dll
R&S TS-PSU : rspsu.dll
R&S TS-PSU12 : rspsu.dll
DriverOption String Optional entry
3.2.3 Entries in APPLICATION.INI
Section [bench->...]
Keyword Value Description
ICTDevice1 String Mandatory entry
ICTDevice2 String Optional entry
ICTDevice3 String Optional entry
Option string being passed to the
device driver during the
Driver_Init function. See the
online help file for the appropriate
device driver.
Refers to the device section of the
R&S TS-PSAM
Refers to the device section of the
R&S TS-PICT or R&S TS-PSU /
R&S TS-PSU12
Refers to the device section of the
R&S TS-PICT or R&S TS-PSU /
R&S TS-PSU12
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R&S®EGTSL
Functional Description
ICT Test Library
Keyword Value Description
ICTCorrResistor2W REAL Optional entry
Unit: Ohm
Bench correction value, that is
taken into account for all 2-wire
resistor test measurements (DCmeasurements). The correction
value is subtracted from the measurement. The result of the subtraction is compared with the limits.
ICTCorrImpedanceRes2W
ICTCorrImpedanceCap2W
ICTCorrImpedanceInd2W
REAL Optional entry
Bench correction value, that is
taken into account for all 2-wire
impedance test resistor measurements (AC-measurements). The
correction value is subtracted
from the measurement. The result
of the subtraction is compared
with the limits.
REAL Optional entry
Bench correction value, that is
taken into account for all 2-wire
impedance test capacitance measurements. The correction value
is subtracted from the measurement. The result of the subtraction
is compared with the limits.
REAL Optional entry
Unit: Henry
Bench correction value, that is
taken into account for all 2-wire
impedance test inductance measurements. The correction value
is subtracted from the measurement. The result of the subtraction
is compared with the limits.
SwitchDevice<i> String Mandatory entry
Refers to a section with switch
devices in PHYSICAL.INI.
<i> stands for a number from
1,2,3,...,n. The numbers must be
assigned in ascending order without gaps.
<i> may be omitted in the case it
is 1.
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R&S®EGTSL
Functional Description
ICT Test Library
Keyword Value Description
AppChannelTable String Mandatory entry
Refers to a section with defined
channel names in APPLICATION.INI.
Simulation 0 / 1 Mandatory entry
Blocks the simulation of the
entered devices (value = 0). Enables simulation of the entered
devices (value = 1).
Default = 0
Trace 0 / 1 Optional entry
Blocks the tracing function of the
library (value = 0). Enables the
tracing function of the library
(value = 1).
Default = 0
ChannelTableCase Sensitive 0 / 1 Optional entry
The channel names in the channel table are treated case-sensitive (value = 1) or case-insensitive
(value = 0).
Compensation 1 / 0 Optional entry
Section [io_channel->...]
Contains a list of user-specific channel names (or ATG-defined channel names) which
are assigned to the physical device names and to the physical device channel names.
The defined names apply only to the relevant application. For details about channel
name syntax, see "Software Description GTSL", chapter 8.3.4.
Keyword Value Description
<user-defined name> String Physical channel description in
3.2.4 Functions
Enables the fixture compensation
mechanism in the EGTSL/ICT
modules. If this option is set to 0,
the module will not write any compensation info into the outgoing
program file.
Default = 0
the combination <device name>!
<device channel name>
Setup ICT_Setup
Library Version ICT_Lib_Version
EGTSL Runtime Version ICT_Runtime_Version
Program Control
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R&S®EGTSL
Functional Description
R&S EGTSL user interface (R&S EGTSL IDE)
Load Program ICT_Load_Program
Run Program ICT_Run_Program
Debug Program ICT_Debug_Program
Unload Program ICT_Unload_Program
Report Generation
Write Report to File ICT_Write_Report
Load Detailed Report ICT_Load_Detailed_Report
Get Detailed Report Entry ICT_Get_Detailed_Report_Entry
Get Detailed Report Entry (Extended)
ICT_Get_Detailed_Report_Entry_Ex
Get TestStand Report Entry ICT_Get_TestStand_Report_Entry
Transfer Report to QUOTIS ICT_Transfer_Quotis_Report
Limit Loader
Load Limits ICT_Load_Limits
Error Handling
Get Error Log ICT_Get_Error_Log
Cleanup ICT_Cleanup
3.3 R&S EGTSL Loader
Using the R&S EGTSL Loader the R&S EGTSL user interface (R&S EGTSL IDE ) can
be opened directly. A function call from the ICT test library is not necessary.
The operation of the R&S EGTSL Loader is described in section 13.2.
3.4 R&S EGTSL user interface (R&S EGTSL IDE)
The R&S EGTSL user interface (R&S EGTSL IDE) for editing and debugging an ICT
program is started either using a function from the ICT test library or using the R&S
EGTSL Loader.
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R&S®EGTSL
Functional Description
R&S EGTSL user interface (R&S EGTSL IDE)
Figure 3-2: R&S EGTSL User interface (R&S EGTSL IDE )
The R&S EGTSL user interface (R&S EGTSL IDE ) provides a wide range of functions
for preparing, editing and debugging an ICT program.
●
Loading ICT programs
●
Editing general ICT program settings
●
Importing and exporting values for limits for all test steps
●
Printing the test report generated
●
Inserting and deleting test steps
●
Editing the test step settings
●
Search functions
●
Setting break points
●
Debugging the ICT program
– Complete execution of the ICT program
– Execution in single steps
– Execution until an error occurs
– Execution of marked test steps
●
Display of the test results (text and graphics)
●
Preparation of a test report
The individual functions of the R&S EGTSL user interface (R&S EGTSL IDE ) are
described in section 5.
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R&S®EGTSL
3.5 Automatic Test Generator ATG
3.6 ICT Correction Data
Functional Description
Hardware for in-circuit test
Using the Automatic Test Generator ATG utility, a circuit description and the description
of the test hardware available are used to generate an ICT program that will run in the
Enhanced Generic Test Software Library R&S EGTSL. The ICT program generated
can be opened in the R&S EGTSL user interface (R&S EGTSL IDE) and edited.
The individual functions of the Automatic Test Generator ATG are described in section 9.
The test system is calibrated using the ICTCorrection utility. Resistances and capacitances in the system are determined and saved as correction data. Using this data, the
values measured during the in-circuit test are corrected.
The individual functions of the ICTCorrection program are described in section 15.
3.7 Hardware for in-circuit test
To be able to perform an in-circuit test using R&S EGTSL the following test hardware
must be available:
●
Test System Versatile Platform R&S CompactTSVP TS-PCA3
●
Test System Versatile Platform R&S PowerTSVP TS-PWA3 (alternative expansion)
●
R&S TS-PSAM Source and Measurement Module
●
R&S TS-PICT In-Circuit Test Module (alternative expansion for certain test methods)
●
R&S TS-PSU Power Supply/Load Module / R&S TS-PSU12 Power Supply/Load
Module 12V (expansion for zener diode and transistor test methods).
●
R&S TS-PMB Matrix Module B
●
Test adapters developed and built especially for the Unit Under Test (UUT) and the
related test program
The precise composition and number of items of hardware is always dependent on the
specific project and the test methods required.
The individual components of test hardware are described in the related user manuals.
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R&S®EGTSL
4.1 General
Getting Started
Preparation of the Circuit Documentation
4 Getting Started
This section describes the development process for an in-circuit test in a step-by-step
manner based on a simple example. The individual steps can be followed using these
instructions so that you can rapidly become familiar with the Enhanced Generic Test
Software Library R&S EGTSL.
The example circuit, the related BDL file and the files generated by the Automatic Test
Generator ATG are listed in appendix A. The related files are saved
in ...\GTSL\EGTSL\Example.
4.2 Development Process for an In-circuit Test
Based on the (existing) circuit documents for a unit under test (for the in-circuit test the
unit is generally a circuit board) an ICT program is to be prepared that can test whether
the circuit board is correctly populated. The mechanical-electrical adaptation of the unit
under test to the test system, i.e. building a bed of nails adapter is also included.
The Enhanced Generic Test Software Library R&S EGTSL provides a series of utilities
that enable these tasks to be tackled largely automatically. Based on an example circuit, the features provided by the software will be demonstrated.
To pass from the circuit documentation to the finished ICT program, the following steps
are necessary:
●
Preparation of the circuit documentation
●
Entry of the circuit description
●
Preparation of the test program by the Automatic Test Generator ATG
●
Preparation of the adapter
●
Commissioning and debugging the test program
4.3 Preparation of the Circuit Documentation
In the first step the test points, i.e. the pins on the bed of nails adapter, are entered on
the circuit diagram. As during the in-circuit test, every component is measured separately, it is important that the test system can make contact to every pin on every component. For this purpose, a test nail must be provided at every node of the circuit.
The names of the test points, also called nodes, appear later in the test program. They
must therefore be clear, i.e. either refer to the function in the circuit (like INPUT, OUTPUT) or to a component connected to the node (like TR1.B for the base of transistor
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4.3.1 Example Circuit
Getting Started
Preparation of the Circuit Documentation
TR1). Special rules apply for ground and supply voltage. The names of such test points
must always start with GND or VCC respectively, so that the automatic test generator
can detect them as ground and supply voltage and treat them appropriately.
Figure 4-1: Circuit example
Figure 4-1 shows the circuit for a low frequency amplifier stage. The names of the test
points are already entered.
4.3.2 Preparation of the Circuit Description
For further processing in R&S EGTSL the circuit description for the circuit to be tested
must be available as a BDL file (see also section 8.2). There are now various ways you
can prepare the necessary BDL file.
1. Prepare the BDL file (circuit description) manually in a text editor based on the circuit diagram.
2. Transfer the circuit description from a CAD system. Modern CAD systems for the
preparation of electronic circuits provide a feature for exporting the circuit description. Using commercially available conversion software, the exported circuit
description can be converted to the BDL format.
The manual preparation of the circuit description is of course tedious for larger circuits.
Here it is best, if possible, to transfer the data from the CAD system. For the small
example with only eight components, it is however easy to enter the BDL data by hand.
The BDL file is saved in ...\GTSL\EGTSL\Example\Example1.BDL.
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4.3.2.1 Entry of the Resistors
Getting Started
Preparation of the Circuit Documentation
BDL example for resistor R1
RESISTOR
NAME 'R1'
PART_ID '1234.5678.90'
VALUE 1.2 MOHM
TOL+ 10% TOL- 10%
I_LIM 100.0 MA
PIN_1 'VCC'
PIN_2 'TR1.B'
ERR_MSG 'Problem with R1'
The following information on a resistor must be entered in the text editor:
NAME Component name
PART_ID Optional component identifier for the component
VALUE Nominal value and unit for the component
TOL+ Positive component tolerance in % (default value 10
%)
TOL- Negative component tolerance in % (default value
10 %)
I_LIMIT Maximum measuring current for determining the
value with unit (default value 100 mA)
PIN_1 Test point 1 for the component
PIN_2 Test point 2 for the component
ERR_MSG Optional error text The text entered here is dis-
played in the report if the component has been
detected as faulty.
For the example circuit, all resistors must be entered in the same manner:
Name Value Pin 1 Pin 2
R1 1.2 MOHM VCC TR1.B
R2 330 KOHM TR1.B GND
R3 40 KOHM VCC TR1.C
R4 10 KOHM TR1.E GND
4.3.2.2 Entry of Capacitors
BDL example for capacitor C1
CAPACITOR
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R&S®EGTSL
Getting Started
Preparation of the Circuit Documentation
NAME 'C1'
PART_ID '0987.6543.21'
VALUE 360 NF
TOL+ 10% TOL- 10%
PIN_1 'INPUT'
PIN_2 'TR1.B'
ERR_MSG 'Problem with C1'
The following information on a capacitor must be entered in the text editor:
NAME Component name
PART_ID Optional component identifier for the component
VALUE Nominal value and unit for the component
TOL+ Positive component tolerance in % (default value 10
%)
TOL- Negative component tolerance in % (default value
10 %)
PIN_1 Test point 1 for the component
PIN_2 Test point 2 for the component
ERR_MSG Optional error text The text entered here is dis-
played in the report if the component has been
detected as faulty.
For the example circuit, all capacitors must be entered in the same manner:
Name Value Pin 1 Pin 2
C1 360 NF INPUT TR1.B
C2 100 NF TR1.C OUTPUT
When entering electrolytic capacitors, attention must be paid to two special aspects:
the unit microfarad is identified using a “U”. The positive pole is termed pin A (=
anode), the minus pole as pin C (=cathode).
BDL example for capacitor C3 (electrolytic)
POL_CAP
NAME 'C3'
PART_ID 'C300.4711'
VALUE 100 UF
TOL+ 10% TOL- 10%
PIN_A 'TR1.E'
PIN_C 'GND'
ERR_MSG 'Problem with C3'
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4.3.2.3 Entry of the Transistor
Getting Started
Preparation of the Circuit Documentation
Name Value Pin A Pin C
C3 100 UF TR1.E GND
BDL example for transistor T1
TRANSISTOR
NAME 'TR1'
PART_ID 'T1000'
NPN
UBE 0.6 V
TOL+ 30% TOL- 30%
I_LIM 100.0 MA
PIN_E 'TR1.E'
PIN_B 'TR1.B'
PIN_C 'TR1.C'
ERR_MSG 'Problem with T1'
The following information on a transistor must be edited in a text editor:
NAME Component name
PART_ID Optional component identifier for the component
NPN, PNP Type of transistor
UBE Base-emitter voltage of the transistor in the forward
bias region
TOL+ Positive component tolerance in %
TOL- Negative component tolerance in %
I_LIMIT Maximum measuring current for determining the
value with unit (default value 100 mA)
PIN_E Test point for the transistor's emitter
PIN_B Test point for the transistor's base
PIN_C Test point for the transistor's collector
ERR_MSG Optional error text The text entered here is dis-
played in the report if the component has been
detected as faulty.
Name Type Pin E Pin B Pin C
TR1 N TR1.E TR1.B TR1.C
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4.4 Preparing the ICT program
Getting Started
Preparing the ICT program
Once the circuit description is available as a BDL file, an ICT program can be prepared
with the aid of the Automatic Test Generator ATG.
The Automatic Test Generator ATG is described in section 9.2.
Start the Automatic Test Generator ATG using Start
-> Programs -> GTSL -> Automatic Test Generator.
The following files must be entered in the ATG:
Example1.BDL
●
path and file name for the BDL file (circuit description)
●
Example_Physical.INI
path and file name for the Physical Layer Configuration File (hardware description
of the test system)
Following the automatic generation process, the ATG prepares the following files:
Example1_Report.TXT
●
report with the data on the generation process
Any errors that have occurred during the generation process are indicated in the
report using error messages and warning messages (see section 9.3.2.1). Only
when there are no error messages or warning messages is the ICT program prepared. In addition, the alternative suggestions (proposals) made by the ATG are to
be noted (see section 9.3.2.2).
Example1.ICT
●
ICT program for execution in R&S EGTSL
The layout of the automatically generated ICT program is defined by a structure
anchored in the ATG. In principle, the fully generated test program has the following layout:
– Capacitor discharging (Discharge)
– Contact test (Contact)
– Continuity and short-circuit test (Short)
– Group of analog tests (In-Circuit)
Example1_Application.INI
●
Application Layer Configuration File for the execution of the ICT program generated in R&S EGTSL
In the Application Layer Configuration File, the specific information for the usage of
the hardware is compiled by the ATG for the ICT program generated. On the execution of the ICT program, the name of the Application Layer Configuration File
generated must be given.
Example1.ICC
●
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4.5 Adapter Manufacture
Getting Started
Commissioning and Debugging
ICC program for execution with IC-Check program. See Chapter 9.3.5, "ICC Pro-
gram", on page 194 and "Software Description IC-Check" for details.
In the Application Layer Configuration File generated by the Automatic Test Generator
ATG, an I/O channel on the R&S TS-PMB Matrix Module B is allocated to each test
point (node) of the circuit.
Example:
[io_channel->ICT]
GND = PMB1!P1
INPUT = PMB1!P2
OUTPUT = PMB1!P3
TR1.B = PMB1!P4
TR1.C = PMB1!P5
TR1.E = PMB1!P6
VCC = PMB1!P7
[io_wiring->ICT]
GND = F1 S15 X10A1
INPUT = F1 S15 X10A2
OUTPUT = F1 S15 X10A3
TR1.B = F1 S15 X10A4
TR1.C = F1 S15 X10A5
TR1.E = F1 S15 X10A6
VCC = F1 S15 X10A7
This information can be used for the manufacture of the adapter.
4.6 Commissioning and Debugging
The newly prepared ICT program is now, together with the finished adapter, ready to
use. However, correct operation should first be checked on a few circuit boards. It may
be necessary to slightly change test value limits or adjust settings.
The user interface for R&S EGTSL ( R&S EGTSL IDE ) for debugging (and executing)
ICT programs can be started in two ways:
1. Start the user interface from a test sequence using a function call from the ICT test
library (see section 13.1)
2. Start the user interface using the Loader (see section 13.2)
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Getting Started
Commissioning and Debugging
Figure 4-2: R&S EGTSL User Interface (R&S EGTSL IDE)
When starting the R&S EGTSL IDE from a test sequence, the ICT program is automatically opened with the corresponding bench. When starting the R&S EGTSL IDE using
the R&S EGTSL Loader, the ICT program must be opened manually using the menu
command File -> Open. When opening the ICT file, the corresponding bench for executing the ICT program must be entered.
Modifications can be made to the ICT program in the various windows of the user interface. When the debugger is activated, various types of program execution are possible:
●
Complete execution of the ICT program
●
Execution in single steps
●
Execution until an error occurs
●
Execution of marked test steps
The various windows, menu commands and buttons on the R&S EGTSL user interface
(R&S EGTSL IDE ) are described in section 5. The detailed procedure for debugging
ICT programs is described in section 15.
As the example circuit will probable not be built and an adapter has not been produced, the ICT program can only be tested and debugged in the simulation mode. For
this purpose it is necessary to activate the simulation in the Application Layer Configuration File in the section [bench->...].
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Getting Started
Commissioning and Debugging
[bench->ICT]
Description = ICT bench (Simulation)
Simulation = 1
Trace = 0
ICTDevice1 = device->psam
ICTDevice2 = device->pict
SwitchDevice1 = device->pmb1
AppChannelTable = io_channel->ICT
When the ICT program is opened with the corresponding bench, all functions in the
ICT program and the R&S EGTSL user interface can be executed in the simulation
mode.
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5.1 General
User Interface (R&S EGTSL IDE)
5 User Interface (R&S EGTSL IDE)
The EGTSL debugging environment has the familiar look of modern Windows applications.
With this graphical user interface, you can quickly master the full spectrum of functionality. There is no need to learn a special programming language or work with a predefined screen layout. Test engineers can create their own desktop and display all
required information on one screen. They can scale, move, and display the windows as
needed.
Within the EGTSL debugging environment, you can do the following:
●
Create, delete or move test steps by a mouse click or drag and drop
●
Change settings of test steps, e.g. limits, test method, stimuli and measurement
●
Define specific timing models
●
Use functionalities such as setting breakpoints, step into or over certain test steps
●
Define and handle different variants
●
Export and import limits
●
Use statistical tools such as histograms to verify stable results
●
Display a detailed test report.
General
To operate the Enhanced Generic Test Software Library R&S EGTSL, basic skills in
the usage of the Microsoft Windows operating systems are required.
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5.2 Menu Structure
User Interface (R&S EGTSL IDE)
Menu Structure
Figure 5-1: Menu structure
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R&S®EGTSL
5.3 Main Screen
User Interface (R&S EGTSL IDE)
Subwindow
Figure 5-2: Main screen R&S EGTSL
1 = Menu bar (see Chapter 5.6, "Menu bar Functions", on page 110)
2 = Toolbars (see Chapter 5.7, "Toolbar Functions", on page 128)
3 = Program subwindow (seeChapter 5.4.2, "Program Subwindow", on page 40)
4 = Test Properties subwindow (see Chapter 5.4.4, "Test Properties Subwindow", on page 43 and Chap-
ter 5.5, "Test Steps", on page 47)
5 = Results subwindow (see Chapter 5.4.5, "Results Subwindow", on page 43)
6 = Status bar
7 = Debug subwindow (seeChapter 5.4.6, "Debug Subwindow", on page 46)
8 = Report subwindow (see Chapter 5.4.3, "Report Subwindow", on page 42)
5.4 Subwindow
5.4.1 Positioning of the Subwindows
See Figure 5-2.
The Program and Report subwindows have a fixed position on the left of the R&S
EGTSL screen. The vertical division between the two windows can be varied using the
mouse.
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R&S®EGTSL
5.4.2 Program Subwindow
User Interface (R&S EGTSL IDE)
Subwindow
The Test Properties, Result and Debug subwindows are displayed on the right of the
R&S EGTSL screen in a fixed position with a fixed size. The size of the Program and
Report subwindows is automatically adjusted when the Test Properties, Result and
Debug subwindows are displayed. The position of the Test Properties, Result and
Debug subwindows can be changed using the mouse. On the right of the R&S EGTSL
screen the Test Properties, Result and Debug subwindows dock in a fixed position
when moved. When the Ctrl key is pressed, the Test Properties, Result and Debug
subwindows can be moved to any position using the mouse (no docking).
The size of the Result subwindow can be changed using the mouse (horizontal and
vertical). By double-clicking the Result subwindow, you can change between the freely
selectable position (and size) and the fixed position on the right of the R&S EGTSL
screen.
Figure 5-3: Program subwindow
The ICT program is displayed on the left of the Program subwindow together with its
individual program groups in a tree structure. The individual test steps in the ICT program are displayed on the right of the Program subwindow.
The horizontal distribution between the two windows can be varied using the mouse.
The navigation within the two windows and the editing of test steps is performed using
the familiar Windows mouse and key commands, e.g.:
Left mouse button pressed Move and mark test steps and groups
Ctrl + left mouse button Mark several test steps
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R&S®EGTSL
5.4.2.1 Context Menu
User Interface (R&S EGTSL IDE)
Subwindow
Shift + left mouse button Mark a range of test steps
Right mouse button Open the context menu
When you click the right mouse button in the Program window, a context menu is
opened.
Figure 5-4: Program context menu
"Cut" Deletes the marked test step or the marked program
group and copies it to the Clipboard.
"Copy" Copies the marked test step or the marked program
group to the Clipboard.
"Paste" Inserts the contents of the Clipboard (test step, pro-
gram group, text content) at the current cursor position.
"Delete" Deletes the marked test step or the marked program
group.
"Insert" Opens the list box for inserting test steps or program
groups. On this topic, see also Chapter 5.5, "Test
Steps", on page 47.
"Rename" Enables the marked test step name or program
group name to be edited.
"Step Properties" Opens the dialog box for the step properties for the
selected test step or the selected program group.
On this topic, see also Chapter 5.6.2.3, "Menu Com-
mand <Step Properties>", on page 121.
"Set Next Step" Marks the cursor position as the test step that is to
be executed next. A yellow arrow is displayed on the
left beside the selected test step.
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5.4.3 Report Subwindow
User Interface (R&S EGTSL IDE)
Subwindow
Figure 5-5: Report subwindow
All messages from the ICT are displayed in the Report window. These messages
include:
●
Information on report preparation
●
The test result for each test step with the measured values determined.
●
Errors during the compilation of the test steps or the ICT program.
The vertical size of the Report window can be changed by dragging using the mouse.
Additional information on the report format is described in Chapter 14, "Report For-
mat", on page 243.
5.4.3.1 Context Menu
When you click the Report window using the right mouse button, a context menu is
opened.
Figure 5-6: Report context menu
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R&S®EGTSL
5.4.4 Test Properties Subwindow
User Interface (R&S EGTSL IDE)
Subwindow
"Copy" Copies all marked entries in the Report window to
the Clipboard. Using the familiar Windows keyboard
and mouse commands, you can mark the entries in
the Report window.
"Select All" Marks all entries in the Report window.
"Clear" Deletes all entries in the Report window.
"Report Enable" With this function activated, a report is displayed in
the Report window.
"Errors Only" With this function activated, only erroneous mea-
surements and error messages are displayed in the
Report window.
In the Test Properties subwindow, the test step-specific settings are made. The various
windows are displayed for every type of test step.
The functions in the individual windows are described in Chapter 5.5, "Test Steps",
on page 47 with the individual test steps.
5.4.5 Results Subwindow
The measured results from the individual test steps of the ICT program are displayed
in the Result windows in various ways.
5.4.5.1 Context Menu
When you click the right mouse button in the Tbl, Gfx and Hist result windows, the following context menu is opened.
Figure 5-7: Results context menu
"Clear" Deletes all entries in the Result windows (Tbl, Gfx,
"Copy" Tbl
Hist) for all test steps.
Copies all test entries for the test step marked to the
Clipboard.
Gfx and Hist
Copies the graphic for the test step marked to the
Clipboard.
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5.4.5.2 Results Tbl
User Interface (R&S EGTSL IDE)
Subwindow
Using the Clipboard, you can copy test and graphics to other programs. There you can,
e.g., edit, save or print the information copied.
Figure 5-8: Results Table
In the Results/Tbl window, the test results for the test step marked are displayed in a
table. The information displayed varies depending on the type of test step selected
(measured values, values for limits, etc.).
5.4.5.3 Results Gfx
Figure 5-9: Results Graphic
In the Results/Gfx window, the test results for the test step marked are displayed
graphically. The information displayed varies depending on the type of test step
selected. The measured results for the individual measurements and the stipulated values for the limits (horizontal lines) are displayed.
If a test step provides several test results (e.g. diode, transistor), the first test result is
displayed in red. The second test result is displayed in blue.
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5.4.5.4 Results Hist
User Interface (R&S EGTSL IDE)
Subwindow
Figure 5-10: Results History
In the Results/Hist window, the distribution of the measured results for the test step
marked is displayed graphically. The information displayed varies depending on the
type of test step selected. In addition, the stipulated values for the limits are displayed
as vertical lines.
If a test step provides several test results (e.g. diode, transistor), the first test result is
displayed in red. The second test result is displayed in blue.
5.4.5.5 Results Details
Figure 5-11: Results Details
In the Results/Details window, detailed information on the test step marked is displayed. The information displayed varies depending on the type of test step selected.
When you click the right mouse button in the Result window, the following context
menu is opened.
Figure 5-12: Results context menu
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5.4.6 Debug Subwindow
User Interface (R&S EGTSL IDE)
Subwindow
"Undo" This function is not available because the Results/
Details window is “read only”.
"Cut" This function is not available because the Results/
Details window is “read only”.
"Copy" Copies the text entry marked to the Clipboard.
"Paste" This function is not available because the Results/
Details window is “read only”.
"Delete" This function is not available because the Results/
Details window is “read only”.
"Select All" Marks all entries in the Results window.
Figure 5-13: Debug
In the "Debug" subwindow, the settings for executing (individual) test steps are made.
The marked test steps are executed. Only contiguous blocks of test steps can be executed. No test steps can be skipped.
To execute the test steps, the debugger must be started (a test step must be selected
using the yellow arrow). The message Debugger ready is given in the status bar. The
debug mode is activated with the following functions:
●
Step Into [F11]
●
Step Over [F10]
●
Step Out [Shift+F11]
●
Run to Cursor [Ctrl+F11]
●
Set Next Step [Ctrl+Shift+F10]
Further information on debugging ICT programs is given in Chapter 12, "Debugger",
on page 226.
"Variant": In the "Variant" list box, the test steps marked with
a variant are enabled for execution. With the selection <default> test steps with a variant marker are
not executed. Test steps without a variant marker
are always executed.
The variants entered in the Variant list box apply not only to the execution of test steps
using the Debug subwindow (see Figure 5-13) but also for all other debug functions
(see Chapter 5.6.4, "Main Menu Command <Debug>", on page 125).
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User Interface (R&S EGTSL IDE)
Test Steps
" Break at fail" With this function activated, the execution of the ICT
program (test steps marked) is interrupted when the
test step result was “Fail”. The program stops at the
erroneous test step. The "Break at fail" function
applies only to the "Repeat" function.
"Stop at fail" With this function activated, the ICT program execu-
tion is stopped when the test step result was “Fail”.
The program stops at the erroneous test step. The
"Stop at fail" function applies to all debug commands with the exception of the "Repeat" function.
Repeat: In the "Repeat" field, you can define how often the
marked test steps are to be executed.
Starts the execution of the test steps marked with
the number of repetitions given
Continues the execution of the test steps marked on
an interruption using the "Break" button.
Interrupts the execution of the test steps marked.
5.5 Test Steps
5.5.1 Contact
The contact test is described in Chapter 10.3, "Contact Test", on page 197.
5.5.1.1 General
Figure 5-14: Test Step Contact, Test Properties General
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User Interface (R&S EGTSL IDE)
Test Steps
Pins
"All but not" With this check box selected, all available measur-
"Pin List" Check box "All but not" cleared:
Evaluation
"Resistor Limit" The maximum resistance that is still evaluated as a
ing pins are checked for contact. The list of available
measuring pins is read from the “Available Pins”
(see Chapter 5.5.12.2, "Editing Pin Lists",
on page 105). The measuring pins given in the "Pin
List" are not checked for contact.
all the measuring pins entered in the Pin List are
checked for contact.
Check box "All but not" selected:
all pins except for the measuring pins entered in the
Pin List are checked for contact.
Opens the "Pins" dialog box for inserting / removing
pins on the Pin List. For more information, see
Chapter 5.5.12.2, "Editing Pin Lists", on page 105.
contact is entered in this field.
Value range:
1 kΩ ... 1 MΩ
Default:
1 MΩ
Source Instrument
"Voltage" The voltage of the voltage source is entered in this
"Current Limit" The current limit of the voltage source is entered in
5.5.1.2 Results Details
For the Contact test step, the following information is displayed in the Results/Details
window after the execution of test step:
field.
Value range:
1.0 V ... 5.0 V
Default:
2.5 V
this field.
Value range:
1.0 µA ... 5.0 mA
Default:
50 µA
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5.5.2 Continuity
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-15: Test Step Contact, Results Details
The continuity test is described in Chapter 10.4, "Continuity Test", on page 199.
5.5.2.1 General
Figure 5-16: Test Step Continuity, Test Properties General
Pins
"Pin List" All measuring pins entered in the "Pin List" are
checked for continuity.
Opens the "Pins" dialog box for inserting / removing
pins on the Pin List. For more information, see
Chapter 5.5.12.2, "Editing Pin Lists", on page 105.
Evaluation
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User Interface (R&S EGTSL IDE)
Test Steps
"Resistor Limit" The maximum resistance that is still evaluated as
continuity is entered in this field.
Value range:
1 Ω ... 1 kΩ
Default:
10 Ω
Source Instrument
"Voltage" The voltage of the voltage source is entered in this
"Current Limit" The current limit of the voltage source is entered in
5.5.2.2 Timing
field.
Value range:
0.1 V ... 0.5 V
Default:
0.2 V
this field.
Value range:
1 µA ... 100 mA
Default:
100 mA
Figure 5-17: Test Step Continuity, Test Properties Timing
The individual options for the timing of the measurement operation are described in
more detail in Chapter 5.5.12.1, "Timing", on page 103.
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User Interface (R&S EGTSL IDE)
Test Steps
"Max. Wait Interval" The maximum duration of the test interval for each
individual pin is entered in this field (maximum 20
samples).
Value range:
0 ms ... 10 s
Resolution:
1 ms (at a Max. Wait Interval of 1 ms a sample is
taken every 50 μs)
Default:
20 ms
"Max. Wait Accuracy" In this field, the maximum percentage difference
between two measured values in succession (samples) is entered for test steps in which the measured
value is applied (measurement with “Max. Wait
Interval”).
Value range:
0.0 % ... 10.0 %
Default:
1.0 %
5.5.2.3 Results Details
For the Continuity test step, the following information is displayed in the Results/
Details window after the execution of test step:
Figure 5-18: Test Step Continuity, Results Details
"Duration" Duration of the last Continuity test step executed
5.5.3 Diode
The diode test is described in Chapter 10.5, "Diode Test", on page 200.
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5.5.3.1 Limits
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-19: Test Step Diode, Test Properties Limits
"Enable" During the diode test, two measurements are per-
formed optionally:
●
"Voltage Measurement"
Measurement of the forward bias voltage (knee
voltage)
●
"Current Measurement"
Measurement of the reverse bias current
The related measurement is performed when the
check box is selected. At least one measurement
must be activated.
Voltage Measurement
"Nominal" The nominal value for the forward bias voltage
"Upper Limit"
"Lower Limit"
"Absolute / Relative" This setting determines whether limits will be
(knee voltage) to be measured is entered in this
field.
The upper and lower limits of the measured forward
bias voltage (knee voltage) can be entered in these
fields. The fields on the left contain the absolute
value in the same unit as the nominal value. The
fields on the right contain the deviation from the
nominal value as a percentage.
Inactive input fields (which appear in gray) are recalculated and displayed with the command "Edit…
Apply".
entered as absolute values or relative values.
Current Measurement
"Nominal" The nominal value for the reverse bias current to be
measured is entered in this field.
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User Interface (R&S EGTSL IDE)
Test Steps
"Upper Limit"
"Lower Limit"
"Absolute / Relative" This setting determines whether limits will be
5.5.3.2 Settings
The upper and lower limits of the measured reverse
bias current can be entered in these fields. The
fields on the left contain the absolute value in the
same unit as the nominal value. The fields on the
right contain the deviation from the nominal value as
a percentage.
Inactive input fields (which appear in gray) are recalculated and displayed with the command "Edit…
Apply".
entered as absolute values or relative values.
Figure 5-20: Test Step Diode, Test Properties Settings
Voltage Measurement
"Voltage" The voltage of the voltage source is entered in this
field.
Value range:
-5.0 V ... 5.0 V
Default:
2.0 V
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User Interface (R&S EGTSL IDE)
Test Steps
"Current" The current limit of the voltage source is entered in
this field.
Value range:
1.0 A ... 100 mA
Default:
10 mA
"Range" The measuring range of the voltmeter is entered in
this field.
Value range:
10 mV ... 5.0 V
Default:
1.0 V
Current Measurement
"Voltage" The voltage of the voltage source is entered in this
"Current" The current limit of the voltage source is entered in
"Range" The measuring range of the current meter is entered
field.
Value range:
-5.0 V ... 5.0 V
Default:
-1.5 V
this field.
Value range:
1.0 µA ... 100.0 mA
Default:
10 mA
in this field.
Value range:
0.0 µA ... 200 mA
Default:
10.0 µA
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5.5.3.3 CNX
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-21: Test Step Diode, Test Properties CNX
"Pin HI" The Pin HI (diode anode) is entered in this field.
"Pin LO" The Pin LO (diode cathode) is entered in this field.
"Pin Guard" The Pin Guard is entered in this field. Several mea-
5.5.3.4 Timing
Only one measuring pin can be entered.
Only one measuring pin can be entered.
suring pins can be entered. The individual entries
(measuring pins) are separated with commas.
Opens the Pins dialog box for inserting / removing
pins on the Pin List. For more information, see
Chapter 5.5.12.2, "Editing Pin Lists", on page 105.
Figure 5-22: Test Step Diode, Test Properties Timing
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User Interface (R&S EGTSL IDE)
Test Steps
The individual options for the timing of the measuring process are described in more
detail in Chapter 5.5.12.1, "Timing", on page 103. The timing settings can be made
separately for the Voltage Measurement and the Current Measurement.
"Delay" The fixed delay to the start of the measurement is
entered in this field.
Value range:
0 ms ... 1 s
Resolution:
1 ms
Default:
0 ms
"Max. Wait Interval" The maximum duration of the test interval is entered
in this field (maximum 20 samples).
Value range:
0 ms ... 10 s
Resolution:
1 ms (at a Max. Wait Interval of 1 ms a sample is
taken every 50 µs)
Default:
0 ms
"Max. Wait Accuracy" In this field, the maximum percentage difference
between two measured values in succession (samples) is entered for test steps in which the measured
value is applied (measurement with “Max. Wait
Interval”).
Value range:
0.0 % ... 10.0 %
Default:
1.0 %
"Average" The number of measured values from which the
mean for the measured result is to be determined is
entered in this field.
Value range:
1 ... 1000
Default:
1
"Sample Interval" The waiting time between the individual measure-
ments for the formation of the mean is entered in
this field (measurement with "Average" ).
Value range:
5 µs ... 1 s
Resolution:
5 µs
Default:
5 µs (200 kHz)
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5.5.3.5 Results Details
User Interface (R&S EGTSL IDE)
Test Steps
For the Diode test step, the following information is displayed in the Results/Details
window after the execution of test step:
Figure 5-23: Test Step Diode, Results Details
"Status" Status of the measuring hardware:
"Range" Range of the measuring hardware in which the mea-
"Duration" Duration of the last measurement carried out.
5.5.4 Discharge
The discharging of capacitors is described in Chapter 10.6, "Discharging Capacitors",
on page 201.
MU = voltage measuring unit
CMU = current measuring unit
Normal, Overrange, Underrange, Max Wait Timeout.
surement was carried out.
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5.5.4.1 General
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-24: Test Step Discharge, Test Properties General
"Reference Pin List" All measuring pins entered in the "Test Pin List"
"Test Pin List" All measuring pins entered in the "Test Pin List"
"Test Time" The maximum duration of the connection between
5.5.4.2 Results Details
are connected one after the other to the measuring
pins in the "Reference Pin List" via a discharge circuit.
are connected one after the other to the measuring
pins in the "Reference Pin List" via a discharge circuit.
the measuring pins from the "Test Pin List" and the
"Reference Pin List" via the discharge circuit is
entered in this field. The maximum duration for the
discharge of all measuring pins is given.
Value range:
1 ms ... 20 s
Default:
3 s
Opens the "Pins" dialog box for inserting / removing
pins on the Pin List.
For more information, see section 5.5.12.2.
For the Discharge test step, the following information is displayed in the Results/Details
window after the execution of test step:
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5.5.5 FET
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-25: Test Step Discharge, Results Details
"Duration" Duration of the last Discharge test step executed.
The FET test is described inChapter 10.7, "FET Test", on page 202.
5.5.5.1 Limits
Figure 5-26: Test Step FET, Test Properties Limits
"Enable" During the FET test, as an option two measure-
ments are performed:
●
"Voltage VDS - FET Off"
Measurement of the drain-source voltage of the
FET while the FET is in switched off state.
●
"Voltage VDS - FET On"
Measurement of the drain-source voltage of the
FET while the FET is in switched on state.
The related measurement is performed when the
check box is activated. At least one measurement
must be activated.
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User Interface (R&S EGTSL IDE)
Test Steps
Voltage VDS - FET Off
"Nominal" The nominal value for the drain-source voltage of
"Upper Limit"
"Lower Limit"
Voltage VDS - FET On
"Nominal" The nominal value for the drain-source voltage of
"Upper Limit"
"Lower Limit"
the switched off FET is entered in this field.
The upper and lower limits of the measured drainsource voltage can be entered in these fields. The
fields on the left contain the absolute value in the
same unit as the nominal value. The fields on the
right contain the deviation from the nominal value as
a percentage.
Inactive input fields (which appear in gray) are recalculated and displayed with the command "Edit…
Apply".
the switched on FET is entered in this field.
The upper and lower limits of the measured drainsource voltage can be entered in these fields. The
fields on the left contain the absolute value in the
same unit as the nominal value. The fields on the
right contain the deviation from the nominal value as
a percentage.
Inactive input fields (which appear in gray) are recalculated and displayed with the command "Edit…
Apply".
"Absolute / Relative" This setting determines whether limits will be
5.5.5.2 Settings
Figure 5-27: Test Step FET, Test Properties Settings
entered as absolute values or relative values.
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User Interface (R&S EGTSL IDE)
Test Steps
Drain - Source
"Voltage" The value of the TS-PSAM DCS voltage source
"Current" The current limit of the TS-PSAM DCS voltage
Gate - Source
(FET Off and FET On)
"Voltage" The value of the TS-PICT AOS voltage source
between drain and source of the FET is entered in
this field.
Value range:
-5.0 V … 5.0 V
Default:
5.0 V
source is entered in this field.
Value range:
3.0 µA … 100.0 mA
Default:
10.0 mA
between gate and source of the FET is entered in
this field.
Value range:
-5.0 V … 5.0 V
Default:
FET Off:
2.0 V
FET On:
3.0 V
"Gate Resistor" The value of the TS-PICT AOS output resistance
which is connected to the gate of the FET is entered
in this field.
Value range:
0.0 Ω … 1.0 kΩ
Default:
1.0 kΩ
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5.5.5.3 Measurement
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-28: Test Step FET, Test Properties Measurement
Voltage VDS-FET Off
and
Voltage VDS-FET On
"Voltage Range" The measuring range of the TS-PSAM voltmeter is
"Autorange" The measuring range for the voltmeter is set auto-
5.5.5.4 CNX
entered in this field.
Value range:
10.0 mV … 200.0 V
Default:
5.0 V
matically when this check box is selected.
Figure 5-29: Test Step FET, Test Properties CNX
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5.5.5.5 Timing
User Interface (R&S EGTSL IDE)
Test Steps
"Pin Gate" The gate pin (gate of the FET) is entered in this
field. Only one measuring pin can be entered.
"Pin Drain" The drain pin (drain of the FET) is entered in this
field. Only one measuring pin can be entered.
"Pin Source" The source pin (source of the FET) is entered in
this field. Only one measuring pin can be entered.
Opens the "Pins" dialog box for inserting / removing
pins on the Pin List. For more information, see section 5.5.12.2.
Figure 5-30: Test Step FET, Test Properties Timing
The individual options for the timing measurement operation are described in more
detail in Chapter 5.5.12.1, "Timing", on page 103.
Voltage VDS-FET Off
and
Voltage VDS-FET On
"Delay" The fixed delay to the start of the measurement is
entered in this field.
Value range:
0 ms ... 1 s
Resolution:
1 ms
Default:
0 ms
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Test Steps
"Max. Wait Interval" The maximum duration of the test interval is entered
in this field (maximum 20 samples).
Value range:
0 ms ... 10 s
Resolution:
1 ms
Default:
0 ms
"Max. Wait Accuracy" In this field, the maximum percentage difference
between two measured values in succession (samples) is entered for test steps in which the measured
value is applied (measurement with "Max. Wait
Interval").
Value range:
0.0 % ... 10.0 %
Default:
1.0 %
"Average" The number of measured values from which the
mean for the measured result is to be determined is
entered in this field.
Value range:
1 ... 1000
Default:
1
"Sample Interval" The waiting time between the individual measure-
5.5.5.6 Results Details
For the FET test step, the following information is displayed in the Results/Details window after the execution of the test step:
ments for the formation of the mean is entered in
this field (measurement with Average ).
Value range:
5 µs ... 1 s
Resolution:
5 µs
Default:
5 µs (200 kHz)
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Test Steps
Figure 5-31: Test Step FET, Results Details
VMU = Voltage measuring unit (TS-PSAM)
DCS = DC Source (TS-PSAM)
Voltage VDS Off
and
Voltage VDS On
"Status VMU" Status of the voltage measurement unit:
"Range VMU" Range of the voltage measurement unit, in which
"Duration" Duration of the last measurement carried out.
"Status DCS" Shows whether the TS-PSAM DCS voltage source
5.5.6 Impedance
The impedance test is described in Chapter 10.8, "Impedance Test", on page 203.
Normal, Overrange, Underrange, Max Wait Timeout
the measurement was carried out.
is in the expected state. At the FET Off measurement the DCS must be in constant voltage state and
at the FET On measurement the DCS must be in
constant current state. If the DCS is in the expected
state 'Normal' is displayed.
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5.5.6.1 Limits
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-32: Test Step Impedance, Test Properties Limits
"Measurement" The type of measured result and the related unit are
selected in this drop-down list box. The internal calculation of the measured result is performed as a
function of the measuring type selected (see also
section Chapter 5.5.6.5, "Determination of Mea-
sured Value", on page 72 ).
"Nominal" The nominal value for the impedance to be mea-
sured is entered in this field.
"Upper Limit"
" Lower Limit"
"Absolute / Relative" This setting determines whether limits will be
"Correction" A correction value can be entered in this field. The
The upper and lower limits of the measured impedance can be entered in these fields. The fields on
the left contain the absolute value in the same unit
as the nominal value. The fields on the right contain
the deviation from the nominal value as a percentage. Inactive input fields (which appear in gray) are
recalculated and displayed with the command
"Edit…Apply".
entered as absolute values or relative values.
unit of the nominal value is assumed for that entry.
The correction value is subtracted from the measurement. The result of the subtraction is compared
with the limits.
The correction value is handled together with the
limits. This makes it possible to load, import and
export it with the limits. See Chapter 5.6.1.7, "Menu
Command <Limits>", on page 114 how to do that.
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5.5.6.2 Method
User Interface (R&S EGTSL IDE)
Test Steps
The value ranges for Nominal, Upper Limit and Lower Limit are defined by the measuring and stimulation properties of the measuring hardware available. The related information is to be found in the user manuals and the data sheets on the measuring hardware.
For the 2-wire measurements, it is possible to specify a common correction value for
all DUTs of a bench in the Application Layer Configuration File. For details, see Chap-
ter 3.2.3, "Entries in APPLICATION.INI", on page 22.
Figure 5-33: Test Step Impedance, Test Properties Method
"Wires" The impedance measuring method is selected in
this drop-down list box. The measuring methods are
described in Chapter 10.9, "Resistor Test",
on page 209.
"Pin HI" The Pin HI for all measuring methods is entered in
this field. Only one measuring pin can be entered.
"Pin LO" The Pin LO for all measuring methods is entered in
this field. Only one measuring pin can be entered.
"Pin Sense HI" The Pin Sense HI is entered in this field for the fol-
lowing measuring methods:
●
4-wire measuring method
●
6-wire guarded measuring method
Only one measuring pin can be entered.
"Pin Sense LO" The Pin Sense LO is entered in this field for the fol-
lowing measuring methods:
●
4-wire measuring method
●
6-wire guarded measuring method
Only one measuring pin can be entered.
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Test Steps
"Pin Guard" The Pin Guard is entered in this field for the follow-
ing measuring methods:
●
3-wire guarded measuring method
●
4-wire guarded measuring method
●
6-wire guarded measuring method
Several measuring pins can be entered.
"Pin Sense Guard" The Pin Sense Guard is entered in this field for the
following measuring methods:
●
4-wire guarded measuring method
●
6-wire guarded measuring method
Only one measuring pin can be entered.
Opens the Pins dialog box for inserting / removing
pins on the Pin List. For more information, see
Chapter 5.5.12.2, "Editing Pin Lists", on page 105.
Exchanges the contents of the Pin HI / Pin LO and
Pin Sense HI / Pin Sense LO edit fields.
Figure 5-34: R&S TS-PMB wiring
As can be seen in Figure 5-34, only the following wiring between analog bus and UUT
is possible for the R&S TS-PMB Matrix Module B:
Analog Bus Pin
A1 P1, P3, P5, P7, P9, ... , P87, P89
A2 P2, P4, P6, P8, P10, ... , P88, P90
B1 P1, P3, P5, P7, P9, ... , P87, P89
B2 P2, P4, P6, P8, P10, ... , P88, P90
C1 P1, P3, P5, P7, P9, ... , P87, P89
C2 P2, P4, P6, P8, P10, ... , P88, P90
D1 P1, P3, P5, P7, P9, ... , P87, P89
D2 P2, P4, P6, P8, P10, ... , P88, P90
For guarded 6-wire impedance measurement, please note that the wiring is to be done
in the following way:
●
The Pins HI and Sense HI must be complementary, i.e. HI even and Sense HI odd
or HI odd and Sense HI even.
●
The Pins LO and Sense LO must also be complementary.
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Test Steps
●
For the Pin Guard and Sense Guard, there are no limitations. Guard is a pin list
and can contain a combination of even and odd pins.
Example:
Pin HI even
Pin Sense HI odd
Pin LO odd
Pin Sense LO even
Pin Guard even, odd...
Pin Sense Guard odd
If this even/odd rule is not adhered to, the Enhanced Generic Test Software Library
R&S EGTSL will report a compile error.
During generation of an ICT program by the Automatic Test Generator ATG this
even/odd rule is followed.
5.5.6.3 Settings
Figure 5-35: Test Step Impedance, Test Properties Settings
Source
"Voltage" The voltage of the signal source is selected in this
drop-down list box.
Value range:
0.1 V, 0.2 V, 1.0 V
Default:
0.2 V
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Test Steps
"Frequency" The frequency of the signal source is selected from
this drop-down list box.
Value range:
100 Hz, 1 kHz, 10 kHz
Default:
10 kHz
"Offset" The offset of the signal source is selected from this
drop-down list box.
Value range:
none, positive, negative
Default:
none
Measurement
"Voltage Range" The measuring range of the voltmeter is entered in
"Current Range" The measuring range of the current meter is entered
"Autorange" The measuring ranges of the voltmeter and current
"Min. Current Range" The smallest permissible measuring range for the
this field.
Value range:
10 mV ... 5 V
Default:
0.2 V
in this field.
Value range:
1 µA ... 100 mA
Default:
100 mA
meter are set automatically when this check box is
selected.
current meter on the use of the Autorange function
is entered in this field.
Value range:
1 µA ... 200 mA
Default:
2 µA
In some measuring conditions, the smallest measuring ranges are unstable. More reliable measured results are obtained in larger measuring ranges.
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5.5.6.4 Timing
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-36: Test Step Impedance, Test Properties Timing
The individual options for the timing of the measurement operation are described in
more detail in Chapter 5.5.12.1, "Timing", on page 103.
"Delay" The fixed delay to the start of the measurement is
entered in this field.
Value range:
0 ms ... 1 s
Resolution:
1 ms
Default:
0 ms
"Max. Wait Interval" The maximum duration of the test interval is entered
in this field (maximum 20 samples).
Value range:
0 ms ... 10 s
Resolution:
1 ms
Default:
0 ms
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5.5.6.5 Determination of Measured Value
User Interface (R&S EGTSL IDE)
Test Steps
"Max. Wait Accuracy" In this field, the maximum percentage difference
between two measured values in succession (samples) is entered for test steps in which the measured
value is applied (measurement with “Max. Wait
Interval”).
Value range:
0.0 % ... 10.0 %
Default:
1.0 %
"Average" The number of signal periods to be measured from
which a mean is formed for the measured result is
entered in this field.
Value range:
1 ... 1000
Default:
1
Figure 5-37: Equivalent circuit diagrams for determination of measured value
An equivalent circuit must be entered for the calculation of the required measured
result for the capacitance measurement and the inductance measurement (see Figure
5-37). The selection is made using the "Measurement" drop-down list box in Test
Properties Limits.
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Test Steps
Table 5-1: Determination of measured value (1/2)
Measurement Measured result Equivalent circuit Unit
CAP-PAR Capacitance Capacitance measure-
ment based on a parallel
equivalent circuit
CAP-SER Capacitance Capacitance measure-
ment based on a serial
equivalent circuit
IND-PAR Inductance Inductance measure-
ment based on a parallel
equivalent circuit
IND-SER Inductance Inductance measure-
ment based on a serial
equivalent circuit
Farad (F)
Farad (F)
Henry (H)
Henry (H)
Two different representations of the impedance are available for the measurement of
the impedance. On the one hand the representation in real and imaginary parts, on the
other hand the representation in magnitude and phase. An equivalent circuit must be
entered for the calculation of the required measured result for the representation in real
and imaginary parts (see Figure 5-37 ).
Table 5-2: Determination of measured value (2/2)
Measurement Measured result Equivalent circuit Unit
RES-SER Real part of the mea-
sured impedance
Impedance measurement based on a serial
equivalent circuit
Ohm (Ω)
RES-PAR Real part of the mea-
REAC-SER Imaginary part of the
REAC-PAR Imaginary part of the
IMP-MAG Magnitude of the impe-
IMP-PHASE Phase of the measured
5.5.6.6 Results Details
For the Impedance test step, the following information is displayed in the "Results/
Detail"s window after the execution of test step:
sured impedance
measured impedance
measured impedance
dance measured
impedance
Impedance measurement based on a parallel
equivalent circuit
Impedance measurement based on a serial
equivalent circuit
Impedance measured Ohm (Ω)
Ohm (Ω)
Ohm (Ω)
Ohm (Ω)
deg
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Test Steps
Figure 5-38: Test Step Impedance, Results Details
Max. Wait measurement count Number of the measurements which were carried
out with Max.Wait until the measured value was stable.
Max. Wait timeout "Yes", if the measured value was not stable even
after 20 Max. Wait measurements.
VMU Status Status of the voltage measuring unit: Normal, Over-
range, Underrange
VMU Range Range of the voltage measuring unit in which the
measurement was carried out.
CMU Status Status of the current measuring unit: Normal, Over-
range, Underrange
CMU Range Range of the current measuring unit in which the
measurement was carried out.
Z Real part and imaginary part of the impedance
|Z|, arg(Z) Magnitude and Phase of the impedance
Capacitor par. Measured value for the parallel equivalent circuit
diagram
Capacitor ser. Measured value for the serial equivalent circuit dia-
gram
Correction Bench Bench-specific correction value taken into account
for calculating the result. The indicated value is
specified in the Application Layer Configuration File.
For details, see Chapter 3.2.3, "Entries in APPLICA-
TION.INI", on page 22section .
Correction Test Test-specific correction value taken into account for
calculating the result. The indicated value is specified in the test properties limits.
Duration Duration of the last Impedance test step carried out.
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5.5.7 Resistor
5.5.7.1 Limits
User Interface (R&S EGTSL IDE)
Test Steps
The resistor test is described in Chapter 10.9, "Resistor Test", on page 209.
Figure 5-39: Test Step Resistor, Test Properties Limits
"Nominal" The nominal value for the resistor to be measured is
entered in this field.
"Upper Limit"
"Lower Limit"
"Absolute / Relative" This setting determines whether limits will be
"Correction" A correction value can be entered in this field. The
The upper and lower limits of the measured resistor
can be entered in these fields. The fields on the left
contain the absolute value in the same unit as the
nominal value. The fields on the right contain the
deviation from the nominal value as a percentage.
Inactive input fields (which appear in gray) are recalculated and displayed with the command "Edit…
Apply".
entered as absolute values or relative values.
unit of the nominal value is assumed for that entry.
The correction value is subtracted from the measurement. The result of the subtraction is compared
with the limits.
The correction value is handled together with the
limits. This makes it possible to load, import and
export it with the limits. See Chapter 5.6.1.7, "Menu
Command <Limits>", on page 114 how to do that.
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R&S®EGTSL
5.5.7.2 Method
User Interface (R&S EGTSL IDE)
Test Steps
The value ranges for Nominal, Upper Limit and Lower Limit are defined by the measuring and stimulation properties of the measuring hardware available. The related information is to be found in the user manuals and the data sheets on the measuring hardware.
For the 2-wire resistor measurements, it is possible to specify a common correction
value for all DUTs of a bench in the Application Layer Configuration File. For details,
see Chapter 3.2.3, "Entries in APPLICATION.INI", on page 22.
Figure 5-40: Test Step Resistor, Test Properties Method
"Wires" The resistance measuring method is selected in this
drop-down list box. The measuring methods are
described in Chapter 10.9, "Resistor Test",
on page 209.
"Pin HI" The Pin HI for all measuring methods is entered in
this field. Only one measuring pin can be entered.
"Pin LO" The Pin LO for all measuring methods is entered in
this field. Only one measuring pin can be entered.
"Pin Sense HI" The Pin Sense HI is entered in this field for the fol-
lowing measuring methods:
●
4-wire measuring method
●
6-wire guarded measuring method
Only one measuring pin can be entered.
"Pin Sense LO" The Pin Sense LO is entered in this field for the fol-
lowing measuring methods:
●
4-wire measuring method
●
6-wire guarded measuring method
Only one measuring pin can be entered.
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Test Steps
"Pin Guard" The Pin Guard is entered in this field for the follow-
ing measuring methods:
●
3-wire guarded measuring method
●
4-wire guarded measuring method
●
6-wire guarded measuring method
Several measuring pins can be entered.
"Pin Sense Guard" The Pin Sense Guard is entered in this field for the
following measuring methods:
●
4-wire guarded measuring method
●
6-wire guarded measuring method
Only one measuring pin can be entered.
Opens the Pins dialog box for inserting / removing
pins on the Pin List. For more information, see
Chapter 5.5.12.2, "Editing Pin Lists", on page 105.
Exchanges the contents of the Pin HI / Pin LO and
Pin Sense HI / Pin Sense LO edit fields.
Figure 5-41: TS-PMB
As can be seen inFigure 5-41, only the following wiring between analog bus and UUT
is possible for the TS-PMB Matrix Module B:
Analog Bus Pin
A1 P1, P3, P5, P7, P9, ... , P87, P89
A2 P2, P4, P6, P8, P10, ... , P88, P90
B1 P1, P3, P5, P7, P9, ... , P87, P89
B2 P2, P4, P6, P8, P10, ... , P88, P90
C1 P1, P3, P5, P7, P9, ... , P87, P89
C2 P2, P4, P6, P8, P10, ... , P88, P90
D1 P1, P3, P5, P7, P9, ... , P87, P89
D2 P2, P4, P6, P8, P10, ... , P88, P90
For guarded 6-wire resistance measurement, the wiring is to be done in the following
way:
●
The Pins HI and Sense HI must be complementary, i.e. HI even and Sense HI odd
or HI odd and Sense HI even.
●
The Pins LO and Sense LO must also be complementary.
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User Interface (R&S EGTSL IDE)
Test Steps
●
For the Pin Guard and Sense Guard, there are no limitations.
Guard is a pin list and can contain a combination of even and odd pins.
Example:
Pin HI even
Pin Sense HI odd
Pin LO odd
Pin Sense LO even
Pin Guard even, odd...
Pin Sense Gurard odd
If this even/odd rule is not adhered to, the Enhanced Generic Test Software Library
R&S EGTSL will report a compile error.
During generation of an ICT program by the Automatic Test Generator ATG this
even/odd rule is followed.
5.5.7.3 Settings
Figure 5-42: Test Step Resistor, Test Properties Settings
"Mode" The type of resistor measurement is selected from
this drop-down list box:
"V": application of voltage with current measurement
" C": application of current with voltage measurement
Source Instrument
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Test Steps
"Voltage" The voltage of the voltage source is entered in this
field.
Value range:
1 mV ... 5 V
Default:
0.2 V
"Current" The current limit of the voltage source is entered in
this field.
Value range:
1 µA ... 100 mA
Default:
100 mA
Measurement Instrument
"Voltage Range" The measuring range of the voltmeter is entered in
"Current Range" The measuring range of the current meter is entered
"Autorange" The measuring ranges for the voltmeter and current
this field.
Value range:
10 mV ... 5 V
Default:
0.2 V
in this field.
Value range:
0 µA ... 200 mA
Default:
100 mA
meter are set automatically when this check box is
selected.
Only one measuring range is relevant depending on the type of resistor measurement:
Mode V: Current Range (application of voltage with current
measurement)
Mode C: Voltage Range (application of current with voltage
measurement)
When Autorange is selected, the search for the optimal measuring range starts with
the values entered in the "Voltage Range" (voltage measurement) and "Current
Range" (current measurement) fields.
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5.5.7.4 Timing
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-43: Test Step Resistor, Test Properties Timing
The individual options for the timing of the measurement operation are described in
more detail in Chapter 5.5.12.1, "Timing", on page 103.
"Delay" The fixed delay to the start of the measurement is
entered in this field.
Value range:
0 ms ... 1 s
Resolution:
1 ms
Default:
0 ms
"Max. Wait Interval" The maximum duration of the test interval is entered
in this field (maximum 20 samples).
Value range:
0 ms ... 10 s
Resolution:
1 ms (at a Max. Wait Interval of 1 ms a sample is
taken every 50 μs)
Default:
0 ms
"Max. Wait Accuracy" In this field, the maximum percentage difference
between two measured values in succession (samples) is entered for test steps in which the measured
value is applied (measurement with “Max. Wait
Interval”).
Value range:
0.0 % ... 10.0 %
Default:
1.0 %
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"Average" The number of measured values from which the
mean for the measured result is to be determined is
entered in this field.
Value range:
1 ... 1000
Default:
1
"Sample Interval" The waiting time between the individual measure-
ments for the formation of the mean is entered in
this field (measurement with Average ).
Value range:
5 µs ... 1 s
Resolution:
5 µs
Default:
5 µs (200 kHz)
5.5.7.5 Results Details
For the Resistor test step, the following information is displayed in the "Results/
Details" window after the execution of test step:
Figure 5-44: Test Step Resistor, Results Details
Max. Wait measurement count Number of the measurements which were carried
Max. Wait timeout "Yes", if the measured value was not stable even
DCS in expected state Shows whether the voltage source is in the expec-
out with Max.Wait until the measured value was stable.
after 20 Max. Wait measurements.
ted status. In Mode C it must be in the current limit,
in Mode V it does not have to be in the current limit.
MU State Status of the voltage measuring unit (Mode C) or of
the current measuring unit (Mode V): Normal, Overrange, Underrange
MU Range Voltage or current range, in which the measurement
was carried out.
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R&S®EGTSL
5.5.8 Short
User Interface (R&S EGTSL IDE)
Test Steps
MU Result Result of the voltage measurement (Mode C) or cur-
rent measurement (Mode V)
Correction Bench Bench-specific correction value taken into account
for calculating the result. The indicated value is
specified in the Application Layer Configuration File.
See section 3.2.3 for details.
Correction Test Test-specific correction value taken into account for
calculating the result. The indicated value is specified in the test properties limits.
Duration Duration of the last Resistor test step carried out
The short-circuit test is described in Chapter 10.10, "Short-circuit Test", on page 213.
5.5.8.1 General
Figure 5-45: Test Step Short, Test Properties General
Pins
"All but not" All available measuring pins are checked for short-
circuit when the check box is selected. The list of
available measuring pins is read from the "Availa-
ble Pins" (see Chapter 5.5.12.2, "Editing Pin Lists",
on page 105). The measuring pins entered in the
"Pin List" are not checked for short-circuit.
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Test Steps
"Pin List" "All but not" check box cleared:
All measuring pins entered in the "Pin List" are
checked for short-circuit.
"All but not" check box selected:
all pins except for the measuring pins entered in the
Pin List are checked for short-circuit.
Opens the Pins dialog box for inserting / removing
pins on the Pin List. For more information, see
Chapter 5.5.12.2, "Editing Pin Lists", on page 105.
Evaluation
"Resistor Limit" The maximum resistance that is still evaluated as a
Source Instrument
"Voltage" The voltage of the voltage source is entered in this
"Current Limit" The current limit of the voltage source is entered in
short-circuit is entered in this field.
Value range:
1 Ω ... 1 kΩ
Default:
10 Ω
field.
Value range:
0.1 V ... 0.5 V
Default:
0.2 V
this field.
Value range:
1 µA ... 100 mA
Default:
100 mA
When the Voltage value is appropriately selected, the threshold voltage can be
designed such that diodes/transistors can be considered the same as missing components. Diode/transistors must not become forward biased.
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5.5.8.2 Timing
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-46: Test Step Short, Test Properties Timing
The individual options for the timing of the measurement operation are described in
more detail in Chapter 5.5.12.1, "Timing", on page 103.
"Max. Wait Interval" The maximum duration of the test interval is entered
in this field (maximum 20 samples).
Value range:
0 ms ... 10 s
Resolution:
1 ms (at a Max. Wait Interval of 1 ms a sample is
taken every 50 μs)
Default:
20 ms
"Max. Wait Accuracy" In this field, the maximum percentage difference
between two measured values in succession (samples) is entered for test steps in which the measured
value is applied (measurement with "Max. Wait
Interval").
Value range:
0.0 % ... 10.0 %
Default:
1.0 %
5.5.8.3 Results Details
For the Short test step, the following information is displayed in the "Results/Details"
window after the execution of test step:
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Test Steps
Figure 5-47: Test Step Short, Results Details
Stage 1:
Duration Duration of the 1st stage.
Suspicious Pins Number of “suspicious” pins found in the first stage.
Total:
Duration Total duration of the measurement.
Failed Pins Number of short-circuited pins.
5.5.9 Transistor
The transistor test is described in Chapter 10.11, "Transistor Test", on page 214.
5.5.9.1 Limits
Figure 5-48: Test Step Transistor, Test Properties Limits
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Test Steps
"Enable" During the transistor test, as an option two measure-
ments are performed:
●
"Voltage VBE"
Measurement of the forward bias voltage (knee
voltage) of the base-emitter diode
●
"Voltage VBC"
Measurement of the forward bias voltage (knee
voltage) of the base-collector diode
The related measurement is performed when the
check box is activated. At least one measurement
must be activated.
"Nominal" The nominal value for the forward bias voltage
(knee voltage) of the base-emitter diode or base-collector diode is entered in this field. The nominal
value and limits are positive for NPN transistors and
negative for PNP transistors.
"Upper Limit"
"Lower Limit"
"Absolute / Relative" This setting determines whether limits will be
5.5.9.2 Settings
The upper and lower limits of the measured forward
bias voltage (knee voltage) of the base-emitter
diode or base-collector diode can be entered in
these fields. The fields on the left contain the absolute value in the same unit as the nominal value.
The fields on the right contain the deviation from the
nominal value as a percentage. Inactive input fields
(which appear in gray) are recalculated and displayed with the command "Edit…Apply".
entered as absolute values or relative values.
Figure 5-49: Test Step Transistor, Test Properties Settings
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Test Steps
Voltage VBE + Voltage VBC
"Voltage" The voltage of the voltage source is entered in this
"Current" The current limit of the voltage source is entered in
"Range" The measuring range of the voltmeter is entered in
field. The voltage is positive for NPN transistors and
negative for PNP transistors.
Value range:
-5.0 V ... 5.0 V
Default:
1.8 V
this field.
Value range:
1.0 µA ... 100.0 mA
Default:
5.0 mA
this field.
Value range:
10.0 mV ... 5.0 V
Default:
1.0 V
5.5.9.3 CNX
Figure 5-50: Test Step Transistor, Test Properties CNX
"Pin Base" The base pin (base of the transistor) is entered in
"Pin Collector" The collector pin (collector of the transistor) is
this field. Only one measuring pin can be entered.
entered in this field. Only one measuring pin can be
entered.
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5.5.9.4 Timing
User Interface (R&S EGTSL IDE)
Test Steps
"Pin Emitter" The emitter pin (emitter of the transistor) is entered
in this field. Only one measuring pin can be entered.
Opens the Pins dialog box for inserting / removing
pins on the Pin List. For more information, see
Chapter 5.5.12.2, "Editing Pin Lists", on page 105.
Figure 5-51: Test Step Transistor, Test Properties Timing
The individual options for the timing of the measurement operation are described in
more detail in Chapter 5.5.12.1, "Timing", on page 103.
Voltage VBE + Voltage VBC
"Delay" The fixed delay to the start of the measurement is
"Max. Wait Interval" The maximum duration of the test interval is entered
entered in this field.
Value range:
0 ms ... 1 s
Resolution:
1 ms
Default:
0 ms
in this field (maximum 20 samples).
Value range:
0 ms ... 10 s
Resolution:
1 ms
Default:
0 ms
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User Interface (R&S EGTSL IDE)
Test Steps
"Max. Wait Accuracy" In this field, the maximum percentage difference
between two measured values in succession (samples) is entered for test steps in which the measured
value is applied (measurement with “Max. Wait
Interval”).
Value range:
0.0 % ... 10.0 %
Default:
1.0 %
"Average" The number of measured values from which the
mean for the measured result is to be determined is
entered in this field.
Value range:
1 ... 1000
Default:
1
"Sample Interval" The waiting time between the individual measure-
ments for the formation of the mean is entered in
this field (measurement with "Average" ).
Value range:
5 µs ... 1 s
Resolution:
5 µs
Default:
5 µs (200 kHz)
5.5.9.5 Results Details
For the Transistor test step, the following information is displayed in the "Results/
Details" window after the execution of test step:
Figure 5-52: Test Step Transistor, Results Details
"Status" Status of the voltage measuring unit:
MU = Voltage measuring unit
Normal, Overrange, Underrange, Max Wait Timeout.
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R&S®EGTSL
5.5.10 Transistor Beta
5.5.10.1 Limits
User Interface (R&S EGTSL IDE)
Test Steps
"Range" Range of the voltage measuring unit, in which the
measurement was carried out.
"Duration" Duration of the last measurement carried out.
The Transistor Beta test is described in Chapter 10.12, "Transistor Beta", on page 214.
Figure 5-53: Test Step Transistor Beta, Test Properties Limits
"Enable" During the transistor beta test, as an option two
measurements are performed:
●
"Voltage VBE"
Measurement of the forward bias voltage (knee
voltage) of the base-emitter diode.
●
"Beta"
Measurement of the dynamic current gain.
The related measurement is performed when the
check box is activated. At least one measurement
must be activated.
Voltage VBE
"Nominal" The nominal value for the forward bias voltage
(knee voltage) of the base-emitter diode is entered
in this field.
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R&S®EGTSL
User Interface (R&S EGTSL IDE)
Test Steps
"Upper Limit"
"Lower Limit"
Beta
"Nominal" The nominal value for the current gain (beta) is
"Upper Limit"
"Lower Limit"
"Absolute / Relative" This setting determines whether limits will be
5.5.10.2 Settings
The upper and lower limits of the measured forward
bias voltage can be entered in these fields. The
fields on the left contain the absolute value in the
same unit as the nominal value. The fields on the
right contain the deviation from the nominal value as
a percentage. Inactive input fields (which appear in
gray) are recalculated and displayed with the command "Edit…Apply".
entered in this field.
The upper and lower limits of the measured current
gain (beta) can be entered in these fields. The fields
on the left contain the absolute value in the same
unit as the nominal value. The fields on the right
contain the deviation from the nominal value as a
percentage. Inactive input fields (which appear in
gray) are recalculated and displayed with the command "Edit…Apply".
entered as absolute values or relative values.
Figure 5-54: Test Step Transistor Beta, Test Properties Settings
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User Interface (R&S EGTSL IDE)
Test Steps
" Transistor Type" The type of the transistor (NPN or PNP).
Note that the voltage values are always entered as
positive numbers.
The actual polarity is determined by the transistor
type.
Collector - Base
"Voltage" The voltage of the R&S TS-PSU / R&S TS-PSU12
"Current" The current limit of the R&S TS-PSU / R&S TS-
Base - Emitter
"Voltage" The voltage of the DCS voltage source between
voltage source between collector and base is
entered in this field.
Value range:
0.0 V … 10.0 V
Default:
5.0 V
PSU12 voltage source is entered in this field.
Value range:
1.0 µA … 100.0 mA
Default:
100.0 mA
base and emitter is entered in this field.
Value range:
0.0 V … 5.0 V
Default:
1.6 V
"Current" The current limit of the DCS voltage source is
entered in this field.
Value range:
1.0 µA … 100.0 mA
Default:
5.0 mA
"Current Delta" The increase of the current limit of the DCS voltage
source between the first and second current measurement is entered in this field.
Value range:
-100.0 mA … 100.0 mA
Default:
2.0 mA
The sum of Current and Current Delta must be in the range 0 mA … 100 mA.
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R&S®EGTSL
5.5.10.3 Measurement
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-55: Test Step Transistor Beta, Test Properties Measurement
Voltage VBE
"Voltage Range" The measuring range of the voltmeter is entered in
"Autorange" The measuring range for the voltmeter is set auto-
Beta
"Current Range" The measuring range of the current meter is entered
"Autorange" The measuring range for the current meter is set
this field.
Value range:
10.0 mV … 100.0 V
Default:
1.0 V
matically when this check box is selected.
in this field.
Value range:
1.0 µA … 100.0 mA
Default:
20.0 mA
automatically when this check box is selected.
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R&S®EGTSL
5.5.10.4 CNX
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-56: Test Step Transistor Beta, Test Properties CNX
"Pin Base" The base pin (base of the transistor) is entered in
this field. Only one measuring pin can be entered.
"Pin Collector" The collector pin (collector of the transistor) is
entered in this field. Only one measuring pin can be
entered.
"Pin Emitter" The emitter pin (emitter of the transistor) is entered
in this field. Only one measuring pin can be entered.
"Pin Guard" The guard pins are entered in this field. Several
measuring pins can be entered. The field remains
empty for unguarded measurements.
Opens the Pins dialog box for inserting / removing
pins on the Pin List. For more information, see
Chapter 5.5.12.2, "Editing Pin Lists", on page 105.
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R&S®EGTSL
5.5.10.5 Timing
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-57: Test Transistor Beta, Test Properties Timing
The individual options for the timing of the measurement operation are described in
more detail in Chapter 5.5.12.1, "Timing", on page 103.
Voltage VBE + Beta
"Delay" The fixed delay to the start of the measurement is
"Max. Wait Interval" The maximum duration of the test interval is entered
entered in this field.
Value range:
0 ms ... 1 s
Resolution:
1 ms
Default:
0 ms
in this field (maximum 20 samples).
Value range:
0 ms ... 10 s
Resolution:
1 ms
Default:
0 ms
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R&S®EGTSL
User Interface (R&S EGTSL IDE)
Test Steps
"Max. Wait Accuracy" In this field, the maximum percentage difference
between two measured values in succession (samples) is entered for test steps in which the measured
value is applied (measurement with “Max. Wait
Interval”).
Value range:
0.0 % ... 10.0 %
Default:
1.0 %
"Average" The number of measured values from which the
mean for the measured result is to be determined is
entered in this field.
Value range:
1 ... 1000
Default:
1
"Sample Interval" The waiting time between the individual measure-
ments for the formation of the mean is entered in
this field (measurement with Average ).
Value range:
5 s ... 1 s
Resolution:
5 µs
Default:
5 µs (200 kHz)
5.5.10.6 Results Details
For the Transistor Beta test step, the following information is displayed in the Results/
Details window after the execution of the test step:
Figure 5-58: Test Step Transistor Beta, Results Details
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User Interface (R&S EGTSL IDE)
Test Steps
Voltage VBE
Status VMU Status of the voltage measurement unit:
Range VMU Range of the voltage measurement unit, in which
Duration Duration of the last measurement carried out.
Current gain BETA
Status CMU Status of the current measurement unit for the first
Range CMU Range of the current measurement unit, in which the
Duration Duration of the last measurement carried out.
Status DCS Status of the DC voltage source DCS:
VMU = Voltage measuring unit (R&S TS-PSAM)
CMU = Current measuring unit (R&S TS-PICT)
DCS = DC Source (R&S TS-PSAM)
PSU = DC Source (R&S TS-PSU / R&S TS-PSU12)
Normal, Overrange, Underrange, Max Wait Timeout
the measurement was carried out.
and second measurement:
Normal, Overrange, Underrange, Max Wait Timeout
measurement was carried out for the first and second measurement.
Normal, Not in constant current state
Status PSU Status of the DC voltage source TS-PSU / TS-
5.5.11 Zener Diode
The Zener Diode test is described in Chapter 5.5.11, "Zener Diode", on page 97.
PSU12:
Normal, Not in constant voltage state
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R&S®EGTSL
5.5.11.1 Limits
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-59: Test Step Zener Diode, Test Properties Limits
"Nominal" The nominal value for the zener voltage (reverse
working voltage) of the zener diode is entered in this
field.
"Upper Limit"
"Lower Limit"
"Absolute / Relative" This setting determines whether limits will be
The upper and lower limits of the measured zener
voltage (reverse working voltage) can be entered in
these fields. The fields on the left contain the absolute value in the same unit as the nominal value.
The fields on the right contain the deviation from the
nominal value as a percentage.
Inactive input fields (which appear in gray) are recalculated and displayed with the command "Edit…
Apply".
entered as absolute values or relative values.
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R&S®EGTSL
5.5.11.2 Settings
User Interface (R&S EGTSL IDE)
Test Steps
Figure 5-60: Test Step Zener Diode, Test Properties Settings
"Voltage" The voltage of the voltage source is entered in this
field.
Value range:
-100 V ... 100 V for TS-PSU
-24 V ... 24 V for TS-PSU12
Default:
3.3 V
"Current" The current limit of the voltage source is entered in
this field.
Value range:
1.0 µA … 100.0 mA
Default:
5.0 mA
When Voltage exceeds 50 V for TS-PSU (12 V for TS-PSU12) , special test adapter
wiring is necessary to cascade the two power supply output channels (see Chap-
ter 5.5.11, "Zener Diode", on page 97).
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5.5.11.3 CNX
User Interface (R&S EGTSL IDE)
Test Steps
"Range" The measuring range of the voltmeter is entered in
this field.
Value range:
10.0 mV … 100.0 V
Default:
5.0 V
"Autorange" The measuring range for the voltmeter is set auto-
matically when this check box is selected.
Figure 5-61: Test Step Zener Diode, Test Properties CNX
" Pin HI (Cathode)" The Pin HI (diode cathode) is entered in this field.
Only one measuring pin can be entered.
"Pin LO (Anode)" The Pin LO (diode anode) is entered in this field.
Only one measuring pin can be entered.
Opens the Pins dialog box for inserting / removing
pins on the Pin List. For more information, see
Chapter 5.5.12.2, "Editing Pin Lists", on page 105.
100User Manual 1143.4140.42 ─ 16
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