ROCKWELLL Bt879KPF, Bt878KPF Datasheet

General Features

• Supports NTSC/PAL/SECAM video decoding

• Supports image resolutions up to 768x576 (full
PAL resolution)

• Supports complex clipping of video source

• Zero wait state PCI burst writes

• Field/frame masking support to throttle
bandwidth to target

• Multiple YCrCb and RGB pixel formats
supported on output

• Image size scalable down to icon using
vertical & horizontal interpolation filtering

• Multiple composite and S-video inputs

• Supports different program control for even
and odd fields

• Supports different color space/scaling factors
for even and odd fields

• Supports planar YUV data format

• Support for mapping of video to 225 color
palette

• VBI data capture for closed captioning,
teletext and Intercast data decoding

• Auxiliary GPIO port to support external
control

• Fully PCI Rev. 2.1 compliant

• Integrated audio ADCs to digitize the
composite audio spectrum

• Mono line level and mic level audio capture

• Audio capture without analog audio cable to
sound card

Bt879 Specific Features

• Full stereo decoding for both TV audio
(BTSC) and FM radio

• Full dbx noise reduction

Applications

• PC Television

• “Smart” PC Radio

• Intercast receiver

• Desktop video phone

• Motion video capture

• Still frame capture

• VBI data services capture

Related Documents

• Fusion Technical Reference Manual

• Fusion Programmers Guide

Advance Information

This document contains information on a product under development.
The parametric information contains target parameters that are subject to change.

40 MHz

ADC

40 MHz

ADC

Decimation LPF

Video FIFO

Target

PCI I/F

Initiator

Composite 1

S-Video (C)

TV

FM

Composite 2

Composite S-Video (Y)

Mic

I

2

S (dig. audio)

(Bt879)

DBX Stereo

Decode

High BW

Audio

ADC

Input

Control

Gain

Ultralock™

and Clock

Generation

Video

and Scaling

Decode

I

2

C

GPIO

Composite 3

DMA

Controller

Audio

FIFO

Audio

Format

Stream

Pixel

Conversion

Format

GPIO and Digital/Video Port

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

Bt878/879

3:1 MUX

Target

Initiator

DMA

Controller

The Bt878/879 is a complete, low cost, single-chip solution for analog broadcast sig­nal capture on the PCI bus. The Bt878/879 takes advantage of the PCI-based sys­tem’s high bandwidth and inherent multimedia capability. It is designed to be inter­operable with any other PCI multimedia device at the component or board level.

The Bt878/879 has all the video capture features of Bt848A, plus integrated
BTSC stereo decode, and FM radio capture data processing. The DMA capability is
enhanced to allow for low latency, digitized audio stream transport. The chip enables
dbx-compliment stereo, TV, FM radio, and base-band video and audio as input
sources. In addition, the chip simplifies the computer/broadcast signal interface
down to a single PCI connection.

Functional Block Diagram

Copyright © 1997 Rockwell Semiconductor Systems. All rights reserved.
Print date: March 1998

Rockwell reserves the right to make changes to its products or specifications to improve performance, reliability, or
manufacturability. Information furnished by Rockwell Semiconductor Systems is believed to be accurate and reliable. Howe ver, no
responsibility is assumed by Rockwell Semiconductor Systems for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by its implication or otherwise under any patent or patent rights of
Rockwell Semiconductor Systems.

Rockwell products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a
Rockwell product can reasonably be expected to result in personal injury or death. Rockwell customers using or selling Rockwell
products for use in such applications do so at their own risk and agree to fully indemnify Rockwell for any damages resulting from
such improper use or sale.

Bt is a registered trademark of Rockwell Semiconductor Systems. Product names or services listed in this publication are for
identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks
mentioned herein are the property of their respective holders.

Specifications are subject to change without notice.

PRINTED IN THE UNITED STATES OF AMERICA

Ordering Information

Model Number

Package Ambient Temperature Range

Bt878KPF 128-pin PQFP 0 ° C to +70 ° C
Bt879KPF 128-pin PQFP 0 ° C to +70 ° C

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List of Figures

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

List of Tables

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

Functional Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Functional Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Video Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Audio Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Analog Video and Digital Camera Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Intel Intercast™ Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

TV/Stereo Support (Bt897 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

FM Radio Stereo Support (Bt879 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Video DMA Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Audio DMA Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Data Transport Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

UltraLock™. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Scaling and Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Input Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

General Purpose I/O (GPIO) Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Vertical Blanking Interval Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Inter-Integrated Circuit (I

2

C) Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Descriptions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

UltraLock™

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

The Challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Operation Principles of UltraLock™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Composite Video Input Formats

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Y/C Separation and Chroma Demodulation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Video Scaling, Cropping, and Temporal Decimation

. . . . . . . . . . . . . . . . . . . . . . . . . . 19

Horizontal and Vertical Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Field Aligned Vertical Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Luminance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Peaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Chrominance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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Scaling Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Image Cropping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Cropping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Temporal Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Video Adjustments

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

The Hue Adjust Register (HUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

The Contrast Adjust Register (CONTRAST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

The Saturation Adjust Registers (SAT_U, SAT_V) . . . . . . . . . . . . . . . . . . . . . . . . . . 32

The Brightness Register (BRIGHT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Automatic Chrominance Gain Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Low Color Detection and Removal

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Coring

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

VBI Data Output Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

VBI Line Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Video Data Format Conversion

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Pixel Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Video Control Code Status Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

YCrCb to RGB Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Gamma Correction Removal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

YCrCb Sub-sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Byte Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Video and Control Data FIFO

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Logical Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

FIFO Data Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Physical Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

FIFO Input/Output Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

DMA Controller

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Target Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

RISC Program Setup and Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

RISC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Complex Clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Executing Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

FIFO Overrun Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

FIFO Data Stream Resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Multifunction Arbiter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Normal PCI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

430FX Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Interfacing with Non-PCI 2.1 Compliant Core Logic . . . . . . . . . . . . . . . . . . . . . . . . . 59

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Bt878/879

Single-Chip Video and Audio Capture for the PCI Bus

Digital Audio Packetizer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Audio FIFO Memory and Status Codes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

PCI Bus Latency Tolerance for Audio Buffer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

FIFO Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Audio Packets and Data Capture

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Digital Audio Input

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Digital Audio Input Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Data Packet Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Audio Data Formats

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Audio Dropout Detection

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Audio A/D

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Muxing and Antialiasing Filtering

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Input Gain Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Electrical Interfaces

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Input Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Analog Signal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Multiplexer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Flash A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

A/D Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Power-up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Automatic Gain Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Crystal Inputs and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

2X Oversampling and Input Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

PCI Bus Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

General Purpose I/O (GPIO) Port

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

GPIO Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

GPIO SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Digital Video Input Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Asynchronous Data Parallel Port Interface: Raw Data Capture

. . . . . . . . . . . . . . . . . 88

I

2

C Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

JTAG Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Need for Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

JTAG Approach to Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Optional Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Verification with the Tap Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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PC Board Layout Considerations

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Layout Considerations

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Split Planes and Voltage Regulators

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Latchup Avoidance

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Control Register Definitions–Function 0

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

PCI Configuration Space

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

PCI Configuration Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Vendor and Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Command and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Revision ID and Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Base Address 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Subsystem ID and Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . 103

Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register . . . . . . . . . . . . . 103

Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Local Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Input Format Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Temporal Decimation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

MSB Cropping Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Vertical Delay Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Vertical Active Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Horizontal Delay Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Horizontal Active Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Horizontal Scaling Register, Upper Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Horizontal Scaling Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Brightness Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Miscellaneous Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Luma Gain Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Chroma (U) Gain Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Chroma (V) Gain Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Hue Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

SC Loop Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

White Crush Up Register (WC_UP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Output Format Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Vertical Scaling Register, Upper Byte (Function 0) . . . . . . . . . . . . . . . . . . 119

Vertical Scaling Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Test Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

AGC Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Burst Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

ADC Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Video Timing Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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Single-Chip Video and Audio Capture for the PCI Bus

White Crush Down Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Timing Generator Load Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Timing Generator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Total Line Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Color Format Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Color Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Capture Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

VBI Packet Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

VBI Packet Size / Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Field Capture Counter-(FCAP) Register . . . . . . . . . . . . . . . . . . . . . . . . . . 128

PLL Reference Multiplier - PLL_F_LO Register . . . . . . . . . . . . . . . . . . . . 128

PLL Reference Multiplier - PLL_F_HI Register . . . . . . . . . . . . . . . . . . . . . 128

Integer- PLL-XCI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Digital Video Signal Interface Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

GPIO and DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

I

2

C Data/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

RISC Program Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

GPIO Output Enable Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

RISC Program Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

GPIO Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Control Register Definitions–Function 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

PCI Configuration Space

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

PCI Configuration Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Vendor and Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Command and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Revision ID and Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Base Address 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Subsystem ID and Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . 141

Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register . . . . . . . . . . . . . 141

Local Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Audio Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Audio Packet Lengths Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

RISC Program Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

RISC Program Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

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Single-Chip Video and Audio Capture for the PCI Bus

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Subsystem Vendor ID

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

I2C Serial EEPROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

EEPROM Upload at PCI Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Programming and Write-Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Register Load from BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Parametric Information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

DC Electrical Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

AC Electrical Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Package Mechanical Drawing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Appendix: Audio Signal Spectrums

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

BTSC MTS Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

FM Radio Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

ix

D879DSA

LIST OF FIGURES

Bt878/879

Single-Chip Video and Audio Capture for the PCI Bus

List of Figures

Figure 1. Bt879 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 2. Bt879 Audio/Video Decoder and Scaler Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 3. Bt879 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4. UltraLock™ Behavior for NTSC Square Pixel Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5. Y/C Separation and Chroma Demodulation for Composite Video . . . . . . . . . . . . . . . . . . 17

Figure 6. Y/C Separation Filter Responses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. Filtering and Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. Optional Horizontal Luma Low-Pass Filter Responses . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. Combined Luma Notch,

2x Oversampling and Optional Low-Pass Filter Response (NTSC) 20

Figure 10. Combined Luma Notch,

2x Oversampling and Optional Low-Pass Filter Response (PAL/SECAM) 21

Figure 11. Combined Luma Notch and 2x Oversampling Filter Response . . . . . . . . . . . . . . . . . . . . 21

Figure 12. Frequency Responses for the Four Optional Vertical Luma Low-Pass Filters . . . . . . . . . 22

Figure 13. Peaking Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14. Luma Peaking Filters with 2x Oversampling Filter and Luma Notch . . . . . . . . . . . . . . . . 24

Figure 15. Effect of the Cropping and Active Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 16. Regions of the Video Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 17. Coring Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 18. Regions of the NTSC Video Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 19. Regions of the PAL Video Frame (Fields 1, 2, 5, and 6). . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 20. VBI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 21. VBI Section Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 22. Video Data Format Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 23. Data FIFO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 24. Audio/Video RISC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 25. Example of Bt879 Performing Complex Clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 26. FIFO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 27. Audio Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 28. Data Packet Mode Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 29. Audio Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 30. Typical External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 31. Clock Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 32. Luma and Chroma 2x Oversampling Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 33. PCI Video Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 34. PCI Audio Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 35. GPIO Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

x

D879DSA

Bt878/879

Single-Chip Video and Audio Capture for the PCI Bus

LIST OF FIGURES

Figure 36. GPIO SPI Input Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 37. GPIO SPI Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 38. Digital Video Input Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 39. Asynchronous Data Parallel Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 40. Video Timing in SPI Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 41. Basic Timing Relationships for SPI Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 42. CCIR 656 Interface to Digital Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 43. The Relationship between SCL and SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 44. I

2

C Typical Protocol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 45. Instruction Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 46. Optional Regulator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 47. Function 0 PCI Configuration Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 48. Function 1 PCI Configuration Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 49. Clock Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 50. GPIO Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 51. JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 52. 128-pin PQFP Package Mechanical Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 53. BTSC MTS Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 54. FM Radio Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

xi

D879DSA

LIST OF TABLES

Bt878/879

Single-Chip Video and Audio Capture for the PCI Bus

List of Tables

Table 1. Audio/Video Capture Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin Descriptions Grouped by Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Video Input Formats Supported by the Bt879. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4. Register Values for Square Pixel Video Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Scaling Ratios for Popular Formats Using Frequency Values. . . . . . . . . . . . . . . . . . . . . . 27

Table 6. Color Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 7. Byte Swapping Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 8. Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 9. FIFO Full/Almost Full Counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 10. Table of PCI Bus Access Latencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 11. RISC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 12. Audio Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 13. Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 14. Recommended Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 15. Synchronous Pixel Interface (SPI) GPIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 16. Synchronous Pixel Interface (SPI) Input GPIO Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 17. Pin Definition of GPIO Port When Using Digital Video-In Mode . . . . . . . . . . . . . . . . . . . . 86

Table 18. Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 19. EEPROM Upload Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 20. Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 21. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 22. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 23. Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 24. GPIO SPI Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 25. Power Supply Current Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 26. JTAG Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 27. Decoder Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

xii

D879DSA

Bt878/879

Single-Chip Video and Audio Capture for the PCI Bus

LIST OF TABLES

1

D879DSA

FUNCTIONAL
DESCRIPTION

Functional Overview

The Bt879 video and audio capture chip is a multi-function Peripheral Component
Interconnect (PCI) device intended for +5 V only operation. The video function
features a Direct Memory Access (DMA)/PCI bus master for analog
NTSC/PAL/SECAM composite, S-V ideo, and digital CCIR656 video capture. The
audio function features a completely independent DMA/PCI bus master for FM ra­dio or TV sound capture.

The Bt878 and Bt879 are based on the Bt848A video capture chip. The Bt879
is a Bt848A upgraded to include various audio capture capabilities. The main fea­tures of the Bt848A are: NTSC/PAL/SECAM video decoding, multiple YCrCb
and RGB pixel formats supported on the output, Vertical Blanking Interval (VBI)
data capture for closed captioning, teletext, and intercast data decoding. The com­plete set of video and audio capture features are documented in this specification.

T able 1 indicates which audio capture features are added to the Bt848A to pro­duce the Bt878/Bt879.

NOTE:

In this specification, Bt878 and Bt879 are referred to generically as the
Bt879, unless the distinction is important to the understanding of a specif­ic version of the chip.

Figure 1 shows a block diagram of the Bt879, and Figure 2 shows a detailed
block diagram of the decoder and scaler sections of the Bt879.

Table 1. Audio/Video Capture Product Family

All Features of the Bt848A, Plus: Bt878 Bt879

Mono line level and mic level audio capture x x
Mono TV audio x x
Full TV stereo decoding for both TV audio (BTSC) and FM audio x
Full DBX noise reduction x

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

2

FUNCTIONAL DESCRIPTION

Functional Overview

D879DSA

Figure 1. Bt879 Detailed Block Diagram

Video

Decoder

Video

Scaler

YCrCb 4:2:2, 4:1:1

CSC/Gamma

8-Bit Dither

Format

MUX

FIFOs

Y: 70x36
Cb: 35x36
Cr: 35x36

# DWORDs

DMA Controller

PCI Initiator

Instruction

Queue

Address Generator

FIFO Data MUX

GPIO

I

2

C Master

PCI

Config

Registers

PCI Target

Controller

Interrupts

AD MUX

Parity Generator

Analog

Video

Bus

Video Data Format Converter

Local Registers

Wr

Instr Data

Rd

PCI

DMA Controller

PCI Initiator

Instruction

Queue

Address Generator

FIFO Data MUX

PCI

Arbiter

Decoder

Audio

FIFO

35x36

Analog

Digital
Audio

Audio

AD MUX

Parity

Config

Controller

PCI

Registers

PCI Target

Local Registers

Wr

Instr

Data

Rd

Interrupts

Generator

Digital Video

I2C

3

FUNCTIONAL DESCRIPTION

Functional Overview

D879DSA

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

Video Capture The Bt879 integrates an NTSC/PAL/SECAM composite and S-Video decoder,

scaler, DMA controller, and PCI Bus master on a single device. The Bt879 can
place video data directly into host memory for video capture applications and into
a target video display frame buf fer for video overlay applications. As a PCI initia­tor, the Bt879 can take control of the PCI bus as soon as it is available, thereby
avoiding the need for on-board frame buffers. The Bt879 contains a pixel data
FIFO to decouple the high speed PCI bus from the continuous video data stream.

The video data input may be scaled, color translated, and burst-transferred to a
target location on a field basis. This allows for simultaneous preview of one field
and capture of the other field. Alternati v ely, the Bt879 is able to capture both fields
simultaneously or preview both fields simultaneously. The fields may be interlaced
into memory or sent to separate field buffers.

Audio Capture The Bt879 can also capture the broadcast audio spectrum over the PCI bus. This

enables system solutions without the use of an analog audio cable. In addition, the
audio capture can be used to implement microphone audio capture for complete
videoconferencing applications.

Figure 2. Bt879 Audio/Video Decoder and Scaler Block Diagram

XTO

XTI

AGCCAP

REFP

CIN

Y/C

Separation

Chroma

Demod

Hue, Saturation,

and Brightness

Adjust

Horizontal and

Vertical Filtering

and Scaling

Clocking

Video Data Format Converter

STV TV-Audio

SFM Radio-Audio

SML Mic or Line-Level

Audio

A/D

Audio

Processing

Audio

Packetizer

Digital

ADATA

ALRCK

ASCLK

C

A/D

Oversampling

Low-Pass Filter

AGC

Composite 1
Composite 2

Composite 3

Composite/S-Video (Y)

S-Video (C)

Audio

Y

A/D

Digital

Audio

Audio FIFO

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

4

FUNCTIONAL DESCRIPTION

Functional Overview

D879DSA

Analog Video and

Digital Camera Capture

The Bt879 includes a digital camera port to support digital video capture. This
specification defines the registers and functionality required for implementing an­alog video capture support. The majority of the analog and digital video register
settings are identical.

In addition to standard CCIR 656 digital interface, the Bt879 can accept digital
video from digital cameras including the Rockwell Quartsight™,
Silicon Vision™, and Logitech™. The digital stream is routed to the high-quality
down-scaler and color adjustment processing. It is then bus-mastered into system
memory or displayed via the graphics frame buffer.

Intel Intercast™

Support

The Bt879 fully supports the Intel Intercast technology. Intel Intercast technology
combines the rich programming of television and the exciting world of the Internet
on your PC. Imagine watching a news broadcast while simultaneously displaying
a historical perspective Web page or viewing a music video while ordering concert
tickets over the Internet. No w your PC and tele vision can interact in useful and en­tertaining ways.

TV/Stereo Support

(Bt897 Only)

The Bt879 supports TV/stereo decoding. The complete Broadcast Television Sys­tems Committee-Multichannel Television Sound (BTSC-MTS) audio spectrum is
digitized. Digital processing is then used to extract the content out of the data
stream. The Bt879 performs the following operations: extract (L+R) sound spec­trum and (L–R) sound spectrum, pilot tone detection, de-emphasize the (L+R) sig­nal, matrix to restore L and R channel signals, and demodulate the (L–R) spectrum
and perform DBX decompression.

FM Radio Stereo Support

(Bt879 Only)

The Bt879 digitizes the composite FM stereo signal, which is an output on com­mercial FM tuners. The system performs demodulation, de-emphasis, decoding,
and re-matrixing. Currently, most available TV stereo decoder chips cannot deal
with this type of FM tuner output effectiv ely because unlike the BTSC scheme, the
(L–R) channel in FM radio broadcasting is not DBX encoded. Rather, it is preem­phasized the same way as with the (L+R) channel, requiring a separate decoder
chip.

Video DMA Channels The Bt879 enables separate destinations for the odd and even fields, each con-

trolled by a pixel Reduced Instruction Set Computing (RISC) instruction list. This
instruction list is created by the Bt879 device driv er and placed in the host memory .
The instructions control the transfer of pixels to target memory locations on a byte
resolution basis. Complex clipping can be accomplished by the instruction list,
blocking the generation of PCI bus cycles for pixels that are not to be seen on the
display.

The DMA channels can be programmed on a field basis to deliver the video data
in packed or planar format. In packed mode, YCrCb data is stored in a single con­tinuous block of memory. In planar mode, the YCrCb data is separated into three
streams which are burst to different target memory blocks. Having the video data
in planar format is useful for applications where the data compression is accom­plished via software and the CPU.

5

FUNCTIONAL DESCRIPTION

Functional Overview

D879DSA

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

Audio DMA Channels The audio channel deliv ers 8-bit or 16-bit samples of a frequency-multiplexed an-

alog signal-to-system memory in packets of DWORDs. RISC controls the audio
DMA Initiator. The flow of audio data and audio RISC instructions is completely
independent and asynchronous to the flow of video data and video RISC instruc­tions.

Since the audio data path operates in continuous transfer mode (no sync gaps),
both the analog and the digital audio inputs can be used for other data capture ap­plications. The analog input offers 360 kHz usable BW at 8 effective bits or 100
kHz usable BW at 12 effective bits. The digital input offers up to 1 MB/s or 8
Mbps.

The audio DMA channel controller is similar to the video DMA controller in
that it supports packed mode RISC instructions. It also only interfaces to one
35x36 FIFO and its associated 6-bit DWORD counter.

The audio PCI initiator is identical to the video PCI initiator; i.e., same DMA
controller interface and same support for interrupts and configuration space. Since
the video and audio initiators are independent, each can handle retries without in­hibiting the other. Thus, the audio function can initiate transfers to the host bridge
even when a GFX target is retrying the video function.

The audio PCI target is similar to the video PCI target with respect to interrupts,
configuration space, memory-mapped registers, and parity error checking. The
main difference in audio is that all of the memory-mapped registers remain in the
PCI clock and 32-bit interface domain. There is no register interface to the audio
clock domain. Thus, this target never issues a disconnect or a retry.

Data Transport Engine The Bt879 data transport engine operates in instruction mode. The audio data is de-

livered over the PCI bus synchronized with the delivery of video data.

PCI Bus Interface The Bt879 is designed to efficiently utilize the available 132 MB/s PCI bus. The

32-bit DWORDs are output on the PCI bus with the appropriate image data under
the control of the DMA channels.

The pixel instruction stream for the DMA channels consumes a minimum of 0.1
MB/s. The Bt879 provides the means for handling the bandwidth bottlenecks
caused by slow targets and long b us access latencies that can occur in some system
configurations. T o overcome these system bottlenecks, the Bt879 gracefully de­grades and recovers from FIFO overruns to the nearest pixel in real time.

UltraLock™ The Bt879 employs a proprietary technique known as UltraLock™ to lock to the

incoming analog video signal. It will always generate the required number of pix­els per line from an analog source in which the line length can vary by as much as
a few microseconds. UltraLock’s™ digital locking circuitry enables the Video­Stream decoders to quickly and accurately lock on to video signals, regardless of
their source. Since the technique is completely digital, UltraLock™ can recognize
unstable signals caused by VCR headswitches or an y other deviation, and adapt the
locking mechanism to accommodate the source. UltraLock™ uses nonlinear tech­niques which are difficult, if not impossible, to implement in genlock systems. And
unlike linear techniques, it adapts the locking mechanism automatically.

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

6

FUNCTIONAL DESCRIPTION

Functional Overview

D879DSA

Scaling and Cropping The Bt879 can reduce the video image size in both horizontal and vertical direc-

tions independently using arbitrarily selected scaling ratios. The X and Y dimen­sions can be scaled down to one-sixteenth of the full resolution. Horizontal scaling
is implemented with a 6-tap interpolation filter, while up to 5-tap interpolation is
used for vertical scaling with a line store.

The video image can be arbitrarily cropped by reducing the number of active

scan lines and active horizontal pixels per line.

The Bt879 supports a temporal decimation feature that reduces video band­width. This is accomplished by allowing frames or fields to be dropped from a vid­eo sequence at fixed but arbitrarily selected intervals.

Input Interface Analog video signals are input to the Bt879 via a three-input multiplexer . The mul-

tiplexer can select between four composite source inputs or between three compos­ite and a single S-Video input source. When an S-Video source is input to the
Bt879, the luma component is fed through the input analog multiplexer, and the
chroma component is fed directly into the C input pin. An automatic gain control
circuit enables the Bt879 to compensate for non-standard amplitudes in the analog
signal input.

The clock signal interface consists of a pair of pins that connect to a 28.63636
MHz (8*NTSC Fsc) crystal. Either fundamental or third harmonic crystals may be
used. Alternatively, CMOS oscillators may be used.

General Purpose I/O

(GPIO) Port

The Bt879 provides a 24-bit GPIO bus. This interface can be used to input or out­put up to 24 general purpose I/O signals. Alternatively, the GPIO port can be used
as a means to input video data. For example, the Bt879 can input the video data
from an external digital camera and bypass the Bt879’s internal video decoder
block.

Vertical Blanking Interval

Data Capture

The Bt879 provides a complete solution for capturing and decoding VBI data. The
Bt879 can operate in a VBI Line Output Mode, in which the VBI data is only cap­tured during select lines. This mode of operation enables concurrent capture of
VBI lines containing ancillary data and normal video image data.

In addition, the Bt879 supports a VBI Frame Output Mode in which every line
in the video frame is treated as if it was a VBI line. This mode of operation is de­signed for use with still frame capture/processing applications.

Inter-Integrated Circuit

(I

2

C) Interface

The Bt879’s I

2

C interface supports both 99.2 kHz timing transactions and 396.8

kHz, repeated start, multi-byte sequential transactions. As an I

2

C master, Bt879
can program other devices on the video card, such as a TV tuner. The Bt879 sup­ports multi-byte sequential reads (more than one transaction) and multi-byte write
transactions (greater than three transactions), which enable communication to de­vices that support auto-increment internal addressing.

For additional information, refer to “I

2

C Interface” on page 89.

7

FUNCTIONAL DESCRIPTION

Pin Descriptions

D879DSA

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

Pin Descriptions

Table 2 provides a description of pin functions grouped by common function. Figure 3 displays the pinout diagram.

Table 2. Pin Descriptions Grouped by Pin Function

(1 of 5)

Pin # Pin Name I/O Signal Description

PCI Interface (50 pins)

40 CLK I Clock This input provides timing for all PCI transactions. All PCI sig-

nals except RST and INTA are sampled on the rising edge of
CLK, and all other timing parameters are defined with
respect to this edge. The Bt879 supports a PCI clock of up to

33.3333 MHz.

127 RST

I Reset This input three-states all PCI signals asynchronous to the

CLK signal.

3 REQ

O Request Agent desires bus.
2 GNT I Grant Agent granted bus.
13 IDSEL I Initialization

Device Select

This input is used to select the Bt879 during configuration
read and write transactions.

4–11,
14–18,
21–23,
34–37,
41–44,
46–53

AD[31:0] I/O Address/Data These three-state, bidirectional I/O pins transfer both

address and data information. A bus transaction consists of
an address phase followed by one or more data phases for
either read or write operations.

The address phase is the clock cycle in which FRAME

is
first asserted. During the address phase, AD[31:0] contains a
byte address for I/O operations and a DWORD address for
configuration and memory operations. During data phases,
AD[7:0] contains the least significant byte and AD[31:24]
contains the most significant byte.

Read data is stable and valid when TRD

Y is asserted and

write data is stable and valid when IRD

Y is asserted. Data is

transferred during the clocks when both TRD

Y and IRDY are

asserted.

12, 24,
33, 45

CBE

[3:0] I/O Bus

Command/Byte
Enables

These three-state, bidirectional I/O pins transfer both bus
command and byte enable information. During the address
phase of a transaction, CBE

[3:0] contain the bus command.

During the data phase, CBE

[3:0] are used as byte enables.
The byte enables are valid for the entire data phase and
determine which byte lanes carry meaningful data. CBE

[3]

refers to the most significant byte and CBE

[0] refers to the

least significant byte.

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

8

FUNCTIONAL DESCRIPTION

Pin Descriptions

D879DSA

32 PAR I/O Parity This three-state, bidirectional I/O pin provides even parity

across AD[31:0] and CBE

[3:0]. This means that the number

of 1s on PAR, AD[31:0], and CBE

[3:0] equals an even num-

ber.

PAR is stable and valid one clock after the address phase.
For data phases, PAR is stable and valid one clock after
either TRD

Y is asserted on a read, or IRDY is asserted on a
write. Once valid, PAR remains valid until one clock after the
completion of the current data phase. PAR and AD[31:0]
have the same timing, but PAR is delayed by one clock. The
target drives PAR for read data phases; the master drives
PAR for address and write data phases.

25 FRAME

I/O Cycle Frame This sustained, three-state signal is driven by the current

master to indicate the beginning and duration of an access.
FRAME

is asserted to signal the beginning of a bus transac­tion. Data transfer continues throughout assertion. At deas­sertion, the transaction is in the final data phase.

26 IRD

Y I/O Initiator Ready This sustained, three-state signal indicates the bus master’s

readiness to complete the current data phase.

IRD

Y is used in conjunction with TRDY. When both IRDY

and TRD

Y are asserted, a data phase is completed on that

clock. During a read, IRD

Y indicates when the initiator is

ready to accept data. During a write, IRD

Y indicates when
the initiator has placed valid data on AD[31:0]. Wait cycles
are inserted until both IRD

Y and TRDY are asserted together .

28 DEVSEL I/O Device Select This sustained, three-state signal indicates device selection.

When actively driven, DEVSEL

indicates the driving device

has decoded its address as the target of the current access.

27 TRD

Y I/O Target Ready This sustained, three-state signal indicates the target’s readi-

ness to complete the current data phase.

IRD

Y is used in conjunction with TRDY. When both IRDY

and TRD

Y are asserted, a data phase is completed on that

clock. During a read, TRD

Y indicates when the target is pre-

senting data. During a write, TRD

Y indicates when the target
is ready to accept the data. Wait cycles are inserted until
both IRD

Y and TRDY are asserted together.

29 STOP I/O Stop This sustained, three-state signal indicates the target is

requesting the master to stop the current transaction.

30 PERR

I/O Parity Error Report data parity error.
31 SERR O System Error Report address parity error. Open drain.
126 INTA O Interrupt A This signal is an open drain interrupt output.
See PCI Specification 2.1 for further documentation.

Table 2. Pin Descriptions Grouped by Pin Function

(2 of 5)

Pin # Pin Name I/O Signal Description

9

FUNCTIONAL DESCRIPTION

Pin Descriptions

D879DSA

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

JTAG (5 pins)

122 TCK I Test clock Used to synchronize all JTAG test structures. When JTAG

operations are not being performed, this pin must be driven
to a logical low.

123 TMS I Test Mode Select JTAG input pin whose transitions drive the JTAG state

machine through its sequences. When JTAG operations are
not being performed, this pin must be left floating or tied high.

125 TDI I Test Data Input JTAG pin used for loading instructions to the TAP controller or

for loading test vector data for boundary-scan operation.
When JTAG operations are not being performed, this pin
must be left floating or tied high.

124 TDO O Test Data Output JTAG pin used for verifying test results of all JTAG sampling

operations. This output pin is active for certain JTAG opera­tions and will be three-stated at all other times.

121 TRST

I Test Reset JTAG pin used to initialize the JTAG controller. When JTAG

operations are not being performed, this pin must be driven
to a logical low.

I

2

C Interface (2 pins)

90 SCL I/O Serial Clock Bus clock, output open drain.
91 SDA I/O Serial Data Bit Data or Acknowledge, output open drain.

General Purpose I/O (25 pins)

66 GPCLK I/O GP Clock Video clock. Internally pulled up to VDD.
56–61,

67–72,
75–86

GPIO[23:0] I/O General Purpose

I/O

Bt879 pin decoding in normal mode. Pins pulled up to VDD.
For additional information, see Tables 15 and 16.

Digital Audio Input/Audio Test Signals (3 pins)

87 ADATA I/O Audio Data Bit serial data.
88 ALRCK I/O Audio Clock Left/right framing clock.
89 ASCLK I/O Audio Serial Clock Bit serial clock.

Reference Timing Interface Signals (2 pins)

62 XTI I A 28.63636 MHz crystal can be tied directly to these pins, or

a single-ended oscillator can be connected to XTI.

63 XTO O

Table 2. Pin Descriptions Grouped by Pin Function

(3 of 5)

Pin # Pin Name I/O Signal Description

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

10

FUNCTIONAL DESCRIPTION

Pin Descriptions

D879DSA

Video Input Signals (7 pins)

114, 116,
118, 120

MUX[0:3] I Analog composite video inputs to the on-chip 4:1 analog mul-

tiplexer. Unused inputs should be tied to A GND. The output of
the mux is direct-coupled to Y-A/D.

112 REFP A The top of the reference ladder for the video A/Ds. Connect

to a 0.1 µF decoupling capacitor to AGND.

111 AGCCAP A The AGC time constant control capacitor node. Must be con-

nected to a 0.1µF capacitor to AGND.

109 CIN I Analog chroma input to the C-A/D.

TV/Radio Audio Input Signals (10 pins)

100 STV I TV sound input from TV tuner.
98 SFM I FM sound input from FM tuner.
94 SML I MIC/line input.
96 SMXC A Audio mux antialias filter RC node. Connect through 68 pF

capacitor to BGND.
106 RBIAS A Connection point for external bias 9.53 k Ω 1% resistor.
105 VCOMO A Common mode voltage f or the audio analog circuitry. This pin

should be connected to an external filtering 0.1 µF capacitor.
104 VCOMI A Common mode voltage f or the audio analog circuitry. This pin

should be connected to an external filtering 0.1 µF capacitor.
107 VCCAP A Audio analog voltage compensation capacitor. This pin

should be connected to an external filtering 0.1 µF capacitor.
103 VRXP A Audio input circuitry reference voltage. This pin should be

connected to an external filtering 0.1 µF capacitor.
102 VRXN A Audio input circuitry reference voltage. This pin should be

connected to an external filtering 0.1 µF capacitor.

I/O and Core Power and Ground (14 pins)

1, 19, 38,
54, 65 73,
92

VDD P Digital outputs power supply.

20, 39,
55, 64,
74, 93,
128

GND G Digital outputs ground.

Table 2. Pin Descriptions Grouped by Pin Function

(4 of 5)

Pin # Pin Name I/O Signal Description

11

FUNCTIONAL DESCRIPTION

Pin Descriptions

D879DSA

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

Analog Video Power and Ground (6 pins)

108 AGND A C video A/D ground. Connect to analog ground AGND.
110 VAA A Charge pump power supply and C video A/D power . Connect

to analog power VAA and a 0.1µF decoupling capacitor to

AGND.
113 AGND A Charge pump ground return.
115 VAA A Y video A/D power. Connect to analog power VAA and a

0.1µF decoupling capacitor to AGND.

117 VAA A Y video A/D power. Connect to analog power VAA and a

0.1µF decoupling capacitor to AGND.

119 AGND A Y video A/D ground. Connect to analog ground AGND.

Analog Audio Power and Ground (4 pins)

95 VBB P Audio A/D power supply.
97 BGND G Ground for audio A/D.
99 BGND G Ground for audio A/D.
101 VBB P Power supply for audio A/D.

Note: I/O Column Legend:

I = Digital Input
O = Digital Output
I/O = Digital Bidirectional
A = Analog
G = Ground
P = Power

Table 2. Pin Descriptions Grouped by Pin Function

(5 of 5)

Pin # Pin Name I/O Signal Description

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

12

FUNCTIONAL DESCRIPTION

Pin Descriptions

D879DSA

Figure 3. Bt879 Pinout Diagram

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

118

119

120

121

122

123

124

125

126

127

128

96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

VDD
GNT

REQ
AD[31]
AD[30]
AD[29]
AD[28]
AD[27]
AD[26]
AD[25]
AD[24]
C

BE[3]

IDSEL
AD[23]
AD[22]
AD[21]
AD[20]
AD[19]

VDD

GND
AD[18]
AD[17]
AD[16]
C

BE[2]

FRAME

IRDY

TRDY

DEVSEL

STOP
PERR
SERR

PAR

GND

RST

INTA

TDI

TDO

TMS

TCK

TRST

MUX3

AGND

MUX2

MUX1

VAA

MUX0

AGND

REFP

AGCCAP

VAA

CIN

AGND

VCCAP

RBIAS

VCOMO

VCOMI

VRXP

VRXN
VBB
STV
BGND
SFM
BGND

C

BE[1]
AD[15]
AD[14]
AD[13]
AD[12]

VDD

GND

CLK

AD[11]

AD[10]

AD[09]

AD[08]

C

BE[0]

AD[07]

AD[06]

AD[05]

AD[04]

AD[03]

AD[02]

AD[01]

AD[00]

VDD

GND

GPIO[23]

GPIO[22]

GPIO[21]

GPIO[20]

GPIO[19]

GPIO[18]

XTI

XTO

GND

SMXC
VBB
SML
GND
VDD
SDA
SCL
ASCLK

GPIO[01]
GPIO[02]
GPIO[03]
GPIO[04]
GPIO[05]
GPIO[06]
GPIO[07]
GPIO[08]
GPIO[09]
GPIO[10]
GPIO[11]
GND
VDD
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPCLK
VDD

ALRCK
ADATA
GPIO[00]

Bt878/879

117

VAA

13

FUNCTIONAL DESCRIPTION

UltraLock™

D879DSA

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

UltraLock™

The Challenge The line length (the interval between the midpoints of the falling edges of succeed-

ing horizontal sync pulses) of analog video sources is not constant. For a stable
source such as studio quality source or test signal generators, this variation is very
small: ±2 ns. However, for an unstable source such as a VCR, laser disk player, or
TV tuner, line length variation is as much as a few microseconds.

Digital display systems require a fixed number of pixels per line despite these
variations. The Bt879 employs a technique known as UltraLock™ to implement
locking to the horizontal sync and the subcarrier of the incoming analog video sig­nal and generating the required number of pixels per line.

Operation Principles of

UltraLock™

UltraLock™ is based on sampling using a fixed-frequency, stable clock. Since the
video line length will vary , the number of samples generated using a fix ed-frequen­cy sample clock will also vary from line to line. If the number of generated samples
per line is always greater than the number of samples per line required by the par ­ticular video format, the number of acquired samples can be reduced to fit the re­quired number of pixels per line.

The Bt879 requires an 8*Fsc (28.63636 MHz for NTSC and 35.46895 MHz for
P AL) reference time source. The 8*Fsc clock signal, or CLKx2, is di vided down to
CLKx1 internally (14.31818 MHz for NTSC and 17.73 MHz for PAL). CLKx2
and CLKx1 are internal signals and are not made available to the system.
UltraLock™ operates at CLKx1 although the input waveform is sampled at
CLKx2 then low pass filtered and decimated to CLKx1 sample rate.

At a 4*Fsc (CLKx1) sample rate there are 910 pixels for NTSC and 1,135 pixels
for PAL/SECAM within a nominal line time interval (63.5 µs for NTSC and 64 µs
for PAL/SECAM). For square pixel NTSC and PAL/SECAM formats, there
should only be 780 and 944 pixels per video line, respectiv ely. This is because the
square pixel clock rates are slower than a 4*Fsc clock rate; i.e., 12.27 MHz for
NTSC and 14.75 MHz for PAL.

UltraLock™ accommodates line length variations from nominal in the incom­ing video by always acquiring more samples, at an effecti ve 4*Fsc rate, than are re­quired by the particular video format and outputting the correct number of pixels
per line. UltraLock™ then interpolates the required number of pixels in a way that
maintains the stability of the original image despite variation in the line length of
the incoming analog waveform.

The example illustrated in Figure 4 shows three successiv e lines of video being
decoded for square pixel NTSC output. The first line is shorter than the nominal
NTSC line time interval of 63.5 µs. On this first line, a line time of 63.2 µs sampled
at 4*Fsc (14.31831 MHz) generates only 905 pixels. The second line matches the
nominal line time of 63.5 µs and provides the expected 910 pixels. Finally, the
third line is too long at 63.8 µs within which 913 pixels are generated. In all three
cases, UltraLock™ outputs only 780 pixels.

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

14

FUNCTIONAL DESCRIPTION

UltraLock™

D879DSA

UltraLock™ can be used to extract any programmable number of pixels from
the original video stream as long as the sum of the nominal pixel line length (910
for NTSC and 1,135 for PAL/SECAM) and the worst case line length validation
from nominal in the active region is greater than or equal to the required number of
output pixels per line; i.e.,

NOTE:

With stable inputs, UltraLock™ guarantees the time between the falling
edges of HRESET only to within one pixel. UltraLock™ does, however,
guarantee the number of active pixels in a line as long as the above rela­tionship holds.

Figure 4. UltraLock™ Behavior for NTSC Square Pixel Output

Analog

Waveform

63.2 µs

63.5 µs

63.8 µs

905 pixels

910 pixels

913 pixels

Line

Length

Pixels

Per Line

780 pixels

780 pixels

780 pixels

Pixels

Sent to

the FIFO

by

UltraLock™

P

NomPVar

+ P

Desired

≥

where: P

Nom

= Nominal number of pixels per line at 4*Fsc sample rate

(910 for NTSC, 1,135 for PAL/SECAM)

P

Var

= Variation of pixel count from nominal at 4*Fsc (can be a

positive or negative number)

P

Desired

= Desired number of output pixels per line

15

FUNCTIONAL DESCRIPTION

Composite Video Input Formats

D879DSA

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

Composite Video Input Formats

Bt879 supports several composite video input formats. Table 3 shows the different
video formats and some of the countries in which each format is used.

The video decoder must be programmed appropriately for each of the compos­ite video input formats. T able 4 lists the register values that need to be programmed
for each input format.

Table 3. Video Input Formats Supported by the Bt879

Format Lines Fields F

SC

Country

NTSC-M 525 60 3.58 MHz U.S., many others
NTSC-Japan

(1)

525 60 3.58 MHz Japan
PAL-B, G, H 625 50 4.43 MHz Western/Central Europe, others
PAL-D 625 50 4.43 MHz China
PAL-I 625 50 4.43 MHz U.K., Ireland, South Africa
PAL-M 525 60 3.58 MHz Brazil
PAL-N

C

625 50 3.58 MHz Argentina
PAL-N 625 50 3.58 MHz Paraguay, Uruguay
SECAM 625 50 4.406 MHz

4.250 MHz

Eastern Europe, France, Middle East

Notes: (1). NTSC-Japan has 0 IRE setup.

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

16

FUNCTIONAL DESCRIPTION

Composite Video Input Formats

D879DSA

Table 4. Register Values for Square Pixel Video Input Formats

Register Bit NTSC-M NTSC-Japan

PAL-B, D,

G, H, I

PAL-M PAL-N

PAL-N

Combination

SECAM

IFORM
(0x01)

FORMAT
[2:0]

001 010 011 100 101 111 110

Cropping:
HDELAY,
VDELAY,
VACTIVE,
CROP,
HACTIVE

[7:0] in
all five
registers

Set to
desired crop­ping values
in registers

Set to
NTSC-M
square pixel
values

Set to
desired
cropping val­ues in regis­ters

Set to
NTSC-M
square pixel
values

Set to PAL-B, D, G, H, I square
pixel values

HSCALE [15:0] 0x02AC 0x02AC 0x033C 0x02AC 0x033C 0x033C

(1)

0x033C
ADELAY [7:0] 0x70 0x70 0x7F 0x70 0x7F 0x7F 0x7F
BDELAY [7:0] 0x5D 0x5D 0x72 0x5D 0x72 0x72 0xA0

Notes: (1). The Bt879 will not output square pixel resolution for PAL N-combination. A smaller number of pixels must be

output.

17

FUNCTIONAL DESCRIPTION

Y/C Separation and Chroma Demodulation

D879DSA

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

Y/C Separation and Chroma Demodulation

Y/C separation and chroma decoding are handled as shown in Figure 5. Bandpass
and notch filters are implemented to separate the composite video stream. The fil­ter responses are shown in Figure 6. The optional chroma comb filter is imple­mented in the vertical scaling block. See “Video Scaling, Cropping, and Temporal
Decimation” on page 19.

Figure 7 schematically describes the filtering and scaling operations.

In addition to the Y/C separation and chroma demodulation illustrated in
Figure 5, the Bt879 also supports chrominance comb filtering as an optional filter­ing stage after chroma demodulation. The chroma demodulation generates base­band I and Q (NTSC) or U and V (PAL/SECAM) color difference signals.

For S-Video operation, the digitized luma data bypasses the Y/C separation
block completely, and the digitized chrominance is passed directly to the chroma
demodulator.

For monochrome operation, the Y/C separation block must be disabled, and the
saturation registers (SAT_U and SAT_V) are set to 0.

Figure 5. Y/C Separation and Chroma Demodulation for Composite Video

Notch Filter

Band Pass Filter

Low Pass Filter

Low Pass Filter

sin

cos

Y

U

V

Composite

Bt878/879

Single-Chip Video and Broadcast Audio Capture for the PCI Bus

18

FUNCTIONAL DESCRIPTION

Y/C Separation and Chroma Demodulation

D879DSA

Figure 6. Y/C Separation Filter Responses

NTSC

PAL/SECAM

NTSC

PAL/SECAM

Luma Notch Filter Frequency Responses for NTSC and PAL/SECAM

Chroma Band Pass Filter Frequency Responses for NTSC and PAL/SECAM

Figure 7. Filtering and Scaling

Note: Z–1 refers to a pixel delay in the horizontal direction, and a line delay in the vertical direction. The coefficients

are determined by UltraLock™ and the scaling algorithm.

Chrominance

1
2

---

1
2

---Z1–+=

Luminance C DZ

1–

+=

Vertical Scaler

Luminance

A BZ1–CZ2–DZ3–EZ4–FZ

5–

+ + + + +=

Chrominance G HZ

1–

+=

Horizontal Scaler

6 Tap, 32 Phase

Interpolation

On-chip Memory

and

Horizontal

Scaling

On-chip Memory

and

Chroma Comb

Low Pass

Filter

Y

Y

C

C

Optional

Horizontal

Vertical Scaling

Luma Comb

(Chroma Comb)

3 MHz

1
4

--- 1 2

Z

1–

1Z

2–

+ +( )=

1
8

--- 1 3

Z

1–

3Z2–1Z

3–

+ + +( )=

1

16

------ 1 4

Z

1–

6Z2–4Z

3–

Z

4–

+ + + +( )=

Vertical Filter Options

Vertical Scaling

Vertical Filtering

Luminance

1
2

--- 1 z1–+( )=

2 Tap, 32 Phase

Interpolation

and

Horizontal

Scaling