Rockchips RK2918 Schematics
RK2918 Datasheet Rev 1.0
RK2918 Datasheet
Preliminary
Revision 1.0
Jan. 2011
Rockchips Confidential 1
RK2918 Datasheet Rev 1.0
Date
Revision
Description
2011-1-9
1.0
Initial Release
Revision History
Rockchips Confidential 2
RK2918 Datasheet Rev 1.0
Table of Content
Table of Content ............................................................................................... 3
Figure Index .................................................................................................... 4
Table Index ..................................................................................................... 5
Chapter 1 Introduction .................................................................................... 6
1.1 Features ........................................................................................... 6
1.1.1 Microprocessor .......................................................................... 6
1.1.2 Memory Organization ................................................................. 7
1.1.3 Internal Memory ........................................................................ 7
1.1.4 External Memory or Storage device .............................................. 7
1.1.5 System Component .................................................................... 9
1.1.6 Video CODEC........................................................................... 11
1.1.7 JPEG CODEC ........................................................................... 12
1.1.8 Image Enhancement ................................................................ 12
1.1.9 Graphics Engine ....................................................................... 14
1.1.10 Video IN/OUT .......................................................................... 14
1.1.11 Audio Interface ........................................................................ 16
1.1.12 Connectivity ............................................................................ 17
1.1.13 Others .................................................................................... 19
1.2 Block Diagram ................................................................................. 19
Chapter 2 Package Description ....................................................................... 21
2.1 Ball Map ......................................................................................... 21
2.2 Pin Number Order ............................................................................ 25
2.3 RK2918 power/ground IO descriptions ............................................... 30
2.3.1 RK2918 function IO descriptions ................................................ 34
2.4 IO pin name descriptions .................................................................. 49
2.4.1 RK2918 IO Type ....................................................................... 56
2.5 Package information ......................................................................... 57
2.5.1 Dimension .............................................................................. 57
Chapter 3 Electrical Specification .................................................................... 60
3.1 Absolute Maximum Ratings ............................................................... 60
3.2 Recommended Operating Conditions .................................................. 60
3.3 DC Characteristics ........................................................................... 61
3.4 Electrical Characteristics for General IO .............................................. 62
3.5 Electrical Characteristics for PLL ........................................................ 63
3.6 Electrical Characteristics for SAR-ADC ................................................ 64
3.7 Electrical Characteristics for USB OTG/Host2.0 Interface ....................... 64
3.8 Electrical Characteristics for USB Host1.1 Interface .............................. 65
3.9 Electrical Characteristics for DDR IO ................................................... 65
3.10 Electrical Characteristics for eFuse ................................................ 65
Chapter 4 Hardware Guideline ........................................................................ 66
4.1 Reference design for RK2918 oscillator PCB connection ........................ 66
4.2 Reference design for PLL PCB connection ............................................ 66
4.3 Reference design for USB OTG/Host2.0 connection .............................. 67
4.4 RK2918 Power up/down sequence requirement ................................... 68
4.5 RK2918 Power on reset descriptions ................................................... 68
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Figure Index
Fig. 1-1 RK2918 Block Diagram ........................................................................ 20
Fig. 2-1 RK2908 Ball Mapping Diagram .............................................................. 24
Fig. 2-2 RK2908 TFBGA512 Package Top View .................................................... 58
Fig. 2-3 RK2908 TFBGA512 Package Side View ................................................... 58
Fig. 2-4 RK2908 TFBGA512 Package Bottom View ............................................... 59
Fig. 2-5 RK2908 TFBGA512 Package Dimension .................................................. 59
Fig. 4-1 External reference circuit for 24MHz/27MHz oscillators ............................. 66
Fig. 4-2 External reference circuit for 32.768KHz oscillator ................................... 66
Fig. 4-3 External reference circuit for PLL .......................................................... 67
Fig. 4-4 RK2918 USB OTG/Host2.0 interface reference connection......................... 67
Fig. 4-5 RK2918 reset signals sequence............................................................. 68
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Table Index
Table 2-1 RK2908 Pin Number Order Information ................................................ 25
Table 2-2 RK2918 Power/Ground IO informations................................................ 30
Table 2-3 RK2908 IO descriptions ..................................................................... 34
Table 2-4 RK2918 IO function description list ..................................................... 49
Table 2-5 RK2918 IO Type List ......................................................................... 56
Table 3-1 RK2918 absolute maximum ratings ..................................................... 60
Table 3-2 RK2918 recommended operating conditions ......................................... 60
Table 3-3 RK2918 DC Characteristics ................................................................ 61
Table 3-4 RK2918 Electrical Characteristics for Digital General IO .......................... 62
Table 3-5 RK2918 Electrical Characteristics for PLL .............................................. 63
Table 3-6 RK2918 Electrical Characteristics for SAR-ADC ...................................... 64
Table 3-7 RK2918 Electrical Characteristics for USB OTG/Host2.0 Interface............. 64
Table 3-8 RK2918 Electrical Characteristics for USB Host1.1 Interface .................... 65
Table 3-9 RK2918 Electrical Characteristics for DDR IO ........................................ 65
Table 3-10 RK2918 Electrical Characteristics for eFuse ......................................... 65
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Chapter 1 Introduction
RK2918 is a low power, high performance processor solution for mobile phones,
personal mobile internet device and other digital multimedia applications.
RK2918 integrates an ARM Cortex-A8 with one NEON coprocessor. Many embedded
powerful hardware accelerators provide optimized hardware performance for high-end
application. RK2918 supports almost full-format video decoder by 1080p@30fps such as
H264, H263, RMVB, MPEG2, MPEG4, VC1, AVS, VP8 etc. Also supports H.264 encoder by
1080P@30fps, high-quality JPEG encoder/decoder and special image preprocessor and
postprocessor.
Embedded 2D/3D hardware engine makes RK2918 completely compatible with
OpenGL ES2.0, OpenGL ES1.1 and OpenVG graphics standards.
RK2918 has high-performance external memory interface (DDRIII/DDRII/LPDDR)
capable of sustaining demanding memory bandwidths, also provides a complete set of
peripheral interface to support very flexible applications as follows:
2 banks, 8bits/16bits Nor Flash/SRAM interface
8 banks, 8bits/16bits Async NAND FLASH, LBA NANDN Flash, 8bits sync ONFI
NAND Flash, all embedded 24bits HW ECC
2 ranks, 2GB Memory space, 16bits/32bits DDRIII,DDRII-800,LPDDR-400
8bits HS-MMC/SD, 4bits SDIO, 8bits eMMC interface
24bits high-performance, 3-layers TFT LCD Controller with post-processor,
1920x1080 maximum display size
eBook display interface with 2048x2048 maximum resolution
8bits sensor/CCIR656 interface and 10bits/12bits Raw data interface
2ch I2S interface, 8ch I2S interface, PCM/SPDIF interface
USB OTG 2.0/USB Host2.0/ USB Host 1.0
RMII/MII interface
High-speed ADC interface, TS stream interface
8bits/16bits async modem interface
4x I2C, 4xUART with hardware flow-control , 2x SPI , PWM
This document will provide guideline on how to use RK2918 correctly and efficiently.
In them, the chapter 1 and chapter 2 will introduce the features, block diagram, and
signal descriptions and system usage of RK2918, the chapter 3 through chapter 46 will
describe the full function of each module in detail.
1.1 Features
1.1.1 Microprocessor
ARM Cortex-A8 processor is a high-performance, low-power, cached application
processor that provides full virtual memory capabilities
Full implementation of the ARM architecture v7-A instruction set
superscalar processor featuring technology for enhanced code density and
performance
Embedded NEON technology for multimedia and signal processing by executing
Advanced SIMD and VFP instruction sets
Jazelle RCT Java-acceleration technology for efficient support of ahead-of-time and
just-in-time compilation of Java and other byte code language
Thumb-2 technology for greater performance, energy efficiency and code density
TrustZone technology for secure transactions and DRM
13-stage main integer core pipeline and 10-stage NEON media core pipeline
Dynamic branch prediction with branch target address cache, global history buffer
and 8-entry return stack
MMU and separate instruction and data TLBs of 32 entries each
64-bit high-speed AXI interface supporting multiple outstanding transactions
Integrated 32KB L1 instruction cache , 32KB L1 data cache, 512KB L2 Cache with
parity and ECC check
ETM support for non-invasive debug, support JTAG and 8-wire trace interface
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ARMv7 debug with watchpoint and breakpoint registers and a 32-bit APB slave
interface to a coresight debug system
Four separate power domain to support Internal power switch on/off based on
different application scene(Integer core/ETM&DBG/Neon/L2 Cache)
Maximum frequency can be up to 650MHz@worst case and 1GHz@typical case
1.1.2 Memory Organization
Internal on-chip memory
10KB Boot Rom
16KB internal SRAM for security and non-security access, detailed size is
programmable
4KB internal SRAM shared with Host slave interface (HIF)
2KB internal SRAM shared with NAND controller
External off-chip memory
DDRIII, DDRII-800, 16/32bits data width, 2 ranks, 1GB(max) address space per
rank
LPDDR-400, 32bits data width, 2 ranks, 1GB(max) address space per rank
Async SRAM/Nor Flash, 8/16bits data width,2banks,1MB(max) address space
per bank
Async NAND Flash(include LBA NAND), 8/16bits data width, 8 banks
Sync DDR NAND Flash, 8bits data width, 8 banks
1.1.3 Internal Memory
①
Internal Boot Rom
Size : 10KB
Support system boot from the following device :
8bits/16bits Async NAND Flash
SPI0 interface
eMMC interface
Support system code download by the following interface:
USB OTG
UART1
Internal SRAM
Size : 16KB
Support security and non-security access
Security or non-security space is software programmable , used together with
TZMA module
Security space can be 0KB, 4KB, 8KB, 12KB, 16KB continuous size
1.1.4 External Memory or Storage device
Dynamic Memory Interface (DDRIII/DDRII/LPDDR)
Compatible with JEDEC standard DDRIII/DDRII/LPDDR SDRAM
Data rates of up to 800Mbps(400MHz) for DDRII and up to 400Mbps(200MHz)
for LPDDR
Support up to 2 ranks (chip selects), maximum 1GB address space per rank
16bits/32bits data width is software programmable
5 host ports with 64bits AXI bus interface for system access, AXI bus clock
asynchronous with DDR clock
Programmable timing parameters support DDRIII/DDRII/LPDDR SDRAM from
various vendor
Advanced command reordering and scheduling to maximize bus utilization
Low power modes, such as power-down and self-refresh for DDRII/LPDDR
SDRAM; clock stop and deep power-down for LPDDR SDRAM
Programmable ultra-high priority port(port0), typically a CPU port
Compensation for board delays and variable latencies through programmable
pipelines
Embedded dynamic drift detection in the PHY to get dynamic drift compensation
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with the controller
Programmable output and ODT impedance with dynamic PVT compensation
Support one low-power work mode: power down DDR PHY and most of DDR IO
except two CS and two CKE output signals, make SDRAM still in self-refresh state
to prevent data missing.
Static Memory Interface (ASRAM/Nor Flash)
Compatible with standard async SRAM or Nor Flash
Support up to 2 banks (chip selects), maximum 1MB address space per bank
For bank0, 8bits/16bits data width is software programmable; For bank1, 16bits
data width is fixed
Support separately data and address bus, also support shared data and address
bus to save IO numbers
NAND Flash Interface
Support 8bits/16bits async NAND flash, up to 8 banks
Support 8bits sync DDR NAND flash, up to 8 banks
Support LBA NAND flash in async or sync mode
16bit/1KB HW ECC, compatible with 8bit/512B
24bit/1KB HW ECC, compatible with 12bit/512B
For DDR NAND flash, support DLL bypass and 1/4 or 1/8 clock adjust, maximum
clock rate is 75MHz
For async NAND flash, support configurable interface timing , maximum data
rate is 16bit/cycle
Embedded two 256x32bits buffers to support ping-pong operation
Embedded AHB master interface to do data transfer by DMA method
Also support data transfer by AHB slave interface together with external DMAC1
eMMC Interface
Compatible with standard INAND interface
Support MMC4.2 protocol
Provide eMMC boot sequence to receive boot data from external eMMC device
One AHB slave interface to complete data transfer together with external DMAC1
or CPU
Support combined single FIFO(32x32bits) for both transmit and receive
operations
Support FIFO over-run and under-run prevention by stopping card clock
automatically
Support CRC generation and error detection
Embedded clock frequency division control to provide programmable baud rate
Support host pull-up control,card detection and initialization, write protection
Support block size from 1 to 65535Bytes
Data bus width is 8bits
SD/MMC Interface
Compatible with SD ver2.00, CE-ATA ver1.1, MMC ver4.2
One AHB slave interface to complete data transfer together with external DMAC1
or CPU
Support combined single FIFO(32x32bits) for both transmit and receive
operations
Support FIFO over-run and under-run prevention by stopping card clock
automatically
Support CRC generation and error detection
Embedded clock frequency division control to provide programmable baud rate
Support host pull-up control, card detection and initialization, write protection
Support block size from 1 to 65535Bytes
Data bus width is flexible to support 1bit/4bits for SD mode and 1bit/4bits/8bits
for MMC mode
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1.1.5 System Component
CRU (clock & reset unit)
Support clock gating control for individual components inside RK2918
Support soft-reset control for individual components inside RK2918
Support flexible clock solution, including clock source, clock MUX, clock
frequency division
Four embedded PLLs, source can be from two external 24MHz or 27MHz
oscillator input, also support two-level cascaded PLL to meet special clock
frequency requirement
Up to 1.6GHz clock output for ARM PLL, up to 1.0GHz clock output for another
three PLLs
PMU(power management unit)
Provide five work modes(slow mode, normal mode, idle mode, stop mode,
power-down mode) to save power by different frequency or automatically clock
gating control or power domain on/off control
Idle mode can be wakeup by any interrupt from every on-chip components or
external GPIO
Stop mode and power-down mode can be wakeup by external dedicated IO or 96
different GPIOs or RTC alarm
Provide 9 separately power domains, which can be power up/down by software
based on different application scenes
RTC
Provides Year, Month, Day, Weekday, Hours, Minutes and Seconds Information
based on 32.768KHz input clock
Programmable alarm with interrupt generation, which can be maskable
Programmable alarm to wake up external PMU device by output control pin
Provide some registers for storage system information in RK2918 power off
mode
Only need 1.2V power supply if not talk with external PMU
Timer
Four on-chip 32bits Timers with interrupt-based operation
Provide two operation modes: free-running and user-defined count
Support timer work state checkable
timer0 and timer1 are for CPU system domain, timer2 and timer3 are for peri
system domain
support independent fixed clock for timer0 and timer1 from external 24MHz
clock input, asynchronous with APB bus clock
support dependent clock for timer2 and timer3 from system, same as APB bus
clock
PWM
Four on-chip PWMs with interrupt-based operation
Programmable 4-bit pre-scalar from apb bus clock
Embedded 32-bit timer/counter facility
Support single-run or continuous-run PWM mode
Support maskable interrupt
Provides reference mode and output various duty-cycle waveform
Provides capture mode and measure the duty-cycle of input waveform
WatchDog
32 bits watchdog counter width
Counter clock is from APB bus clock
Counter counts down from a preset value to 0 to indicate the occurrence of a
timeout
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WDT can perform two types of operations when timeout occurs:
Generate a system reset
First generate an interrupt and if this is not cleared by the service routine by
the time a second timeout occurs then generate a system reset
Programmable reset pulse length
Totally 16 defined-ranges of main timeout period
Bus Architecture
64-bit multi-layer AXI/AHB composite bus architecture
Six embedded AXI interconnect
CPU L1 interconnect with two 64-bits AXI masters and six 32/64bits AXI
slaves
CPU L2 interconnect with one 32-bits AXI master, 32-bits AXI slave and lots
of 32-bits AHB /APB slaves
Peri interconnect with two 64-bits AXI masters, one 64-bits AXI slave, one
32-bits AXI slave, two 32-bits AHB masters and lots of 32-bits AHB/APB
slaves
Display interconnect with three 64-bits AXI masters, two 32-bits AHB
masters and one 64-bits AXI slave
GPU and VCODEC interconnect also with one 64-bits AXI master and one
64-bits AXI slave ,they are point-to-point AXI-lite architecture
For each interconnect with AXI/AHB/APB composite bus, clocks for AXI/AHB/APB
domains are always synchronous, and different integer ratio is supported for
them.
For CPU L1/CPU L2/Peri three interconnects, provide GPV registers to be
programmed by software to support different application scenes
Interrupt Controller
Support 71 interrupt sources input from different components inside RK2918 or
GPIO
Support 16 software-triggered interrupts
Two AXI slave interfaces for shared distributor and cpu to manage individual
registers with different intention
Input interrupt level is fixed , only high-level sensitive
Two interrupt output (nFIQ and nIRQ) to Cortex-A8, both are low-level sensitive
Support different interrupt priority for each interrupt source, and they are
always software-programmable
Support security extension to make some registers only be accessed in system
security mode
DMAC
Micro-code programming based DMA
The specific instruction set provides flexibility for programming DMA transfers
Linked list DMA function is supported to complete scatter-gather transfer
Support internal instruction cache
Embedded DMA manager thread
Support data transfer types with memory-to-memory, memory-to-peripheral,
peripheral-to-memory
Signals the occurrence of various DMA events using the interrupt output signals
Mapping relationship between each channel and different interrupt outputs is
software-programmable
Two embedded DMA controller , DMAC0 is for CPU system, DMAC1 is for peri
system
DMAC0 features:
6 channels totally
8 hardware request from peripherals
3 interrupt output
Dual APB slave interface for register configure, designated as secure and
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non-secure
Support trustzone technology and programmable secure state for each DMA
channel
DMAC1 features:
7 channels totally
20 hardware request from peripherals
4 interrupt output
Not support trustzone technology
Security system
Support trustzone technology for the following components inside RK2918
Cortex-A8, support security and non-security mode, switch by software
Interrupt controller, support some registers and dedicated interrupt sources
to work only in security mode
DMAC0, support some dedicated channels work only in security mode
eFuse, only accessed by Cortex-A8 in security mode
Internal memory , part of space is addressed only in security mode, detailed
size is software-programmable together with TZMA(trustzone memory
adapter) and TZPC(trustzone protection controller)
1.1.6 Video CODEC
Shared internal memory and bus interface for video decoder and encoder
Video Decoder
Real-time video decoder of MPEG-1, MPEG-2, MPEG-4,H.263, H.264 , AVS ,
VC-1 , RV , VP8 , Sorenson Spark
Error detection and concealment support for all video formats
Output data structure after decoder is YCbCr 4:2:0 semi-planar to have more
efficient bus usage, For H.264, YCbCr 4:0:0(monochrome) is also supported
Minimum image size is 48x48 for all video formats
H.264 up to HP level 4.2 : 1080p@60fps (1920x1088)
③
MPEG-4 up to ASP level 5 : 1080p@60fps (1920x1088)
MPEG-2 up to MP : 1080p@60fps (1920x1088)
MPEG-1 up to MP : 1080p@60fps (1920x1088)
H.263 : 576p@60fps (720x576)
Sorenson Spark : 1080p@60fps (1920x1088)
VC-1 up to AP level 3 : 1080p@30fps (1920x1088)
RV8/RV9/RV10 : 1080p@60fps (1920x1088)
VP6/VP7/VP8 : 1080p@60fps (1920x1088)
AVS : 1080p@60fps (1920x1088)
For AVS, 4:4:4 sampling not supported
For H.264, Image cropping not supported
For MPEG-4,GMC(global motion compensation) not supported
For VC-1, upscaling and range mapping are supported in image post-processor
For MPEG-4 SP/H.263/Sorenson spark, using a modified H.264 in-loop filter to
implement deblocking filter in post-processor unit
Video Encoder
Encoder only for H.264 (BP@level4.0, MP@level4.0,HP@level4.0) standard
Only support I and P slices, not B slices
Entropy encoding is CAVLC in BP and CABAC in MP
Support error resilience based on constrained intra prediction and slices
Maximum MV length is +/- 14 pixels in vertical direction and +/-30 pixels in
horizontal direction
Motion vector pixel accuracy is up to 1/4 pixels in 720p resolution and 1/2 pixels
in 1080p resolution
12 intra prediction modes
Number of reference frames is 1
Maximum number of slice groups is 1
②
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Input data format :
YCbCr 4:2:0 planar
YCbCr 4:2:0 semi-planar
YCbYCr 4:2:2
CbYCrY 4:2:2 interleaved
RGB444 and BGR444
RGB555 and BGR555
RGB565 and BGR565
RGB888 and BRG888
RGB101010 and BRG101010
Output data format : H.264 byte unit stream and H.264 NAL unit stream
Image size is from 96x96 to 1920x1088(Full HD)
Maximum frame rate is up to 30fps@1920x1080
Bit rate supported is from 10Kbps to 20Mbps
1.1.7 JPEG CODEC
JPEG decoder
Input JPEG file : YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4 sampling
formats
Output raw image : YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4
semi-planar
Decoder size is from 48x48 to 8176x8176(66.8Mpixels)
Maximum data rate
④
is up to 76million pixels per second
Thumbnail decoding and error detection is supported
Non-interleaved data order not supported
JPEG encoder
Input raw image :
YCbCr 4:2:0 planar
YCbCr 4:2:0 semi-planar
YCbYCr 4:2:2
CbYCrY 4:2:2 interleaved
RGB444 and BGR444
RGB555 and BGR555
RGB565 and BGR565
RGB888 and BRG888
RGB101010 and BRG101010
Output JPEG file : JFIF file format 1.02 or Non-progressive JPEG
Encoder image size up to 8192x8192(64million pixels) from 96x32
Maximum data rate
④
up to 90million pixels per second
Support thumbnail insertion with RGB8bits, RGB24bits and JPEG compressed
thumbnails
1.1.8 Image Enhancement
③
Image pre-processor
Only used together with video encoder inside RK2918 , not support stand-alone
mode
Provides RGB to YCbCr 4:2:0 color space conversion, compatible with BT.601 ,
BT.709 or user defined coefficients
Provides YCbCr4:2:2 to YCbCr4:2:0 color space conversion
Support cropping operation from 8192x8192 to any supported encoding size
Support rotation with 90 or 270 degrees
Video stabilization
Work in combined mode with video encoder inside RK2918 and stand-alone
mode
Maximum stabilization displacement in pixels for two sequential input video
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pictures is +/- 16 pixels
Adaptive motion compensation filter
Offset around stabilized picture is minimum 8 pixels in standalone mode and 16
pixels in combined mode
Support scene detection from video sequence, encodes key frame when scene
change noticed
Image post-processor
Combined with video/jpeg decoder, post-processor can read input data directly
from decoder output to reduce bus bandwidth
Also work as a stand-alone mode, its input data is from a camera interface or
other image data stored in external memory
Input data format :
any format generated by video decoder in combined mode
YCbCr 4:2:0 semi-planar
YCbCr 4:2:0 planar
YCbYCr 4:2:2
YCrYCb 4:2:2
CbYCrY 4:2:2
CrYCbY 4:2:2
Ouput data format:
YCbCr 4:2:0 semi-planar
YCbYCr 4:2:2
YCrYCb 4:2:2
CbYCrY 4:2:2
CrYCbY 4:2:2
Fully configurable ARGB channel lengths and locations inside 32bits, such as
ARGB 32bit(8-8-8-8),RGB 16bit(5-6-5),ARGB 16bit(4-4-4-4)
Input image size:
Combined mode : from 48x48 to 8176x8176 (66.8Mpixels)
Stand-alone mode : width from 48 to 8176,height from 48 to 8176, and
maximum size limited to 16.7Mpixels
Step size is 16 pixels
Output image size: from 16x16 to 1920x1088 (horizontal step size 8,vertical
step size 2)
Support image up-scaling :
Bicubic polynomial interpolation with a four-tap horizontal kernel and a
two-tap vertical kernel
Arbitrary non-integer scaling ratio separately for both dimensions
Maximum output width is 3x input width
Maximum output height is 3x input height, and 2.5x input height when
running RV/VP7/VP8 format decoder
Support image down-scaling:
Arbitrary non-integer scaling ratio separately for both dimensions
Unlimited down-scaling ratio
Not allowed to perform horizontal up-scaling and vertical down-scaling at the
same time
Support YCbCr to RGB color conversioin, compatible with BT.601-5 ,BT.709 and
user definable conversion coefficient
Support dithering (2x2 ordered spatial dithering for 4,5,6bit RGB channel
precision
Support programmable alpha channel and alpha blending operation with the
following overlay input formats:
8bit alpha value+YCbCr4:4:4,big endian channel order being AYCbCr, 8bits
each
8bit alpha value+24bit RGB,big endian channel order being ARGB,8bits each
Support deinterlacing with conditional spatial deinterlace filtering, only
compatible with YCbCr4:2:0 input format
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Support RGB image contrast / brightness / color saturation adjustment
Support image cropping & digital zoom only for JPEG or stand-alone mode
Support picture in pcture
Support image rotation (horizontal flip, vertical flip, rotation 90,180 or 270
degrees)
1.1.9 Graphics Engine
Compatible with OpenGL ES2.0 , OpenGL ES1.1, OpenVG1.1, DirectFB,
GDI/DirectDraw, EGL1.4
Support shader model3.0
Geometry rate : 60M tri/s
Depth-only Pixel rate : 600M pix/s
Textured Pixel rate : 600M pix/s
Vertex rate : 300M vert/s
2D Graphics Engine :
Bit Blit, Stretch Blit, Filter Blit
Rectangle fill and clear
Line drawing
Copy bit
Filter
High-performance stretch and shrink
Monochrome expansion for text rendering
ROP2,ROP3,ROP4 full alpha blending and transparency
Alpha blending modes including Java 2 Porter-Duff compositing blending rules,
chroma key, and pattern mask
Transparency by monochrome mask
32K x 32K raster 2D coordinate system
90,180 and 270 degrees rotation on every 2D primitive
Programmable high quality 9-tap,32-phase filter to support image scaling
Blending, scaling and rotation are supported in one pass for stretch Blit
Source format :
RGBA4444,5551,8888
RGBX4444,5551,8888
RGB565
UYVY4:2:2, YUY2(4:2:2),YV12(4:2:0)
Destination formats :
RGBA4444,5551,8888
RGBX4444,5551,8888
RGB565
3D Graphics Engine :
IEEE 32-bit floating-point pipeline
Ultra-threaded, unified vertex and fragment shaders
Low CPU loading and low bandwidth at both high and low data rates
Up to 12 programmable elements per vertex
Dependent texture operation with high-performance
Alpha blending
Support video texture
Depth and stencil compare
Support for 8 fragment shader simultaneous textures
Support for 12 vertex shader simultaneous textures
Point sampling,bit-linear sampling,tri-linear filtering and cubic textures
Resolve and fast clear
8k x 8k texture size and 8k x 8k rendering target
1.1.10 Video IN/OUT
Camera Interface
Support CMOS type image sensor interface
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Support CCIR656 interface
Support CCIR656 YCbCr 4:2:2 raster video input for 8bit mode in 525/60 NTSC
and 625/50 PAL video system
Data input clock is 27MHz for CCIR656 and 24MHz/48MHz for sensor, and max
up to 96MHz for raw data
Provide YUV 4:2:2/4:2:0 output
Support up to 3856x2764 resolution and maximum 10M pixels
Support YUYV/UYVY format input
Support 10/12-bit raw data input
In sensor mode, support software-programmable vsync and href high active or
low active
Embedded AXI 64bits master interface to improve performance, also compatible
with AHB 32bits master interface
Display Interface
Image Post-Processor (IPP)
memory to memory mode
input data format and size
RGB888 : 16x16 to 8191x8191
RGB565 : 16x16 to 8191x8191
YUV422/YUV420 : 16x16 to 8190x8190
YUV444 : 16x16 to 8190x8190
pre scaler
integer down-scaling(ratio: 1/2,1/3,1/4,1/5,1/6,1/7,1/8) with linear
filter
deinterlace(up to 1080i) to support YUV422&YUV420 input format
post scaler
down-scaling with 1/2 ~ 1 arbitary non-integer ratio
up-scaling with 1~4 arbitary non-integer ratio
4-tap vertical, 2-tap horizontal filter
The max output image width of post scaler is 4096
Support rotation with 90/180/270 degrees and x-mirror, y-mirror
LCD Controller
Display Interface
Parallel RGB LCD Interface:
24bit(RGB888)
18bit(RGB666)
16bit(RGB565)
Serial RGB LCD Interface:
3x8bit (RGB delta support)
3x8bit + dummy
16bit + 8bit
MCU LCD interface:
I-8080 (up to 24-bit RGB)
Hold/Auto/Bypass modes
TV interface : ITU-R BT.656(8-bits, 480i/576i/1080i)
Display Process
One background layer: programmable 24-bit color
One video layer(win0)
ARGB888, RGB565, YCbCr422, YCbCr420, YCbCr444, AYCbCr
maximum resolution is 1920x1080
virtual display
1/8 to 8 scaling-down and scaling-up engine with arbitrary
non-integer ratio
256 level alpha blending(no scaling in ARGB/AYCbCr mode)
transparency color key
deflicker support for interlace output
sharp/smooth filter
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RK2918 Datasheet Rev 1.0
One graphic layer(win1)
RGB888, ARGB888, RGB565
maximum resolution is 1920x1080
virtual display
256 level alpha blending
transparency color key
One OSD layer(win2)
1/2/4/8bpp palette mode
maximum resolution is 1920x1080
8-bit alpha Alpha
transparency color key
Hardware cursor(HWC)
32x32x2bpp
3-color and transparent mode
2-color + transparency + tran_invert mode
16 level alpha blending
3 x 256 x 8 bits display LUTs
Graphic layer and video layer overlay exchangeable
Support color space conversion : YCbCr-to-RGB(rec601-mpeg/
rec601-jpeg/rec709) and RGB-to-YCbCr
Support replication(16-bit to 24-bit) and dithering(24-bit to 16-bit/18-bit)
operation
Blank and black display
Standby mode
eBook display controller
System interface
AHB slave for register configuration
AHB master for frame data transfer（DMA）
Interrupt output
EPD interface
up to 2048x2048 resolution
up to 16 level gray scale
LUT can be updated
direct mode and LU T mode
all-update mode and diff-update mode
single-phase and multi-phase mode
support window display
source driver interface
gate driver interface
1.1.11 Audio Interface
I2S/PCM with 8ch
Compatible audio resolution from 16bits to 32bits
Sample rate up to 192KHz
Provides master and slave work mode, software configurable
Embedded 4 TX FIFO and 1 RX FIFO with 32x32bits size
Support I2S normal , left-justified , right-justified three data formats in I2S
mode
Support early , late1 , late2 , late3 four data formats in PCM mode
For I2S mode only, support software-configurable channel number(TX : 2/4/6/8;
RX:2)
For PCM mode only, support software-configurable channel number(TX : 2/4/6/8;
RX:2)
In master TX mode, Support I2S and PCM work simultaneously in condition of
same audio data and same sample rate , and only use two channels separately
for I2S and PCM
Support SCLK and LRCK polarity software-configurable
SCLK can be even-divided by 2 to 64 from i2s main clock
Rockchips Confidential 16
RK2918 Datasheet Rev 1.0
I2S/PCM with 2ch
Compatible audio data width from 16bits to 32bits
Sample rate up to 192KHz
Provides master and slave work mode, software configurable
Embedded 1 TX FIFO and 1 RX FIFO with 32x32bits size
Support I2S normal mode, I2S left-justified mode , I2S right-justified mode
Support PCM early mode , late1 mode, late2 mode , late3 mode
I2S and PCM cannot be used at the same time
Support SCLK and LRCK polarity software-configurable
SCLK can be even-divided by 2 to 64 from i2s main clock
SPDIF
Embedded one 32x32bits buffer
Provides audio data with biphase encode
Support stereo voice replay with 2 channels
Support software configurable sample rates (48KHz, 44.1KHz, 32KHz)
Support audio data width 16bits/20bits/24bits
Frame frequency is 128x audio data sample rates
1.1.12 Connectivity
SDIO interface
Compatible with SDIO ver1.00
One AHB slave interface to complete data transfer together with external DMAC1
or CPU
Support combined single FIFO(32x32bits) for both transmit and receive
operations
Support FIFO over-run and under-run prevention by stopping card clock
automatically
Support CRC generation and error detection
Embedded clock frequency division control to provide programmable baud rate
Support host pull-up control, card detection and initialization, write protection
Support block size from 1 to 65535Bytes
Data bus width is flexible to support 1bit/4bits
Support SDIO suspend and resume operation
Support SDIO read wait
Host Slave Interface
Asynchronous 8bits/16bits 68/80 series MCU interface
Support direct and indirect access mode
On-chips 4KB dual-port SRAM buffer for direct access
In indirect mode, host interface can access any of space inside or outside of
RK2918
High-speed ADC & TS stream interface
Only support one-channel (only I, not Q channel) 8bits/10bits data input
DMA-based and interrupt-based operation
Support 8bits TS stream data receive
Support PID filter operation
Combined with high-speed ADC interface to implement filter from original TS
data
Provide PID filter up to 64 channels PID simultaneously
Support sync-byte detection in transport packet head
Support packet lost mechanism in condition of limited bandwidth
MAC 10/100M Ethernet Controller
IEEE802.3u compliant Ethernet Media Access Controller(MAC)
10Mbps and 100Mbps compatible
Rockchips Confidential 17
RK2918 Datasheet Rev 1.0
Automatic retry and automatic collision frame deletion
Full duplex support
PAUSE full-duplex flow-control support
Address filtering(broadcast, multicast, logical, physical)
Support RMII(Reduced MII) and MII(Media Independent Interface) mode
In RMII mode, clock can be from RK2918 or external Ethernet PHY
SPI Controller
Two on-chip SPI controller inside RK2918
Support serial-master and serial-slave mode, software-configurable
DMA-based or interrupt-based operation
Embedded two 32x16bits FIFO for TX and RX operation respectively
Support 2 chip-selects output in serial-master mode
UART Controller
Four on-chip UART controller inside RK2918
DMA-based or interrupt-based operation
Embedded two 32Bytes FIFO for TX and RX operation respectively
Support 5bit,6bit,7bit,8bit serial data transmit or receive
Standard asynchronous communication bits such as start, stop and parity
Support different input clock for UART operation to get up to 4Mbps or other
special baud rate
Support non-integer clock divides for baud clock generation
Support IrDA1.0 SIR(115.2Kbps) mode for UART1
Auto flow control mode is only for UART0,UART2,UART3
I2C controller
Four on-chip I2C controller in RK2918
Multi-master I2C operation
Support 7bits and 10bits address mode
Software programmable clock frequency and transfer rate up to 400Kbit/s in the
fast mode
Serial 8bits oriented and bidirectional data transfers can be made at up to
100Kbit/s in the standard mode
GPIO
7 groups of GPIO (GPIO0~GPIO6) , 32 GPIOs per group, totally have 224 GPIOs
All of GPIOs can be used to generate interrupt to cortex-A8
In power-down mode, status(IO direction and output level) of GPIO0~GPIO5
can be controlled by another registers in always-on domain
Totally 96 GPIOs(GPIO0,GPIO4,GPIO6) can be used to wakeup system from stop
mode or power-down mode
All of pull-up GPIOs are software-programmable for pull-up resistor or not
All of pull-down GPIOs are software-programmable for pull-down resistor or not
All of GPIOs are pull-up or pull-down in default except GPIO1[5] MUX with PWM3
after power-on-reset
All of GPIOs are always in input direction in default after power-on-reset
USB Host1.1
Compatible with USB host1.1 specification
Only supports full-speed transfer up to 12Mbps
Provides 6 host mode channels
Support periodic out channel
USB Host2.0
Compatible with USB host2.0 specification
Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps)
mode
Rockchips Confidential 18
RK2918 Datasheet Rev 1.0
Provides 3 host mode channels
USB OTG2.0
Compatible with USB otg2.0 specification
Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps)
mode
Support up to 6 device mode endpoints in addition to control endpoint 0
Support up to 4 device mode IN endpoints including control endpoint 0
Endpoints 1/3/5 can be used only as data IN endpoint
Endpoints 2/4/6 can be used only as data OUT endpoint
Provides 6 host mode channels
Support periodic out channel in host mode
1.1.13 Others
SAR-ADC(Successive Approximation Register)
4-channel single-ended 10-bit SAR analog-to-digital converter
Conversion speed range is from 0.1 to 1 MSPS
SAR-ADC clock must be less than 1MHz
DNL less than ±1 LSB , INL less than ±2.0 LSB
Power down current is about 1uA
2.5V Power supply for analog interface
eFuse
1024bits (128x8) high-density electrical Fuse
Programming condition : VQPS must be 2.5V(±10%)
Program time is about 4~6us
Read condition : VQPS must be 0V or floating or 2.5V(±10%)
Provide power-down and standby mode
Package Type
TFBGA512 (body: 16mm x 16mm ; ball size : 0.3mm ; ball pitch : 0.65mm)
Notes :
internal buffer
① :
DDRII and LPDDR are not used simultaneously as well as async and sync DDR NAND flash
②:
In RK2918, Video decoder and encoder are not used simultaneously because of shared
③:
Actual maximum frame rate will depend on the clock frequency and system bus performance
④:
Actual maximum data rate will depend on the clock frequency and JPEG compression rate
1.2 Block Diagram
The following diagram shows the basic block diagram for RK2918.
Rockchips Confidential 19
RK2918 Datasheet Rev 1.0
RK2918
32KB ICache
ETM NEON
Cortex-A8
32KB DCache
512KB L2 Cache
TrustZone
LCD Controller
(1920x1080 output
24 bits panel
4-layer window
Scale up/Down)
EPD driver I/F
Camera I/F
(8bits CCIR / 8bits
Sensor)
Image Interface
2D Graphics Engine
1080p Video encoder
(H.264)
Image pre processor
3D Graphics Engine
1080p Video decoder
(H263/H264/MPEG2
/MPEG4/VC-1/VP8/
RMVB/AVS)
JPEG Encoder
Image post processor
JPEG Decoder
Multi-Media Processor
SDR/DDR/LBA Nand
Flash
(24bit ECC)
LPDDR
(200MHz, 32bits)
External Memory Interface
DDRII
(400MHz,
32bits/16bits)
SD2.0 / HS-MMC4.2
(8bits)
Inand /eMMC I/F
Nor Flash /Async
SRAM
USB OTG 2.0
SDIO
UARTx4
I2S/PCM
(M/S) (8ch )
I2C x4
SPI(M/S) x2
GPIO
SPDIF (1ch)
USB HOST 2.0
USB HOST 1.1
Modem I/F
MAC (MII/RMII)
I2S/PCM
(M/S) (2ch)
TS I/F
Connectivity
DMACx2 (13ch)
Interrupt Controller
PMU
PWMx3
WatchDog
Timerx4
Clock & Reset
System register
RTC
SAR-ADC
PLL x 4
System Peripheral
SRAM (16KB)
(security/non-security)
ROM (10KB)
eFuse
(128 x 8bits )
Memory
Rockchips Confidential 20
Fig. 1-1 RK2918 Block Diagram
RK2918 Datasheet Rev 1.0
1 2 3 4 5 6 7 8 9
10
11
12
A
GPIO6_A[0]
GPIO6_B[7]
GPIO1_C[0]/
UART0_CTS_N/
SDMMC1_DETECT_
N
GPIO3_A[5]/
I2S1_LRCK_TX
GPIO3_A[4]/
I2S1_SDO
GPIO5_D[6]/
SDMMC1_PWR_EN
GPIO5_D[5]/
SDMMC0_PWR_EN
GPIO2_B[2]/
UART3_SIN
GPIO1_A[5]/
EMMC_PWR_EN/
PWM3
GPIO1_A[4]/EMMC
_WRITE_PRT/SPI0_
CSN1
GPIO6_C[2]
GPIO1_A[6]/
I2C1_SDA
B
GPIO6_B[6]
GPIO6_B[5]
GPIO6_A[1]
GPIO2_A[7]/
UART2_RTS_N
GPIO3_A[3]/
I2S1_SDI
GPIO3_A[1]/
I2S1_SCLK
GPIO5_D[2]/
PWM1/
UART1_SIR_IN
GPIO5_D[3]/
I2C2_SDA
GPIO2_A[3]/
SDMMC0_WRITE_P
RT/
PWM2/
UART1_SIR_OUT
GPIO2_A[2]/
SDMMC0_DETECT_
N
GPIO4_A[6]/
OTG1_DRV_VBUS
GPIO1_A[7]/
I2C1_SCL
C
GPIO6_A[5]
GPIO6_B[4]
GPIO6_A[2]
GPIO1_C[1]/
UART0_RTS_N/
SDMMC1_WRITE_P
RT
GPIO2_A[6]/
UART2_CTS_N
GPIO3_A[2]/
I2S1_LRCK_RX
GPIO2_A[4]/
UART1_SIN
GPIO1_B[5]/
PWM0
GPIO2_B[6]/
I2C0_SDA
GPIO4_D[4]
GPIO6_C[6]
GPIO6_C[0]
D
GPIO6_A[6]
GPIO6_A[7]
GPIO6_B[3]
GPIO6_A[3]
GPIO1_B[7]/
UART0_SOUT
GPIO2_B[4]/
UART3_CTS_N/
I2C3_SDA
GPIO3_A[0]/
I2S1_CLK
GPIO1_B[6]/
UART0_SIN
GPIO5_D[4]/
I2C2_SCL
GPIO2_B[7]/
I2C0_SCL
GPIO0_A[7]/
MII_MDCLK
GPIO4_D[0]
E
GPIO6_B[0]
GPIO5_A[0]
GPIO6_B[2]
GPIO5_A[2]
GPIO6_A[4]
GPIO2_B[0]/
UART2_SIN
GPIO2_B[5]/
UART3_RTS_N/
I2C3_SCL
GPIO2_B[1]/
UART2_SOUT
GPIO2_A[5]/
UART1_SOUT
GPIO6_C[5]
GPIO4_D[1]
GPIO6_C[1]
F
GPIO6_B[1]
GPIO0_A[1]
GPIO5_A[1]
GPIO0_A[0]
AVDD_DPLL
AHVDD_APLL
AHVSS_APLL
GPIO2_B[3]/
UART3_SOUT
GPIO4_D[3]
GPIO4_D[2]
GPIO4_D[5]
GPIO5_D[7]
G
XOUT24M
XIN24M
GPIO0_A[2]
GPIO0_A[4]
DVDD_APLL
AVSS_DPLL
DVSS_APLL
VDDIO_AP1
VDDIO_AP0
VDDCORE
VDDIO6
VDDCORE
H
XOUT27M
XIN27M
GPIO0_A[3]
GPIO4_A[3]
DVDD_DPLL
DVSS_DPLL
DVSS_CGPLL
NP
NP
NP
NP
NP
J
GPIO4_A[0]
GPIO4_A[1]
GPIO4_A[2]
GPIO4_A[4]
AVDD_CGPLL
DVDD_CGPLL
AVSS_CGPLL
NP
NP
NP
NP
NP
K
DQ[3]
DQ[2]
DQ[1]
DQ[0]
TRST_N
NPOR
VDDIO0
NP
NP
GND
GND
GND
L
DQS[0]
DQS_b[0]
DQ[5]
DQ[4]
TCK
TDI
VDDCORE
NP
NP
GND
GND
GND
M
DQ[7]
DQ[6]
DQ[17]
DM[0]
VSSIO_DDR0
TMS
TDO
NP
NP
GND
GND
GND
Chapter 2 Package Description
2.1 Ball Map
Rockchips Confidential 21
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