Rockchip RK3568 Design Guide

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RK3568

Hardware

Design Guide

Release Version: V1.2

Release Date: 2022-01-26

RK3568 Hardware Design Guide Rev V1.2

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LTD.(“ROCKCHIP”)DOES NOT PROVIDE ANY WARRANTY OF ANY KIND, EXPRESSED,

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瑞芯微电子股份有限公司

Rockchip Electronics Co., Ltd.

Address: No. 18 Building, A District, No.89, software Boulevard Fuzhou, Fujian, PRC Website: www.rock-chips.com Customer service tel.: +86-4007-700-590 Customer service fax: +86-591-83951833 Customer service e-mail: FAE@rock-chips.com

RK3568 Hardware Design Guide Rev V1.2

Preface

Overview

This document presents the key points of hardware design and notices for RK3568 processors, aiming to help

customers shorten developing period of product, improving product design stability and reducing fault rate. Please

refer to the requirements of this guide for hardware design, and use the relevant core templates released by

Rockchip. If you need to modify for special reasons, please strictly follow the design rule of

high-speed-digital-circuit and Rockchip Schematic&PCB checklist requirements.

Chipset Model

This document is suitable for the following chipset model: RK3568

Intended Audience

This document (this guide) is mainly intended for:

 Hardware development engineers  Layout engineers  Technical support engineers  Test engineers

RK3568 Hardware Design Guide Rev V1.2

Revision History

This revision history recorded description of each version, and any updates of previous versions are included

in the latest one.

Version

No.

Author

Revision

Date

Revision Description

Remark

V1.2

Zhangdz

2021-10-14

1:Update the description of ECC (Section 2.1.7.2)

V1.1

Zhangdz

2021-06-08

1: Update the description of wake-up and standby of

infrared receiver (Section 2.3.17)

2: Add IO Domain power supply and software

configuration attentions (Section 2.1.11)

3: Update the DCDC power supply capacity requirements

of VDD_NPU and VDD_LOGIC power supplies, which

require 2A or more (Section 2.2.2.6 and 2.2.2.7)

4: VDD_LOGIC peak current is updated to 1.2A (Section

2.2.6)

5: Add a description of the module that does not supply

power, and the corresponding node in DTS should be

disabled (Section 2.2.2.1)

V1.0

Zhangdz

2021-04-16

The initial release version

RK3568 Hardware Design Guide Rev V1.2

Acronyms

Acronyms include the abbreviations of commonly used phrases in this document:

ARM

Advanced RISC Machine

高级精简指令集计算机

CAN

Controller Area Network

控制器局域网络

CEC

Consumer Electronics Control

消费电子控制

CIF

Camera Input Format

相机并行接口

CPU

Central processing unit

中央处理器

CSI

Camera Serial Interface

相机串行接口

DC/DC

Direct current-Direct current converter

直流/直流变换器

DDR

Double Data Rate

双倍速率同步动态随机存储器

DisplayPort

显示接口

DSI

Display Serial Interface

显示串行接口

EBC

E-book controller

电子书控制器

eDP

Embedded DisplayPort

嵌入式数码音视讯传输接口

eMMC

Embedded Multi Media Card

内嵌式多媒体存储卡

ESD

Electro-Static discharge

静电释放

ESR

Equivalent Series Resistance

等效电阻

Flash_VOL_SEL

Flash voltage selection

eMMC/Nand Flash IO电压选择

FSPI

Flexible Serial Peripheral Interface

灵活串行外设接口

GPU

Graphics Processing Unit

Figure形处理单元

HDMI

High Definition Multimedia Interface

高清晰度多媒体接口

HPD

Hot Plug Detect

热插拔检测

I2C

Inter-Integrated Circuit

内部整合电路(两线式串行通讯总线)

I2S

Inter-IC Sound

集成电路内置音频总线

ISP

Image Signal Processing

Figure像信号处理

JTAG

Joint Test Action Group

联合测试行为组织定义的一种国际标准测试协议（IEEE 1149.1兼容）

LDO

Low Drop Out Linear Regulator

低压差线性稳压器

LCDC

LCD Controller

LCD 控制器并行接口

LCM

LCD Module

LCD显示模组

LVDS

Low-Voltage Differential Signaling

低电压差分信号

MAC

Media Access Control

以太网媒体接入控制器

MIPI

Mobile Industry Processor Interface

移动产业处理器接口

NPU

Neural network Processing Unit

神经网络处理器

PCB

Printed Circuit Board

印制电路板

RK3568 Hardware Design Guide Rev V1.2

PCIe

Peripheral Component Interconnect

-express

外设组件互联标准

PCM

Pulse Code Modulation

脉冲编码调制

PDM

Pulse density modulation

脉冲密度调制

PLL

Phase-locked loop

锁相环

PMIC

Power Management IC

电源管理芯片

PMU

Power Management Unit

电源管理单元

PWM

Pulse width modulation

脉冲宽度调制

QSGMII

Quad Serial Gigabit Media Independent Interface

四串行千兆媒体独立接口

RGB

RGB color mode is a color standard in industry

RGB色彩模式, 是工业界的一种颜

色标准

GMAC

Gigabit Media Access Controller

千兆媒体访问控制器

RGMII

Reduced Gigabit Media Independent Interface

简化千兆媒体独立接口

RMII

Reduced Media Independent Interface

简化媒体独立接口

Rockchip Electronics Co.,Ltd.

瑞芯微电子股份有限公司

SARADC

successive approximation register Analog to digital

converter

逐次逼近寄存器型模数转换器

SATA

Serial Advanced Technology Attachment

串行高级技术附件

SCR

Smart Card Reader

智能卡读卡器

SD Card

Secure Digital Memory Card

安全数码卡

SDIO

Secure Digital Input and Output Card

安全数字输入输出卡

SDMMC

Secure Digital Multi Media Card

安全数字多媒体存储卡

SGMII

Serial Gigabit Media Independent Interface

串行千兆媒体独立接口

SPDIF

Sony/Philips Digital Interface Format

SONY、PHILIPS数字音频接口

SPI

Serial Peripheral Interface

串行外设接口

SubLVDS

Sub- Low-Voltage Differential Signaling

低摆幅差分信号技术

TF Card

Micro SD Card(Trans-flash Card)

外置记忆卡

TSADC

Temperature sensing A / D converter

温度感应模数转换器

UART

Universal Asynchronous Receiver / Transmitter

通用异步收发传输器

VOP

Video Output Processor

视频输出处理器

VPU

Video Processing Unit

视频处理器

USB2.0

Universal Serial Bus 2.0

通用串行总线

USB3.0

Universal Serial Bus 3.0

通用串行总线

RK3568 Hardware Design Guide Rev V1.2

Contents ...................................................................................................................................................................... V

Figures ................................................................................................................................................................... VIII

Tables ....................................................................................................................................................................... XV

1 System Introduction ............................................................................................................................................... 1

1.1 Overview ........................................................................................................................................................... 1

1.2 Block Diagram ................................................................................................................................................... 1

1.3 Application Block Diagram ............................................................................................................................... 2

RK3568 EVB Application Block Diagram ................................................................................................. 2

RK3568 Smart NVR Application Block Diagram ...................................................................................... 3

2 Schematic Design Recommendation ..................................................................................................................... 4

2.1 Minimum System Design .................................................................................................................................. 4

Clock Circuit ............................................................................................................................................... 4

Reset/watchdog/TSADC Circuit ................................................................................................................. 6

PMU Circuit................................................................................................................................................ 7

System Boot Sequence ............................................................................................................................... 8

System Initialization Configuration Signal ................................................................................................. 8

JTAG and UART Debug Circuit ............................................................................................................... 10

DDR Circuit .............................................................................................................................................. 12

eMMC Circuit ........................................................................................................................................... 25

FSPI Flash Circuit ..................................................................................................................................... 28

Nand Flash Circuit .................................................................................................................................. 30

GPIO Circuit ........................................................................................................................................... 32

2.2 Power Supply Design ...................................................................................................................................... 36

RK3568 Power Supply Introduction ......................................................................................................... 36

Power Supply Design Suggestion ............................................................................................................. 37

RK809-5 Solution Introduction ................................................................................................................ 53

Discrete Power Supply Solution Introduction .......................................................................................... 59

Standby Control Circuit ............................................................................................................................ 61

Power Peak Current Table ........................................................................................................................ 62

2.3 Functional Interface Circuit Design Guide ...................................................................................................... 64

SDMMC0/1/2 ........................................................................................................................................... 64

SARADC Circuit ...................................................................................................................................... 69

OTP Circuit ............................................................................................................................................... 71

USB2.0/USB3.0 Circuit ............................................................................................................................ 71

SATA3.0 Circuit........................................................................................................................................ 78

QSGMII/SGMII Circuit ............................................................................................................................ 81

PCIe2.0 Circuit ......................................................................................................................................... 87

PCIe3.0 Circuit ......................................................................................................................................... 89

RK3568 Hardware Design Guide Rev V1.2

Video Input Interface Circuit .................................................................................................................... 93

Video Output Interface Circuit ................................................................................................................ 98

Audio Interface Circuit .......................................................................................................................... 118

GMAC Interface Circuit ........................................................................................................................137

UART Interface Circuit .........................................................................................................................144

SPI Interface Circuit ..............................................................................................................................146

CAN Interface Circuit ............................................................................................................................146

I2C Interface Circuit ..............................................................................................................................147

PWM Interface Circuit...........................................................................................................................148

RK3568 Unused Modules Pins Processing............................................................................................150

3 PCB Design recommendations ...........................................................................................................................151

3.1 PCB Layers Design.........................................................................................................................................151

Six Layers PCB Design ...........................................................................................................................151

Four Layers PCB Design .........................................................................................................................152

RK3568 Fan-out Design ..........................................................................................................................152

3.2 Interface PCB Design Recommendations .......................................................................................................155

Clock/Reset Circuit PCB Design .............................................................................................................157

PMIC/Power Circuit PCB Design ...........................................................................................................158

DRAM Circuit PCB design .....................................................................................................................177

Flash Circuit PCB design .........................................................................................................................194

SDMMC0/1/2 Interface Crcuit PCB Design ...........................................................................................199

SARADC/OTP Interface Circuit PCB Design .........................................................................................200

USB2.0 Interface Circuit PCB Design.....................................................................................................200

USB3.0 Interface Circuit PCB Design.....................................................................................................201

SATA3.0 Interface Circuit PCB Design ...................................................................................................202

QSGMII/SGMII Interface Circuit PCB Design .....................................................................................203

PCIe2.0 Interface Circuit PCB Design ..................................................................................................204

PCIe3.0 Interface Crcuit PCB Design ...................................................................................................206

MIPI CSI RX Interface Circuit PCB Design .........................................................................................207

CIF Interface Circuit PCB Design .........................................................................................................208

MIPI DSI TX Interface Circuit PCB Design .........................................................................................208

LVDS TX Interface Circuit PCB Design ...............................................................................................209

eDP TX Interface Circuit PCB Design ..................................................................................................210

HDMI TX Interface Circuit PCB Design ..............................................................................................210

RGB TX Interface Circuit PCB Design ................................................................................................. 211

BT1120 TX Interface Circuit PCB Design ............................................................................................212

Audio Interface Circuit PCB Design .....................................................................................................213

GMAC Interface Circuit PCB Design ...................................................................................................214

WIFI/BT PCB Design ............................................................................................................................218

VGA OUT PCB Design .........................................................................................................................219

RK3568 Hardware Design Guide Rev V1.2

LCD Screen and Touch Screen PCB Design .........................................................................................220

Camera PCB Design ..............................................................................................................................220

4 Thermal Design Suggestion .................................................................................................................................221

4.1 Thermal Simulation Result .............................................................................................................................221

Result Overview ......................................................................................................................................221

PCB Description ......................................................................................................................................221

Terms Interpretation .................................................................................................................................221

4.2 Thermal Control Method inside the Chip .......................................................................................................222

Thermal Control Strategy ........................................................................................................................222

Temperature Control Configuration .........................................................................................................223

4.3 Thermal Design Reference .............................................................................................................................223

Circuit Schematic Thermal Design Reference .........................................................................................223

PCB Thermal Design Reference ..............................................................................................................223

5 ESD/EMI Protection Design ...............................................................................................................................225

5.1 Overview ........................................................................................................................................................225

5.2 Terms Interpretation ........................................................................................................................................225

5.3 ESD Protection ...............................................................................................................................................225

5.4 EMI Protection ...............................................................................................................................................226

6 Soldering Process .................................................................................................................................................229

6.1 Overview ........................................................................................................................................................229

6.2 Terms Interpretation ........................................................................................................................................229

6.3 Reflow Soldering Requirements .....................................................................................................................229

Solder Paste Composition Requirements .................................................................................................229

SMT Profile .............................................................................................................................................229

SMT Recommendation Profile ................................................................................................................231

7 Packages and Storage Conditions ......................................................................................................................232

7.1 Overview ........................................................................................................................................................232

7.2 Terms Interpretation ........................................................................................................................................232

7.3 Moisture Packages ..........................................................................................................................................232

7.4 Product Storage ...............................................................................................................................................233

Storage Environment ...............................................................................................................................233

Exposure Time .........................................................................................................................................233

7.5 Usage of Moisture Sensitive Products ............................................................................................................234

RK3568 Hardware Design Guide Rev V1.2

Figures

Figure 1-1 RK3568 block diagram ........................................................................................................................... 1

Figure 1-2 RK3568 EVB application block diagram ............................................................................................... 2

Figure 1-3 RK3568 Smart NVR application block diagram..................................................................................... 3

Figure 2-1 RK3568 Crystal circuit and components parameters .............................................................................. 4

Figure 2-2 RK3568 the 32.768KHz clock input pin in standby ............................................................................... 5

Figure 2-3 RK3568 reset input (RK809-5 solution) ................................................................................................. 6

Figure 2-4 RK3568 reset input (discrete power solution) ........................................................................................ 7

Figure 2-5 RK3568 the path of reset signal .............................................................................................................. 7

Figure 2-6 RK3568 VCCIO2 power supply and FLASH_VOL_SEL...................................................................... 9

Figure 2-7 RK3568 SDMMC0/ARM JTAG multiplexed pins and SDMMC0 DET pin .......................................... 9

Figure 2-8 RK3568 JTAG connection schematic ................................................................................................... 10

Figure 2-9 RK3568 ARM JTAG pin ....................................................................................................................... 11

Figure 2-10 RK3568 UART2 M0 pin ..................................................................................................................... 11

Figure 2-11 RK3568 Debug UART2 Connection diagram..................................................................................... 11

Figure 2-12 RK3568 16bit ECC DDR3/DDR3L processing method ..................................................................... 15

Figure 2-13 RK3568 16bit ECC DDR4 processing method ................................................................................... 15

Figure 2-14 RK3568 DDR_RZQ pin ..................................................................................................................... 16

Figure 2-15 DDR3/DDR3L VREF circuit .............................................................................................................. 16

Figure 2-16 LPDDR3 VREF circuit ....................................................................................................................... 17

Figure 2-17 DDR4 VREF circuit ............................................................................................................................ 17

Figure 2-18 DDR3/DDR3L T topology .................................................................................................................. 18

Figure 2-19 The CLKP/CLKN termination of DDR3/DDR3L T topology ............................................................ 18

Figure 2-20 DDR3/DDR3L Fly-by topology.......................................................................................................... 19

Figure 2-21 DDR4 T topology ................................................................................................................................ 19

Figure 2-22 The CLKP/CLKN termination of DDR4 T topology .......................................................................... 20

Figure 2-23 DDR4 Fly-by topology ....................................................................................................................... 20

Figure 2-24 LPDDR3 point-to-point topology ....................................................................................................... 21

Figure 2-25 LPDDR3 CLKP/CLKN termination ................................................................................................... 21

Figure 2-26 LPDDR4 point-to-point topology ....................................................................................................... 21

Figure 2-27 LPDDR4X point-to-point topology .................................................................................................... 22

Figure 2-28 RK809-5 BUCK3 parameters regulation ............................................................................................ 23

Figure 2-29 Power selection of LPDDR4/LPDDR4x compatible design ............................................................... 23

Figure 2-30 DDR3 SDRAM power up sequence ................................................................................................... 24

Figure 2-31 LPDDR3 SDRAM power up sequence ............................................................................................... 24

Figure 2-32 DDR4 SDRAM power up sequence ................................................................................................... 24

Figure 2-33 LPDDR4/4x SDRAM power up sequence .......................................................................................... 25

Figure 2-34 eMMC_D0 test point .......................................................................................................................... 26

Figure 2-35 eMMC connection diagram ................................................................................................................ 26

RK3568 Hardware Design Guide Rev V1.2

Figure 2-36 Connection diagram of eMMC and Nand Flash in compatible design ............................................... 27

Figure 2-37 eMMC power up and power down sequence ...................................................................................... 28

Figure 2-38 FSPI_CLK test point ........................................................................................................................... 29

Figure 2-39 FSPI Flash connection diagram .......................................................................................................... 29

Figure 2-40 Flash_D0 test point ............................................................................................................................. 30

Figure 2-41 Nand Flash connection diagram .......................................................................................................... 31

Figure 2-42 Nand Flash power up and down sequence .......................................................................................... 32

Figure 2-43 RK3568 PMU PLL power pin ............................................................................................................ 40

Figure 2-44 RK3568 SYS PLL power pin .............................................................................................................. 40

Figure 2-45 RK3568 PMU_VDD_LOGIC_0V9 power pin ................................................................................... 41

Figure 2-46 RK3568 VDD_CPU power pin and power supply DC/DC ................................................................ 42

Figure 2-47 RK3568 VDD_GPU power pin .......................................................................................................... 43

Figure 2-48 RK3568 VDD_NPU power pin .......................................................................................................... 43

Figure 2-49 RK3568 VDD_LOGIC power pin ...................................................................................................... 44

Figure 2-50 RK3568 VCC_DDR power pin in DDR3/DDR3L/DDR4/LPDDR3/LPDDR4 mode ....................... 44

Figure 2-51 RK3568 VCC_DDR and VCC0V6_DDR power pins in LPDDR4x mode ........................................ 45

Figure 2-52 RK3568 USB2.0 PHY power pin ....................................................................................................... 46

Figure 2-53 RK3568 MULTI_PHY power pin ....................................................................................................... 47

Figure 2-54 RK3568 PCIe3.0 PHY power pin ....................................................................................................... 47

Figure 2-55 RK3568 MIPI CSI RX PHY power pin .............................................................................................. 48

Figure 2-56 RK3568 MIPI DSI TX0 and LVDS TX Combo PHY power pin ....................................................... 49

Figure 2-57 RK3568 MIPI DSI TX1 PHY power pin ............................................................................................ 50

Figure 2-58 RK3568 eDP TX PHY power pin ....................................................................................................... 50

Figure 2-59 RK3568 HDMI2.0 TX PHY power pin .............................................................................................. 51

Figure 2-60 RK3568 SARADC and OTP power pin .............................................................................................. 52

Figure 2-61 RK809-5 block diagram ...................................................................................................................... 53

Figure 2-62 RK3568 and RK809-5 power tree ...................................................................................................... 55

Figure 2-63 RK809-5 power-on sequence .............................................................................................................. 56

Figure 2-64 RK3568 + discrete power architecture ................................................................................................ 59

Figure 2-65 Discrete power power-on sequence .................................................................................................... 60

Figure 2-66 RK3568 PMIC_SLEEP output ........................................................................................................... 62

Figure 2-67 RK809-5 PMIC_SLEEP input ............................................................................................................ 62

Figure 2-68 The PMIC_SLEEP input of VDD_CPU BUCK ................................................................................. 62

Figure 2-69 RK3568 SDMMC0 interface pin ........................................................................................................ 64

Figure 2-70 SD card interface circuit ..................................................................................................................... 65

Figure 2-71 RK3568 SDMMC1 interface pin ........................................................................................................ 66

Figure 2-72 RK3568 SDMMC2 interface M0 functional pins ............................................................................... 67

Figure 2-73 RK3568 SDMMC2 interface M1 functional pins ............................................................................... 68

Figure 2-74 SARADC VIN0 interface ................................................................................................................... 69

Figure 2-75 RK3568 SARADC module ................................................................................................................. 70

RK3568 Hardware Design Guide Rev V1.2

Figure 2-76 The button circuit using SARADC sampling ...................................................................................... 70

Figure 2-77 RK3568 OTP power pin...................................................................................................................... 71

Figure 2-78 Multiplexing relationship between MULTI_PHY0/1and USB3.0 controllers .................................... 71

Figure 2-79 USB3.0 OTG0 pin .............................................................................................................................. 72

Figure 2-80 USB3.0 HOST1 pin ............................................................................................................................ 73

Figure 2-81 USB2.0 HOST2 pin ............................................................................................................................ 73

Figure 2-82 USB2.0 HOST3 pin ............................................................................................................................ 74

Figure 2-83 RK3568 VBUSDET and ID Circuit .................................................................................................... 75

Figure 2-84 USB2.0 PHY power supply magnetic bead isolation circuit .............................................................. 75

Figure 2-85 USB2.0 signal is connected in series with a 2.2ohm resistor .............................................................. 76

Figure 2-86 USB2.0 signal is connected in series with common mode choke circuit ............................................ 76

Figure 2-87 USB OTG ID pin circuit ..................................................................................................................... 76

Figure 2-88 USB 5V current-limiting circuit.......................................................................................................... 77

Figure 2-89 USB3.0 ESD circuit ............................................................................................................................ 77

Figure 2-90 MULTI PHY power supply decoupling circuit ................................................................................... 77

Figure 2-91 MULTI_PHY0/1/2 and SATA3.0 controller multiplexing relationship .............................................. 78

Figure 2-92 SATA0/1/2 related control IO pins ...................................................................................................... 80

Figure 2-93 The paths of GMAC0, GMAC1, QSGMII/SGMII PCS and QSGMII/SGMII PHY .......................... 82

Figure 2-94 The application block diagram of QSGMII-MULTI_PHY1Y1 .......................................................... 82

Figure 2-95 The application block diagram of QSGMII-MULTI_PHY2 ............................................................... 83

Figure 2-96 The application block diagram of GMAC0-SGMII-MULTI_PHY1 .................................................. 84

Figure 2-97 The application block diagram of GMAC1-SGMII-MULTI_PHY1 .................................................. 84

Figure 2-98 The application block diagram of GMAC0-SGMII-MULTI_PHY2 .................................................. 85

Figure 2-99 The application block diagram of GMAC1-SGMII-MULTI_PHY2 .................................................. 86

Figure 2-100 PCIe3.0 controller/PCIe3.0 PHY block diagram .............................................................................. 89

Figure 2-101 Reference clock paths in RK3568 PCIe3.0 x2 Lane RC mode ......................................................... 90

Figure 2-102 Reference clock paths in RK3568 PCIe3.0 x2 Lane EP mode .......................................................... 90

Figure 2-103 The reference clock paths in RK3568 PCIe3.0 x1 Lane RC mode + PCIe3.0 x1 Lane RC mode .... 91

Figure 2-104 PCIe3.0 PHY power decoupling capacitors ...................................................................................... 91

Figure 2-105 PCIe3.0 PHY RESREF pin ............................................................................................................... 91

Figure 2-106 RK3568 MIPI CSI RX signal pins .................................................................................................... 93

Figure 2-107 RK3568 MIPI CSI working mode and data, clock allocation ........................................................... 94

Figure 2-108 MIPI CSI PHY power circuit isolated with magnetic beads ............................................................. 94

Figure 2-109 MIPI CSI RX PHY power decoupling capacitors ............................................................................. 94

Figure 2-110 RK3568 CIF functional pins ............................................................................................................. 95

Figure 2-111 RK3568 Relationship between data of CIF ....................................................................................... 96

Figure 2-112 RK3568 the output path diagram of VOP and video interface .......................................................... 98

Figure 2-113 RK3568 HDMI2.0 TX PHY TMDS pins .......................................................................................... 99

Figure 2-114 RK3568 HDMI2.0 TX PHY power supply decoupling capacitances ............................................... 99

Figure 2-115 RK3568 HDMI2.0 TX PHY REXT pins........................................................................................... 99

RK3568 Hardware Design Guide Rev V1.2

Figure 2-116 RK3568 HDMI2.0 TX PHY HPD pins ............................................................................................. 99

Figure 2-117 RK3568 HDMI2.0 TX PHY HPD circuit ....................................................................................... 100

Figure 2-118 HDMI CEC protocol requirements ................................................................................................. 100

Figure 2-119 HDMI CEC CEC isolating circuit ................................................................................................... 100

Figure 2-120 HDMI DDC level conversion circuit .............................................................................................. 101

Figure 2-121 ESD circuit of HDMI connector ..................................................................................................... 102

Figure 2-122 RK3568 MIPI DSI TX0/LVDS TX Combo PHY pins ................................................................... 103

Figure 2-123 Magnetic bead isolation circuit of MIPI DSI PHY power supply ................................................... 103

Figure 2-124 RK3568 MIPI DSI TX0/LVDS TX Combo PHY power decoupling capacitors ............................ 103

Figure 2-125 RK3568 MIPI DSI TX1 PHY pins.................................................................................................. 104

Figure 2-126 Magnetic bead isolation circuit of MIPI DSI TX1 PHY power supply .......................................... 105

Figure 2-127 RK3568 MIPI DSI TX1 PHY power decoupling capacitors .......................................................... 105

Figure 2-128 RK3568 eDP TX PHY pins ............................................................................................................. 106

Figure 2-129 Figure 2–129 RK3568 eDP TX PHY power decoupling capacitors ............................................... 106

Figure 2-130 RK3568 eDP TX signal AC decoupling capacitors ........................................................................ 106

Figure 2-131 RK3568 eDP AUX signal AC decoupling capacitors ..................................................................... 107

Figure 2-132 RK3568 LCDC functional pins ....................................................................................................... 109

Figure 2-133 The decoupling capacitors of RK3568 VCCIO5 power supply ...................................................... 110

Figure 2-134 RK3568 VOP BT1120 functional pins ............................................................................................ 111

Figure 2-135 RK3568 VOP BT656 M0 functional pins ....................................................................................... 113

Figure 2-136 RK3568 VOP BT656 M1 functional pins ....................................................................................... 114

Figure 2-137 RK3568 EBC functional pins ......................................................................................................... 116

Figure 2-138 The decoupling capacitors of RK3568 VCCIO6 power supply ...................................................... 116

Figure 2-139 Connection diagram of RK3568 I2S in Master mode ..................................................................... 120

Figure 2-140 Connection diagram of RK3568 I2S in Slave mode ....................................................................... 120

Figure 2-141 RK3568 I2S1 M0 functional pins ................................................................................................... 121

Figure 2-142 RK3568 I2S1 M1 functional pins ................................................................................................... 121

Figure 2-143 RK3568 I2S1 M2 functional pins ................................................................................................... 122

Figure 2-144 RK3568 I2S2 M0 functional pins ................................................................................................... 124

Figure 2-145 RK3568 I2S2 M1 functional pins ................................................................................................... 124

Figure 2-146 RK3568 I2S3 M0 functional pins ................................................................................................... 126

Figure 2-147 RK3568 I2S3 M1 functional pins ................................................................................................... 126

Figure 2-148 RK3568 PDM M0 functional pins .................................................................................................. 127

Figure 2-149 RK3568 PDM M1 functional pins .................................................................................................. 128

Figure 2-150 RK3568 PDM M2 functional pins .................................................................................................. 128

Figure 2-151 Process mode of related pins when RK809-5 Codec module is not used ....................................... 130

Figure 2-152 RK809-5 Codec module.................................................................................................................. 131

Figure 2-153 RK809 Codec output earphone circuit ............................................................................................ 132

Figure 2-154 RK809-5 SPK/HP power supply pins ............................................................................................. 132

Figure 2-155 RK809-5 SPK output circuit ........................................................................................................... 132

RK3568 Hardware Design Guide Rev V1.2

Figure 2-156 External SPK circuit ....................................................................................................................... 133

Figure 2-157 Electret MIC differential input circuit ............................................................................................. 133

Figure 2-158 Four-segment headset with MIC single-ended input circuit ........................................................... 134

Figure 2-159 Electret MIC single-ended input circuit .......................................................................................... 134

Figure 2-160 RK809-5 MIC input circuit pins ..................................................................................................... 134

Figure 2-161 Array MIC solution I2S/PDM connection diagram 1 ..................................................................... 136

Figure 2-162 Array MIC solution I2S/PDM connection diagram 2 ..................................................................... 136

Figure 2-163 Path block diagram of RK3568 GMAC0, GMAC1 reused with IO ............................................... 137

Figure 2-164 RK3568 GMAC0 functional pins ................................................................................................... 137

Figure 2-165 RK3568 GMAC1 M0 functional pins ............................................................................................. 138

Figure 2-166 RK3568 GMAC1 M1 functional pins ............................................................................................. 138

Figure 2-167 RGMII connection example 1 ......................................................................................................... 140

Figure 2-168 RGMII connection example 2 ......................................................................................................... 141

Figure 2-169 RMII connection example 1 ............................................................................................................ 141

Figure 2-170 RMII connection example 2 ............................................................................................................ 142

Figure 2-171 RMII connection example 3 ............................................................................................................ 142

Figure 2-172 RMII connection example 4 ............................................................................................................ 143

Figure 2-173 RMII connection example 5 ............................................................................................................ 143

Figure 2-174 IR receiver circuit............................................................................................................................ 150

Figure 3-1 Six layers PCB design ......................................................................................................................... 152

Figure 3-2 Four layers PCB design....................................................................................................................... 152

Figure 3-3 RK3568 Fan-out diagram 1 ................................................................................................................. 153

Figure 3-4 RK3568 Fan-out diagram 2 ................................................................................................................. 154

Figure 3-5 RK3568 Fan-out diagram 3 ................................................................................................................. 154

Figure 3-6 RK3568 Fan-out diagram 4 ................................................................................................................. 155

Figure 3-7 A diagram of space between signals.................................................................................................... 155

Figure 3-8 A diagram of equal length within and between differential pairs ........................................................ 156

Figure 3-9 A diagram of differential pair length compensation requirements ...................................................... 156

Figure 3-10 Stitching vias requirement diagram .................................................................................................. 156

Figure 3-11 Edge requirement of signal reference plane diagram ........................................................................ 157

Figure 3-12 RK3568 Crystal layout and routing .................................................................................................. 157

Figure 3-13 RK809-5 BUCK1/BUCK2 Layout and routing ................................................................................ 159

Figure 3-14 RK809-5 BUCK3 Layout and routing .............................................................................................. 159

Figure 3-15 RK809-5 BUCK4 Layout and routing .............................................................................................. 160

Figure 3-16 RK809-5 BUCK5 Layout and routing .............................................................................................. 161

Figure 3-17 RK809-5 EPAD vias layout .............................................................................................................. 162

Figure 3-18 Discrete power supply DC/DC layout and routing ........................................................................... 162

Figure 3-19 VDD_CPU Power supply DC/DC layout and tracing....................................................................... 163

Figure 3-20 A diagram of DC/DC remote feedback design .................................................................................. 164

Figure 3-21 RK3568 VDD_CPU Power pin routing and vias .............................................................................. 165

RK3568 Hardware Design Guide Rev V1.2

Figure 3-22 Placement of decoupling capacitors on the back of RK3568 VDD_CPU power pins ...................... 165

Figure 3-23 Copper-covering on RK3568 VDD_CPU power layer ..................................................................... 166

Figure 3-24 RK3568 VDD_LOGIC power supply pin routing and vias .............................................................. 167

Figure 3-25 Placement of decoupling capacitors on the back of RK3568 VDD_LOGIC power pins ................. 167

Figure 3-26 Copper-covering on RK3568 VDD_LOGIC power layer ................................................................ 168

Figure 3-27 RK3568 VDD_GPU Power pin traces and vias ................................................................................ 169

Figure 3-28 Placement of decoupling capacitors on the back of RK3568 VDD_GPU power pins ...................... 169

Figure 3-29 Copper covering on RK3568 VDD_GPU power layer ..................................................................... 170

Figure 3-30 RK3568 VDD_NPU Power pin routing and vias .............................................................................. 171

Figure 3-31 Placement of decoupling capacitors on the back of VDD_NPU power ............................................ 171

Figure 3-32 Copper covering on RK3568 VDD_NPU power layer ..................................................................... 172

Figure 3-33 RK3568 VCC_DDR power pin routing and vias .............................................................................. 173

Figure 3-34 RK3568 VCC_DDR/VCC0V6_DDR Power pin routing and vias in LPDDR4x mode ................... 173

Figure 3-35 Placement of decoupling capacitor on the back of the power supply pin of RK3568 VCC_DDR ... 174 Figure 3-36 Placement of decoupling capacitors on the back of the power supply pins of

VCC_DDR/VCC0V6_DDR of RK3568 in LPDDR4x mode ...................................................................... 174

Figure 3-37 Copper covering on RK3568 VCC_DDR power layer ..................................................................... 175

Figure 3-38 RK3568 VSS pin routing and vias .................................................................................................... 176

Figure 3-39 Ground copper-covering of RK3568 ................................................................................................ 176

Figure 3-40 DDR3/DDR3L DQS/DQ/DM signal routing topology ..................................................................... 178

Figure 3-41 DDR3/DDR3L CLK signal routing topology ................................................................................... 179

Figure 3-42 DDR3/DDR3L CLK signal RC circuit ............................................................................................. 179

Figure 3-43 DDR3/DDR3L CSn/CKE/ODT signal routing topology .................................................................. 180

Figure 3-44 Other CA/CMD signal of DDR3/DDR3L routing topology except CSn/CKE/ODT ....................... 181

Figure 3-45 DDR3/DDR3L+ECC DQS/DQ/DM signal routing topology ........................................................... 181

Figure 3-46 DDR3/DDR3L+ECC CLK signal routing topology ......................................................................... 182

Figure 3-47 DDR3/DDR3L+ECC CSn/CKE/ODT signal routing topology ........................................................ 183

Figure 3-48 DDR3/DDR3L+ECC other CA/CMD signal routing topology except CSn/CKE/ODT ................... 184

Figure 3-49 DDR4 DQS/DQ/DM signal routing topology ................................................................................... 185

Figure 3-50 DDR4 CLK signal routing topology ................................................................................................. 187

Figure 3-51 RC circuit for DDR4 CLK signal ..................................................................................................... 187

Figure 3-52 CLK/CA/CMD signal routing diagram on the L3 plane of DDR4 4-layer board ............................. 188

Figure 3-53 DDR4 CSn/CKE/ODT signal routing topology ................................................................................ 188

Figure 3-54 Other CA /CMD signal routing topologies except CSN/CKE/ODT when using DDR4 .................. 189

Figure 3-55 DDR4+ECC DQS/DQ/DM signal routing topology ......................................................................... 189

Figure 3-56 DDR4+ECC CLK signal routing topology ....................................................................................... 190

Figure 3-57 DDR4+ECC CSn/CKE/ODT signal routing topology ...................................................................... 191

Figure 3-58 DDR4+ECC other CA/CMD signal routing topology except CSn/CKE/ODT ................................ 192

Figure 3-59 Branch resistances of eMMC and Nand Flash compatible design .................................................... 197

Figure 3-60 Branch resistor layout and routing of eMMC and NAND flash compatible design ......................... 198

RK3568 Hardware Design Guide Rev V1.2

Figure 3-61Figure 3–61 DATA routing of eMMC and Nand Flash compatible design ........................................ 198

Figure 3-62 Schematic diagram of empty space below the pad of USB3 connector and the pad of AC coupling

capacitor........................................................................................................................................................ 202

Figure 3-63 PCB fiberweave effect to improve routing way ................................................................................ 202

Figure 3-64 Schematic diagram of empty space below the pad of SATA connector and the pad of AC coupling

capacitor........................................................................................................................................................ 203

Figure 3-65 Schematic diagram of empty space below the pad of PCIe Slot and the pad of AC coupling capacitor

...................................................................................................................................................................... 205

Figure 3-66 Schematic diagram of empty space below the pad of HDMI connector and the pad of TVS diode . 211

Figure 3-67 RK809-5 HP_SNS resistor layout and routing ................................................................................. 213

Figure 3-68 RK809-5 HPL/HPR/HP_SNS routing .............................................................................................. 213

Figure 3-69 Schematic diagram of prohibited routing area for RJ45 interface and network transformer ............ 217

Figure 3-70 Schematic diagram of RJ45 interface and network transformer slotting .......................................... 217

Figure 3-71 Schematic diagram of inductance and capacitance of the WIFI module routing .............................. 218

Figure 3-72 Schematic diagram of WIFI module antenna routing ....................................................................... 219

Figure 4-1 θJA definition ....................................................................................................................................... 222

Figure 4-2 θ

definition ........................................................................................................................................ 222

Figure 4-3 θJB definition ....................................................................................................................................... 222

Figure 6-1 Reflow soldering profile classification ............................................................................................... 230

Figure 6-2 Heat resistance of lead-free process device packages standard .......................................................... 230

Figure 6-3 Lead-free reflow profile ...................................................................................................................... 230

Figure 6-4 Lead-free reflow soldering process recommended profile parameters ............................................... 231

Figure 7-1 Chipset dry vacuum package .............................................................................................................. 233

Figure 7-2 Six-point humidity card ...................................................................................................................... 233

RK3568 Hardware Design Guide Rev V1.2

Tables

Table 2–1 RK3568 24MHz clock requirements ....................................................................................................... 4

Table 2–2 RK3568 32.768KHz clock requirements ................................................................................................. 5

Table 2–3 RK3568 System initialization configuration signal description ............................................................ 10

Table 2–4 RK3568 JTAG debug interface signal ................................................................................................... 10

Table 2–5 RK3568 DDR PHY I/O map.................................................................................................................. 12

Table 2–6 RK3568 eMMC interface design ........................................................................................................... 26

Table 2–7 RK3568 FSPI interface design ............................................................................................................... 29

Table 2–8 RK3568 Nand Flash interface design .................................................................................................... 31

Table 2–9 RK3568 GPIO power pins description .................................................................................................. 33

Table 2–10 RK3568 power supply requirements .................................................................................................... 36

Table 2–11 RK3568 power supply requirement of each module for the first powered on ..................................... 37

Table 2–12 RK3568 standby power supply requirements ...................................................................................... 38

Table 2–13 RK3568 internal PLL Introduction ...................................................................................................... 39

Table 2–14 RK3568 peak current table .................................................................................................................. 63

Table 2–15 SDMMC0 interface design .................................................................................................................. 65

Table 2–16 SDMMC1 interface design .................................................................................................................. 66

Table 2–17 SDMMC2 interface design .................................................................................................................. 68

Table 2–18 RK3568 USB2.0/USB3.0 interface design .......................................................................................... 78

Table 2–19 RK3568 SATA interface design ........................................................................................................... 81

Table 2–20 RK3568 QSGMII/SGMII interface design .......................................................................................... 87

Table 2–21 RK3568 PCIe2.0 interface design ........................................................................................................ 89

Table 2–22 RK3568 PCIe3.0 interface design ........................................................................................................ 92

Table 2–23 RK3568 MIPI CSI RX interface design............................................................................................... 94

Table 2–24 RK3568 Data relationship in BT1120 16bit mode ............................................................................... 96

Table 2–25 RK3568 CIF interface design .............................................................................................................. 97

Table 2–26 RK3568 HDMI2.0 TX interface design ............................................................................................. 102

Table 2–27 RK3568 MIPI DSI TX0 and LVDS TX Combo PHY interfaces design............................................ 104

Table 2–28 RK3568 MIPI DSI TX1 PHY interface design .................................................................................. 105

Table 2–29 RK3568 eDP TX PHY interface design ............................................................................................. 107

Table 2–30 RK3568 parallel RGB interface formats ............................................................................................ 108

Table 2–31 RK3568 parallel RGB interface design ............................................................................................. 110

Table 2–32 RK3568 BT1120 output formats ........................................................................................................ 111

Table 2–33 RK3568 BT1120 output interface design........................................................................................... 112

Table 2–34 RK3568 BT656 output interface design ............................................................................................ 115

Table 2–35 RK3568 EBC output interface design ................................................................................................ 117

Table 2–36 RK3568 I2S1 interface design ........................................................................................................... 123

Table 2–37 RK3568 I2S2 interface design ........................................................................................................... 125

Table 2–38 RK3568 I2S3 interface design ........................................................................................................... 127

RK3568 Hardware Design Guide Rev V1.2

Table 2–39 RK3568 PDM interface design .......................................................................................................... 129

Table 2–40 RK3568 SPDIF interface design ....................................................................................................... 130

Table 2–41 RK3568 matching relationship between audio applications and the circuit diagram ........................ 135

Table 2–42 RK3568 RGMII/RMII interface design ............................................................................................. 139

Table 2–43 RK3568 UART interface distribution................................................................................................ 145

Table 2–44 RK3568 UART interface design ....................................................................................................... 145

Table 2–45 RK3568 SPI interface distribution ..................................................................................................... 146

Table 2–46 RK3568 SPI interface design ............................................................................................................. 146

Table 2–47 RK3568 CAN interface distribution .................................................................................................. 147

Table 2–48 RK3568 CAN interface design .......................................................................................................... 147

Table 2–49 RK3568 I2C interface distribution .................................................................................................... 148

Table 2–50 RK3568 I2C interface design ............................................................................................................ 148

Table 2–51 RK3568 PWM interface distribution ................................................................................................. 149

Table 3–1 DDR3/DDR3L DQS/DQ/DM signal impedance and routing requirements ........................................ 179

Table 3–2 DDR3/DDR3L CLK signal impedance and routing requirements ...................................................... 180

Table 3–3 DDR3/DDR3L CSn/CKE/ODT signal impedance and routing requirements ..................................... 180

Table 3–4 Other CA/CMD signal of DDR3/DDR3L routing topology except CSn/CKE/ODT .......................... 181

Table 3–5 DDR3/DDR3L+ECC DQS/DQ/DM signal impedance and routing requirements .............................. 182

Table 3–6 DDR3/DDR3L+ECC CLK signal impedance and routing requirements ............................................ 183

Table 3–7 DDR3/DDR3L+ECC CSn/CKE/ODT signal impedance and routing requirements ........................... 183

Table 3–8 DDR3/DDR3L+ECC other CA/CMD signal impedance and routing requirements except

CSn/CKE/ODT ............................................................................................................................................. 184

Table 3–9 LPDDR3 signal impedance and routing requirements ......................................................................... 184

Table 3–10 DDR4 DQS/DQ/DM signal impedance and routing requirements .................................................... 185

Table 3–11 DDR4 CLK signal impedance and routing requirements .................................................................. 187

Table 3–12 DDR4 CSn/CKE/ODT signal impedance and routing requirements ................................................. 188

Table 3–13 Other CA /CMD signal routing topologies except CSN/CKE/ODT when using DDR4 ................... 189

Table 3–14 DDR4+ECC DQS/DQ/DM signal impedance and routing requirements .......................................... 190

Table 3–15 DDR4+ECC CLK signal impedance and routing requirements ........................................................ 191

Table 3–16 DDR4+ECC CSn/CKE/ODT signal impedance and routing requirements ....................................... 191

Table 3–17 DDR4+ECC other CA/CMD signal impedance and routing requirements except CSn/CKE/ODT .. 192

Table 3–18 LPDDR4 signal impedance and routing requirements ....................................................................... 192

Table 3–19 LPDDR4 signal impedance and routing requirements ....................................................................... 193

Table 3–20 eMMC signal impedance and routing requirements .......................................................................... 194

Table 3–21 FSPI signal impedance and routing requirements .............................................................................. 195

Table 3–22 Nand Flash signal impedance and routing requirements ................................................................... 196

Table 3–23 SDMMC0/1/2 signal impedance and routing requirements ............................................................... 199

Table 3–24 USB2.0 signal impedance and routing requirements ......................................................................... 200

Table 3–25 USB3.0 signal impedance and routing requirements ......................................................................... 201

Table 3–26 SATA3.0 signal impedance and routing requirements ....................................................................... 202

RK3568 Hardware Design Guide Rev V1.2

Table 3–27 QSGMII/SGMII signal impedance and routing requirements ........................................................... 203

Table 3–28 PCIe2.0 signal impedance and routing requirements ......................................................................... 204

Table 3–29 PCIe3.0 signal impedance and routing requirements ......................................................................... 206

Table 3–30 MIPI CSI RX signal impedance and routing requirements................................................................ 207

Table 3–31 CIF signal impedance and routing requirements ............................................................................... 208

Table 3–32 MIPI DSI TX signal impedance and routing requirements ................................................................ 208

Table 3–33 LVDS TX signal impedance and routing requirements ..................................................................... 209

Table 3–34 eDP TX signal impedance and routing requirements ......................................................................... 210

Table 3–35 HDMI TX signal impedance and routing requirements ..................................................................... 210

Table 3–36 RGB TX signal impedance and routing requirements ....................................................................... 211

Table 3–37 BT1120 TX signal impedance and routing requirements................................................................... 212

Table 3–38 RGMII signal impedance and routing requirements .......................................................................... 214

Table 3–39 RMII signal impedance and routing requirements ............................................................................. 215

Table 4–1 RK3568 thermal resistance simulation report results .......................................................................... 221

Table 4–2 RK3568 PCB structure used for thermal resistance simulation ........................................................... 221

Table 7–1 Moisture Sensitivity Levels (MSL) ...................................................................................................... 234

Table 7–2 RV11XX chipset Re-bake reference table............................................................................................ 234

RK3568 Hardware Design Guide Rev V1.2

1 System Introduction

1.1 Overview

RK3568 is a low-power and high-performance processor designed for personal mobile Internet devices and AIoT devices.

RK3568 provides many powerful embedded hardware engines to optimize the performance of advanced

applications. RK3568 supports almost all formats of H.264 4k@60fps decoding, and supports H.265 4k@60fps

decoding, H.264/ H.265 1080p@60fps encoding, and high-quality JPEG encoding/decoding.

RK3568 embedded 3D GPU is fully compatible with OpenGL ES 1.1/2.0/3.2, OpenCL 2.0 and Vulkan 1.1;

the special 2D hardware engine maximizes the display performance and provides a smooth operating experience

also.

The built-in NPU supports INT8/INT16 mixed operation. Due to strong compatibility, network models based on a series of frameworks such as TensorFlow/MXNet/PyTorch/Caffe can be easily converted.

There are high-performance external memory interfaces in RK3568 to ensure high-capacity and high-stability system operating memory bandwidth, and it supports multiple memory models such as DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, LPDDR4X, etc.

1.2 Block Diagram

Figure 1-1 RK3568 block diagram

RK3568 Hardware Design Guide Rev V1.2

1.3 Application Block Diagram

RK3568 EVB Application Block Diagram

Figure 1-2 RK3568 EVB application block diagram

RK3568 Hardware Design Guide Rev V1.2

RK3568 Smart NVR Application Block Diagram

Figure 1-3 RK3568 Smart NVR application block diagram

The figures above are example application block diagrams of RK3568, please refer to the reference design

schematic released by RK for more details.

RK3568 Hardware Design Guide Rev V1.2

2 Schematic Design Recommendation

2.1 Minimum System Design

Clock Circuit

 The oscillator circuit inside RK3568 and the external 24MHz crystal form the system clock, as shown in

Figure 2-1.

 The 22ohm resistor connected to the XOUT24M network in series must be added to limit current and

prevent overdrive.

 The 1M ohm resistor between XOUT24M and XIN24M network cannot be modified at will.

Figure 2-1 RK3568 Crystal circuit and components parameters

Note

The load capacitances of crystal should be selected according to the CL capacitance value of the crystal actually used, and the

frequency tolerance at room temperature should be controlled within 20ppm.

18pF is the capacitance value of the crystal selected by RK, not a general value, and COG or NPO material are recommended. It is recommended to use 4Pin SMT crystal, with 2 GND pins fully connected with the ground of the PCB to enhance ESD

anti-interference ability

 The system clock can also be directly generated by an external active crystal circuit with a clock

amplitude of 1.8V. When working, the clock is input through the XIN24M pin, and the XOUT24M pin

can be floated. The clock parameters are shown in the following Table 2-1:

Table 2–1 RK3568 24MHz clock requirements

Parameters

Spec

Description

Min.

Max.

Unit

Frequency

24.000000

MHz

Frequency tolerance

+/-20

ppm

Clock amplitude

1.8

Peak-to-peak

Operating temperature

-20

℃

ESR / 40

Ohm

RK3568 Hardware Design Guide Rev V1.2

 When RK3568 is in standby, you can choose to switch the working clock source to the clock provided by

the PMU_PVTM module or an external 32.768KHz clock. Turn off the OSC oscillator circuit to get

better standby power consumption. At this time, only the IO interrupt in the PMUIO1 and PMUIO2

power domain are supported to wake up. If the required wake-up source is related to the 24MHz clock, the 24MHz clock cannot be turned off.

 The clock oscillation loop integrated in PVTM (Process-Voltage-Temperature Monitor) module can

generate a clock, its frequency is determined by the delay unit of the clock oscillation loop circuit. The

generated clock can be used as a clock source for the chip in standby; the external clock 32.768KHz will

reach optimal chip standby power consumption when RK3568 chip in sleeps, and the PVTM module can

also be turned off at this time.

 The external 32.768KHz clock can be obtained from PMIC or external RTC clock source. The

32.768KHz clock input pin of RK3568 is shown in the figure below:

Figure 2-2 RK3568 the 32.768KHz clock input pin in standby

 The external 32.768kHz RTC clock parameters are shown in Table 2-2 below

Table 2–2 RK3568 32.768KHz clock requirements

Parameters

Spec

Description

Min.

Max.

Unit

Frequency

32.768000

kHz

Frequency

tolerance

+/-30

ppm

Clock amplitude

0.65*VDD

VDD+0.3V

VDD:PMUIO2 voltage

Operating

temperature

-20

℃

Duty Ratio

Note

When using this function, the IOMUX pin must be set to CLK32K_IN function, and the input amplitude must meet the power

supply requirements of PMUIO2 Domain.

 RK3568 can provide working clocks to peripherals:

 REFCLK_OUT: 24MHz clock output as default, which can be provided to Camera and other devices

as working clock

 CLK32K_OUT0: 32.768KHz clock output, which can be provided to WIFI, BT, PCIe and other

devices as sleep or working clock

 CLK32K_OUT1: 32.768KHz clock output, which can be provided to WIFI, BT, PCIe and other

devices as sleep or working clock

RK3568 Hardware Design Guide Rev V1.2

 ETH0_REFCLKO_25M: 25MHz clock output, which can be provided to Ethernet PHY and other

devices as working clock

 ETH1_REFCLKO_25M_M0/ETH1_REFCLKO_25M_M1: 25MHz clock output, which can be

provided to Ethernet PHY and other devices as working clock

 CIF_CLKOUT: 24MHz clock output by default, other frequency value can be obtained according to

PLL frequency division, which can be provided to Camera and other devices as working clock

 CAM_CLKOUT0: 24MHz clock output by default, other frequency points can be obtained

according to PLL frequency division, which can be provided to Camera and other devices as

working clock

 CAM_CLKOUT1: 24MHz clock output by default, other frequency value can be obtained according

to PLL frequency division, which can be provided to Camera and other devices as working clock

Note

The IO Domains where the above clocks are located must match the IO level of connected peripherals. If they do not match, a

level conversion circuit must be added.

Please evaluate whether they can meet the clock requirements of the peripheral device.

Reset/watchdog/TSADC Circuit

The hardware reset signal of RK3568 is input through Pin AH27 (NPOR_u), which must be controlled

externally and is active at low level. In order to ensure the stability and normal operation of the chip, the minimum

reset time required is 100 cycles of the 24MHz main clock, that is, at least 4us or more.

Pin AH27 (NPOR_u) has to add a 100nF capacitor to eliminate jitter of the reset signal, enhance

anti-interference ability, and prevent abnormal system reset caused by false triggering.

The pull-up power of the RESETn network must be consistent with the IO domain (PMUIO1) where the

nPOR pin is located.

Figure 2-3 RK3568 reset input (RK809-5 solution)

RK3568 Hardware Design Guide Rev V1.2

 When using a discrete power solution, the reset signal circuit diagram is as follows:

Figure 2-4 RK3568 reset input (discrete power solution)

Note: The reset IC must be with open-drain output, and low level active.

 The RK3568 chip integrates a Watchdog Timer. When a reset signal is generated, a low level will be

output through TSADC_SHUT_M0 or TSADC_SHUT_M1 pin, and then resets RK3568 by hardware.

 The RK3568 chip integrates two TSADC (Temperature-Sensor ADC) modules. When the temperature

inside the chip exceeds the threshold, the internal TSHUT signal can be passed to the CRU module and

reset RK3568 chip, or it can output low level through TSADC_SHUT_M0 or TSADC_SHUT_M1 pin to

reset RK3568 by hardware. As shown in the figure above, the TSADC_SHUT_M0 network is connected

to the RESETn network.

 RK3568 reset signal path diagram is as follows:

Figure 2-5 RK3568 the path of reset signal

 When the RESETB pin of RK809-5 is powered on for the first time, after all power supplies are powered

on, RESETB will change from low level to high level (open drain output) after delaying the set time, to

complete the power-on reset process; when RK809-5 is in working or sleep mode, if the RESETB pin is pulled low, RK809-5 will also be restarted. The restart power-on sequence is the same as the first time power-on.

PMU Circuit

In order to meet the requirement of low power consumption products, RK3568 has designed a power

management unit (PMU) to control and manage the internal power supply of the chip.

This module supports registers inside chip or PMUIO power domain IO control peripheral power circuit,

RK3568 Hardware Design Guide Rev V1.2

realize power on and power off to other functional modules, and also support IO interrupt wake-up, so as to realize the chip's standby and wake-up functions.

System Boot Sequence

The RK3568 chip supports multiple booting ways. After chip reset, the boot code integrated inside the chip

will automatically boot in the following sequence:

 Serial Nor Flash (FSPI)  Serial Nand Flash (FSPI)  Nand Flash  eMMC  SDMMC0 Card

If there is no boot code in the above devices, you can download the system code to these devices through the

USB3_OTG0_DP/USB3_OTG0_DM signal of the USB3.0 OTG0 interface.

System Initialization Configuration Signal

There are two important signals in RK3568 will affect the system boot configuration, which need to be

configured and kept stable before power-on. They are:

 FLASH_VOL_SEL pin (Pin AG25): hardware configuration VCCIO2 power domain IO driver voltage  SDMMC0_DET pin (Pin Y22): determine whether VCCIO3 power domain IO is SDMMC0 or JTAG

function

After the system reset, the chip will configure the default power-on function of the corresponding module

according to the input level of the two pins

 The IO drive voltage mode of RK3568 VCCIO2 power domain is configured by hardware by default.

Because it belongs to FLASH power domain, it’s used during system boots. Therefore, when the system

is booting, the IO drive voltage mode must be set through the hardware configuration first instead of

setting by register operation, as shown below:

 When VCCIO2 voltage is connected to 1.8V, FLASH_VOL_SEL must be high;  When VCCIO2 voltage is connected to 3.3V, FLASH_VOL_SEL must be low;  If the IO power supply is changed, the FLASH_VOL_SEL pin must be changed synchronously, they

cannot be mismatch, otherwise the function will be abnormal or the chip may even be damaged.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-6 RK3568 VCIO2 power supply and FLASH_VOL_SEL

 The ARM JTAG function of RK3568 is reused with the SDMMC0 function, and the IOMUX function is

switched through the SDMMC0_DET pin. Therefore, you have to finish configuration operate of this pin

before power-on, otherwise the ARM JTAG function has no output that will affect the debugging during booting, no output from SDMMC0 will affect the boot function of SDMMC0.

Figure 2-7 RK3568 SDMMC0/ARM JTAG multiplexed pins and SDMMC0 DET pin

If this pin is detected as high level, the corresponding IO will be switched to ARM JTAG function;

When it is detected as low level (If there is no special requirement, most SD card insertion will pull down this

RK3568 Hardware Design Guide Rev V1.2

pin), the corresponding IO is switched to the SDMMC0 function.

After the system is up, it can be switched to register to control IOMUX, then the pin can be released. In order to query easily, the configuration status and function of the two pins are shown as follows:

Table 2–3 RK3568 System initialization configuration signal description

Signal name

Internal up and

down

Description

FLASH_VOL_SEL

Pull up

IO drive voltage mode of FLASH VCCIO2 power domain: 0: IO level mode is 3.3V; 1: IO level mode is 1.8V

SDMMC0_DET

Pull up

SDMMC0/ARM JATG pin multiplexing selection control signal:

0: Recognized as SD card insertion, SDMMC0/ARM JATG pins

are multiplexed as SDMMC0 function;

1: Not recognized as SD card insertion, SDMMC0/ARM JATG

pins are multiplexed as ARM JTAG function (Default)

JTAG and UART Debug Circuit

The ARM JTAG interface of RK3568 conforms to the IEEE1149.1 standard. The PC can be connected to the

DSTREAM emulator through SWD mode (two-wire mode) to debug ARM Core inside the chip.

When connecting to emulator during booting, you need to ensure that the SDMMC0_DET pin is at a high

level, otherwise the JTAG debugging mode cannot be entered. The management configuration is described in the

previous sections.

After the system is up, it will switch to control IOMUX by register. The ARM JTAG interface introduction is

shown in the following Table:

Table 2–4 RK3568 JTAG debug interface signal

Signal name

Description

ARM_JTAG_TCK

Clock input in SWD mode

ARM_JTAG_TMS

Data input and output in SWD mode

The connection way of JTAG and the definition of standard connector pins are shown in the figure below:

Figure 2-8 RK3568 JTAG connection schematic

RK3568 Hardware Design Guide Rev V1.2

 If there is no SD Card function, it is recommended to reserve the ARM JTAG function to facilitate debug.

The reserved circuit is as shown in the figure below:

Note that the VCCIO3 power supply must be powered, and the power supply voltage could be VCCIO_SD or

VCC_3V3

Figure 2-9 RK3568 ARM JTAG pin

 The MCU_JTAG module of RK3568 is temporarily not released, no special processing is required.  The UART2_RX_M0/UART2_TX_M0 is used for RK3568 UART Debug by default, with default baud

rate 1500000M.

Figure 2-10 RK3568 UART2 M0 pin

The 100ohm resistor connected in series with UART2_RX_M0/UART2_TX_M0 shall not be deleted, and

TVS tube shall be added to strengthen the anti-static surge capability and prevent the chip pins from being damaged

during the development process. It is recommended to reserve 2.54 pins as much as possible. If conditions are not

allowed, it is recommended to use test points above 0.7mm or larger to facilitate soldering.

Figure 2-11 RK3568 Debug UART2 Connection diagram

RK3568 Hardware Design Guide Rev V1.2

DDR Circuit

2.1.7.1 DDR Controller Introduction

The RK3568 DDR controller interface supports JEDEC SDRAM standard interface with following features:

 Support DDR3/DDR3L/LPDDR3/DDR4/LPDDR4/LPDDR4X, etc.  Support 32-bits data bus width, 2 ranks (chip selects), totally 8GB (max) address;  Support Power Down, Self-Refresh and other modes;  Compensate the PCB delay through software;  For DDR3/DDR3L/DDR4, support 8 bits ECC;  Programmable output and ODT impedance with dynamic PVT compensation.

2.1.7.2 Circuit Design Suggestion

The schematic of RK3568 DDR PHY and each DRAM need to be consistent with the reference design

diagram, including power supply decoupling capacitors.

RK3568 supports DDR3/DDR3L, LPDDR3, DDR4 or LPDDR4/LPDDR4X. These DRAM have different I/O

signals. Choose the signal according to the DRAM type. The RK3568 DDR PHY I/O Map is as follows:

Table 2–5 RK3568 DDR PHY I/O map

DDR4

LPDDR4/LPDDR4x

DDR3

LPDDR3

DDR_DQ0_A

DDR4_DQL0_A

LPDDR4_DQ0_A

DDR3_DQ0

LPDDR3_D15

DDR_DQ1_A

DDR4_DQL2_A

LPDDR4_DQ1_A

DDR3_DQ1

LPDDR3_D14

DDR_DQ2_A

DDR4_DQL4_A

LPDDR4_DQ2_A

DDR3_DQ2

LPDDR3_D10

DDR_DQ3_A

DDR4_DQL6_A

LPDDR4_DQ3_A

DDR3_DQ3

LPDDR3_D9

DDR_DQ4_A

DDR4_DQL7_A

LPDDR4_DQ4_A

DDR3_DQ4

LPDDR3_D13

DDR_DQ5_A

DDR4_DQL5_A

LPDDR4_DQ5_A

DDR3_DQ5

LPDDR3_D12

DDR_DQ6_A

DDR4_DQL3_A

LPDDR4_DQ6_A

DDR3_DQ6

LPDDR3_D8

DDR_DQ7_A

DDR4_DQL1_A

LPDDR4_DQ7_A

DDR3_DQ7

LPDDR3_D11

DDR_DM0_A

DDR4_DML_A

LPDDR4_DM0_A

DDR3_DM0

LPDDR3_DM1

DDR_DQS0P_A

DDR4_DQSL_P_A

LPDDR4_DQS0P_A

DDR3_DQS0P

LPDDR3_DQS1P

DDR_DQS0N_A

DDR4_DQSL_N_A

LPDDR4_DQS0N_A

DDR3_DQS0N

LPDDR3_DQS1N

DDR_DQ8_A

DDR4_DQU3_A

LPDDR4_DQ8_A

DDR3_DQ8

LPDDR3_D25

DDR_DQ9_A

DDR4_DQU1_A

LPDDR4_DQ9_A

DDR3_DQ9

LPDDR3_D24

DDR_DQ10_A

DDR4_DQU7_A

LPDDR4_DQ10_A

DDR3_DQ10

LPDDR3_D28

DDR_DQ11_A

DDR4_DQU5_A

LPDDR4_DQ11_A

DDR3_DQ11

LPDDR3_D29

DDR_DQ12_A

DDR4_DQU2_A

LPDDR4_DQ12_A

DDR3_DQ12

LPDDR3_D26

DDR_DQ13_A

DDR4_DQU4_A

LPDDR4_DQ13_A

DDR3_DQ13

LPDDR3_D31

DDR_DQ14_A

DDR4_DQU6_A

LPDDR4_DQ14_A

DDR3_DQ14

LPDDR3_D30

DDR_DQ15_A

DDR4_DQU0_A

LPDDR4_DQ15_A

DDR3_DQ15

LPDDR3_D27

DDR_DM1_A

DDR4_DMU_A

LPDDR4_DM1_A

DDR3_DM1

LPDDR3_DM3

DDR_DQS1P_A

DDR4_DQSU_P_A

LPDDR4_DQS1P_A

DDR3_DQS1P

LPDDR3_DQS3P

DDR_DQS1N_A

DDR4_DQSU_N_A

LPDDR4_DQS1N_A

DDR3_DQS1N

LPDDR3_DQS3N

DDR_DQ0_B

DDR4_DQU7_B

LPDDR4_DQ0_B

DDR3_DQ16

LPDDR3_D1

DDR_DQ1_B

DDR4_DQU5_B

LPDDR4_DQ1_B

DDR3_DQ17

LPDDR3_D5

DDR_DQ2_B

DDR4_DQU3_B

LPDDR4_DQ2_B

DDR3_DQ18

LPDDR3_D6

DDR_DQ3_B

DDR4_DQU1_B

LPDDR4_DQ3_B

DDR3_DQ19

LPDDR3_D4

DDR_DQ4_B

DDR4_DQU0_B

LPDDR4_DQ4_B

DDR3_DQ20

LPDDR3_D2

RK3568 Hardware Design Guide Rev V1.2

DDR4

LPDDR4/LPDDR4x

DDR3

LPDDR3

DDR_DQ5_B

DDR4_DQU6_B

LPDDR4_DQ5_B

DDR3_DQ21

LPDDR3_D3

DDR_DQ6_B

DDR4_DQU4_B

LPDDR4_DQ6_B

DDR3_DQ22

LPDDR3_D7

DDR_DQ7_B

DDR4_DQU2_B

LPDDR4_DQ7_B

DDR3_DQ23

LPDDR3_D0

DDR_DM0_B

DDR4_DMU_B

LPDDR4_DM0_B

DDR3_DM2

LPDDR3_DM0

DDR_DQS0P_B

DDR4_DQSU_P_B

LPDDR4_DQS0P_B

DDR3_DQS2P

LPDDR3_DQS0P

DDR_DQS0N_B

DDR4_DQSU_N_B

LPDDR4_DQS0N_B

DDR3_DQS2N

LPDDR3_DQS0N

DDR_DQ8_B

DDR4_DQL0_B

LPDDR4_DQ8_B

DDR3_DQ24

LPDDR3_D18

DDR_DQ9_B

DDR4_DQL2_B

LPDDR4_DQ9_B

DDR3_DQ25

LPDDR3_D19

DDR_DQ10_B

DDR4_DQL4_B

LPDDR4_DQ10_B

DDR3_DQ26

LPDDR3_D22

DDR_DQ11_B

DDR4_DQL6_B

LPDDR4_DQ11_B

DDR3_DQ27

LPDDR3_D23

DDR_DQ12_B

DDR4_DQL7_B

LPDDR4_DQ12_B

DDR3_DQ28

LPDDR3_D16

DDR_DQ13_B

DDR4_DQL5_B

LPDDR4_DQ13_B

DDR3_DQ29

LPDDR3_D17

DDR_DQ14_B

DDR4_DQL1_B

LPDDR4_DQ14_B

DDR3_DQ30

LPDDR3_D20

DDR_DQ15_B

DDR4_DQL3_B

LPDDR4_DQ15_B

DDR3_DQ31

LPDDR3_D21

DDR_DM1_B

DDR4_DML_B

LPDDR4_DM1_B

DDR3_DM3

LPDDR3_DM2

DDR_DQS1P_B

DDR4_DQSL_P_B

LPDDR4_DQS1P_B

DDR3_DQS3P

LPDDR3_DQS2P

DDR_DQS1N_B

DDR4_DQSL_N_B

LPDDR4_DQS1N_B

DDR3_DQS3N

LPDDR3_DQS2N

DDR_ECC_DQ0

DDR4_ECC_DQ7

DDR3_ECC_DQ0

DDR_ECC_DQ1

DDR4_ECC_DQ0

DDR3_ECC_DQ1

DDR_ECC_DQ2

DDR4_ECC_DQ2

DDR3_ECC_DQ2

DDR_ECC_DQ3

DDR4_ECC_DQ1

DDR3_ECC_DQ3

DDR_ECC_DQ4

DDR4_ECC_DQ6

DDR3_ECC_DQ4

DDR_ECC_DQ5

DDR4_ECC_DQ4

DDR3_ECC_DQ5

DDR_ECC_DQ6

DDR4_ECC_DQ3

DDR3_ECC_DQ6

DDR_ECC_DQ7

DDR4_ECC_DQ5

DDR3_ECC_DQ7

DDR_ECC_DM

DDR4_ECC_DM

DDR3_ECC_DM

DDR_ECC_DQSP

DDR4_ECC_DQSP

DDR3_ECC_DQSP

DDR_ECC_DQSN

DDR4_ECC_DQSN

DDR3_ECC_DQSN

AC0

DDR4_A0

LPDDR4_CLKP_B

DDR3_A9

AC1

DDR4_A1

DDR3_A2

AC2

DDR4_A2

LPDDR4_A1_A

DDR3_A4

LPDDR3_A6

AC3

DDR4_A3

LPDDR4_CKE1_A

DDR3_A3

AC4

DDR4_A4

LPDDR4_A3_B

DDR3_BA1

LPDDR3_A3

AC5

DDR4_A5

LPDDR4_A5_B

DDR3_A11

LPDDR3_A2

AC6

DDR4_A6

LPDDR4_A1_B

DDR3_A13

LPDDR3_A1

AC7

DDR4_A7

LPDDR4_ODT0_CA_B

DDR3_A8

AC8

DDR4_A8

LPDDR4_ODT0_CA_A

DDR3_A6

LPDDR3_A9

AC9

DDR4_A9

LPDDR4_CLKN_B

DDR3_A5

AC10

DDR4_A10

LPDDR4_CKE0_B

DDR3_A10

AC11

DDR4_A11

LPDDR4_A0_A

DDR3_A7

LPDDR3_A8

AC12

DDR4_A12

LPDDR4_A3_A

DDR3_BA2

AC13

DDR4_A13

LPDDR4_A0_B

DDR3_A14

LPDDR3_A0

AC14

DDR4_A14_WEN

LPDDR4_A4_A

DDR3_A15

LPDDR3_A5

AC15

DDR4_A15_CASN

LPDDR4_A2_A

DDR3_A0

AC16

DDR4_A16_RASN

LPDDR4_A5_A

DDR3_RASN

LPDDR3_A7

AC17

DDR4_ACTN

LPDDR4_CKE1_B

DDR3_CASN

AC18

DDR4_BA0

LPDDR4_A2_B

DDR3_A1

AC19

DDR4_BA1

LPDDR4_A4_B

DDR3_A12

LPDDR3_A4

RK3568 Hardware Design Guide Rev V1.2

DDR4

LPDDR4/LPDDR4x

DDR3

LPDDR3

AC20

DDR4_BG0

LPDDR4_ODT1_CA_B

DDR3_WEN

AC21

DDR4_BG1

LPDDR4_ODT1_CA_A

DDR3_BA0

AC22

DDR4_CKE

LPDDR4_CKE0_A

DDR3_CKE

LPDDR3_CKE

AC23

DDR4_CLKP

LPDDR4_CLKP_A

DDR3_CLKP

LPDDR3_CLKP

AC24

DDR4_CLKN

LPDDR4_CLKN_A

DDR3_CLKN

LPDDR3_CLKN

AC25

DDR4_CS0N

LPDDR4_CS0N_A

DDR3_ODT1

LPDDR3_ODT0

AC26

DDR4_CS1N

LPDDR4_CS1N_A

DDR3_CS1N

LPDDR3_ODT1

AC27

DDR4_ODT0

LPDDR4_CS1N_B

DDR3_ODT0

LPDDR3_CS1N

AC28

DDR4_ODT1

LPDDR4_CS0N_B

DDR3_CS0N

LPDDR3_CS0N

AC29

DDR4_RESETN

LPDDR4_RESETN

DDR3_RESETN

 For DDR3/DDR3L:

Support the entire group swap between Byte; support DQ swap within Byte; The CA sequence cannot be swapped and must be allocated according to the schematic design ;

If need to support the template with a total bit width of 16bit and a template with a total bit width

compatible of 16bit/32bit, it’s must use the template provided by RK, and no difference is allowed.  For DDR3/DDR3L and ECC:

ECC Byte is fixed, cannot swap with other Bytes; Support the entire group swap among other bytes;

Support DQ swap within Byte;

The CA sequence cannot be swapped and must be allocated according to the schematic design .

 For LPDDR3:

It is necessary to maintain the one-to-one connection between LPDDR3 D0-D7 and LPDDR3_D0-D7 of

controller, as well as the corresponding relationship between the associated DQS and DM, does not

support adjustment. Other Bytes support the entire group swap; Support DQ swap within other Bytes; The CA sequence cannot be swapped and must be allocated according to the schematic design .

 For DDR4:

Support the entire group swap between Byte; support DQ swap within Byte; The CA sequence cannot be swapped and must be allocated according to the schematic design ;

If need to support the template with a total bit width of 16bit and a template with a total bit width

compatible of 16bit/32bit, it’s must use the template provided by RK, and no difference is allowed.  For DDR4 and ECC:

ECC Byte is fixed, cannot swap with other Bytes;

The DQ sequence in the ECC Byte does not support swapping, and the DQ in other Bytes does not

support swapping also, and must be allocated according to the reference diagram;

The CA sequence cannot be swapped, must be allocated according to the schematic design .

 For LPDDR4/LPDDR4X:

All DQ and CA sequences cannot be swapped, must be allocated according to the schematic design .

8bits ECC function is supported in DDR3/DDR3L/DDR4 mode, requirements for the DDR with ECC

function:

Select the same model of 8bit or 16bit DDR, the row/bank/col must be the same as the main DDRs(the

RK3568 Hardware Design Guide Rev V1.2

two DDRs you have already selected), and the rate must be greater than or equal to the main DDRs, it is

recommended to use the same model as the main DDRs.

When using 16bit ECC DDR, since RK3568 only supports 8bits ECC, one of the Bytes of the 16bit ECC

needs to be processed as shown below:  DDR3/DDR3L 16bit ECC processing method: as shown below, DMU pin is connected to power, DQSU

pin is connected to power, DQSU pin is grounded.

Figure 2-12 RK3568 16bit ECC DDR3/DDR3L processing method

 DDR4 16bit ECC process method: as shown below, DMU_n/DBIU_n pin is connected to power,

DQSU_P pin is connected to power, DQSU_N pin is grounded.

Figure 2-13 RK3568 16bit ECC DDR4 processing method

RK3568 Hardware Design Guide Rev V1.2

RK3568 DDR PHY’s DDR_RZQ (Pin H7) pin connection method:

 For DDR3/DDR3L/DDR4/LPDDR3, DDR_RZQ pin must be grounded with a 120ohm 1% resistor.  For LPDDR4/LPDDR4X, a 120ohm 1% resistor is connected to DDRPHY_VDDQ power (VCC_DDR).

Figure 2-14 RK3568 DDR_RZQ pin

RK3568 DDR PHY can provide voltage to VREFDQ or VREFCA of DRAM, that is, DDR_VREFOUT pin

(Pin P8) can output a voltage to DRAM as VREF voltage.

 For DDR3/DDR3L: the default voltage of VREFDQ (VREF_DDR_DQ network) provided for

DDR3/DDR3L is 0.75V/0.675V, and the voltage can be adjusted through registers according to the actual

needs. The VREFCA of DDR3/DDR3L still uses two 1Kohm 1% resistor for voltage-dividing.

Figure 2-15 DDR3/DDR3L VREF circuit

 For LPDDR3: the voltage of VREFDQ provided for LPDDR3 is related to the configuration of ODT, and

the voltage can be adjusted through registers according to the actual needs. The VREFCA of LPDDR3

still uses two 1Kohm 1% resistor for voltage-dividing.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-16 LPDDR3 VREF circuit

 For DDR4: the default voltage of VREFCA (VREF_DDR4_CA network) provided for DDR4 is 0.6V, and

the voltage can be adjusted through registers according to the actual needs.

Figure 2-17 DDR4 VREF circuit

 For LPDDR4/LPDDR4X: when it is not used, leave floating.

Note: the 1nF capacitors connected to the ground and power of DDRPHY_VREFOUT network cannot be

deleted or modified randomly; the VREF pins of DDR must be with a 1nF decoupling capacitor, and the capacity

cannot be modified randomly.

2.1.7.3 DDR Peripheral Circuit Design

 The ZQ of DDR3/DDR3L/DDR4/LPDDR3 must connect a 240 ohm 1% resistor to ground;  The ZQ of LPDDR4 must connect a 240 ohm 1% resistor to the VCC_DDR power;  The ZQ of LPDDR4x must connect a 240 ohm 1% resistor to the VCC0V6_DDR power;  It is recommended to reserve a 1nF capacitor for the DDR RESET pin to improve the anti-ESD

interference capability

RK3568 Hardware Design Guide Rev V1.2

 For 16bit DDR4 template, reserved to support DDP (Dual-Die Package), the default configuration

parameter is SDP (Single-Die Package). When DDP is needed, the following parameters should be updated synchronously:

1) DDR4 M9 pin connect to DDR_BG1 net of SOC

2) DDR4 T7 pin connect to GND

3) DDR4 E9 pin connect to GND by 240ohm 1% resistor

2.1.7.4 DDR Topology and Matching Design

 For DDR3/DDR3L 4 16bit 2CS, DQ uses T topology (one drive two), CA uses double T topology (one

drive four).

Figure 2-18 DDR3/DDR3L T topology

Clock matching mode: Place the RC circuit at the branch point as shown in the figure below, which can

improve signal quality and reduce EMI.

Figure 2-19 The CLKP/CLKN termination of DDR3/DDR3L T topology

 For DDR3/DDR3L+ ECC six 16bit 2CS, DQ uses T topology (one drive two), CA uses Fly-by topology

(one drive six).

RK3568 Hardware Design Guide Rev V1.2

Figure 2-20 DDR3/DDR3L Fly-by topology

Clock, control, address line signal matching mode: add 39ohm resistor to the VTT power at the end,

please refer circuit shown in the schematic design.

In addition, a 2pF capacitor is reserved for connecting between the clock P and the clock N near RK3568,

whether to add the capacitor according to the actual debugging, and the signal quality can be improved.

 For DDR4 two 16bit 1CS, DQ uses point-to-point connection (one drive one), CA uses T topology (one

drive two).

Figure 2-21 DDR4 T topology

Clock signal matching method: Place the RC circuit at the branch point, it is also necessary to connect

resistors in series to DDR4 on the branch line, and the series resistor must be placed at the branch point to

RK3568 Hardware Design Guide Rev V1.2

improve the quality of the clock signal.

Figure 2-22 The CLKP/CLKN termination of DDR4 T topology

 For DDR4 and ECC 3 16bit 1CS, DQ uses point-to-point connection (one drive one), CA uses Fly-by

topology (one drive three).

Figure 2-23 DDR4 Fly-by topology

Clock, control, address line signal matching mode: Add 39ohm resistor to the VTT power at the end, refer

to the circuit shown in the reference diagram/ schematic design.

In addition, a 2pF capacitor is reserved for connecting between the clock P and the clock N near RK3568,

and the signal quality can be improved.

Note: When chooses a VTT power chip, it needs to support DDR4.

 For LPDDR3 1 32bit, DQ and CA use point-to-point topology.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-24 LPDDR3 point-to-point topology

Clock matching method: the RC circuit is placed at the end of the line, as shown in the figure below,

which can improve signal quality and reduce EMI.

Figure 2-25 LPDDR3 CLKP/CLKN termination

 For one 32bit LPDDR4, DQ and CA use point-to-point topology.

Figure 2-26 LPDDR4 point-to-point topology

Matching method: The DQ, CLK, CMD and CA of LPDDR4 all support ODT, all use point-to-point

connection.

RK3568 Hardware Design Guide Rev V1.2

 For one 32bit LPDDR4X, DQ and CA use point-to-point topology.

Figure 2-27 LPDDR4X point-to-point topology

Matching method: The DQ, CLK, CMD and CA of LPDDR4X all support ODT, all use point-to-point

connection.

2.1.7.5 DDR Power Design and Power up Sequence Requirement

RK3568 DDR PHY have two groups of power supplies, DDRPHY_VDDQ和DDRPHY_VDDQL.

 For DDR3: DDRPHY_VDDQ for 1.5V, DDRPHY_VDDQL for 1.5V  For DDR3L: DDRPHY_VDDQ for 1.35V, DDRPHY_VDDQL for 1.35V  For LPDDR3: DDRPHY_VDDQ for 1.2V, DDRPHY_VDDQL for 1.2V (Actually supply 1.25V for

improved compatibility）

 For DDR4: DDRPHY_VDDQ for 1.2V, DDRPHY_VDDQL for 1.2V  For LPDDR4: DDRPHY_VDDQ for 1.1V, DDRPHY_VDDQL for 1.1V  For LPDDR4X: DDRPHY_VDDQ for 1.1V, DDRPHY_VDDQL for 0.6V

Notes of power supply circuit:  When using the RK809-5 power solution, it is important to note that according to the actual use of

DRAM particles, the voltage divider resistance value of RK809-5 FB3 (pin27) should be modified synchronously to make the VCC_DDR output voltage match the particle.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-28 RK809-5 BUCK3 parameters regulation

 When using discrete power supply solution, the voltage-dividing resistance value of power supply BUCK

should be modified synchronously to make the VCC_DDR output voltage match with the DRAM.

 RK3568 reference template provides LPDDR4 and LPDDR4X compatible design

"RK3568_Template_LP4XD200P132SD6_43x28_1600MHz", it should be noted that the circuit must be

selected according to the actual materials. When using LPDDR4, only need to connect the R3804 resistor

as shown below, all component s in the green box below are not needed; when using LPDDR4X, R3804

is not connected, all components in the green box below are needed.

Figure 2-29 Power selection of LPDDR4/LPDDR4x compatible design

For all types of DRAM power-up sequence, please refer to JEDEC standards:

 The power-up sequence of DDR3/DDR3L SDRAM is shown in the figure below:

RK3568 Hardware Design Guide Rev V1.2

Figure 2-30 DDR3 SDRAM power up sequence

 The power-up sequence of LPDDR3 SDRAM is shown in the figure below:

Figure 2-31 LPDDR3 SDRAM power up sequence

 The power-up sequence of DDR4 SDRAM is shown in the figure below:

Figure 2-32 DDR4 SDRAM power up sequence

 The power-up sequence of LPDDR4/4x SDRAM is shown in the figure below:

RK3568 Hardware Design Guide Rev V1.2

Figure 2-33 LPDDR4/4x SDRAM power up sequence

2.1.7.6 DDR Support List

For the DDR support list, please refer to the document "Rockchip_Support_List_DDR", which can be

downloaded from Rockchip redmine platform:

https://redmine.rockchip.com.cn/projects/fae/documents?tdsourcetag=s_pctim_aiomsg

eMMC Circuit

2.1.8.1 eMMC Controller Introduction

The features of RK3568 eMMC controller are as follows:

 Compatible with standard iNAND interface;  Compatible with the 4.41,4.51,5.0, and 5.1 specifications;  Support three data bus widths of 1-bit, 4-bit and 8-bit;  Support HS200 mode;  Support CMD Queue;

2.1.8.2 eMMC Circuit Design Suggestion

RK3568 eMMC interface is multiplexed with Nand Flash and FSPI Flash interface, in the design of eMMC

interface, please refer to the schematic for the eMMC signal connection method, including the decoupling

capacitors of each power supply.

The boot code is placed in eMMC, when using eMMC, it must be noted that whether the IO drive voltage

mode configuration of RK3568 VCCIO2 power domain is matched with the actual supply voltage, please see

Section 2.1.5 System Initialization Configuration Signal for details.

During the design, be sure to reserve test points on the EMMC_D0 or EMMC_CLK network, in order to

prevent the abnormal booting caused by flashing a wrong firmware during the development process. Make the

EMMC_D0 or EMMC_CLK short to ground, and power on, RK3568 will enter into the Maskrom mode, then

download a new firmware through the PC tool (after the PC tool recognizes the Maskrom, it must release the

grounding short circuit of EMMC_D0 or EMMC_CLK, otherwise the flashing will fail).

Normally, it is not recommended to update the firmware in this way, because improper operation may cause

RK3568 Hardware Design Guide Rev V1.2

IO damage.

Figure 2-34 eMMC_D0 test point

2.1.8.3 eMMC Topology and Matching Method Design

 eMMC connection diagram:

Figure 2-35 eMMC connection diagram

 eMMC interface pull up and down and matching design suggestions as shown in Table 2-6:

Table 2–6 RK3568 eMMC interface design

Signal

Internal pull

up/down

Connection mode

Description(chipset)）

eMMC_D[7:0]

pull up

direct connection, D0 external

pull-up with a 10K ohm resistor, other data use the pull-up resistor inside the RK3568 chip

eMMC data send/receive eMMC_CLK

pull down

connect 22ohm resistor in series

with RK3568

eMMC clock send

eMMC_CMD

pull up

direct connection, D0 external

pull-up with a 10K ohm resistor

eMMC command send/receive

eMMC_DATA_

Strobe

pull down

connect a 0ohm resistor in series with the eMMC, and reserve a

47K ohm pull-down resistor

eMMC data and command receive

refer to Strobe

 Connection diagram of eMMC and Nand Flash in compatible design:

RK3568 Hardware Design Guide Rev V1.2

Figure 2-36 Connection diagram of eMMC and Nand Flash in compatible design

In compatible design, there will be branches in the multiplexed signal routing. To ensure that the impact of

eMMC signal quality is minimized, the three signals eMMC_CMD/FLASH_WRn, eMMC_CLK/FLASH_DQS,

eMMC_DS/FLASH_CLE should reserve series resistors at the branch points. For example: when using eMMC, the

0ohm resistors that branch to the eMMC are needed, and the 0ohm resistors that branch to the Nand Flash are not

needed, which will minimize the branching impact in routing. D0-D7 can minimize the branching impact through PCB Layout (For Nand, the D0 pull-up resistor cannot be connected, please refer to the PCB Layout design below.

2.1.8.4 eMMC Power up Sequence Requirement

The eMMC interface of RK3568 belongs to VCCIO2 power domain, only one power supply, so there is no

sequence requirements.

The eMMC have two sets of power supplies, refer to JEDEC standard for power-on sequence:

RK3568 Hardware Design Guide Rev V1.2

Figure 2-37 eMMC power up and power down sequence

2.1.8.5 eMMC Support List

For RK3568 eMMC support list, please refer to the document "RKeMMCSupportList", which can be

downloaded from Rockchip redmine platform:

https://redmine.rockchip.com.cn/projects/fae/documents?tdsourcetag=s_pctim_aiomsg

FSPI Flash Circuit

2.1.9.1 FSPI Flash（Boot is supported）Interface Introduction

FSPI is a flexible serial interface controller. There is a FSPI controller in RK3568 chip, which can be used to

connect FSPI devices.

The features of RK3568 FSPI controller are as follows:

 Support serial NOR and NAND FLASH;  Support SDR mode;  Support single/dual/four-line mode;

2.1.9.2 FSPI Flash Circuit Design Suggestion

FSPI Flash interface of RK3568 is multiplexed with Nand Flash and eMMC interface. In FSPI Flash interface

design, please refer to the schematic for the FSPI Flash signal connection mode, including the decoupling

capacitors for each power supply.

The boot code is placed in FSPI Flash, when using the FSPI Flash, it must be noted that whether the IO drive

voltage mode configuration of RK3568 VCCIO2 power domain is matched with the actual supply voltage, please

see Section 2.1.5 System Initialization Configuration Signal for details.

During the design, be sure to reserve test points on the FSPI_CLK network, in order to prevent the abnormal

booting caused by flashing a wrong firmware during the development process. Make the FSPI_CLK short to

ground, and then power on, RK3568 will enter Maskrom mode, then download a new firmware through the PC tool

(after the PC tool recognizes the Maskrom, it must release the grounding short circuit of FSPI_CLKK, and

otherwise the flashing will fail).

RK3568 Hardware Design Guide Rev V1.2

Normally, it is not recommended to update the firmware in this way, because improper operation may cause IO

damage.

Figure 2-38 FSPI_CLK test point

2.1.9.3 FSPI Flash Topology and Matching Design

 FSPI Flash connection diagram:

Figure 2-39 FSPI Flash connection diagram

 FSPI interface pull up and down and matching design suggestions as shown in Table 2-7:

Table 2–7 RK3568 FSPI interface design

Signal

Internal pull up/down

Connection mode

Description(chipset)

FSPI_D[3:0]

D2 pull down D0/D1/D3 pull up

direct connection, D2, D3 external pull-up with a 10K ohm resistor,

FSPI data send/receive

FSPI0_CLK

pull down

connect 22ohm resistor in series with RK3568

FSPI clock send FSPI0_CS0n

pull up

direct connection

FSPI chip select signal

2.1.9.4 FSPI Power up Sequence Requirement

The FSPI Flash interface of RK3568 chip belongs to the VCCIO2 power domain, only one power supply, so

there is no sequence requirements.

The SPI Flash have only one power supply, the power supply must be the same as the VCCIO2 power domain

power supply.

2.1.9.5 SPI Flash Support List

For RK3568 SPI Flash support list, please refer to the document "RK SpiNor and SLC Nand SupportLis",

which can be downloaded from Rockchip redmine platform:

https://redmine.rockchip.com.cn/projects/fae/documents?tdsourcetag=s_pctim_aiomsg

RK3568 Hardware Design Guide Rev V1.2

Nand Flash Circuit

2.1.10.1 Nand Flash Controller Introduction

RK3568 Nand Flash controller supports the following features:

 Support asynchronous Nand Flash interface, 8bits data bus width, support up to 2 chip selects;  Support ONFI synchronous Nand Flash interface, 8bits data bus width, support up to 2 chip selects;  Support Toggle Flash interface, 8bits data bus width, support up to 2 chip selects;  Support SLC, MLC, TLC Flash;  Support ECC and so on;

2.1.10.2 Nand Flash Circuit Design Suggestion

The Nand Flash interface of RK3568 is multiplexed with FSPI Flash and eMMC interface. In Nand Flash

interface design, please refer to the schematic for the Nand Flash signal connection mode, including the decoupling

capacitors for each power supply.

The reference schematic is compatible with different types of Nand Flash. Please select the peripherals

according to the model actually used. When using Nand Flash in DDR mode, Pin28 and 45 of Nand Flash should

be connected to the VCCIO_FLASH power; and Pin38 of some SLC is for protection. If such Flash are used, Pin38

leave floating

The boot code is placed in Nand Flash, when using the Nand Flash, it must be noted that whether the IO drive

voltage mode configuration of RK3568 VCCIO2 power domain is matched with the actual supply voltage, please

see Section 2.1.5 System Initialization Configuration Signal for details.

During the design, be sure to reserve test points on the Flash_D0 network, in order to prevent the abnormal

booting caused by flashing a wrong firmware during the development process. Make the Flash_D0 short to the

ground, and power on, RK3568 will enter the Maskrom mode, then download a new firmware through the PC tool

(after the PC tool recognizes the Maskrom, it must release the grounding short circuit of Flash_D0, otherwise the

flashing will fail)..

Normally, it is not recommended to update the firmware in this way, because improper operation may cause

IO damage.

Figure 2-40 Flash_D0 test point

RK3568 Hardware Design Guide Rev V1.2

2.1.10.3 Nand Flash Topology and Matching Design

 Nand Flash connection diagram:

Figure 2-41 Nand Flash connection diagram

 Nand Flash interface pull up and down and matching design suggestions as shown in Table 2-8:

Table 2–8 RK3568 Nand Flash interface design

Signal

Internal pull

up/down

Connection mode

Description(chipset)

Flash_D[7:0]

pull up

direct connection

Nand Flash data send and receive

Flash_WRn

pull up

direct connection

Nand Flash write enable

Flash_DQS

pull down

connect 22ohm resistor in series with RK3568

Nand Flash data strobe

Flash_CLE

pull down

direct connection

Nand Flash command latch enable

Flash_WPn

pull down

direct connection

Nand Flash write protected

Flash_RDY

pull up

direct connection, external pull-up with a 4.7K ohm resistor

Nand Flash ready/busy Flash_RDn

pull up

direct connection

Nand Flash read enable

Flash_CS0n

pull up

direct connection, external pull-up with a 4.7K ohm resistor

Nand Flash chip select 0

Flash_CS1n

pull up

direct connection, external pull-up with a 4.7K ohm resistor

Nand Flash chip select 1 Flash_ALE

pull down

direct connection

Nand Flash address latch enable

 When using eMMC and Nand Flash compatible design, please see eMMC circuit description.

RK3568 Hardware Design Guide Rev V1.2

2.1.10.4 Nand Flash Power up Sequence Requirement

The Nand Flash interface of RK3568 chip belongs to the VCCIO2 power domain, only one power supply, so

there are no sequence requirements.

 The Nand Flash have only one power supply, the power supply must be the same as the VCCIO2 power

domain power supply.

 The Nand Flash have two sets of power supplies, refer to JEDEC standard for power-on sequence:

Figure 2-42 Nand Flash power up and down sequence

2.1.10.5 Nand Flash Support List

For RK3568 Nand Flash support list, please refer to the document "RK Nand Flash SupportList", which can

be downloaded from Rockchip redmine platform:

https://redmine.rockchip.com.cn/projects/fae/documents?tdsourcetag=s_pctim_aiomsg

GPIO Circuit

In RK3568, there are three types of GPIO: only support 1.8V, only support 3.3V, and support configurable

1.8V/3.3V two voltages.

2.1.11.1 GPIO Pins Description

For example, the function SDMMC1_D0, GMAC0_RXD2 and UART6_RX_M0 in the figure below are

multiplexed on GPIO2_A3, and only one of the functions can be selected for use when assigning.

RK3568 Hardware Design Guide Rev V1.2

 Except for boot related GPIO, the rest of IOs are reset to input by defaults;  GPIOx_xx_u where _u indicates that the default state of this IO reset is internal pull-up;  GPIOx_xx_d where _d indicates that the default state of this IO reset is internal pull-down;  GPIOx_xx_z where _z indicates that the default state of this IO reset is high impedance;

 The name suffix of each function with _M0 or M1 or _M2 indicates that the same function is

multiplexed on different IO, only one of them can be selected at the same time. For example, when

selecting the UART2 function, the UART2_ TX_ M0 and UART2_ RX_ M0 combination must be

selected. The combination of UART2_TX_M0 and UART2_RX_M1 is not supported. This is the

constraint for all functions with different IOMUX.

2.1.11.2 GPIO Drive Capability

In RK3568, GPIO provides multiple levels of adjustable driving strength. Most are Level 0-5 and some GPIO

can achieve Level 0-11 adjustment levels. For details, please refer to the "RK3568_PinOut" document. In addition,

depending on the type of GPIO, the initial default driving strength is different. Please refer to the chip TRM for

configuration modification, or refer to Table 5 "SupportDriveStrength" and "DefaultIO DriveStrength" columns in

the "RK3568_PinOut" document.

2.1.11.3 GPIO Power

The power pins of the GPIO power domain are described as follows:

Table 2–9 RK3568 GPIO power pins description

Power domain

GPIO Type

Pin name

Description

PMUIO0

1.8V

PMUPLL_AVDD_1V8

1.8V Only IO supply for this GPIO domain (group).

PMUIO1

3.3V

PMUIO1

3.3V Only IO supply for this GPIO domain (group).

PMUIO2

1.8V/3.3V

PMUIO2

1.8V or 3.3V IO supply for this GPIO domain (group).

VCCIO1

1.8V/3.3V

VCCIO1

1.8V or 3.3V IO supply for this GPIO domain (group).

VCCIO2

1.8V/3.3V

VCCIO2

1.8V or 3.3V IO supply for this GPIO domain (group).

VCCIO3

1.8V/3.3V

VCCIO3

1.8V or 3.3V IO supply for this GPIO domain (group).

VCCIO4

1.8V/3.3V

VCCIO4

1.8V or 3.3V IO supply for this GPIO domain (group).

VCCIO5

1.8V/3.3V

VCCIO5

1.8V or 3.3V IO supply for this GPIO domain (group).

VCCIO6

1.8V/3.3V

VCCIO6

1.8V or 3.3V IO supply for this GPIO domain (group).

VCCIO7

1.8V/3.3V

VCCIO7

1.8V or 3.3V IO supply for this GPIO domain (group).

PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured;

PMUIO2 and VCCIO1, VCCIO [3:7] power domains require that their hardware power supply voltages

must be consistent with the software configuration correspondingly:

 When the hardware IO is connected to 1.8V, the software voltage configuration should be set to

1.8V accordingly;

RK3568 Hardware Design Guide Rev V1.2

 When the hardware IO is connected to 3.3V, the software voltage configuration should be set to

3.3V accordingly;

There is no need to configure VCCIO2 power domain by software, but its hardware power supply and

FLASH_VOL_SEL status must be matched:

 When VCCIO2 voltage is connected to 1.8V, FLASH_VOL_SEL must be high;  When VCCIO2 voltage is connected to 3.3V, FLASH_VOL_SEL must be low;

Otherwise:  If the software configuration is 1.8V, but the hardware power supply is 3.3V, it will cause the low

withstand voltage circuit working in overvoltage state, and the IO will be damaged after long time

working;

 If the software configuration is 3.3V, but the hardware power supply is 1.8V, the circuit will work

abnormally;

For example, the default dts configuration is as follows: &pmu_io_domains {

status = "okay"; pmuio1-supply = <&vcc_3v3>; pmuio2-supply = <&vcc_3v3>; vccio1-supply = <&vcc_3v3>; vccio3-supply = <&vcc_3v3>; vccio4-supply = <&vcc_1v8>; vccio5-supply = <&vcc_3v3>; vccio6-supply = <&vcc_1v8>; vccio7-supply = <&vcc_3v3>;

}; If the actual VCCIO4 power supply is 3.3V, then dts needs to be updated to: &pmu_io_domains {

status = "okay"; pmuio1-supply = <&vcc_3v3>; pmuio2-supply = <&vcc_3v3>; vccio1-supply = <&vcc_3v3>; vccio3-supply = <&vcc_3v3>; vccio4-supply = <&vcc_3v3>; vccio5-supply = <&vcc_3v3>; vccio6-supply = <&vcc_1v8>; vccio7-supply = <&vcc_3v3>;

};

If other power domains have changed and they must be updated and matched accordingly.

Various documents released by Rockchip have emphasized this notice, please review the voltage

RK3568 Hardware Design Guide Rev V1.2

configuration and hardware power supply of your projects as soon as possible!

Reference documents:

1) DTS configuration documentation: https://redmine.rock-chips.com/documents/106

2) Checklist: Rockchip_RK3568_IO Power Domain Description and Checklist_V1.0_CN.xlsx

Also, note that the IO level of the power domain should be consistent with the IO level of the peripheral

chip/device.

At least one 100nF decoupling capacitor must be placed nearby the power supply pins of each power domain.

See the reference schematic for the detailed design and they cannot be deleted at will.

If all IOs in a power domain are not used, then the power supply of this power domain does not need to supply

power, and the pin leave floating.

RK3568 Hardware Design Guide Rev V1.2

2.2 Power Supply Design

RK3568 Power Supply Introduction

2.2.1.1 Power Supply Requirements of RK3568

Table 2–10 RK3568 power supply requirements

Module

Power Pin

Description

PMUPLL

PMUPLL_AVDD_0V9、PMUPLL_AVDD_1V8

PMU PLL Power

SYSPLL

SYSPLL_AVDD_0V9、SYSPLL_AVDD_1V8

System PLL Power

CPU

VDD_CPU

ARM Power

GPU

VDD_GPU

GPU Power

NPU

VDD_NPU

NPU Power

Logic

VDD_LOGIC

SOC Logic Power

PMU Logic

PMU_VDD_LOGIC_0V9

PMU Logic Power

DDR

DDRPHY_VDDQ、 DDRPHY_VDDQL

DDR PHY Power

GPIO

PMUIO0, PMUIO1, PMUIO2, VCCIO1, VCCIO2, VCCIO3, VCCIO4, VCCIO5, VCCIO6, VCCIO7

IO Domain Power SARADC

SARADC_AVDD_1V8

SAR ADC Power

OTP

OTP_VCC18

OTP Power

USB2.0 PHY

USB3_AVDD_0V9 、 USB3_AVDD_1V8 、 USB3_AVDD_3V3

USB2.0 PHY Power(Controller use USB3.0, it is combined with the SS signal of MULTI PHY0/1 to form a complete USB3.0 interface, so the name starts with USB3)

USB2.0 PHY

USB2_AVDD_0V9 、 USB2_AVDD_1V8 、 USB2_AVDD_3V3

USB2.0 PHY Power

MULTI_PHY

MULTI_PHY_AVDD_0V9 、 MULTI_PHY_AVDD_1V8

MULTI_PHY Power

PCIe3.0 PHY

PCIE30_AVDD_0V9、 PCIE30_AVDD_1V8

PCIe3.0 PHY Power

MIPI CSI RX PHY

MIPI_CSI_RX_AVDD_0V9 、 MIPI_CSI_RX_AVDD_1V8

MIPI CIS RX PHY Power

MIPI DSI TX0/LVDS TX Combo PHY

MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9 、 MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8

MIPI DSI TX0/LVDS TX Combo PHY Power

MIPI DSI TX1 PHY

MIPI_DSI_TX1_AVDD_0V9 、 MIPI_DSI_TX1_AVDD_1V8

MIPI DSI TX1 PHY Power

eDP TX PHY

eDP_TX_AVDD_0V9、 eDP_TX_AVDD_1V8

eDP TX PHY Power

HDMI2.0 TX PHY

HDMI_TX_AVDD_0V9、 HDMI_TX_AVDD_1V8

HDMI2.0 TX PHY Power

2.2.1.2 Power-on Sequence Requirements of RK3568

Theoretically, follow the principle: for the same module, low voltage power on first, high voltage power on

later; for the same module with the same voltage can power on together, and there is no timing requirement

between different modules, after the last voltage is stable, RESETn can only be released after at least 10ms.

 The recommended power-on sequence of the digital power supply is as follows: PMU_VDD_LOGIC_0V9  VDD_LOGIC  VDD_CPU/VDD_GPU/VDD_NPU

RK3568 Hardware Design Guide Rev V1.2

The recommended power-on sequence for SARADC is as follows: VDD_LOGIC  SARADC_AVDD_1V8  The recommended power-on sequence for OTP is as follows: VDD_LOGIC  OTP_VCC18  The recommended power-on sequence for USB PHY is as follows: USB3_AVDD_0V9  USB3_AVDD_1V8  USB3_AVDD_3V3 USB2_AVDD_0V9  USB2_AVDD_1V8  USB2_AVDD_3V3  The recommended power-on sequence for MIPI CSI RX PHY is as follows: MIPI_CSI_RX_AVDD_0V9  MIPI_CSI_RX_AVDD_1V8  The recommended power-on sequence for MIPI DSI TX0/LVDS Combo PHY is as follows: MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9  MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8  There is no restriction on other modules power-on sequence.

According to the power network name assigned by the reference schematic, the overall recommended

power-on sequence is as follows:

VDDA0V9_PMU、VDDA_0V9、VDD_LOGIC  VCCA1V8_PMU、VCCA_1V8、VDD_GPU、 VCC3V3_PMU、VCC_1V8  VDD_CPU、VCC2V5_DDR  VCC_DDR  VCC_3V3、VCCIO_SD、 VCC3V3_SD  RESETn

Intervals>=0us

2.2.1.3 Power-off Sequence Requirements of RK3568

During the power-off process, RESETn must be pulled down first, and then each power supply will be powered off.

Power Supply Design Suggestion

2.2.2.1 Power-on and Standby Circuit Scheme

 The power supply status of each module of RK3568 is shown as the following Table when it is first

powered on:

Table 2–11 RK3568 power supply requirement of each module for the first powered on

Module

Power Pin

Power supply

requirements in first

power-on

PMUPLL

PMUPLL_AVDD_0V9、PMUPLL_AVDD_1V8

Must be powered

SYSPLL

SYSPLL_AVDD_0V9、SYSPLL_AVDD_1V8

Must be powered

CPU

VDD_CPU

Must be powered

GPU

VDD_GPU

Can be unpowered

NPU

VDD_NPU

Can be unpowered

Logic

VDD_LOGIC

Must be powered

PMU Logic

PMU_VDD_LOGIC_0V9

Must be powered

RK3568 Hardware Design Guide Rev V1.2

Module

Power Pin

Power supply

requirements in first

power-on

DDR

DDRPHY_VDDQ、DDRPHY_VDDQL

Must be powered

GPIO

PMUIO0、PMUIO1、PMUIO2

Must be powered

GPIO

VCCIO2

Must be powered

GPIO

VCCIO3

Must be powered

GPIO

VCCIO1、VCCIO4、VCCIO5、VCCIO6、VCCIO7

Can be unpowered

SARADC

SARADC_AVDD_1V8

Must be powered

OTP

OTP_VCC18

Must be powered

USB2.0 PHY

USB3_AVDD_0V9、USB3_AVDD_1V8、 USB3_AVDD_3V3、

Must be powered

USB2.0 PHY

USB2_AVDD_0V9、USB2_AVDD_1V8、USB2_AVDD_3V3

Can be unpowered

MULTI_PHY

MULTI_PHY_AVDD_0V9、MULTI_PHY_AVDD_1V8

Can be unpowered

PCIe3.0 PHY

PCIE30_AVDD_0V9、PCIE30_AVDD_1V8

Can be unpowered

MIPI CSI RX PHY

MIPI_CSI_RX_AVDD_0V9、MIPI_CSI_RX_AVDD_1V8

Can be unpowered

MIPI DSI TX0/LVDS Combo PHY

MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9、 MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8

Can be unpowered MIPI DSI TX1 PHY

MIPI_DSI_TX1_AVDD_0V9、MIPI_DSI_TX1_AVDD_1V8

Can be unpowered

deep TX PHY

eDP_TX_AVDD_0V9、 eDP_TX_AVDD_1V8

Can be unpowered

HDMI2.0 TX PHY

HDMI_TX_AVDD_0V9、 HDMI_TX_AVDD_1V8

Can be unpowered

Note: If the unused module is not powered, the software is required to disable the configuration of the

corresponding node in the DTS, otherwise it may cause the kernel initialization stuck.

 The RK3568 chip can support a low-power standby solution. When entering the standby mode, the power

supply and power-off conditions are as follows:

Table 2–12 RK3568 standby power supply requirements

Module

Power Pin

Power supply

requirements in Low

power consumption

standby

PMUPLL

PMUPLL_AVDD_0V9、PMUPLL_AVDD_1V8

Power must be supplied

SYSPLL

SYSPLL_AVDD_0V9、SYSPLL_AVDD_1V8

Can support power off

CPU

VDD_CPU

Can support power off

GPU

VDD_GPU

Can support power off

NPU

VDD_NPU

Can support power off

Logic

VDD_LOGIC

Can support power off

PMU Logic

PMU_VDD_LOGIC_0V9

Power must be supplied

DDR

DDRPHY_VDDQ、 DDRPHY_VDDQL

Power must be supplied

RK3568 Hardware Design Guide Rev V1.2

Module

Power Pin

Power supply

requirements in Low

power consumption

standby

GPIO

PMUIO0、PMUIO1、PMUIO2

Power must be supplied

GPIO

VCCIO2

Can support power off

GPIO

VCCIO3

Can support power off

GPIO

VCCIO1、VCCIO4、VCCIO5、VCCIO6、VCCIO7

Can support power off

SARADC

SARADC_AVDD_1V8

Can support power off

OTP

OTP_VCC18

Can support power off

USB2.0 PHY

USB3_AVDD_0V9、USB3_AVDD_1V8、USB3_AVDD_3V3、

Can support power off

USB2.0 PHY

USB2_AVDD_0V9、USB2_AVDD_1V8、USB2_AVDD_3V3

Can support power off

MULTI_PHY

MULTI_PHY_AVDD_0V9、MULTI_PHY_AVDD_1V8

Can support power off

PCIe3.0 PHY

PCIE30_AVDD_0V9、 PCIE30_AVDD_1V8

Can support power off

MIPI CSI RX PHY

MIPI_CSI_RX_AVDD_0V9、MIPI_CSI_RX_AVDD_1V8

Can support power off

MIPI DSI TX0/LVDS Combo PHY

MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9 、 MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8

Can support power off

MIPI DSI TX1 PHY

MIPI_DSI_TX1_AVDD_0V9、MIPI_DSI_TX1_AVDD_1V8

Can support power off

eDP TX PHY

eDP_TX_AVDD_0V9、 eDP_TX_AVDD_1V8

Can support power off

HDMI2.0 TX PHY

HDMI_TX_AVDD_0V9、 HDMI_TX_AVDD_1V8

Can support power off

This standby solution can only support IO interrupt wake-up of PMUIO0, PMUIO1 and PMUIO2.

In the standby state, at least the following four groups of power supplies should be kept turning on (refer to the

power supply network name in the schematic):

 VCC_DDR/VCC0V6_DDR: Provide power for DDR self-refresh (DDR4: 2.5V power supply also needs

power supply, LPDDR3/LPDDR4/LPDDR4x: 1.8V power supply also needs power supply);

 VDDA0V9_PMU: Provide power for the logic of PMUIO0 & PMUIO1 & PMUIO2 power domain; It

also provides power for PMUPLL and chip OSC work;

 VCCA1V8_PMU: Provide power for PMUPLL work; provide IO power for PMUIO0 power domain to

maintain output status and interrupt response;

 VCC3V3_PMU: Provide IO power for PMUIO1 & PMUIO2 power domain to maintain output status and

interrupt response;

In standby, if it need to supports USB HID device wake-up, the USB PHY power supply must remain powered; if it need to supports IO interrupt wake-up in VCCIO1, VCCIO2, VCCIO3, VCCIO4, VCCIO5, VCCIO6, VCCIO7,

VDD_LOGIC and VCCIO1, VCCIO2, VCCIO3, VCCIO4, VCCIO5, VCCIO6, VCCIO7 power supply must be

kept.

2.2.2.2 PLL Power Supply

The PLL of RK3568 chip is distributed in two parts as follows:

Table 2–13 RK3568 internal PLL Introduction

Power

Standby Mode

Inside the PMU unit

PMUPLL_AVDD_0V9、PMUPLL_AVDD_1V8

Can't turn off the power

Modules in the chip

SYSPLL_AVDD_0V9、SYSPLL_AVDD_1V8

Can turn off the power

RK3568 Hardware Design Guide Rev V1.2

 PMUPLL_AVDD_0V9: Peak current 10mA

 PMUPLL_AVDD_1V8: Peak current 9mA

 SYSPLL_AVDD_0V9: Peak current 30mA

 SYSPLL_AVDD_1V8: Peak current 18mA

It is recommended to use LDO for power supply, PSRR@1KHz should be greater than 65dB, and the power

supply capacity should be more than 200mA.

0.9V AC requirement: <20mV;

1.8V AC requirement: <50mV;

A stable PLL power supply will improve the stability of the chip, and the decoupling capacitors should be

placed close to the pins. Refer to the schematic for the detailed number and capacity of the capacitors. Please do not

change them at will.

Figure 2-43 RK3568 PMU PLL power pin

Figure 2-44 RK3568 SYS PLL power pin

RK3568 Hardware Design Guide Rev V1.2

2.2.2.3 PMU LOGIC Power Supply

The PMU_VDD_LOGIC_0V9 power supply of RK3568 supplies the LOGIC of the internal PMU unit with a

peak current of 50mA. Please do not delete the decoupling capacitor in the RK3568 chip reference schematic.

DC/DC or LDO can be used for power supply. From the cost considerations, it can work with

PMUPLL_AVDD_0V9 power supply together.

Figure 2-45 RK3568 PMU_VDD_LOGIC_0V9 power pin

2.2.2.4 CPU Power Supply

The VDD_CPU power of RK3568 supplies power to the internal ARM Cortex-A55 core, which is

independently powered by DC/DC power supply and supports dynamic frequency and voltage regulation function.

The peak current can reach more than 3A, please do not delete the decoupling capacitors in the RK3568 chip

reference schematic.

The main requirements for DC/DC BUCK are as follows:

 Output current is greater than or equal to 4A;

 The output voltage accuracy is required at ±1.5%;

 BUCK transient response requirements: I

load

=BUCK Max current*10%~BUCK Max current*80% jump,

slope 1A/μs, ripple requirement within ±3%;

 If it is sensitive to the power consumption of the whole machine, efficiency also needs to be considered.

Place the C1000, C1001, and C1004 capacitors in the figure below on the back of the RK3568 chip during

layout. C1002 and C1003 should be as close as possible to RK3568. The total capacitance of the VDD_CPU power

supply must be greater than 135μF (it is recommended to reserve one or two 22μF capacitors, which cannot be

connected by default), in order to ensure that the power supply ripple is within 80mV, then avoid large power

supply ripples under heavy load conditions.

The VDD_CPU_COM signal is the VDD_CPU power feedback pin, which needs to be connected to the FB of

the DC/DC power supply, which can effectively improve the voltage drop caused by PCB routing and improve the

timeliness of power dynamic adjustment.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-46 RK3568 VDD_CPU power pin and power supply DC/DC

2.2.2.5 GPU Power Supply

The VDD_GPU power of RK3568 supplies power to the internal GPU unit. It uses DC/DC power supply and

supports dynamic frequency and voltage regulation. The peak current can reach 1.2A. Please do not delete the

decoupling capacitors in the RK3568 chip reference schematic.

The main requirements for DC/DC BUCK are as follows:

 Output current is greater than or equal to 2A;

 The output voltage accuracy is required to be ±1.5%;

 BUCK transient response requirements: I

load

=BUCK Max current*10%~BUCK Max current*80% jump,

slope 1A/μs, ripple requirement within ±3%;

 If it is sensitive to the power consumption of the whole machine, efficiency also needs to be considered.

Place the C1012, C1013, and C1014 capacitors in the figure below on the back of the RK3568 chip during

layout. C1015 and C1016 should be as close as possible to RK3568. The total capacitance of the VDD_CPU power

supply need to be greater than 90μF, in order to ensure that the power supply ripple is within 60mV, and avoid large

power supply ripples under heavy load conditions.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-47 RK3568 VDD_GPU power pin

2.2.2.6 NPU Power Supply

The VDD_NPU power of RK3568 supplies the internal NPU unit with DC/DC power supply and supports

dynamic frequency and voltage regulation. The peak current can reach 1A, please do not delete the decoupling

capacitors in the RK3568 chip reference schematic.

The main requirements for DC/DC BUCK are as follows:

 Output current is greater than or equal to 2A;

 The output voltage accuracy is required to be ±1.5%;

 BUCK transient response requirements: I

load

=BUCK Max current*10%~BUCK Max current*80% jump,

slope 1A/μs, ripple requirement within ±3%;

 If it is sensitive to the power consumption of the whole machine, efficiency also needs to be considered.

Place the C1017 and C1018 capacitors in the figure below on the back of the RK3568 chip during layout.

C1019 and C1020 should be as close as possible to RK3568. The total capacitance of the VDD_CPU power supply

need to be greater than 90μF, in order to ensure that the power supply ripple is within 60mV, then avoid large power

supply ripples under heavy load conditions.

Figure 2-48 RK3568 VDD_NPU power pin

2.2.2.7 Logic Power Supply

The VDD_LOGIC power of RK3568 supplies power to the internal logic unit. It uses a DC/DC power supply

for independent power supply, which can support dynamic frequency and voltage regulation, and the default fixed

voltage for power supply. The peak current can reach 1A, please do not delete the decoupling capacitors in the

RK3568 chip reference schematic.

The main requirements for DC/DC BUCK are as follows:

 Output current is greater than or equal to 2A;

 The output voltage accuracy is required to be ±1.5%;

 BUCK transient response requirements: I

load

=BUCK Max current*10%~BUCK Max current*80% jump,

slope 1A/μs, ripple requirement within ±3%;

 If it is sensitive to the power consumption of the whole machine, efficiency also needs to be considered.

RK3568 Hardware Design Guide Rev V1.2

Place the C1005, C1006, C1007 and C1008 capacitors in the figure below on the back of the RK3568 chip

during layout. C1010 and C1011 should be as close as possible to RK3568. The total capacitance of the

VDD_LOGIC power supply need to be greater than 90μF, in order to ensure that the power supply ripple is within

60mV, then avoid large power supply ripples under heavy load conditions.

Figure 2-49 RK3568 VDD_LOGIC power pin

2.2.2.8 DDR Power Supply

The DDR PHY interface of RK3568 chip supports DDR3/DDR3L/DDR4/LPDDR4/LPDDR4x level standards.

RK3568 DDR PHY has two power supplies, DDRPHY_VDDQ and DDRPHY_VDDQL. For power supply

introduction, please refer to Section 2.1.7.5 DDR power supply design and power-on sequence requirements. When designing a product, please confirm whether it meets the design requirements according to the use of DDR.

Similarly, use DC/DC for power supply; different DDR with different peak current, please evaluate the peak

current according to the actual selected DDR. For a single LPDDR3 or a single LPDDR4 or a single LPDDR4x or

two 16bit DDR3/3L or two 16bit DDR4, 1A DC/DC can be selected; for more than two DDR3 or DDR4, it is

recommended to use a DC/DC above 2A. In addition, please do not delete the decoupling capacitors in the RK3568

chip reference schematic.

Figure 2-50 RK3568 VCC_DDR power pin in DDR3/DDR3L/DDR4/LPDDR3/LPDDR4 mode

Place the C1100, C1101, C1102, C1103 and C1104 capacitors in the figure above on the back of the RK3568

chip during layout, in order to ensure that the power supply ripple is within 60mV, then avoid large power supply

ripples under heavy load conditions.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-51 RK3568 VCC_DDR and VCC0V6_DDR power pins in LPDDR4x mode

Place the C1100, C1101, C1102, C1103, C1104, C1105, C1106, C1107, C1108 and C1109 capacitors in the

figure above on the back of the RK3568 chip during layout, in order to ensure that the power supply ripple is within

60mV, then avoid large power supply ripples under heavy load conditions.

2.2.2.9 USB2.0 PHY Power Supply

RK3568 has four USB2.0 interfaces, and USB3_OTG0_DP/M, USB3_HOST1_DP/M with MULTI_PHY0,

MULTI_PHY1 can form a USB3.0 interface. For details, please refer to Section 2.3.4 USB2.0/USB3.0 Circuit.

The USB3_AVDD_0V9, USB3_AVDD_1V8, USB3_AVDD_3V3 supply power to the USB3_OTG0_DP/M

and USB3_HOST1_DP/M PHY, please do not delete the magnetic beads and decoupling capacitors in the RK3568

reference schematic.

The USB2_AVDD_0V9, USB2_AVDD_1V8, and USB2_AVDD_3V3 supplies power to the

USB2_HOST2_DP/M and USB2_HOST3_DP/M PHY. Please do not delete the magnetic beads and decoupling

capacitors in the RK3568 chip reference schematic.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-52 RK3568 USB2.0 PHY power pin

 USB3_AVDD_0V9: Peak current 5mA

 USB3_AVDD_1V8: Peak current 30mA

 USB3_AVDD_3V3: Peak current 10mA

 USB2_AVDD_0V9: Peak current 5mA

 USB2_AVDD_1V8: Peak current 30mA

 USB2_AVDD_3V3: Peak current 10mA

It is recommended to use LDO for power supply, PSRR@1KHz should be greater than 65dB, and the power

supply capacity should be more than 200mA.

 0.9V AC requirement: <25mV;

 1.8V AC requirement: <50mV;

 3.3V AC requirement: <200mV;

A stable power supply helps to improve the stability of the chip, and the decoupling capacitors should be

placed close to the pins. Please refer to the schematic for the detailed number and capacity of the capacitors. Please

do not change at will.

Since the firmware of the RK3568 chip must be downloaded from the USB3_OTG0_DP/M interface,

USB3_AVDD_0V9, USB3_AVDD_1V8, USB3_AVDD_3V3 must be powered in the first time power-on.

If USB2_HOST2_DP/M and USB2_HOST3_DP/M are not used, then USB2_AVDD_0V9,

USB2_AVDD_1V8, USB2_AVDD_3V3 could be unpowered, and they are recommended to be grounded. But

attention please: when the PHY is not powered, if the USB controller node corresponding to PHY in the

kernel DTS is not disabled, it will cause to be stuck in the initialization of the USB controller during kernel

initialization.

2.2.2.10 MULTI PHY Power Supply

The RK3568 has three MULTI PHY interfaces:

MULTI_PHY0 is the function multiplexing of USB3.0 OTG0 SS signal and SATA0;

MULTI_PHY1 is the function multiplexing of USB3.0 HOST1 SS signal, SATA1 and QSGMII_M0;

MULTI_PHY2 is the function multiplexing of PCIe2.0, SATA2 and QSGMII_M1;

MULTI_PHY_AVDD_0V9_1, MULTI_PHY_AVDD_0V9_2 and MULTI_PHY_AVDD_1V8 supply power to

MULTI_PHY0, 1, 2, please do not delete the decoupling capacitors in the RK3568 chip reference schematic.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-53 RK3568 MULTI_PHY power pin

 MULTI_PHY_AVDD_0V9: Peak current 150mA

 MULTI_PHY_AVDD_1V8: Peak current 21mA

It is recommended to use LDO for power supply,

 PSRR@1KHz need to >65dB;

 0.9V AC requirement: <20mV, power supply capacity above 250mA;

 1.8V AC requirement: <50mV, power supply capacity above 200mA;

A stable power supply helps to improve the stability of the chip, and the decoupling capacitors should be

placed close to the pins. Please refer to the schematic for the detailed number and capacity of the capacitors. Please

do not change at will.

If MULTI_PHY0/1/2 functions are not used, then MULTI_PHY_AVDD_0V9 and MULTI_PHY_AVDD_1V8

can be powered off, and grounding is recommended.

2.2.2.11 PCIe3.0 PHY Power Supply

The RK3568 has a PCIe3.0 interface.

PCIE30_AVDD_0V9_1, PCIE30_AVDD_0V9_2, and PCIE30_AVDD_1V8 supply power to PCIe3.0 PHY,

please do not delete the decoupling capacitors in the RK3568 chip reference schematic.

Figure 2-54 RK3568 PCIe3.0 PHY power pin

 PCIE30_AVDD_0V9: Peak current 160mA

RK3568 Hardware Design Guide Rev V1.2

 PCIE30_AVDD_1V8: Peak current 60mA

 It is recommended to use LDO for power supply,

 PSRR@1KHz need to >65dB;

 0.9V AC requirement: <20mV, power supply capacity above 250mA;

 1.8V AC requirement: <50mV, power supply capacity above 200mA;

A stable power supply helps to improve the stability of the chip, and the decoupling capacitors should be

placed close to the pins. Please refer to the schematic for the detailed number and capacity of the capacitors. Please

do not change at will.

If the PCIe3.0 function is not used, then PCIE30_AVDD_0V9 and PCIE30_AVDD_1V8 do not need to be

powered. Grounding is recommended.

2.2.2.12 MIPI CSI RX PHY Power Supply

The RK3568 has a MIPI CSI RX interface.

MIPI_CSI_RX_AVDD_0V9, and MIPI_CSI_RX_AVDD_1V8 supply power to MIPI CSI RX PHY, please do

not delete the magnetic beads and decoupling capacitors in the RK3568 chip reference schematic.

Figure 2-55 RK3568 MIPI CSI RX PHY power pin

 MIPI_CSI_RX_AVDD_0V9: Peak current 10mA

 MIPI_CSI_RX_AVDD_1V8: Peak current 2.5mA

 It is recommended to use LDO for power supply,  PSRR@1KHz need to >65dB;  0.9V AC requirement: <20mV, power supply capacity above 200mA;  1.8V AC requirement: <50mV, power supply capacity above 200mA;

A stable power supply helps to improve the stability of the chip, and the decoupling capacitors should be

placed close to the pins. Please refer to the schematic for the detailed number and capacity of the capacitors. Please

do not change at will.

If MIPI CSI RX function is not used, MIPI_CSI_RX_AVDD_0V9 and MIPI_CSI_RX_AVDD_1V8 can be

unpowered, and grounding is recommended.

2.2.2.13 MIPI DSI TX0/LVDS PHY Power Supply

The RK3568 has a MIPI DSI TX0 and a LVDS TX Combo PHY interface.

RK3568 Hardware Design Guide Rev V1.2

MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9 and MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8 supply power to

MIPI DSI TX0 and LVDS TX Combo PHY, please do not delete the magnetic beads and decoupling capacitors in

the RK3568 chip reference schematic.

Figure 2-56 RK3568 MIPI DSI TX0 and LVDS TX Combo PHY power pin

 MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9: Peak current 50mA  MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8: Peak current 15mA

It is recommended to use LDO for power supply,

 PSRR@1KHz need to >65dB;  0.9V AC requirement: <20mV, power supply capacity above 200mA;  1.8V AC requirement: <50mV, power supply capacity above 200mA;

A stable power supply helps to improve the stability of the chip, and the decoupling capacitors should be

placed close to the pins. Please refer to the schematic for the detailed number and capacity of the capacitors. Please

do not change at will.

If MIPI DSI TX0 and LVDS TX functions are not used, MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9 and

MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8 can be powered off, and grounding is recommended.

2.2.2.14 MIPI DSI TX1 PHY Power Supply

The RK3568 has a MIPI DSI TX1 PHY interface.

MIPI_DSI_TX1_AVDD_0V9, and MIPI_DSI_TX1_AVDD_1V8 power supplies which supply power to MIPI

DSI TX1 PHY, please do not delete the magnetic beads and decoupling capacitors in the RK3568 chip reference

schematic.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-57 RK3568 MIPI DSI TX1 PHY power pin

 MIPI_DSI_TX1_AVDD_0V9: Peak current 50mA  MIPI_DSI_TX1_AVDD_1V8: Peak current 15mA

It is recommended to use LDO for power supply,

 PSRR@1KHz need to >65dB;  0.9V AC requirement: <20mV, power supply capacity above 200mA;  1.8V AC requirement: <50mV, power supply capacity above 200mA;

A stable power supply helps to improve the stability of the chip, and the decoupling capacitors should be

placed close to the pins. Please refer to the schematic for the detailed number and capacity of the capacitors. Please

do not change at will.

If MIPI DSI TX1 function is not used, MIPI_DSI_TX1_AVDD_0V9 and MIPI_DSI_TX1_AVDD_1V8 can be

powered off, and grounding is recommended.

2.2.2.15 eDP PHY Power Supply

The RK3568 has an eDP TX PHY interface.

eDP_TX_AVDD_0V9 and eDP_TX_AVDD_1V8 supply power to eDP TX PHY, please do not delete the

decoupling capacitors in the RK3568 chip reference schematic.

Figure 2-58 RK3568 eDP TX PHY power pin

 eDP_TX_AVDD_0V9: Peak current 150mA  eDP_TX_AVDD_1V8: Peak current 100mA

RK3568 Hardware Design Guide Rev V1.2

It is recommended to use LDO for power supply,

 PSRR@1KHz need to >65dB;  0.9V AC requirement: <20mVpower supply capacity above 250mA;  1.8V AC requirement: <50mV, power supply capacity above 200mA;

A stable power supply helps to improve the stability of the chip, and the decoupling capacitors should be

placed close to the pins. Please refer to the schematic for the detailed number and capacity of the capacitors. Please

do not change at will.

If the eDP TX function is not used, then eDP_TX_AVDD_0V9 and eDP_TX_AVDD_1V8 do not need to be

powered, and grounding is recommended.

2.2.2.16 HDMI2.0 PHY Power Supply

The RK3568 has an HDMI2.0 TX PHY interface.

HDMI_TX_AVDD_0V9_1, HDMI_TX_AVDD_0V9_2 and HDMI_TX_AVDD_1V8 supply power to

HDMI2.0 TX PHY, please do not delete the decoupling capacitors in the RK3568 chip reference schematic.

Figure 2-59 RK3568 HDMI2.0 TX PHY power pin

 HDMI_TX_AVDD_0V9: Peak current 25mA  HDMI_TX_AVDD_1V8: Peak current 16mA

It is recommended to use LDO for power supply,

 PSRR@1KHz need to >65dB;  0.9V AC requirement: <20mV, power supply capacity above 200mA;  1.8V AC requirement: <50mV, power supply capacity above 200mA;

A stable power supply helps to improve the stability of the chip, and the decoupling capacitors should be

placed close to the pins. Please refer to the schematic for the detailed number and capacity of the capacitors. Please

do not change at will.

If the HDMI2.0 TX function is not used, then HDMI_TX_AVDD_0V9 and HDMI_TX_AVDD_1V8 do not

need to be powered, they are recommended to be grounded.

2.2.2.17 SARADC/OTP Power Supply

The RK3568 has a SARADC, which can support 8 channels. SARADC_AVDD_1V8 supplies power to

SARADC. Please do not delete the decoupling capacitors in the RK3568 chip reference schematic.

 SARADC_AVDD_1V8: Peak current 1.5mA It is recommended to use LDO for power supply,  PSRR@1KHz should >65dB;

RK3568 Hardware Design Guide Rev V1.2

 1.8V AC requirement: <50mV, power supply capacity above 200mA;

Figure 2-60 RK3568 SARADC and OTP power pin

The RK3568 has an OTP, OTP_VCC18 supplies power to OTP, please do not delete the capacitor in the

RK3568 chip reference schematic.

 OTP_VCC18: Peak current 59mA

LDO or DC/DC can be used to supply power to OTP.

A stable power supply helps to improve the stability of the chip, and the decoupling capacitors should be

placed close to the pins. Please refer to the schematic for the detailed number and capacity of the capacitors. Please

do not change at will.

RK3568 Hardware Design Guide Rev V1.2

RK809-5 Solution Introduction

2.2.3.1 RK809-5 Block Diagram

Figure 2-61 RK809-5 block diagram

2.2.3.2 RK809-5 Features

 Power input range: 2.7V-5.5V  Accurate fuel gauge with two ADC of separate battery voltage and current  Built-in real-time clock (RTC)  Very low standby current of 35uA (at 32KHz clock frequency)

RK3568 Hardware Design Guide Rev V1.2

 Support real ground class-AB PA to drive Head-phone  1.3W Class-D power amplifier without filter inductor  Fixed and programmable optional power start sequence control  Built-in high-performance audio codec

◆ Built-in independent PLL

◆ Support microphone input

◆ Both DAC and ADC support I2S digital input

◆ Support ALC, limiter and noise gate

◆ Support programmable digital and analog gain

◆ Support 16bits-32bits bit rate

◆ Sampling rate up to 192kHz

◆ The software supports two working mode configurations of master and slave

◆ Support three I2S formats (standard, left-aligned, right-aligned)

◆ Support PDM mode (external input PCLK)

 Power channels:

◆ BUCK1: Synchronous step-down DC-DC converter, 2.5A max

◆ BUCK2: Synchronous step-down DC-DC converter, 2.5A max

◆ BUCK3: Synchronous step-down DC-DC converter, 1.5A max

◆ BUCK4: Synchronous step-down DC-DC converter, 1.5A max

◆ BUCK5: Synchronous step-down DC-DC converter, 2.5A max

◆ LDO1-LDO2, LDO4~LDO9: Low-dropout linear regulator, 400mA max

◆ LDO3: Low-noise and high PSRR low-dropout linear regulator, 100mA max

◆ Switch1: Switch, 2.1A max, Rdson=90 mohm

◆ Switch2: Switch, 2.1A max, Rdson=100 mohm

 Package: 7mmx7mm QFN68

RK3568 Hardware Design Guide Rev V1.2

2.2.3.3 RK3568+RK809-5 Power Tree

Figure 2-62 RK3568 and RK809-5 power tree

2.2.3.4 RK809-5 Power-on Sequence

The power-on sequence of RK809-5 has been solidified and cannot be changed. Note that the power-on

sequence of RK809-5 is different with the power-on sequence of RK809-1, RK809-2 and RK809-3, and cannot be mixed.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-63 RK809-5 power-on sequence

RK3568 Hardware Design Guide Rev V1.2

2.2.3.5 Notices of RK809-5

 Please select the load capacitance of 32.768KHz crystal according to the CL capacitance value of the

crystal actually used. It is recommended to choose the capacitance not less than 18pF. If the load

capacitance is too low, it may cause unstable start-up. The recommended value is 22pF.

Note

In order to reduce the power consumption, the crystal oscillation of the PMIC RTC is relatively weak. Using an ordinary

oscilloscope on the XOUT or XIN pins cannot detect the oscillation signal, or the oscilloscope probe will stop oscillation when it touches it. Please test the CLK32K pin for the 32.768k signal.

 VCC_RTC (Pin45) of RK809-5: It is the internal digital logic, part of analog control and RTC clock

power supply pin of RK809 chip. The design of this pin requires that the power supply voltage must be

the highest voltage among all the power supply pins of RK809-5 or be greater than Vmax-0.3V (except

for VCC_SPK_HP power supply), so VCC_RTC must be powered on first, or powered on together with

other power supplies. It is not allowed to supply other power sources before VCC_RTC.

It is recommended to connect the same power supply with VCC9 (Pin54) of RK809-5;

 If you need button batteries to save the real-time clock, it is recommended to use an external RTC IC. The

RTC current of RK809-5 is about 35~50μA, and when an external RTC IC is used as the real-time clock,

and you need time alarm clock PowerOn function, please contact Rockchip to provide the reference

circuit. The built-in RTC of RK809-5 supports time alarm clock PowerOn function. To use an external

RTC IC, you must confirm whether its IO level matches the power supply voltage of the RTC chip;  Pin 67 (RESETB) of RK809-5 needs a 100nF capacitor to improve the anti-interference ability and

cannot be deleted at will.  The SDA\SCL\INT\CLK32K\RESETB GPIOs of PMIC RK809-5 are open-drain output, and their

highest allowable input voltage is the voltage of VCC_RTC, they need to add pull-up resistors externally

or use the pull-up resistors inside RK3568 IO. SCL\SDA\SLEEP\PWRON\RESETB as input VL\VH are

fixed to 0.4V\1.26V.  If Gas Gauge is not used, it is recommended that Pin56 (BATDIV), Pin62 (SNSP), and Pin63 (SNSN) are

grounded. If you want to enable it, please contact Rockchip to provide a reference circuit.  I2S: The VCCIO of pin LRCK\BCLK\MCLK\SDI\PDMCLK are connected to LDO4, so LDO4 is

generally allocated to the power domain where the I2S of the controller is located for power supply at the

same time.  The DC-DC inductor reference value of RK809-5 is: inductance 0.47μH, saturation current above 3.5A,

DCR less than 50mΩ (in order to achieve better conversion efficiency, it is recommended to choose DCR

less than 20mΩ).  The input capacitance of BUCK1/BUCK2 of RK809-5 must be greater than 10μF, and the output

capacitance must be greater than 30μF to ensure a better decoupling effect, especially in the case of high

current and high dynamic load, the output decoupling capacitor can be appropriately increased;  The input capacitance of BUCK3 of RK809-5 must be greater than 10μF, and the output capacitance must

be greater than 30μF to ensure a better decoupling effect. The output voltage value is determined by the

RK3568 Hardware Design Guide Rev V1.2

external resistor, and the voltage value must be matched according to the DDR model used in the project.

The reference voltage is 0.8V. Select the voltage-dividing resistor RH=(VBUCK3-0.8)*RL/0.8, RH and

RL are the voltage-dividing pull-up resistor and pull-down resistor respectively, the resistor value is

recommended to be between 10KΩ and 1MΩ, and the accuracy is 1%. It is recommended to refer to the

parameters provided by the reference design.  The input capacitance of BUCK4 of RK809-5 must be greater than 10μF, and the output capacitance must

be greater than 30μF to ensure a better decoupling effect, especially in the case of high current and high

dynamic load, the output decoupling capacitor can be appropriately increased;  The input capacitance of BUCK5 of RK809-5 must be greater than 10μF, and the output capacitance must

be greater than 33μF to ensure a better decoupling effect, especially in the case of high current and high

dynamic load, the output decoupling capacitor can be appropriately increased;  LDO power supply: VCC5\VCC6\VCC7 are the LDO power supply input pin, which support at least 2V

input, but the output current will drop to 50% of the rated output when 2V is input.  VCC9: is not only the power supply input pin of VSWOUT1 and BUCK5, but is also the chip

under-voltage and over-voltage protection detection pin. If the voltage of VCC9 is lower than 3.0V after

power-on, it will automatically shut down.  RK809-5 power on and off conditions:

VDC boot process:

 VCC_RTC has powered and must be greater than 3.0V;

 The value of VDC pin is higher than 0.55V, and the recommended value is about 1.2V;

 EXT_EN outputs high level;

 VCC9 needs to exceed 3.0V within 1.5ms of EXT_EN output high level, otherwise it will not turn

on;

 Start the power-on process, each DC/DC, LDO is powered on according to the sequence;

 After starting up, VDC can be pulled down or kept at high level without affecting the starting state.

Power Key boot process:

 VCC_RTC has be powered and must be greater than 3.0V;

 PWRON pin are pulled down by more than 500ms;

 EXT_EN outputs high level;

 VCC9 needs to exceed 3.0V within 1.5ms of EXT_EN output high level, otherwise it will not turn

on;

 Start the power-on process, each DC/DC, LDO is powered on according to the sequence.

Alarm boot process:

 VCC_RTC has be powered and must be greater than 3.0V;

 Alarm timing time is up, and turn on the timing boot function;

 EXT_EN outputs high level;

 VCC9 needs to exceed 3.0V within 1.5ms of EXT_EN output high level, otherwise it will not turn

on;

 Start the power-on process, each DC/DC, LDO is powered on according to the sequence.

RK3568 Hardware Design Guide Rev V1.2

Shut down:

 VCC9 voltage is lower than the under voltage design value;

 I2C command shutdown;

 Over temperature protection shutdown (145 degrees);

 Press and hold Power Key for more than six seconds to force shutdown.

2.2.3.6 RK809-5 Design Description

Please refer to RK PMIC related design document "AN_RK809_V1.1" for detailed design instructions of

RK809-5.

Discrete Power Supply Solution Introduction

2.2.4.1 Power Tree of RK3568+Discrete Power（Based NVR_DEMO）

Mainly for products with low requirements of standby power.

Figure 2-64 RK3568 + discrete power architecture

RK3568 Hardware Design Guide Rev V1.2

2.2.4.2 Power-on and Power-off Sequence of Discrete Power

Figure 2-65 Discrete power power-on sequence

The power-on sequence of each power supply of RK3568 chip: in theory, follow the low-voltage first,

high-voltage second, and after the last one voltage is stable, RESETn can be released after at least 10ms;

Power-off sequence: During power-off, RESETn must be pulled down first, and then each power supply can

be powered off. If there is a product that needs to be powered on and off quickly, pay attention to the discharge time

of the capacitor. If the power is not completely powered off and then powered on again, it may cause the system to

work abnormally; In addition, if you use SPI Flash, it is recommended to use a reset IC with a threshold of 2.93V,

when the power supply of the SPI Flash drops to 2.93V, the reset must be pulled low first to prevent the SPI Flash

data error caused by the out-of-control and disoperation of the under-voltage logic during the power down process.

2.2.4.3 Notices of Discrete Power Supply

 VDD_CPU uses dynamic voltage and frequency regulation. It is not recommended to use together with

other power supplies. Please refer to the reference design for BUCK model requirements, and using I2C

voltage regulation. If you have to replace with other models, the BUCK with a power supply capacity of

≥4A can be selected. If it is not I2C voltage regulation, PWM can be used for voltage regulation. Please

refer to the reference design for voltage regulation parameters, the voltage regulation range is 0.8-1.2V,

and the default voltage is about 0.938V (note that the software configuration must be filled in according

to actual values, otherwise, inaccurate voltage regulation will occur). Other requirements of BUCK are as follows:

1）The output voltage accuracy is required to be ±1.5%; 2）BUCK transient response requirements: I

load

=BUCK Max current*10%-BUCK Max current*80% jump,

slope 1A/μs, ripple requirement within ±5%.

The input capacitance of BUCK must be greater than 22μF, and the output capacitor has to meet the

requirement of VDD_CPU power supply with a total capacitance greater than 135μF (it is recommended to reserve

one or two 22μF capacitors, which can be leave floating by default), to ensure that the power supply ripple is within

RK3568 Hardware Design Guide Rev V1.2

80mV, then avoid large power supply ripples under heavy load conditions

 VDD_GPU and VDD_NPU adopt dynamic voltage and frequency regulation, they can be used together

for power supply according to different cases, and for example, when it is not sensitive to working power

consumption. Please refer to the reference design for selecting BUCK models. If you have to replace with

other models, the power supply capacity of the BUCK should be ≥3A and use PWM for voltage

regulation, please refer to the reference design for voltage regulation parameters, the voltage regulation

range is 0.81-1.1V, and the default voltage is about 0.92V (note that the software configuration must be

filled in according to the actual values, otherwise, inaccurate voltage regulation will occur).

Other requirements of BUCK are as follows: 1）The output voltage accuracy is required to be ±1.5%; 2）BUCK transient response requirements: Iload=BUCK Max current*10%-BUCK Max current*80% jump,

slope 1A/μs, ripple requirement within ±5%.

The input capacitance of BUCK must be greater than 10μF, and the output capacitor should meet the

requirement of VDD_GPU and VDD_NPU power supply with a total capacitance greater than 135μF (it is

recommended to reserve one or two 22μF capacitors, which cannot be attached by default), to ensure that the power

supply ripple is within 60mV, then avoid large power supply ripples under heavy load conditions.

 VDD_LOGIC defaults to a fixed voltage of about 0.92V, and it is reserved for dynamic voltage

adjustment. It is not recommended to combine with other power supplies. The BUCK model requires

refer to the reference design. If you need to replace other models, you need to select a BUCK with a

power supply capacity of ≥1.5A, reserved PWM voltage regulation, the voltage regulation parameters can

refer to the reference design, the voltage adjustment range is 0.81-1.0V, and the default voltage is about

0.92V (note that the software configuration must be filled in according to the actual, otherwise the

voltage adjustment problem will be inaccurate).

Other requirements of BUCK are as follows:

1）The output voltage accuracy is required to be ±1.5%; 2）BUCK transient response requirements: Iload=BUCK Max current*10%-BUCK Max current*80% jump,

slope 1A/μs, ripple requirement within ±5%.

The input capacitance of BUCK must be greater than 10μF, and the output capacitor needs to meet the

requirement of VDD_LOGIC power supply with a total capacitance greater than 99μF (it is recommended to

reserve 1-2 22μF capacitors, which can be hanged up by default), to ensure that the power supply ripple is within 60mV, then avoid large power supply ripples under heavy load conditions.

 VCC_3V3 power-on sequence must meet the requirements, and the MOS control circuit is not

allowed to be deleted;

 The reset IC must be an open-leakage output, which is active at low level. The power supply of the reset

IC needs to be connected to VCC3V3_PMUIO, which is the same as the power supply of PMUIO1.

Standby Control Circuit

If the product requires low-power standby, it is recommended to use the RK809-5 power supply solution. The following introduces the standby PMIC_SLEEP control circuit using RK809-5:

RK3568 Hardware Design Guide Rev V1.2

When the RK3568 chip is in the normal working mode, the state pin PMIC_SLEEP of the chip will maintain a

low level output.

When the system enters the standby mode, the PMIC_SLEEP pin will output a high-level sleep indicator

signal. At this time, the PMIC is controlled by the signal to enter the standby state. According to the configuration

of the software dts file, part of the power supplies will be turned off, and some of the power supplies will be

lowered.

When the system is awakened from the standby mode, the PMIC_SLEEP pin will output a low level for the

first time. At this time, the PMIC will resume the working state before standby and restore the power output of each

channel.

PMIC_SLEEP is a special function signal, please do not change the usage at will.

Figure 2-66 RK3568 PMIC_SLEEP output

Figure 2-67 RK809-5 PMIC_SLEEP input

Figure 2-68 The PMIC_SLEEP input of VDD_CPU BUCK

Power Peak Current Table

The following data is the peak current of each module, they are used for evaluating power supply solution and

PCB Layout, and they are used for reference only.

Note: It cannot be simply added up as the peak current of SOC. Please evaluate the heat dissipation solution

according to the average current of the actual scenes.

RK3568 Hardware Design Guide Rev V1.2

Table 2–14 RK3568 peak current table

Power Name

Voltage（V）

Peak Current(mA)

PMUPLL_AVDD_0V9

0.9

PMUPLL_AVDD_1V8

1.8 9 SYSPLL_AVDD_0V9

0.9

SYSPLL_AVDD_1V8

1.8

PMU_VDD_LOGIC_0V9

0.9

VDD_CPU

DVFS

3000

VDD_GPU

DVFS

1200

VDD_NPU

DVFS

1000

VDD_LOGIC

0.9

1200

DDRPHY_VDDQ

1.1/1.2/1.35/1.5

TBD

DDRPHY_VDDQL

0.6/1.1/1.2/1.35/1.5

TBD

USB3_AVDD_0V9

0.9

USB3_AVDD_1V8

1.8

USB3_AVDD_3V3

3.3

USB2_AVDD_0V9

0.9 5 USB2_AVDD_1V8

1.8

USB2_AVDD_3V3

3.3

MULTI_PHY_AVDD_0V9

0.9

150

MULTI_PHY_AVDD_1V8

1.8

PCIE30_AVDD_0V9

0.9

160

PCIE30_AVDD_1V8

1.8

MIPI_CSI_RX_AVDD_0V9

0.9

MIPI_CSI_RX_AVDD_1V8

1.8

2.5

MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9

0.9

MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8

1.8

MIPI_DSI_TX1_AVDD_0V9

0.9

MIPI_DSI_TX1_AVDD_1V8

1.8

eDP_TX_AVDD_0V9

0.9

150

eDP_TX_AVDD_1V8

1.8

100

HDMI_TX_AVDD_0V9

0.9

HDMI_TX_AVDD_1V8

1.8

SARADC_AVDD_1V8

1.8

1.5

OTP_VCC18

1.8

PMUIO0

1.8

TBD

PMUIO1

3.3

TBD

PMUIO2/VCCIO1/2/3/4/5/6/7/

1.8/3.3

TBD

RK3568 Hardware Design Guide Rev V1.2

2.3 Functional Interface Circuit Design Guide

SDMMC0/1/2

The RK3568 integrates three SDMMC controllers, all of which support SD V3.01 and MMC V4.51 protocols. SDMMC0 and SDMMC1 support up to 200MHz, and SDMMC2 only support up to 150MHz.

2.3.1.1 SDMMC0 Interface

 SDMMC0 interface is multiplexed in the VCCIO3 power domain;  Support System Boot, default allocation of SD card function;  SDMMC0 is multiplexed with JTAG and other functions, functions selection is realized through the state

of SDMMC0_DET by default. Please refer to the introduction in the section 2.1.5 for details;

 VCCIO3 power supply, need external 3.3V or 1.8V power supply,

When connecting an SD card: if it only supports SD2.0 mode: it can directly supply 3.3V power; If you want

to support SD3.0 mode compatible with SD2.0 mode: default 3.3V power supply, after negotiating with SD card to

run SD3.0 mode, the power supply voltage needs to be switched to 1.8V power supply, RK809-5 LDO5 supplies power to VCCIO3 alone, so this process can be achieved.

When connected a SDIO device: supply 1.8V or 3.3V according to the peripherals and the actual operating

mode.

Figure 2-69 RK3568 SDMMC0 interface pin

 When the board-to-board connection is realized through the connector, it is recommended to connect a

certain resistance resistor in series (between 22ohm-100ohm, as long as it can meet the SI test), and reserve TVS devices.

 When using SD card, pay attention to the following items:

 The supply voltage of VDD pin of the SD card is 3.3V, and the decoupling capacitors are not

allowed to be deleted. Place them close to the connector when layout.

 SDMMC0_D [3:0], SDMMC0_CMD, SDMMC0_CLK need to be connected to a 22ohm resistor in

RK3568 Hardware Design Guide Rev V1.2

series, and SDMMC0_DET to be connected to a 100ohm resistor in series;

 You have to add ESD device when SDMMC0_D [3:0], SDMMC0_CMD, SDMMC0_CLK,

SDMMC0_DET signals are close the SD card position. If it requires to support SD3.0 mode, the

junction capacitance of the ESD device must be less than 1pF. And if it only requires to support

SD2.0 mode, the junction capacitance of the ESD device can be extended to 9pF.

Figure 2-70 SD card interface circuit

 SDMMC0 interface pull-up and pull-down and matching design recommendations are shown in the

Table:

Table 2–15 SDMMC0 interface design

Signal

Internal pull-up

and pull-down

Connection mode

Description (chipset)

SDMMC0_D[3:0]

pull up

connect a 22ohm resistor in series,

use the corresponding IO internal

pull-up resistor

SD data send/receive

SDMMC0_CLK

pull down

connect a 22ohm resistor in series

SD clock send

SDMMC0_CMD

pull up

connect a 22ohm resistor in series,

use the corresponding IO internal

pull-up resistor

SD command

send/receive

SDMMC0_DET

pull up

connect a 100ohm resistor in

series,

use the corresponding IO internal

pull-up resistor

SD card insertion

detection

2.3.1.2 SDMMC1 Interface

 SDMMC1 interface is multiplexed in the VCCIO4 power domain;  Does not support System Boot, default allocate to SDIO WIFI function;  VCCIO4 power supply, supplies 1.8V or 3.3V according to the peripheral and the actual operating mode,

need to be consistent with the peripheral IO. For the SD card function, pay attention to the power domain voltage,

the requirements same as SDMMC0;

RK3568 Hardware Design Guide Rev V1.2

Figure 2-71 RK3568 SDMMC1 interface pin

 SDMMC1 interface pull-up and pull-down and matching design recommendations are shown in the

Table:

Table 2–16 SDMMC1 interface design

Signal

Internal

pull-up and

pull-down

Connection mode

Description (chipset)

SDMMC1_D[3:0]

pull up

connect a 22ohm resistor in series which can be deleted

when the trace is short;

use the corresponding IO

internal pull-up resistor

SD data send/receive

SDMMC1_CLK

pull down

connect a 22ohm resistor in

series

SD clock send

SDMMC1_CMD

pull up

connection a 22ohm resistor in series which can be deleted when the trace is

short;

use the corresponding IO

internal pull-up resistor

SD command

send/receive

 When connecting SDIO WIFI, you need to consider a low-power standby solution, that is, when using

VDD_LOGIC standby and power-off solution, then the relevant control pins of SDIO WIFI need to be

moved to the PMUIO1/2 power domain. After VDD_LOGIC is powered off, the IO status of

VCCIO1/2/3/4/5/6/7 power domain cannot be maintained.

 When the board-to-board connection is realized through the connector, it is recommended to connect a

certain resistance resistor in series (between 22ohm-100ohm, as long as it can meet the SI test), and reserve TVS devices.

2.3.1.3 SDMMC2 Interface

 The SDMMC2 interface is multiplexed in two power domains, one is in the VCCIO5 power domain and

RK3568 Hardware Design Guide Rev V1.2

the other is in the VCCIO6 power domain. Only one of them can be used: either all using VCCIO5 power

domain or all using VCCIO6 power domains; in other words, it is not supported that some using VCCIO5

power domain and the rest using VCCIO6 power domain;

 Does not support System Boot;  Using VCCIO5 or VCCIO6 to supply 1.8V or 3.3V power according to the peripheral and the actual

operating mode, and it should be consistent with the peripheral IO. For the SD card function, pay

attention to the power domain voltage, please refer to SDMMC0 for detailed requirements;

Figure 2-72 RK3568 SDMMC2 interface M0 functional pins

RK3568 Hardware Design Guide Rev V1.2

Figure 2-73 RK3568 SDMMC2 interface M1 functional pins

 SDMMC2 interface pull-up and pull-down and matching design recommendations are shown in the

Table:

Table 2–17 SDMMC2 interface design

Signal

Internal pull-up

and pull-down

Connection mode

Description (chipset)

SDMMC2_D[3:0]

pull up

connect a 22ohm resistor in series which can be deleted

when the trace is short;

use the corresponding IO

internal pull-up resistor

SD data send/receive

SDMMC2_CLK

pull down

connect a 22ohm resistor in

series

SD clock send

SDMMC2_CMD

pull up

connect a 22ohm resistor in series which can be deleted

when the trace is short;

use the corresponding IO

internal pull-up resistor

SD command

send/receive

 When the board-to-board connection is realized through the connector, it is recommended to connect a

certain resistance resistor in series (between 22ohm-100ohm, as long as it can meet the SI test), and reserve TVS devices.

2.3.1.4 Notice of SDIO WIFI Interface

 Please ensure that the IO level of the module is consistent with the IO level of CPU, otherwise, level

RK3568 Hardware Design Guide Rev V1.2

matching processing is required.

 The crystal load capacitance should be selected according to the CL capacitance value of the crystal

actually used, and the frequency tolerance at room temperature should be controlled within 10ppm.

 The antenna reserves a π-type circuit for antenna matching adjustment.  Confirm the connection direction of PCM and UART interface, such as IN and OUT, TXD and RXD.  If you use a module that requires 32.768k clock input, please pay attention to the clock amplitude.  The schematic design is compatible with multiple modes. In the process of SMT, you must select

according to the actual used module, and do not do SMT at will.

SARADC Circuit

 The RK3568 integrates a SARADC controller, which can provide 8 SARADC inputs.  The SARADC_VIN0 of the RK3568 chip is used as the key value input sampling port by default, and is

multiplexed as the Recovery mode button (cannot be modified). SARADC_VIN0 is pulled up to

VCCA_1V8 through a 10Kohm pull-up resistor, and the default voltage is high voltage (1.8V). Under the

premise that there is no key action and the system has burned the firmware, power on and directly enter

the system; if the Recovery mode button has been pressed when the system is started, that is,

SARADC_VIN0 is kept at low level (0V), RK3568 enters Loader flashing mode. When the PC

recognizes the USB device, release the button to restore SARADC_VIN0 to high level (1.8V) for

flashing firmware. Therefore, when a product without buttons, if SARADC_VIN0 is left hanged up, it

will be unstable, which may affect booting. Therefore, the 10Kohm pull-up resistor of SARADC_VIN0

must be reserved and cannot be deleted to ensure the default normal booting judgment. In addition, for

the convenience of development, it is recommended to reserve keys or test points.

Figure 2-74 SARADC VIN0 interface

 On RK3568, the SARADC sampling range is 0-1.8V, with 10 bits sampling accuracy. The key array is in

parallel, and the input key value can be adjusted by increasing or decreasing the keys and adjusting the

ratio of the voltage-dividing resistance, so as to realize multi-key input to meet requirements of different

customer products. In the process of design, it is recommended that the sampling value of any two keys

must be greater than +/-35, that is, the center voltage difference must be greater than 123mV.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-75 RK3568 SARADC module

 Pay attention to the following items in RK3568 SARADC design:

 The decoupling capacitors of the SARADC_AVDD_1V8 power supply must not be deleted, and

they should be placed close to the RK3568 pin during layout.

 When SARADC_VIN [7:0] is used, a 1nF capacitor must be added close to the pin to eliminate

jitter.

 When it is used for button collection, ESD protection is required close to the button, and the button

with 0 key value must be connected in series with a 100ohm resistor to strengthen the anti-static

surge capability (if there is only one button, ESD components must be close to the button, first pass

ESD components 100ohm resistor1nF chip pin).

Figure 2-76 The button circuit using SARADC sampling

RK3568 Hardware Design Guide Rev V1.2

OTP Circuit

 The RK3568 integrates an 8Kbit OTP, 7Kbit can be used for security applications.  Support write, read and idle mode, in these modes, OTP_VCC18 pin must be powered.  The decoupling capacitor of the OTP_VCC18 power supply must not be deleted. Place it close to the

RK3568 pin during layout.

Figure 2-77 RK3568 OTP power pin

USB2.0/USB3.0 Circuit

There are one USB3.0 OTG controller, one USB3.0 HOST controller, and two USB2.0 HOST controllers in

RK3568, see the pink and green boxes as below:

 The USB SS signal of the USB3.0 OTG controller uses MULTI_PHY0, and the USB LS/FS/HS signal

uses USB2.0 OTG0 PHY.

 The USB SS signal of the USB3.0 HOST controller uses MULTI_PHY1, and the USB LS/FS/HS signal

uses USB2.0 HOST1 PHY.

 Two USB2.0 HOST controllers use USB2.0 HOST2 PHY and USB2.0 HOST3 PHY respectively.

Figure 2-78 Multiplexing relationship between MULTI_PHY0/1and USB3.0 controllers

RK3568 Hardware Design Guide Rev V1.2

 In the USB3.0 OTG0 controller, the USB LS/FS/HS mode signal uses USB2.0 OTG0 PHY, and the USB

SS mode signal uses MULTI_PHY0 (multiplexed with the SATA0 controller). The signals in the box

below form a complete USB3.0 OTG0 interface, other combinations are not supported;

If you only need USB2.0 interface, just select the DP/DM signal, and MULTI_PHY0 can be configured

as SATA0 function.

Figure 2-79 USB3.0 OTG0 pin

Note

Only USB3_OTG0_DP and USB3_OTG0_DM support downloading firmware. If a product does not use this interface, it must be

reserved during debugging and production process. Note: USB3_OTG0_VBUSDET must also be connected.

 In the USB3.0 HOST1 controller, the USB LS/FS/HS mode signal uses USB2.0 HOST1 PHY, and the

USB SS mode signal uses MULTI_PHY1 (multiplexed with the SATA1 controller and the QSGMII

controller). The signals in the box below form a complete USB3.0 HOST1 interface, other combinations

are not supported;

If you only need USB2.0 interface, just select the DP/DM signal, and MULTI_PHY1 can be configured

as SATA1 or QSGMII function.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-80 USB3.0 HOST1 pin

 The USB2.0 HOST2 controller uses USB2.0 HOST2 PHY, the signals in the box below form the USB2.0

HOST2 interface.

Figure 2-81 USB2.0 HOST2 pin

 The USB2.0 HOST3 controller uses USB2.0 HOST3 PHY, the signals in the box below form the USB2.0

HOST3 interface.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-82 USB2.0 HOST3 pin

 Pay attention to the following items in USB2.0/USB3.0 design:

 Only USB3_OTG0_DP/USB3_OTG0_DM is the system firmware flashing port. If a product does

not use this port, this port must be reserved during the debugging and production process, otherwise,

firmware flashing is disabled during debugging and production process.

 There is an internal about 200Kohm resistor in USB3_OTG0_ID to pull up to USB3_AVDD_1V8;  USB3_OTG0_VBUSDET is the OTG and Device mode detection pin, high effective, 2.7-3.3V, TYP:

3.0V, it is recommended to place a 100nF capacitor on the pin.

OTG mode can be set to the following three modes:  OTG mode: it can switch to device mode or HOST mode according to the status of the ID pin

automatically. When ID pin is pulled high, it is device mode, and when ID pin is pulled low, it is HOST mode.

When in device mode, it will also judge whether the VBUSDET pin is high. If it is high, DP will be pulled up

and enumeration will start.

 Device mode: When set to this mode, ID pin is not needed, just judge whether the VBUSDET pin is

high, if it is high, DP will be pulled up and enumeration will start.

 HOST mode: When set to this mode, there is no need to care about ID and VBUSDET status. (If the

product only needs HOST mode, but only USB3_OTG0_DP/USB3_OTG0_DM is the system firmware

flashing port, and this port is needed during debugging and production. So when flashing and adb debugging,

it needs to be set to device mode, the USB3_OTG0_VBUSDET signal must also be connected).

 Before uboot is up, it is device mode by default. After entering uboot, you can configure these three

modes according to actual needs.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-83 RK3568 VBUSDET and ID Circuit

 USB3_AVDD_0V9, USB2_AVDD_0V9, USB3_AVDD_1V8, USB2_AVDD_1V8 power pins and

VDDA_0V9, VCCA_1V8 are required to be isolated by magnetic beads, please refer to the reference diagram/ schematic design for the details;

Figure 2-84 USB2.0 PHY power supply magnetic bead isolation circuit

 In order to improve the USB performance, the decoupling capacitors of each power supply of the

PHY must not be deleted. Please place them close to the pins during layout;

 In order to strengthen the anti-static and surge capability, ESD devices must be reserved on signal.

The ESD parasitic capacitance of the USB2.0 signal cannot exceed 3pF. In addition, the DP/DM of the USB2.0 signal is connected in series with a 2.2ohm resistor to strengthen the anti-static surge capability, it cannot be deleted. The following figure is an example of USB2_HOST2_DP/DM, other USB2.0 interfaces also need to be processed in the same way;

RK3568 Hardware Design Guide Rev V1.2

Figure 2-85 USB2.0 signal is connected in series with a 2.2ohm resistor

 In order to suppress electromagnetic radiation, you can consider to reserve a common mode choke

on the signal line. In the debugging process, you can choose to use a resistor or a common mode choke according to the actual situation. The diagram below is an example of USB2_HOST2_DP/DM, other USB2.0 interfaces also need to be processed in the same way;

Figure 2-86 USB2.0 signal is connected in series with common mode choke circuit

 If the USB3_OTG0_ID signal is used, in order to strengthen the anti-static and surge capability,

ESD devices must be reserved on the signal, and a 100ohm resistor must be connected in series, which cannot be deleted. See the following diagram:

Figure 2-87 USB OTG ID pin circuit

 For the HOST function, it is recommended to add a current-limiting switch for the 5V power supply.

The current-limiting size can be adjusted according to application needs. The current-limiting switch is controlled by GPIO, it is recommended to add more than 100μF and 100nF capacitor for the 5V power supply.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-88 USB 5V current-limiting circuit

 It requires to add a 100nF AC coupling capacitor to the SSTXP/N line in the USB 3.0 protocol.

The AC coupling capacitor is recommended to use 0201 package for lower ESR and ESL and fewer impedance changes on the line.

 All signals of the USB3 connector must be added with ESD devices which should be placed close to

the USB connector. For SSTXP/N, SSRXP/N signals, the ESD parasitic capacitance must not

exceed 0.4pF.

Figure 2-89 USB3.0 ESD circuit

 MULTI_PHY_AVDD_0V9/1V8 power supply pins should be placed 4.7μF and 100nF decoupling

capacitors, which must not be deleted. Place them close to the RK3568 pin during layout.

Figure 2-90 MULTI PHY power supply decoupling circuit

 USB2.0/USB3.0 interface matching design recommendations are shown in the following Table.

RK3568 Hardware Design Guide Rev V1.2

Table 2–18 RK3568 USB2.0/USB3.0 interface design

Signal

Connection mode

Description

USB3_OTG0_DP/DM

Connect 2.2ohm resistor in series

data input and output in USB

HS/FS/LS mode

USB3_OTG0_SSTXP/SSTXN

Connect a 100nF capacitor in series

(0201 package is recommended)

data output in USB SS mode

USB3_OTG0_SSRXP/SSRXN

Connect 0ohm resistor in series

data input in USB SS mode

USB3_OTG0_ID

Connect a 100ohm resistor in series (to strengthen the external power supply, the power supply needs to be connected to the same power supply as

USB3_AVDD_1V8)

USB OTG ID recognition, required for

Micro-USB interface USB3_OTG0_VBUSDET

Resistance voltage-dividing detection

USB OTG insertion detection

USB3_HOST1_DP/DM

Connect 2.2ohm resistor in series

data input and output in USB

HS/FS/LS mode

USB3_HOST1_SSTXP/SSTXN

Connect a 100nF capacitor in series

(0201 package is recommended)

data output in USB SS mode USB3_HOST1_SSRXP/SSRXN

Connect 0ohm resistor in series

data input in USB SS mode

USB3_HOST2_DP/DM

Connect 2.2ohm resistor in series

data input and output in USB

HS/FS/LS mode

USB3_HOST3_DP/DM

Connect 2.2ohm resistor in series

data input and output in USB

HS/FS/LS mode

SATA3.0 Circuit

There are three SATA3.0 controllers in RK3568, see the blue box below, using MULTI_PHY0/1/2

respectively.

 Support SATA PM function, each port can support 5 devices.  Support SATA 1.5Gb/s, SATA 3.0Gb/s, SATA 6.0Gb/s speeds.  Support eSATA.

Figure 2-91 MULTI_PHY0/1/2 and SATA3.0 controller multiplexing relationship

RK3568 Hardware Design Guide Rev V1.2

 The SATA0 controller uses MULTI_PHY0 (multiplexed with USB3.0 OTG0 controller).

 The SATA1 controller uses MULTI_PHY1 (multiplexed with USB3.0 HOST1 and QSGMII controller).

 The SATA2 controller uses MULTI_PHY2 (multiplexed with PCIe2.0 and QSGMII controller).

 The related control IOs of SATA0/1/2 controller:

SATA0_ACT_LED: LED blinking control output when SATA0 interface has data transmission; SATA1_ACT_LED: LED blinking control output when SATA1 interface has data transmission; SATA2_ACT_LED: LED blinking control output when SATA2 interface has data transmission; SATA_CP_DET: Plug in and out detection input of SATA hot-plug device SATA_MP_SWITCH: Switch detection input of SATA hot-plug device SATA_CP_POD: Power switch output of SATA hot-plug device

SATA_CP_DET, SATA_MP_SWITCH, SATA_CP_POD are multiplexed with SATA0/1/2 interfaces,

which can be configured by register to be SATA0, SATA1 or SATA2.

RK3568 Hardware Design Guide Rev V1.2

Figure 2-92 SATA0/1/2 related control IO pins

 Pay attention to the following items in SATA design:

 When designing the slot, the peripheral circuit and power supply should meet the requirements of

Spec.

 MULTI_PHY_AVDD_0V9/1V8 power supply pins should add 4.7μF and 100nF decoupling

capacitors, which must not be deleted. Place them close to the RK3568 pin during layout.

 10nF AC coupling capacitors connected in series on the TXP/N, RXP/N differential signals of

SATA interface. The AC coupling capacitor is recommended to use 0201 package for lower ESR and ESL and fewer impedance changes on the line.

 ESD devices must be added to all signals of the eSATA interface connector, Place them close to the

RK3568 Hardware Design Guide Rev V1.2

connector during layout. The ESD parasitic capacitance cannot exceed 0.4pF.

 SATA interface matching design recommendations are shown in the following Table.

Table 2–19 RK3568 SATA interface design

Signal

Connection mode

Description

SATA0_TXP/TXN

Connect a 10nF capacitor in series (0201 package is recommended)

SATA data output

SATA0_RXP/RXN

Connect a 10nF capacitor in series (0201 package is recommended)

SATA data input

SATA1_TXP/TXN

Connect a 10nF capacitor in series (0201 package is recommended)

SATA data output

SATA1_RXP/RXN

Connect a 10nF capacitor in series (0201 package is recommended)

SATA data input

SATA2_TXP/TXN

Connect a 10nF capacitor in series (0201 package is recommended)

SATA data output

SATA2_RXP/RXN

Connect a 10nF capacitor in series (0201 package is recommended)

SATA data input

QSGMII/SGMII Circuit

There is one QSGMII or SGMII interface in RK3568.

 SGMII (Serial Gigabit Media Independent Interface) converts the RGMII or RMII interface between

gigabit MAC and gigabit PHY into a serial interface. Using a SGMII interface is to reduce the

number of pins required for the RGMII interface, and the rate of SGMII interface is 1.25Gbps.

 QSGMII (Quad Serial Gigabit Media Independent Interface) is an extension of SGMII. QSGMII

interface transfers data between a 4-port gigabit MAC and a 4-port gigabit PHY via a serial line

running at a 5Gbps rate. Each Port can run at a 10/100/1000Mbps rate, but RK3568 has only two

gigabit MACs inside, that is to say, it can only support 2 Port 10/100/1000Mbps interface via the

QSGMII interface.

 QSGMII interface of RK3568 is compatible with SGMII.  GMAC0/GMAC1 controller used by QSGMII/SGMII and RGMII/RMII interface from MUX to IO

are multiplexed.

 QSGMII/SGMII PCS interface is multiplexed to two PHY interfaces: MULTI_PHY1 and MULTI_PHY2,

but only one of the PHY interfaces can be used.

The paths of GMAC0, GMAC1, QSGMII/SGMII PCS and QSGMII/SGMII PHY are shown in the

following diagram with green lines.

Rockchip RK3568 Design Guide

Specifications and Main Features

Frequently Asked Questions

User Manual

Preface

Revision History

Acronyms

Contents

Figures

Tables

1 System Introduction

1.1 Overview

1.2 Block Diagram

1.3 Application Block Diagram

RK3568 EVB Application Block Diagram

RK3568 Smart NVR Application Block Diagram

2 Schematic Design Recommendation

2.1 Minimum System Design

Clock Circuit

Reset/watchdog/TSADC Circuit

PMU Circuit

System Boot Sequence

System Initialization Configuration Signal

JTAG and UART Debug Circuit

DDR Circuit

2.1.7.1 DDR Controller Introduction

2.1.7.2 Circuit Design Suggestion

2.1.7.3 DDR Peripheral Circuit Design

2.1.7.4 DDR Topology and Matching Design

2.1.7.5 DDR Power Design and Power up Sequence Requirement

2.1.7.6 DDR Support List

eMMC Circuit

2.1.8.1 eMMC Controller Introduction

2.1.8.2 eMMC Circuit Design Suggestion

2.1.8.3 eMMC Topology and Matching Method Design

2.1.8.4 eMMC Power up Sequence Requirement

2.1.8.5 eMMC Support List

FSPI Flash Circuit

2.1.9.1 FSPI Flash（Boot is supported）Interface Introduction

2.1.9.2 FSPI Flash Circuit Design Suggestion

2.1.9.3 FSPI Flash Topology and Matching Design

2.1.9.4 FSPI Power up Sequence Requirement

2.1.9.5 SPI Flash Support List

Nand Flash Circuit

2.1.10.1 Nand Flash Controller Introduction

2.1.10.2 Nand Flash Circuit Design Suggestion

2.1.10.3 Nand Flash Topology and Matching Design

2.1.10.4 Nand Flash Power up Sequence Requirement

2.1.10.5 Nand Flash Support List

GPIO Circuit

2.1.11.1 GPIO Pins Description

2.1.11.2 GPIO Drive Capability

2.1.11.3 GPIO Power

2.2 Power Supply Design

RK3568 Power Supply Introduction

2.2.1.1 Power Supply Requirements of RK3568

2.2.1.2 Power-on Sequence Requirements of RK3568

2.2.1.3 Power-off Sequence Requirements of RK3568

Power Supply Design Suggestion

2.2.2.1 Power-on and Standby Circuit Scheme

2.2.2.2 PLL Power Supply

2.2.2.3 PMU LOGIC Power Supply

2.2.2.4 CPU Power Supply

2.2.2.5 GPU Power Supply

2.2.2.6 NPU Power Supply

2.2.2.7 Logic Power Supply

2.2.2.8 DDR Power Supply

2.2.2.9 USB2.0 PHY Power Supply

2.2.2.10 MULTI PHY Power Supply

2.2.2.11 PCIe3.0 PHY Power Supply

2.2.2.12 MIPI CSI RX PHY Power Supply

2.2.2.13 MIPI DSI TX0/LVDS PHY Power Supply

2.2.2.14 MIPI DSI TX1 PHY Power Supply

2.2.2.15 eDP PHY Power Supply

2.2.2.16 HDMI2.0 PHY Power Supply

2.2.2.17 SARADC/OTP Power Supply

RK809-5 Solution Introduction

2.2.3.1 RK809-5 Block Diagram

2.2.3.2 RK809-5 Features

2.2.3.3 RK3568+RK809-5 Power Tree