Rockchip RK3568 Schematic

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REF Schematic for RK3568
Main Functions Introduction
1)PMIC: RK809-5+DiscretePower
2)RAM: DDR4 2x16Bit------------------Default
D D
Option:LPDDR4/4x 1X32bit(200ball) Option:DDR3 4x16bit
Option:DDR3 4x16bit+2x16bit ECC
Option:DDR4 2x16bit+1x16bit ECC Option:LPDDR3 1x32bit(178ball) Option:DDR4 4x16bit
3)ROM: eMMC--------------------------Default
Option:Nand Flash Option:SPI Flash
4)Support:1 x Micro SD Card3.0
5)Support:1 x USB3.0 OTG0 + 1 x USB3.0 HOST1 + 1 x SATA3.0 Port2 ----------------------------------------------------Default
Option:1 x USB3.0 OTG0 + 1 x USB3.0 HOST1 + 1 x 1Lane PCIe2.0(RC Mode) Option:1 x USB3.0 OTG0 + 1 x USB2.0 HOST1 + 1 x SATA3.0 Port1 + 1 x SATA3.0 Port2
C C
B B
A A
Option:1 x USB3.0 OTG0 + 1 x USB2.0 HOST1 + 1 x SATA3.0 Port1 + 1 x 1Lane PCIe2.0(RC Mode) Option:1 x USB2.0 OTG0 + 1 x SATA3.0 Port0 + 1 x USB3.0 HOST1 + 1 x SATA3.0 Port2
Option:1 x USB2.0 OTG0 + 1 x SATA3.0 Port0 + 1 x USB3.0 HOST1 + 1 x 1Lane PCIe2.0(RC Mode)
Option:1 x USB2.0 OTG0 + 1 x SATA3.0 Port0 + 1 x USB2.0 HOST1 + 1 x SATA3.0 Port1 + 1 x SATA3.0 Port2 Option:1 x USB2.0 OTG0 + 1 x SATA3.0 Port0 + 1 x USB2.0 HOST1 + 1 x SATA3.0 Port1 + 1 x 1Lane PCIe2.0(RC Mode)
7)Support:4G module Via MiniPCIe2.0 Slot With PCIE2.0 and USB2.0 HOST3 function ------Option
Option:1 x 2Lanes PCIe3.0 Connector (RC Mode) Option:1 x 2Lanes PCIe3.0 Connector (EP Mode)
9)Support:1 x HDMI2.0 TX
10)Support:1 x LCM MIPI DSI TX0 -----------------------Default
Option:1 x LCM MIPI DSI TX1 Option:1 x LCM LVDS TX Option:1 x LCM Dual MIPI DSI TX Option:1 x LCM eDP TX
11)Support:1 x VGA OUT --------------------------------Default
12)Support:1 x 4Lanes Camera MIPI CSI RX --------------Default
Option:2 x 2Lanes Camera MIPI CSI RX Option:1 x HDMI1.4 RX(HDMI to MIPI CSI)
13)Support:a/b/g/n/ac 2X2 SDIO WIFI5+BT5.0+PCM --------Default
Option:a/b/g/n/ac 1X1 SDIO WIFI+BT+PCM Option:a/b/g/n/ac/ax 2X2 PCIe WIFI6+BT5.0+PCM
14)Support:1 x 10/100/1000M Ethernet(RGMII1_M1) -------Default
Option:1 x 10/100/1000M Ethernet(RGMII0) or 1 x 10/100M Ethernet(RMII0) Option:1 x 10/100/1000M PCIe Ethernet Card or 2 x 10/100/1000 Ethernet(QSGMII) or 1 x 10/100/1000 Ethernet(SGMII)
15)Support:1 x Headphone output -----------------------Default
16)Support:1 x ECM MIC + 1 x Speaker out -------------Default
Option:4 x MEMS MIC + 1 x Speaker out + Loopback or 2 x MEMS MIC + 1 x Speaker out + Loopback Option:4 x MEMS MIC + 2 x Speaker out + Loopback
17)Support:1 x IR Receiver ----------------------------Default
18)Support:Array Key(MENU,VOL+,VOL-,ESC),Reset,Power on/off Key
19)Support:3 x UART + 1 x RS485 + 1 x CAN FD(Option)
20)Support:Debug UART and ARM JTAG
Rockchip Confidential
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Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
00.Cover Page
00.Cover Page
00.Cover Page
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Designed by:
2
Designed by:
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
1
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
1 72
Sheet: of
1 72
Sheet: of
1 72
Page 2
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Table of Content
Page 1 Page 2 Page 3 Page 4
D D
Page 5 Page 6 Page 7 Page 8 Page 9 Page 10 Page 11 Page 12 Page 13 Page 14 Page 15 Page 16 Page 17 Page 18 Page 19
C C
Page 20 Page 21 Page 22 Page 23 Page 24 Page 25 Page 26 Page 27 Page 28 Page 29 Page 30 Page 31 Page 32 Page 33
B B
Page 34 Page 35 Page 36 Page 37 Page 38 Page 39 Page 40 Page 41 Page 42 Page 43 Page 44 Page 45 Page 46 Page 47
A A
Page 48 Page 49 Page 50 Page 51 Page 52 Page 53
Rockchip Confidential
00.Cover Page
01.Index and Notes
02.Revision History
03.Block Diagram
04.Power Diagram
05.Power Sequence
06.IO Power Domain Map
07.UART Map/GMAC0/1 Path Map
08.I2C Bus Map
09.PCIE30/MULTI_PHY/VOP Fun Map
10.RK3568_Power/GND
11.RK3568_DDR PHY
12.RK3568_OSC/PLL/PMUIO
13.RK3568_Flash/SD Controller
14.RK3568_USB/PCIe/SATA PHY
15.RK3568_SARADC/GPIO
16.RK3568_VI Interface
17.RK3568_VO Interface_1
18.RK3568_VO Interface_2
19.RK3568_Audio Interface
20.Power_DC IN
21.Power_PMIC
22.Power_Ext Discrete/RTC IC
23.Power_Flash Power Manage
25.USB2/USB3 Port
31.DRAM-DDR3_4X16Bit_96P
32.DRAM-DDR3_4X16+ECC_2X16_96P
33.DRAM-DDR4_2x16bit_96P
34.DRAM-DDR4_4x16Bit_96P
35.DRAM-DDR4_96P_2X16+ECC_1X16
36.DRAM-LPDDR3_1X32bit_178P
38.DRAM-LPDDR4X_1X32bit_200P
40.Flash-eMMC Flash
41.Flash-Nand Flash
42.Flash-MicroSD Card
43.Flash-SPI Flash
45.VI-Camera_Power
47.VI-Camera_MIPI_CSI_1x 4Lanes
Default Default Default Default Default Default Default Default Default Default Default Default Default Default Default Default Default Default Default Default Default Default Default Default Default
Option Option
Default
Option Option Option Option
Default
Option
Default
Option
Default Default
48.VI-Camera_MIPI_CSI_2x 2Lanes Option
49.VI-HDMI1.4 RX(To MIPICSI RX)
50.VO-HDMI2.0 TX
52.VO-LCM_MIPI_DSI_TX0/TX1
53.VO-LCM_Dual MIPI_DSI TX
54.VO-LCM_LVDS TX
56.VO-LCM_eDP TX
58.TP Connector_COF
59.VO-VGA Output(eDP To VGA)
60.WIFI/BT-SDMMC1_1T1R + UART
62.WIFI/BT-SDMMC1_2T2R + UART
64.WIFI6/BT-PCIe_2T2R + UART
Option
Default Default
Option Option Option
Default Default
Option
Default
Option Option65.Ethernet-FEPHY_RMII0
67.Ethernet-GEPHY_RGMII0
Option
68.Ethernet-GEPHY_RGMII1_M1 Default
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Page 54 Page 55 Page 56 Page 57 Page 58 Page 59 Page 60 Page 61 Page 62 Page 63 Page 64 Page 65 Page 66 Page 67 Page 68 Page 69 Page 70 Page 71 Page 72
69.Ethernet-PCIE Ethernet Option
70.Audio-Headphone Port
Default
71.Audio-SingleMic+RK809_SPK Default
72.Audio-MicArray+RK809_SPK Option
74.Audio-MicArray+EXT Dual_SPK
82.SATA-SATA3.0 Slot_7P
83.PCIE-PCIE2.0_1x1Lane_RC_36P
84.PCIE-PCIE3.0_1x2Lanes_RC_64P
85.PCIE-PCIE3.0_2x1Lane_RC_32P
86.PCIE-PCIE3.0_1x2Lanes_EP_64P
87.MiniPCIe2.0 Slot_With 4G Fun
88.Ethernet-GEPHY_SGMII
89.Ethernet-GEPHY_QSGMII
90.IR Receiver
91.Debug UART
92.KEY Array/SARADC
93.LED/HW_ID/BOM_ID
95.UART/RS485/CAN Port
99.Mark/Hole/Heatsink
Option
Default
Option Option
Default
Option Option Option Option
Default Default Default Default Default
Default Page 73 Page 74 Page 75 Page 76
Generate Bill of Materials
Header:
Item\tPart\tDescription\tPCB Footprint\tReference\tQuantity\tOption
Combined property string:
{Item}\t{Value}\t{Description}\t{PCB Footprint}\t{Reference}\t{Quantity}\t{Option}
Notes
NOTE 1 Component parameter description
1. DNP stands for component not mounted temporarily
2. If Value or option is DNP, which means the area is reserved without being mounted
NOTE 2: Please use our recommended components to avoid too many changes. For more informations about the second source,please refer to our AVL.
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Description
Note
Option
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
01.Index and Notes
01.Index and Notes
01.Index and Notes
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
Default
Default
Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
2 72
Sheet: of
2 72
Sheet: of
2 72
Page 3
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Revision History
4
3
2
1
Version
D D
V1.0
V1.1 2021-06-11 Zhangdz 1:Change content Please Refer to
Date By Change Dsecription Approved
1:Revision preliminary version2021-02-04 Zhangdz
RK3568_AIoT_REF_SCH_V11_20210611_Modify_Notes
C C
B B
A A
Rockchip Electronics Co., Ltd
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Rockchip Electronics Co., Ltd
Project:
Project:
Rockchip Confidential
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Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
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3
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
02.Revision History
02.Revision History
02.Revision History
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Default
Default
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
3 72
Sheet: of
3 72
Sheet: of
3 72
Page 4
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RK3568 Ref Block Diagram(Default configuration)
Debug UART2
IR Receiver
DC/DC
12V Adapter
D D
RK809-5
32.768KHz
PMIC+Codec
Speaker Max 1.3W
SKP OUT HP OUTMIC
Power Key
PCIe3.0 x1
C C
RC Mode
PCIe3.0 x1
RC Mode
SATA3.0
USB3.0 HOST1
USB3.0 OTG0
B B
VGA OUT Port
SS
SS
3.3V
Headphone
Power for RK3568
I2S1
32.768KHz OUT
I2C0/Sleep/INT
RESETn
1 Lane
1 Lane
eDP to VGA
PWM3_IR
UART2
Reset Key
I2C1
PMUIO2
OSC
2 Lane
SATA2
USB3_HOST1_SS
USB3_OTG0_SS
USB2_HOST1_LS/FS/HS
USB2_OTG0_LS/FS/HS
eDP
SDMMC0 x 4bit
24MHz
SDMMC1 x 4bit
UART1/PCM2
SARADC_IN0
PCIE3.0
MULTI_ PHY2
MULTI_ PHY1
MULTI_ PHY0
USB2 OTG0 HOST1
eDP
VCCIO3
VCCIO4
SARADC VCCIO2
HDMI2.0 TX
HDMI2.0 TX
PCIE2.0 SATA2 QSGMII_M1
USB3_HOST1 SATA1 QSGMII_M0
USB3_OTG0 SATA0
CEC HDMI_I2C HPD
4 Lane MIPI DSI or LVDS
MIPI DSI TX1
x 4 Lane
MIPI CSI RX
TMDS
MIPI DSI LVDS TX0
x 4 Lane
Rockchip
RK3568
Quad A55
DDR DQ8-15
VCCIO1
_B
Panel
VCCIO7 VCCIO5PMUIO1
DDR DQ0-7 _B
TP I2C1
CEC HDMI_I2C HPD
VCCIO6
USB2 HOST2 HOST3
DDR ECC DQ0-7
DDR DQ8-15 _A
DDR DQ0-7 _A
DDR PHY CA/CLK
Camera
I2C2
I2C2
RGMII1_M1
HOST2_LS/FS/HS
HOST3_LS/FS/HS
UART3 UART4 RS485
RS485
DDR4 16bit
UART7
RJ-45
Giga PHY
USB2.0 HOST2
USB2.0 HOST3
Micro SD Card
Micro SD Card
x 8bit
I2S1 I2C3
DDR4 16bit
2.4/5GHz
2.4/5GHz
A A
WIFI/BT
802.11 a/b/g/n/ac
BT5.0
Keys
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eMMC
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
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2
Designed by:
Rockchip Electronics Co., Ltd
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
03.Block Diagram
03.Block Diagram
03.Block Diagram
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Zhangdz
Zhangdz
Zhangdz
1
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
Sheet: of
Sheet: of
4 72
4 72
4 72
Page 5
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Default Power Diagram
12V Adapter
D D
VCC3V3_SYS
3000mADC/DC
Max:
RK809-5
VCC1
VCC2
VCC3
VCC4
VCC5
C C
VCC6
VCC7
VCC8
VCC9
B B
VCC_RTC
VCC5V0_SYS
A A
BUCK1
0.5V~2.4V, 2.5A max
BUCK2
0.5V~2.4V, 2.5A max
BUCK3
0.5V~2.4V, 1.5A max
BUCK4
0.5V~3.4V, 1.5A max
LDO1
0.6V~3.4V, 400mA max
LDO2
0.6V~3.4V, 400mA max
LDO3
0.6V~3.4V, 100mA max
LDO4(Codec VDDIO)
0.6V~3.4V, 400mA max
LDO5
0.6V~3.4V, 400mA max
LDO6
0.6V~3.4V, 400mA max
LDO7
0.6V~3.4V, 400mA max
LDO8
0.6V~3.4V, 400mA max
LDO9
0.6V~3.4V, 400mA max
Switch2
2.1 A max, Rdson=100mΩ
Switch1
2.1 A max, Rdson=90mΩ
BUCK5:
1.5V~3.6V, 2.5 A max
EXT DC/DC ,5A
EXT LDO ,0.3A
Seq:0
Power on Sequence
Seq:1
Seq:2
Seq:3
OFF
OFF
Seq:1
Seq:1
OFF
Seq:4
Seq:2
Seq:2
Seq:2
OFF
Seq:4
Seq:4
Seq:2
Seq:2A
Seq:2A
4
VDD_LOGIC
Max:
VDD_GPU
Max:
VCC_DDR
Max:
VDD_NPU
Max:
VDDA0V9_IMAGE
Max:
VDDA_0V9
Max:
VDDA0V9_PMU
Max:
VCCIO_ACODEC
Max:
VCCIO_SD
Max:
VCC3V3_PMU
Max:
VCCA_1V8
Max:
VCCA1V8_PMU
Max:
VCCA1V8_IMAGE
Max:
VCC3V3_SD
Max:
VCC_3V3
Max:
VCC_1V8
Max:
VDD_CPU
Max:
VCC2V5_DDR
Max:
VCC3V3_SYS
RK3568_Logic
RK3568_GPU
RK3568_DDRC DRAM
RK3568_NPU
VCCIO1--I2S1/PDM MIC/PDM ADC
VCCIO3--SDMMC0
PMUIO1/ PMUIO2
PMUPLL_AVDD_1V8 VCC1V8_DDR
Micro SD Card
RK3568_CPU
DDR4 DRAM
LCD Panel
Mos-->
Mos-->VCC3V3_VGA
Mos-->
RK628D
VDDA0V9_IMAGE
VDDA0V9_PMU
VCCA_1V8
Max:
Max:
Max:
Max:WIFI/BT VBAT
Max:LDO-->Camera 1.2V
Max:LDO-->Camera 1.8V
Max:RTC IC
VCC_3V3
VCC_1V8
3
MOS
DC/DC 3000mA
DC/DC 3000mA
DC/DC 3000mA
DC/DC 3000mA
MIPI_CSI_RX_AVDD_0V9
MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9
MIPI_DSI_TX1_AVDD_0V9
EDP_TX_AVDD_0V9
HDMI_TX_AVDD_0V9
PMU_VDD_LOGIC_0V9
PMUPLL_AVDD_0V9
SYSPLL_AVDD_1V8
USB2_AVDD_1V8
USB3_AVDD_1V8
MULTI_PHY_AVDD_1V8
PCIE30_AVDD_1V8
SARADC_AVDD_1V8
USB3_AVDD_3V3
USB2_AVDD_3V3
VCCIO5,VCCIO7
eMMC_VCC
VCC3V3_PHY0/1/2
VCC3V3_TP
IR Receiver
UART Device
RS485 Device
CAN IC
OTP_VCC18
VCCIO2(Default) --eMMC/Nand IO
VCCIO4(Default)
VCCIO6(Default)
GiGa PHY0/1 IO-Option
WIFI/BT IO
Nand_VCC
/
OFF
Seq:0
Seq:0
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
VCC5V0_USB
Max:
VCC5V0_SYS
Max:
VCC3V3_PCIE
Max:
VCC3V3_MINIPCIE
Max:
VDDA_0V9
VCCA1V8_IMAGE
2
PCIe Slot
SATA
SATA
USB HOST
RK809_SPK_PA
MOS
LDO
LDO Max:
VCC5V0_VGA
VCC3V3_PI6C
Camera 2.8V
1
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:DDR VTT
LCM Backlight
MOS
VCC5V_HDMI_TX
CAN transceiver IC
Max:
Max:
Max:
Max:EXT SPK PA
EXT DC/DC Max:VCC1V05_QS_VDDL
EXT DC/DC Max:VCC3V3_QS_VDDH
SYSPLL_AVDD_0V9
USB2_AVDD_0V9
USB3_AVDD_0V9
MULTI_PHY_AVDD_0V9
PCIE30_AVDD_0V9
MIPI_CSI_RX_AVDD_1V8
MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8
MIPI_DSI_TX1_AVDD_1V8
EDP_TX_AVDD_1V8
HDMI_TX_AVDD_1V8
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:
Max:VCC18_LCD(Option)
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Designed by:
Rockchip Electronics Co., Ltd
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
04.Power Diagram
04.Power Diagram
04.Power Diagram
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Zhangdz
Zhangdz
Zhangdz
1
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
Sheet: of
Sheet: of
5 72
5 72
5 72
Page 6
5
4
3
2
1
Power Sequence
VCC12V_DCIN
VCC3V3_SYS
VCC5V0_SYS
D D
VCC5V0_USB
VDDA0V9_PMU
VDDA_0V9
VDD_LOGIC
VDD_GPU
VCCA1V8_PMU
VCCA_1V8
VCC_1V8
VCC3V3_PMU
C C
VCC2V5_DDR
VDD_CPU
VCC_DDR
VCC_3V3
Power description
Power Supply
VCC3V3_SYS RK809_BUCK1 2.5A
VCC3V3_SYS RK809_BUCK2 2.5A
VCC3V3_SYS RK809_BUCK3 1.5A VCC_DDR Slot:3 ADJ ON TBDTBD
VCC3V3_SYS RK809_BUCK4 1.5A VDD_NPU TBDTBD
VCC3V3_SYS RK809_LDO2 0.4A TBDTBD
VCC3V3_SYS RK809_LDO5 0.4A TBDTBD
VCC3V3_SYS RK809_LDO8 0.4A TBDTBD
VCC3V3_SYS RK809_SW2
VCC3V3_SYS
VCC12V_DCIN
VCC5V0_SYS EXT BUCK 6.0A
VCC3V3_SYS EXT LDO 0.3A VCC 2V5_DDR 2.5V ON TBDTBD
PMIC Channel
RK809_LDO1 0.4A VDDA0V9_IMAGE 0.9V TBDTBD
RK809_LDO3 0.1A VDDA0V9_PMU Slot:1 0.9V ON TBDTBD
RK809_LDO4 0.4A VCC IO_ACODEC N/A 3.3V TBDTBD
RK809_LDO6 0.4A
RK809_LDO7 0.4A VCC A_1V8 1.8V ON TBDTBD
RK809_LDO9 0.4A
100mohm
RK809_SW1 VCC_3V3 3.3V ON TBDTBD
90mohm
RK809_BUCK5
RK809_RESETn
EXT BUCK 3.0A
Supply Limit
2.1A
2.1A
2.5A VCC _1V8 1.8V ON TBDTBD
3.0A
Power Name
VDD_LOGIC
VDD_GPU
VDDA_0V9 Slot:1 0.9V ON
VCCIO_SD 3.3V ONSlot:4
VCC3V3_PMU
VCCA1V8_PMU Slot:2 1.8V ON
VCCA1V8_IMAGE 1.8VOFFN/A
VCC3V3_SD
VCC3V3_SYS
VCC5V0_SYS Slot:0
VDD_CPU
Time Slot
Slot:1 0.9V ON TBD TBD
Slot:2 0.9V ON TBD TBD
N/A OFF
N/A
Slot:2
Slot:2
Slot:4
Slot:4
Slot:2
Slot:4+5
Slot:0 3.3V
Slot:2A
Slot:2A
Default Voltage
FB=0.8V
0V
0V
0V
3.3V ON
0V
3.3V ON TBDTBD
5.0V
1.025V ON TBDTBD
Default
ON/OFF
OFF
OFF
ON
ONVCC12V_DCIN EXT BUCK
Work Voltage
0.9V
DVFS
1.2V
(DDR4)
DVFS
0.9V
0.9V
3.3V or 1.8V
(SD2.0=3.3V,SD3.0=1.8V)
3.3V
1.8V
1.8V
3.3V
3.3V
1.8V
3.3V
5.0V
DVFS
2.5V
Peak Current
TBD TBD
TBD
Sleep Current
TBDTBD
TBDTBD
TBD
VCCIO_SD
VCC3V3_SD
RESETn
VDD_NPU
VDDA0V9_IMAGE
VCCA1V8_IMAGE
B B
VCCIO_ACODEC
A A
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05.Power Sequence
05.Power Sequence
05.Power Sequence
Rockchip Confidential
5
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Designed by:
4
3
2
Designed by:
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
1
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
6 72
Sheet: of
6 72
Sheet: of
6 72
Page 7
5
IO Power Domain Map
4
3
If IO domain power voltage is adjusted, the software DTS configuration must be updated synchronously, otherwise the IO may be damaged!
2
1
Support
IO Domain
D D
PMUIO0 Pin Y21
(PMUPLL_AVDD_1V8)
PMUIO1
PMUIO2
VCCIO1
VCCIO2
C C
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
B B
Pin Num
Pin Y20
Pin W19
Pin H17
Pin H18
Pin L22
Pin J21
Pin V10 Pin V11
Pin R9 Pin U9
Pin V12
IO Voltage
3.3V 1.8V
Notes
PMUIO0 are fixed 1.8V level mode, which cannot be configured.
PMUIO1 are fixed 3.3V level mode, which cannot be configured.
PMUIO2 supports 1.8V or 3.3V level mode
Support configurable but require that their hardware power supply voltages must be consistent with the software configuration correspondingly.[2]
VCCIO1 supports 1.8V or 3.3V level mode
Support configurable but require that their hardware power supply voltages must be consistent with the software configuration correspondingly.[2]
VCCIO2 supports 1.8V or 3.3V level mode
Default is configured by hardware,namely PIN "FLASH_VOL_SEL" state determines which mode to work in.[1][2]
VCCIO3 supports 1.8V or 3.3V level mode
Support configurable but require that their hardware power supply voltages must be consistent with the software configuration correspondingly.[2][3]
VCCIO4 supports 1.8V or 3.3V level mode
Support configurable but require that their hardware power supply voltages must be consistent with the software configuration correspondingly.[2]
VCCIO5 supports 1.8V or 3.3V level mode
Support configurable but require that their hardware power supply voltages must be consistent with the software configuration correspondingly.[2]
VCCIO6 supports 1.8V or 3.3V level mode
Support configurable but require that their hardware power supply voltages must be consistent with the software configuration correspondingly.[2]
VCCIO7 supports 1.8V or 3.3V level mode
Support configurable but require that their hardware power supply voltages must be consistent with the software configuration correspondingly.[2]
Default IO Domain Voltage
Supply Power Net Name
VCCA1V8_PMU VCCA1V8_PMU
VCC3V3_PMU
VCC3V3_PMU
VCCIO_ACODEC 3.3V
VCCIO_FLASH
VCCIO_SD
VCCIO4
VCC_3V3
VCCIO6
VCC_3V3
Power Source
VCC3V3_PMU
VCC3V3_PMU
VCCIO_ACODEC
VCC_1V8
VCCIO_SD
VCC_1V8
VCC_3V3
VCC_1V8
VCC_3V3
Voltage
1.8V
3.3V
3.3V
1.8V
3.3V
1.8V
3.3V
1.8V
3.3V
For example, the VCCIO4 hardware has been modified to 3.3V power supply, and the corresponding DTS must be modified to 3.3V configuration, otherwise the IO of VCCIO4 will be damaged.
If a board needs to be compatible with two voltage choices, recommended to enable BOM ID
Notes
[1]:When VCCIO2 voltage is connected to 1.8V, FLASH_VOL_SEL must be high When VCCIO2 voltage is connected to 3.3V, FLASH_VOL_SEL must be low If VCCIO2 power supply voltage and FLASH_VOL_SEL fails to meet the above relationship, its function will be abnormally(for example, it cannot be started normally) or IO will be damaged.
[2]:When the IO domain power supply voltage is 1.8V, the IO domain voltage configuration in DTS must be set to 1.8V mode. If it is misconfigured to 3.3V mode, the IO function of this power domain will be abnormally; When the IO domain power supply voltage is 3.3V, the IO domain voltage configuration in DTS must be set to 3.3V mode. If it is misconfigured to 1.8V mode, the IO in this power domain will be in overvoltage state, and the IO will be damaged after long-term operation.
[3]:When VCCIO3 IO domain is assigned as SD card function,: If SD3.0 mode is to be supported, VCCIO3 power supply voltage must be support configurable, 3.3V in SD2.0 mode and 1.8V in SD3.0 mode. If only SD2.0 mode is supported (SD3.0 card only works in SD2.0 mode), VCCIO3 only needs fixed power supply of 3.3V. When VCCIO3 IO domain is assigned as other function,: Such as uart5 and uart6, then note [2] should be followed
A A
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Project:
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06.IO Power Domain Map
06.IO Power Domain Map
06.IO Power Domain Map
Rockchip Confidential
5
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Designed by:
4
3
2
Designed by:
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
1
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
7 72
Sheet: of
7 72
Sheet: of
7 72
Page 8
5
4
3
2
1
Default UART Map
GMAC0/1 Path Map
Rockchip Confidential
RK3568
UART0
D D
UART1
UART2
UART3
C C
UART4
UART5
Mux
Mux
Mux
Mux
Mux
M0
M1
M0
M1
M0
M1
M0
M1
M0
M1
UART1_M0
UART2_M0
UART3_M1
UART4_M1
BT
Debug UART2 Port
M0
UART6
B B
Mux
M1
UART6_M1
If no MicroSD Card function
M0
UART7
UART8
A A
UART9
Mux
M1
UART7_M1 RS485
M2
M0
Mux
M1
M0
M1
Mux UART9_M1
M2
5
RS485
Note:
M0 M1 M2 indicates that the same function is multiplexed to different IO When selecting, only M0 or M1 or M2 can be selected eg:Not supported UART1_TX_M0 and UART1_RX_M1 combination
X0
XX0
UART1_TX_M0 UART1_RX_M0
UART1
4
Mux
UART1_TX_M1 UART1_RX_M1
XXX0
X2
XX2
XXX2
3
Mux Mux
GPIO3_D7
Mux
X1
XX1
XXX1
X3
XX3
XXX3
2
Mux
GPIO2_B4GPIO2_B3
GPIO3_D6
It is suitable for other interfaces
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07.UART Map/GMAC0/1 Path Map
07.UART Map/GMAC0/1 Path Map
07.UART Map/GMAC0/1 Path Map
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
1
Default
Default
Default
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Sheet: of
V1.1
V1.1
V1.1
8 72
8 72
8 72
Page 9
5
4
3
2
1
VCC3V3_PMU
Default I2C Map
Note:
M0 M1 M2 indicates that the same function is multiplexed to different IO. When selecting, only M0 or M1 or M2 can be selected
D D
eg: Not supported I2C1_SCL_M0 and I2C1_SDA_M1 combination
RK3568
I2C0
I2C1
I2C0_SCL_PMIC I2C0_SDA_PMIC
Rate:
I2C1_SCL I2C1_SDA
VCC3V3_PMU
PMIC RK809-5
I2C add = 0x20
Touch Panel
I2C add = TBD
TCS4525
I2C add = 0x1C
Rate:
M0
VCC_1V8
I2C2
Mux
M1
I2C2_SCL I2C2_SDA
Camera
I2C add = TBD
Rate:
C C
M0
VCC_3V3
I2C3
Mux
M1
I2C3_SCL_M1 I2C3_SDA_M1
RK628D
I2C add = 0X50
ES7202
I2C add = 0X30/31/32
Rate:
M0
B B
I2C4
Mux
M1
VCC_3V3
M0
I2C5_SCL_M0 I2C5_SDA_M0
HYM8563TS
I2C add = 0x51
RTD2166
I2C add = TBD
Rate:
I2C5
Mux
M1
A A
VCC_3V3 VCC5V0_SYS
HDMI Port
Rockchip Confidential
5
I2C_HDMI
I2C add = TBD
HDMI_SCL HDMI_SDA
Rate: 50KHz
4
Voltage Level
3
2
Project:
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File:
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Date:
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RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
08.I2C Bus Map
08.I2C Bus Map
08.I2C Bus Map
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
Zhangdz
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
9 72
Sheet: of
9 72
Sheet: of
9 72
Page 10
5
4
3
2
1
MULTI_PHY0/1/2 Path Map
USB2.0 HOST2 Controller
USB2.0 HOST3 Controller
D D
USB2.0 HOST2 PHY
USB2.0 HOST3 PHY
USB2.0 OTG0 PHY
VOP Path Map
Port0 4096/30bit
MUX HDMI2.0 TX
MUX
MIPI DSI TX0
USB2.0 HOST1 PHY
USB3_OTG0 Controller
USB2_OTG0
USB3_OTG0
SATA3.0 Controller 0
USB3_HOST1 Controller
USB2_HOST1
USB3_HOST1
SATA3.0 Controller 1
MUX
MUX
MULTI_PHY0
MULTI_PHY1
VOP
Port1 2048/24bit
Port2 2048/24bit
MUX
MUX
MUX
MUX
MIPI DSI TX1
eDP TX
LVDS TX
RGB888 TX
QSGMII Controller
C C
SATA3.0 Controller 2
MUX
MULTI_PHY2
MUX
MUX
BT1120 TX
BT656 TX
PCIE2.1 Controller
USB3.0 OTG0 USB3.0 HOST1
USB3.0 OTG0_HS/FS/LS
SS
MULTI_PHY0 USB3.0
B B
OTG0_SS
USB3.0 OTG0
PCIe3.0 PHY
PCIE30_TX0
PCIE30_RX0
PCIE30_TX1
PCIE30_RX1
PCIE30_TX0
PCIE30_RX0
PCIE30_TX1
PCIE30_RX1
Option1
PCIe3.0 x2Lane
PCIE30_REFCLK (RC/EP:input)
PCIe3.0
Option2
x1Lane +
PCIE30_REFCLK (RC:input)
PCIe3.0 x1Lane
A A
PCIE30X2_CLKREQn PCIE30X2_WAKEn PCIE30X2_PERSTn PCIE30X2_BUTTONRSTn
PCIE30X2_CLKREQn PCIE30X2_WAKEn PCIE30X2_PERSTn PCIE30X2_BUTTONRSTn
PCIE30X1_CLKREQn PCIE30X1_WAKEn PCIE30X1_PERSTn PCIE30X1_BUTTONRSTn
RC or EP
Only RC
Only RC
PCIe2.1 PHY
MULTI_ PHY2
PCIe2.1 x1Lane
PCIE20_REFCLK (RC:output)
Rockchip Confidential
5
PCIE20_TX
PCIE20_RX
PCIE20_CLKREQn PCIE20_WAKEn PCIE20_PERSTn PCIE20_BUTTONRSTn
4
Only RC
3
USB3.0 HOST0_HS/FS/LS
MULTI_PHY1 USB3.0 HOST1_SS
PCIe3.0 REFCLK-RC Mode
100MHz
PCIe Clock Generator IC
25MHz
100MHz
100MHz
RK3568
PCIe Slot
PCIe Slot
PCIe2.1 REFCLK-RC Mode
100MHz
RK3568
PCIe Slot
2
SS
USB3.0 HOST1
PCIe3.0 REFCLK-EP Mode
PCIe RC Device
100MHz
RK3568
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09.PCIE30/MULTI_PHY/VOP Fun Map
09.PCIE30/MULTI_PHY/VOP Fun Map
09.PCIE30/MULTI_PHY/VOP Fun Map
Date:
Wednesday, J une 16, 2021
Date:
Wednesday, J une 16, 2021
Date:
Wednesday, J une 16, 2021
Designed by:
Designed by:
Designed by:
Zhangdz
Zhangdz
Zhangdz
1
Reviewed by:
Reviewed by:
Reviewed by:
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
10 72
Sheet: of
10 72
Sheet: of
Default
Default
Default
10 72
Page 11
5
RK3568_ABCDE (Power&Gnd)
U1000A
VDD_CPU_1
D D
C C
RK3568
B B
BGA636_19R00X19R00X1R20
U1000D
A A
RK3568
BGA636_19R00X19R00X1R20
VDD_CPU_2 VDD_CPU_3 VDD_CPU_4 VDD_CPU_5 VDD_CPU_6 VDD_CPU_7 VDD_CPU_8 VDD_CPU_9
VDD_CPU_10
VDD_CPU_COM
VDD_LOGIC_1 VDD_LOGIC_2 VDD_LOGIC_3 VDD_LOGIC_4 VDD_LOGIC_5 VDD_LOGIC_6 VDD_LOGIC_7 VDD_LOGIC_8 VDD_LOGIC_9
VDD_LOGIC_10
VDD_GPU_1 VDD_GPU_2 VDD_GPU_3 VDD_GPU_4 VDD_GPU_5
VDD_NPU_1 VDD_NPU_2 VDD_NPU_3 VDD_NPU_4 VDD_NPU_5
VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146
Rockchip Confidential
J15 K15 K16 K17 K18 L15 L16 L17 L18 M17
M15
L12 M12 N13 N16 P13 P16 R12 R16 T12 T16
R13 T13 U11 U12 U13
M19 N19 P18 P19 P20
Y11 Y12 AA4 AA9 AA23 AB2 AB6 AD3 AE6 AE21 AF3 AF26 AG5 AH1 AH8 AH28
5
C1000
12
100nF
X5R 10V
C0402
VDD_CPU_COM
C1005
12
100nF
X5R 10V
C0201
C1012
12
100nF
X5R 10V
C0201
C1017
12
100nF
X5R 10V
C0201
12
12
12
12
12
12
12
C1004 22uF
X5R
6.3V C0603
C1007 1uF
X5R
6.3V C0402
C1014 22uF
X5R
6.3V C0603
C1001
4.7uF
X5R
6.3V C0402
C1006
4.7uF
X5R
6.3V C0402
C1013
4.7uF
X5R
6.3V
C0402
C1018 22uF
X5R
6.3V C0603
Caps should be placed under the U1000 package
12
4
C1008 1uF
X5R
6.3V C0402
4
12
C1009 22uF
X5R
6.3V C0603
3
VDD_CPU
12
12
12
12
C1003 22uF
X5R
6.3V C0603
C1011 10uF
X5R
6.3V C0603
C1016 10uF
X5R
6.3V C0603
C1020 10uF
X5R
6.3V C0603
C1002
12
22uF
X5R
6.3V C0603
VDD_LOGIC
C1010
12
22uF
X5R
6.3V C0603
VDD_GPU
C1015
12
22uF
X5R
6.3V C0603
VDD_NPU
C1019
12
22uF
X5R
6.3V C0603
Caps should be placed close to the U1000 package
3
U1000B
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8
VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64
RK3568
BGA636_19R00X19R00X1R20
VSS_65
A1 A3 A6 A10 A14 A18 A28 B5 B9 B12 B16 B23 B26 C3 C6 C8 C9 C11 C12 C14 C15 C17 C18 C25 D2 D3 D11 D28 E3 E7 F1 F3 F9 F12 F14 F15 F17 G5 G6 G8 G9 G11 G12 G14 G15 G17 G18 G24 H2 H3 H6 J3 J5 J17 J18 J20 J22 J26 K1 K11 K12 K13 K14 K19 L3
2
U1000C
VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98
VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129
RK3568
BGA636_19R00X19R00X1R20
2
VSS_130
Project:
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File:
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File:
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
L5 L8 L11 L13 L14 L19 L20 L21 M2 M3 M6 M8 M11 M13 M14 M16 M18 N1 N12 N14 N15 N17 N18 P3 P6 P12 P14 P15 P17 R3 R6 R10 R11 R14 R15 R17 R18 R19 T10 T11 T14 T15 T17 T18 T19 U1 U6 U7 U8 U10 U14 U15 U16 U17 U18 V3 V8 V9 V13 W10 W11 W12 W13 Y8 Y9
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
10.RK3568_Power/GND
10.RK3568_Power/GND
10.RK3568_Power/GND
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
Zhangdz
U1000E
RK3568
BGA636_19R00X19R00X1R20
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
1
AVSS_1 AVSS_2 AVSS_3 AVSS_4 AVSS_5 AVSS_6 AVSS_7 AVSS_8
AVSS_9 AVSS_10 AVSS_11 AVSS_12 AVSS_13 AVSS_14 AVSS_15 AVSS_16 AVSS_17 AVSS_18 AVSS_19 AVSS_20 AVSS_21 AVSS_22 AVSS_23 AVSS_24 AVSS_25 AVSS_26 AVSS_27 AVSS_28 AVSS_29 AVSS_30 AVSS_31 AVSS_32 AVSS_33 AVSS_34 AVSS_35 AVSS_36 AVSS_37 AVSS_38 AVSS_39 AVSS_40 AVSS_41 AVSS_42 AVSS_43 AVSS_44 AVSS_45 AVSS_46 AVSS_47 AVSS_48 AVSS_49 AVSS_50 AVSS_51 AVSS_52 AVSS_53 AVSS_54 AVSS_55 AVSS_56 AVSS_57 AVSS_58 AVSS_59
1
J27 L24 L26 M21 M26 N28 P21 P26 R23 R26 U23 U26 V14 V15 V16 V22 V23 V26 W17 Y18 Y23 Y24 Y26 AA12 AA14 AA15 AA17 AA24 AA26 AB11 AB12 AB14 AB15 AB17 AC9 AC11 AC12 AC15 AC18 AC25 AC26 AD26 AE14 AE17 AE20 AE27 AE28 AF9 AF11 AF12 AF14 AF15 AF17 AF18 AF20 AF21 AG18 AH18 AH23
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
11 72
Sheet: of
11 72
Sheet: of
11 72
Page 12
5
4
3
2
1
RK3568_F (DDR PHY)
U1000F
DDR_DQ0_A
F2
DDR_DQ1_A
E1
DDR_DQ2_A
E2
DDR_DQ3_A
D1
DDR_DQ4_A
J1
DDR_DQ5_A
J2
DDR_DQ6_A
H1
DDR_DQ7_A
H4
DDR_DM0_A
D D
C C
DDR_DQS0P_A DDR_DQS0N_A
DDR_DQ8_A DDR_DQ9_A DDR_DQ10_A DDR_DQ11_A DDR_DQ12_A DDR_DQ13_A DDR_DQ14_A DDR_DQ15_A
DDR_DM1_A
DDR_DQS1P_A DDR_DQS1N_A
DDR_DQ0_B DDR_DQ1_B DDR_DQ2_B DDR_DQ3_B DDR_DQ4_B DDR_DQ5_B DDR_DQ6_B DDR_DQ7_B
DDR_DM0_B
DDR_DQS0P_B DDR_DQS0N_B
DDR_DQ8_B DDR_DQ9_B DDR_DQ10_B DDR_DQ11_B DDR_DQ12_B DDR_DQ13_B DDR_DQ14_B DDR_DQ15_B
DDR_DM1_B
DDR_DQS1P_B DDR_DQS1N_B
DDR_ECC_DQ0 DDR_ECC_DQ1 DDR_ECC_DQ2 DDR_ECC_DQ3 DDR_ECC_DQ4 DDR_ECC_DQ5 DDR_ECC_DQ6 DDR_ECC_DQ7
DDR_ECC_DM
DDR_ECC_DQSP DDR_ECC_DQSN
H5
G1 G2
M1 N2 L7 L6 K2 J6 J7 L4
J4
L2 L1
B10
A9 D12 E12 A12 D15 E15 E14
D14
A11 B11
A16 B17 A17 B18 B13 A13 D17 B14
E17
B15 A15
P5
M4
M5
R5
M7
R7
P4
R4
P7
P2
P1
DDR4
DDR4_DQL0_A
/
DDR_DQ0_A
/
DDR4_DQL2_A
DDR_DQ1_A
DDR4_DQL4_A
/
DDR_DQ2_A
DDR4_DQL6_A
/
DDR_DQ3_A
/
DDR4_DQL7_A
DDR_DQ4_A
DDR4_DQL5_A
/
DDR_DQ5_A
DDR4_DQL3_A
/
DDR_DQ6_A
/
DDR4_DQL1_A
DDR_DQ7_A
/
DDR4_DML_A
DDR_DM0_A
/
DDR4_DQSL_P_A
DDR_DQS0P_A
DDR4_DQSL_N_A
/
DDR_DQS0N_A
/
DDR4_DQU3_A
DDR_DQ8_A
DDR4_DQU1_A
/
DDR_DQ9_A
/
DDR4_DQU7_A
DDR_DQ10_A
/
DDR4_DQU5_A
DDR_DQ11_A
/
DDR4_DQU2_A
DDR_DQ12_A
DDR4_DQU4_A
/
DDR_DQ13_A
/
DDR_DQ14_A
/
DDR4_DQU0_A
DDR_DQ15_A
/
DDR4_DMU_A
DDR_DM1_A
DDR4_DQSU_P_A
/
DDR_DQS1P_A
DDR4_DQSU_N_A
/
DDR_DQS1N_A
DDR4_DQU7_B
/
DDR_DQ0_B
DDR4_DQU5_B
/
DDR_DQ1_B
/
DDR4_DQU3_B
DDR_DQ2_B
DDR4_DQU1_B
/
DDR_DQ3_B
DDR4_DQU0_B
/
DDR_DQ4_B
/ /
DDR4_DQU6_B
DDR_DQ5_B
DDR4_DQU4_B
/
DDR_DQ6_B
/
DDR4_DQU2_B
DDR_DQ7_B
/
DDR4_DMU_B
DDR_DM0_B
DDR4_DQSU_P_B
/
DDR_DQS0P_B
/
DDR4_DQSU_N_B
DDR_DQS0N_B
/
DDR4_DQL0_B
DDR_DQ8_B
/
DDR4_DQL2_B
DDR_DQ9_B
/
DDR4_DQL4_B
DDR_DQ10_B
DDR4_DQL6_B
/
DDR_DQ11_B
DDR4_DQL7_B
/
DDR_DQ12_B
DDR4_DQL5_B
/
DDR_DQ13_B
/
DDR4_DQL1_B
DDR_DQ14_B
DDR4_DQL3_B
/
DDR_DQ15_B
DDR4_DML_B
/
DDR_DM1_B
DDR4_DQSL_P_B
DDR_DQS1P_B
/
DDR4_DQSL_N_B
DDR_DQS1N_B
/
DDR4_ECC_DQ7
DDR_ECC_DQ0
/
DDR4_ECC_DQ0
DDR_ECC_DQ1
/
DDR4_ECC_DQ2
DDR_ECC_DQ2
/
DDR4_ECC_DQ1
DDR_ECC_DQ3
/
DDR4_ECC_DQ6
DDR_ECC_DQ4
/
DDR4_ECC_DQ4
DDR_ECC_DQ5
/
DDR4_ECC_DQ3
DDR_ECC_DQ6
/
DDR4_ECC_DQ5
DDR_ECC_DQ7
/
DDR4_ECC_DM
DDR_ECC_DM
/
DDR4_ECC_DQS_P
DDR_ECC_DQS_P
/
DDR4_ECC_DQS_N
DDR_ECC_DQS_N
RK3568
BGA636_19R00X19R00X1R20
LPDDR4
LPDDR4_DQ0_A
/ /
LPDDR4_DQ1_A
/
LPDDR4_DQ2_A LPDDR4_DQ3_A/
/
LPDDR4_DQ4_A LPDDR4_DQ5_A
/ /
LPDDR4_DQ6_A LPDDR4_DQ7_A
/
/
LPDDR4_DM0_A
/
LPDDR4_DQS0P_A LPDDR4_DQS0N_A /
/
/
LPDDR4_DQ8_A
/
LPDDR4_DQ9_A LPDDR4_DQ10_A
/
LPDDR4_DQ11_A
/
LPDDR4_DQ12_A
/ /
LPDDR4_DQ13_A LPDDR4_DQ14_A LPDDR4_DQ15_A
/
LPDDR4_DM1_A /
/
LPDDR4_DQS1P_A
/ /
LPDDR4_DQS1N_A
LPDDR4_DQ0_B
/ /
LPDDR4_DQ1_B LPDDR4_DQ2_B
/
LPDDR4_DQ3_B
/ /
LPDDR4_DQ4_B
/
LPDDR4_DQ5_B
/
LPDDR4_DQ6_B LPDDR4_DQ7_B
/
/
LPDDR4_DM0_B
/
LPDDR4_DQS0P_B LPDDR4_DQS0N_B
/
LPDDR4_DQ8_B
/
LPDDR4_DQ9_B
/ /
LPDDR4_DQ10_B
/
LPDDR4_DQ11_B LPDDR4_DQ12_B
/
LPDDR4_DQ13_B
/
LPDDR4_DQ14_B
/
LPDDR4_DQ15_B
/
LPDDR4_DM1_B
/
//
LPDDR4_DQS1P_B
/
LPDDR4_DQS1N_B
--/ / -­/ -­/ -­/ -­/ -­/ -­/ --
/ --
/ -­/ -- DDR3_ECC_DQS_N
DDR3
DDR3_DQ0
/ /
DDR3_DQ1 DDR3_DQ2
/
DDR3_DQ3
/
DDR3_DQ4
/ /
DDR3_DQ5 DDR3_DQ6
/
DDR3_DQ7
/
DDR3_DM0 /
/
DDR3_DQS0P
/
DDR3_DQS0N
/
/
DDR3_DQ8
/
DDR3_DQ9
/
DDR3_DQ10 DDR3_DQ11
/ /
DDR3_DQ12 DDR3_DQ13
/
DDR3_DQ14DDR4_DQU6_A / DDR3_DQ15
/
DDR3_DM1
/
DDR3_DQS1P DDR3_DQS1N
/
/
DDR3_DQ16
/
DDR3_DQ17
/
DDR3_DQ18
/
DDR3_DQ19
/
DDR3_DQ20
/
DDR3_DQ21
/
DDR3_DQ22 / DDR3_DQ23
/
/
DDR3_DM2
DDR3_DQS2P
/
DDR3_DQS2N
/
DDR3_DQ24
/
DDR3_DQ25
/
DDR3_DQ26
/ /
DDR3_DQ27 DDR3_DQ28
/
DDR3_DQ29
/ /
DDR3_DQ30
/
DDR3_DQ31
/
DDR3_DM3
/
DDR3_DQS3P DDR3_DQS3N
/
DDR3_ECC_DQ0/ DDR3_ECC_DQ1/ DDR3_ECC_DQ2/ DDR3_ECC_DQ3/ DDR3_ECC_DQ4/ DDR3_ECC_DQ5/ DDR3_ECC_DQ6/ DDR3_ECC_DQ7/
DDR3_ECC_DM/
DDR3_ECC_DQS_P/
/
LPDDR3
/
LPDDR3_DQ15 LPDDR3_DQ14
/
LPDDR3_DQ10
/ /
LPDDR3_DQ9 LPDDR3_DQ13
/ /
LPDDR3_DQ12 LPDDR3_DQ8
/ /
LPDDR3_DQ11
LPDDR3_DM1
LPDDR3_DQS1P
/
LPDDR3_DQS1N
LPDDR3_DQ25
/
LPDDR3_DQ24
/ /
LPDDR3_DQ28 LPDDR3_DQ29
/
LPDDR3_DQ26
/
LPDDR3_DQ31
/ //
LPDDR3_DQ30
/
LPDDR3_DQ27
/
LPDDR3_DM3
LPDDR3_DQS3P
/
LPDDR3_DQS3N
/
LPDDR3_DQ1
/
LPDDR3_DQ5
/ /
LPDDR3_DQ6
/
LPDDR3_DQ4
/
LPDDR3_DQ2 LPDDR3_DQ3 LPDDR3_DQ7
/
LPDDR3_DQ0
LPDDR3_DM0
/
/
LPDDR3_DQS0P
/
LPDDR3_DQS0N
LPDDR3_DQ18
/
LPDDR3_DQ19
/ /
LPDDR3_DQ22 LPDDR3_DQ23
/
LPDDR3_DQ16
/ /
LPDDR3_DQ17 LPDDR3_DQ20
/
LPDDR3_DQ21
/
LPDDR3_DM2
/
LPDDR3_DQS2P
/
LPDDR3_DQS2N
/
DDR4_A0 DDR4_A1 DDR4_A2 DDR4_A3
DDR4_A4 DDR4_A5 DDR4_A6 DDR4_A7
DDR4_A8 DDR4_A9 DDR4_A10 DDR4_A11 /
DDR4_A12 DDR4_A13 DDR4_A14_WEn DDR4_A15_CASn
DDR4_A16_RASn DDR4_ACTn DDR4_BA0
DDR4_BG0 DDR4_BG1 DDR4_CKE
DDR4_CLKP DDR4_CLKN
DDR4_CS0n DDR4_CS1n DDR4_ODT0 DDR4_ODT1
DDR4_RESETn
Note: Sequences can not be swap
Note: Except DDR3, other DQ sequences can not be swap
LPDDR4 DDR3DDR4 LPDDR3
/
LPDDR4_CLKP_B
/
--­LPDDR4_A1_A
/
LPDDR4_CKE1_A
/
/
LPDDR4_A3_B
/
LPDDR4_A5_B LPDDR4_A1_B
/ /
LPDDR4_ODT0_CA_B
/
LPDDR4_ODT0_CA_A
LPDDR4_CLKN_B
/ /
LPDDR4_CKE0_B LPDDR4_A0_A
/
LPDDR4_A3_A
/
LPDDR4_A0_B
/
LPDDR4_A4_A
/ /
LPDDR4_A5_A
/ /
LPDDR4_CKE1_B LPDDR4_A2_B
/ / LPDDR3_A4DDR4_BA1
LPDDR4_A4_B
LPDDR4_ODT1_CA_B
/ /
LPDDR4_ODT1_CA_A LPDDR4_CKE0_A
/
/ /
LPDDR4_CLKP_A LPDDR4_CLKN_A
/
LPDDR4_CS0n_A
/ /
LPDDR4_CS1n_A LPDDR4_CS1n_B
/
LPDDR4_CS0n_B
/
LPDDR4_RESETn
/
/
/
DDR3_A9
---
/
/ / /
/ /
/
/ / / DDR3_A5 / /
/ / / /LPDDR4_A2_A
/ / / /
/ / /
/
/ / / /
/
DDR3L =1.35V DDR3 =1.5V DDR4 =1.2V LPDDR3 =1.2V LPDDR4 =1.1V LPDDR4x =1.1V
DDR3L =1.35V DDR3 =1.5V DDR4 =1.2V LPDDR3 =1.2V LPDDR4 =1.1V LPDDR4x
---
DDR3_A2
/
DDR3_A4 LPDDR3_A6
---
/
DDR3_A3
/
LPDDR3_A3
DDR3_BA1
/
DDR3_A11
LPDDR3_A2 LPDDR3_A1
DDR3_A13
//
DDR3_A8
/
---
DDR3_A6
LPDDR3_A9
---
/ /
---
DDR3_A10 DDR3_A7
/
LPDDR3_A8
DDR3_BA2
---
/ /
DDR3_A14
LPDDR3_A0
DDR3_A15
/
LPDDR3_A5
DDR3_A0
---
/
LPDDR3_A7
DDR3_RASn
/
DDR3_CASn
---
DDR3_A1
/
---
DDR3_A12
/ /
/
DDR3_WEn
---
DDR3_BA0
---
/
LPDDR3_CKE
DDR3_CKE
/
/
LPDDR3_CLKP
DDR3_CLKP
/
DDR3_CLKN
LPDDR3_CLKN
/ LPDDR3_ODT0
DDR3_ODT1
/
LPDDR3_ODT1
DDR3_CS1n
/
DDR3_ODT0
LPDDR3_CS1n LPDDR3_CS0n
/
DDR3_CS0n
---
DDR3_RESETn
/
=0.6V
DDRPHY_VDDQL_1 DDRPHY_VDDQL_2 DDRPHY_VDDQL_3 DDRPHY_VDDQL_4 DDRPHY_VDDQL_5 DDRPHY_VDDQL_6
/ / / /
/ / / /
/ / /
/ / / /
// / /
/ / /
/ /
/ / / /
/
DDR_RZQ
DDR_VREFOUT
DDRPHY_VDDQ_1 DDRPHY_VDDQ_2 DDRPHY_VDDQ_3 DDRPHY_VDDQ_4 DDRPHY_VDDQ_5 DDRPHY_VDDQ_6 DDRPHY_VDDQ_7 DDRPHY_VDDQ_8
DDR_AVSS
B6
AC0
F5
AC1
B1
AC2
F4
AC3
D9
AC4
B7
AC5
A7
AC6
A8
AC7
C1
AC8
A5
AC9
D6
AC10
C2
AC11
C4
AC12
B8
AC13
C5
AC14
E4
AC15
D5
AC16
E6
AC17
E11
AC18
E9
AC19
F8
AC20
F7
AC21
B3
AC22
B4
AC23
A4
AC24
A2
AC25
B2
AC26
E8
AC27
D8
AC28
F11
AC29
H7
P8
H9 H11 H12 H14 H15 J9 L9 M9
J11 J12 J14 K10 L10 M10
J8
Default DDR4 AC LPDDR4/4x AC DDR3 AC LPDDR3 AC
AC0 AC1 AC2 AC3
AC4 AC5 AC6 AC7
AC8 AC9 AC10 AC11
AC12 AC13 AC14 AC15
AC16 AC17 AC18 AC19
AC20 AC21 AC22
AC23 AC24
AC25 AC26 AC27 AC28
AC29
DDR_RZQ
AC0
DDR4_A0
AC1
DDR4_A1
AC2
DDR4_A2
AC3
DDR4_A3
AC4
DDR4_A4
AC5
DDR4_A5
AC6
DDR4_A6
AC7
DDR4_A7
AC8
DDR4_A8
AC9
DDR4_A9
AC10
DDR4_A10
AC11
DDR4_A11
AC12
DDR4_A12
AC13
DDR4_A13
AC14
DDR4_A14_WEn
AC15
DDR4_A15_CASn
AC16
DDR4_A16_RASn
AC17
DDR4_ACTn
AC18
DDR4_BA0
AC19
DDR4_BA1
AC20
DDR4_BG0
AC21
DDR4_BG1
AC22
DDR4_CKE
AC23
DDR4_CLKP
AC24
DDR4_CLKN
AC25
DDR4_CS0n
AC26
DDR4_CS1n
AC27
DDR4_ODT0
AC28
DDR4_ODT1
AC29
DDR4_RESETn
For DDR4/DDR3/LPDDR3 mode,
R1100 120R
R1101 120R
DDRPHY_VREFOUT
12
Note:
LPDDR4x mode: Pin J11,J12,J14,K10,L10,M10 connected to VCC0V6_DDR power supply For example
C1100 100nF
X5R 10V C0201
R0201
R0201
C1101
12
100nF
X5R 10V C0201
|| || \/
a 120 ohm +/-1% tolerance external
1%1 2
resistor must be connected between the DDR_RZQ pin and VSS pin
For LPDDR4/LPDDR4x mode,
1%DNP1 2
VCC_DDR
a 120 ohm +/-1% tolerance external resistor must be connected between the DDR_RZQ pin and DDRPHY_VDDQ pin
C1102
C1103
12
12
4.7uF
4.7uF
X5R
X5R
6.3V
6.3V
C0402
C0402
VCC_DDR
AC0
AC2 AC3
AC4 AC5 AC6 AC7
AC8 AC9 AC10 AC11
AC12 AC13 AC14 AC15
AC16 AC17 AC18 AC19
AC22
AC23 AC24
AC25 AC26 AC27 AC28
AC29
Default DDR4
C1104
12
10uF
X5R
6.3V
Note:
C0603
Caps should be placed under the U1000 package
LPDDR4_CLKP_B
LPDDR4_A1_A LPDDR4_CKE1_A
LPDDR4_A3_B LPDDR4_A5_B LPDDR4_A1_B LPDDR4_ODT0_CA_B
LPDDR4_ODT0_CA_A LPDDR4_CLKN_B LPDDR4_CKE0_B LPDDR4_A0_A
LPDDR4_A3_A LPDDR4_A0_B LPDDR4_A4_A LPDDR4_A2_A
LPDDR4_A5_A LPDDR4_CKE1_B LPDDR4_A2_B LPDDR4_A4_B
LPDDR4_CKE0_A
LPDDR4_CLKP_A LPDDR4_CLKN_A
LPDDR4_CS0n_A LPDDR4_CS1n_A LPDDR4_CS1n_B LPDDR4_CS0n_B
LPDDR4_RESETn
AC0
DDR3_A9
AC1
DDR3_A2
AC2
DDR3_A4
AC3
DDR3_A3
AC4
DDR3_BA1
AC5
DDR3_A11
AC6
DDR3_A13
AC7
DDR3_A8
AC8
DDR3_A6
AC9
DDR3_A5
AC10
DDR3_A10
AC11
DDR3_A7
AC12
DDR3_BA2
AC13
DDR3_A14
AC14
DDR3_A15
AC15
DDR3_A0
AC16
DDR3_RASn
AC17
DDR3_CASn
AC18
DDR3_A1
AC19
DDR3_A12
AC20
DDR3_WEn
AC21
DDR3_BA0
AC22
DDR3_CKE
AC23
DDR3_CLKP
AC24
DDR3_CLKN
AC25
DDR3_ODT1
AC26
DDR3_CS1n
AC27
DDR3_ODT0
AC28
DDR3_CS0n
AC29
DDR3_RESETn
AC2
LPDDR3_A6
AC4
LPDDR3_A3
AC5
LPDDR3_A2
AC6
LPDDR3_A1
AC8
LPDDR3_A9
AC11
LPDDR3_A8
AC13
LPDDR3_A0
AC14
LPDDR3_A5
AC16
LPDDR3_A7
AC19
LPDDR3_A4
AC22
LPDDR3_CKE
AC23
LPDDR3_CLKP
AC24
LPDDR3_CLKN
AC25
LPDDR3_ODT0
AC27
LPDDR3_CS1n
AC28
LPDDR3_CS0n
Default DDR4 DQ LPDDR4/4x DQ DDR3 DQ LPDDR3 DQ
5
DDR_DQ0_A DDR_DQ1_A DDR_DQ2_A DDR_DQ3_A DDR_DQ4_A DDR_DQ5_A DDR_DQ6_A DDR_DQ7_A
DDR_DM0_A
DDR_DQS0P_A DDR_DQS0N_A
DDR_DQ8_A DDR_DQ9_A DDR_DQ10_A DDR_DQ11_A DDR_DQ12_A DDR_DQ13_A DDR_DQ14_A DDR_DQ15_A
DDR_DM1_A
DDR_DQS1P_A DDR_DQS1N_A
DDR_DQ0_B DDR_DQ1_B DDR_DQ2_B DDR_DQ3_B DDR_DQ4_B DDR_DQ5_B DDR_DQ6_B DDR_DQ7_B
DDR_DM0_B
DDR_DQS0P_B DDR_DQS0N_B
DDR_DQ8_B DDR_DQ9_B DDR_DQ10_B DDR_DQ11_B DDR_DQ12_B DDR_DQ13_B DDR_DQ14_B DDR_DQ15_B
DDR_DM1_B
DDR_DQS1P_B DDR_DQS1N_B
LPDDR4_DQ0_A LPDDR4_DQ1_A LPDDR4_DQ2_A LPDDR4_DQ3_A LPDDR4_DQ4_A LPDDR4_DQ5_A LPDDR4_DQ6_A LPDDR4_DQ7_A
LPDDR4_DM0_A
LPDDR4_DQS0P_A LPDDR4_DQS0N_A
LPDDR4_DQ8_A
LPDDR4_DQ9_A LPDDR4_DQ10_A LPDDR4_DQ11_A LPDDR4_DQ12_A LPDDR4_DQ13_A LPDDR4_DQ14_A LPDDR4_DQ15_A
LPDDR4_DM1_A
LPDDR4_DQS1P_A LPDDR4_DQS1N_A
LPDDR4_DQ0_B
LPDDR4_DQ1_B
LPDDR4_DQ2_B
LPDDR4_DQ3_B
LPDDR4_DQ4_B
LPDDR4_DQ5_B
LPDDR4_DQ6_B
LPDDR4_DQ7_B
LPDDR4_DM0_B
LPDDR4_DQS0P_B LPDDR4_DQS0N_B
LPDDR4_DQ8_B
LPDDR4_DQ9_B LPDDR4_DQ10_B LPDDR4_DQ11_B LPDDR4_DQ12_B LPDDR4_DQ13_B LPDDR4_DQ14_B LPDDR4_DQ15_B
LPDDR4_DM1_B
LPDDR4_DQS1P_B LPDDR4_DQS1N_B
DDR4_DQL0_A DDR4_DQL2_A DDR4_DQL4_A
B B
A A
DDR4_DQL6_A DDR4_DQL7_A DDR4_DQL5_A DDR4_DQL3_A DDR4_DQL1_A
DDR4_DML_A
DDR4_DQSL_P_A DDR4_DQSL_N_A
DDR4_DQU3_A DDR4_DQU1_A DDR4_DQU7_A DDR4_DQU5_A DDR4_DQU2_A DDR4_DQU4_A DDR4_DQU6_A DDR4_DQU0_A
DDR4_DMU_A
DDR4_DQSU_P_A DDR4_DQSU_N_A
DDR4_DQU7_B DDR4_DQU5_B DDR4_DQU3_B DDR4_DQU1_B DDR4_DQU0_B DDR4_DQU6_B DDR4_DQU4_B DDR4_DQU2_B
DDR4_DMU_B
DDR4_DQSU_P_B DDR4_DQSU_N_B
DDR4_DQL0_B DDR4_DQL2_B DDR4_DQL4_B DDR4_DQL6_B DDR4_DQL7_B DDR4_DQL5_B DDR4_DQL1_B DDR4_DQL3_B
DDR4_DML_B
DDR4_DQSL_P_B DDR4_DQSL_N_B
Rockchip Confidential
DDR_DQ0_A DDR_DQ1_A DDR_DQ2_A DDR_DQ3_A DDR_DQ4_A DDR_DQ5_A DDR_DQ6_A DDR_DQ7_A
DDR_DM0_A
DDR_DQS0P_A DDR_DQS0N_A
DDR_DQ8_A DDR_DQ9_A DDR_DQ10_A DDR_DQ11_A DDR_DQ12_A DDR_DQ13_A DDR_DQ14_A DDR_DQ15_A
DDR_DM1_A
DDR_DQS1P_A DDR_DQS1N_A
DDR_DQ0_B DDR_DQ1_B DDR_DQ2_B DDR_DQ3_B DDR_DQ4_B DDR_DQ5_B DDR_DQ6_B DDR_DQ7_B
DDR_DM0_B
DDR_DQS0P_B DDR_DQS0N_B
DDR_DQ8_B DDR_DQ9_B DDR_DQ10_B DDR_DQ11_B DDR_DQ12_B DDR_DQ13_B DDR_DQ14_B DDR_DQ15_B
DDR_DM1_B
DDR_DQS1P_B DDR_DQS1N_B
DDR3_DQ0 DDR3_DQ1 DDR3_DQ2 DDR3_DQ3 DDR3_DQ4 DDR3_DQ5 DDR3_DQ6 DDR3_DQ7
DDR3_DM0
DDR3_DQS0P DDR3_DQS0N
DDR3_DQ8
DDR3_DQ9 DDR3_DQ10 DDR3_DQ11 DDR3_DQ12 DDR3_DQ13 DDR3_DQ14 DDR3_DQ15
DDR3_DM1
DDR3_DQS1P DDR3_DQS1N
DDR3_DQ16 DDR3_DQ17 DDR3_DQ18 DDR3_DQ19 DDR3_DQ20 DDR3_DQ21 DDR3_DQ22 DDR3_DQ23
DDR3_DM2
DDR3_DQS2P DDR3_DQS2N
DDR3_DQ24 DDR3_DQ25 DDR3_DQ26 DDR3_DQ27 DDR3_DQ28 DDR3_DQ29 DDR3_DQ30 DDR3_DQ31
DDR3_DM3
DDR3_DQS3P DDR3_DQS3N
DDR_DQ0_A DDR_DQ1_A DDR_DQ2_A DDR_DQ3_A DDR_DQ4_A DDR_DQ5_A DDR_DQ6_A DDR_DQ7_A
DDR_DM0_A
DDR_DQS0P_A DDR_DQS0N_A
DDR_DQ8_A DDR_DQ9_A DDR_DQ10_A DDR_DQ11_A DDR_DQ12_A DDR_DQ13_A DDR_DQ14_A DDR_DQ15_A
DDR_DM1_A
DDR_DQS1P_A DDR_DQS1N_A
DDR_DQ0_B DDR_DQ1_B DDR_DQ2_B DDR_DQ3_B DDR_DQ4_B DDR_DQ5_B DDR_DQ6_B DDR_DQ7_B
DDR_DM0_B
DDR_DQS0P_B DDR_DQS0N_B
DDR_DQ8_B DDR_DQ9_B DDR_DQ10_B DDR_DQ11_B DDR_DQ12_B DDR_DQ13_B DDR_DQ14_B DDR_DQ15_B
DDR_DM1_B
DDR_DQS1P_B DDR_DQS1N_B
4
LPDDR3_D15 LPDDR3_D14 LPDDR3_D10
LPDDR3_D9 LPDDR3_D13 LPDDR3_D12
LPDDR3_D8 LPDDR3_D11
LPDDR3_DM1
LPDDR3_DQS1P LPDDR3_DQS1N
LPDDR3_D25 LPDDR3_D24 LPDDR3_D28 LPDDR3_D29 LPDDR3_D26 LPDDR3_D31 LPDDR3_D30 LPDDR3_D27
LPDDR3_DM3
LPDDR3_DQS3P LPDDR3_DQS3N
LPDDR3_D1
LPDDR3_D5
LPDDR3_D6
LPDDR3_D4
LPDDR3_D2
LPDDR3_D3
LPDDR3_D7
LPDDR3_D0
LPDDR3_DM0
LPDDR3_DQS0P LPDDR3_DQS0N
LPDDR3_D18 LPDDR3_D19 LPDDR3_D22 LPDDR3_D23 LPDDR3_D16 LPDDR3_D17 LPDDR3_D20 LPDDR3_D21
LPDDR3_DM2
LPDDR3_DQS2P LPDDR3_DQS2N
DDR_DQ0_A DDR_DQ1_A DDR_DQ2_A DDR_DQ3_A DDR_DQ4_A DDR_DQ5_A DDR_DQ6_A DDR_DQ7_A
DDR_DM0_A
DDR_DQS0P_A DDR_DQS0N_A
DDR_DQ8_A DDR_DQ9_A DDR_DQ10_A DDR_DQ11_A DDR_DQ12_A DDR_DQ13_A DDR_DQ14_A DDR_DQ15_A
DDR_DM1_A
DDR_DQS1P_A DDR_DQS1N_A
DDR_DQ0_B DDR_DQ1_B DDR_DQ2_B DDR_DQ3_B DDR_DQ4_B DDR_DQ5_B DDR_DQ6_B DDR_DQ7_B
DDR_DM0_B
DDR_DQS0P_B DDR_DQS0N_B
DDR_DQ8_B DDR_DQ9_B DDR_DQ10_B DDR_DQ11_B DDR_DQ12_B DDR_DQ13_B DDR_DQ14_B DDR_DQ15_B
DDR_DM1_B
DDR_DQS1P_B DDR_DQS1N_B
DDR4 ECC DQ DDR3 ECC DQ
DDR4_ECC_DQ7 DDR4_ECC_DQ0 DDR4_ECC_DQ2 DDR4_ECC_DQ1 DDR4_ECC_DQ6 DDR4_ECC_DQ4 DDR4_ECC_DQ3 DDR4_ECC_DQ5
DDR4_ECC_DM
DDR4_ECC_DQS_P DDR4_ECC_DQS_N
3
DDR_ECC_DQ0 DDR_ECC_DQ1 DDR_ECC_DQ2 DDR_ECC_DQ3 DDR_ECC_DQ4 DDR_ECC_DQ5 DDR_ECC_DQ6 DDR_ECC_DQ7
DDR_ECC_DM
DDR_ECC_DQSP DDR_ECC_DQSN
DDR3_ECC_DQ0 DDR3_ECC_DQ1 DDR3_ECC_DQ2 DDR3_ECC_DQ3 DDR3_ECC_DQ4 DDR3_ECC_DQ5 DDR3_ECC_DQ6 DDR3_ECC_DQ7
DDR3_ECC_DM
DDR3_ECC_DQSP DDR3_ECC_DQSN
2
DDR_ECC_DQ0 DDR_ECC_DQ1 DDR_ECC_DQ2 DDR_ECC_DQ3 DDR_ECC_DQ4 DDR_ECC_DQ5 DDR_ECC_DQ6 DDR_ECC_DQ7
DDR_ECC_DM
DDR_ECC_DQSP DDR_ECC_DQSN
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
11.RK3568_DDR PHY
11.RK3568_DDR PHY
11.RK3568_DDR PHY
Date:
Wednesday, J une 16, 2021
Date:
Wednesday, J une 16, 2021
Date:
Wednesday, J une 16, 2021
Designed by:
Zhangdz
Designed by:
Zhangdz
Designed by:
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
1
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
12 72
Sheet: of
12 72
Sheet: of
Default
Default
Default
12 72
Page 13
5
4
3
2
1
RK3568_G(OSC/PLL/PMUIO1/2)
Note:
Adjusted the load capacitance according to the crystal specification.
D D
C C
B B
R1200 22R
1 2
Y1200 24MHz
1
X1
GND2X2
CRY4_3R20X2R50X0R80
C1201
12
18pF
C0G 50V
C0402
HDMIRX_PWREN_H_GPIO0_D6
VDDA0V9_PMU
12
VCCA1V8_PMU
12
VDDA_0V9
12
VCCA_1V8
12
RTCIC_INT_L_GPIO0_D3
PCIE_PWREN_H_GPIO0_D4
VGA_PWREN_H_GPIO0_D5
C1204 1uF
X5R 10V C0402
C1206 1uF
X5R 10V C0402
C1208 1uF
X5R 10V C0402
C1211 1uF
X5R 10V C0402
5%
R0402
GND
XOUT24M
12
R1202 1M
5% R0402
4
3
XIN24M
C1202
12
18pF
C0G 50V
C0402
C1205
12
100nF
X5R 10V C0201
C1207
12
100nF
X5R 10V C0201
C1209
12
100nF
X5R 10V C0201
C1212
12
100nF
X5R 10V C0201
U1000G
OSC PMUIO1 Domain
AF27
XOUT24M
AF28
XIN24M
PMUIO0 Domain
Operating Voltage =1.8V(PMUPLL_AVDD_1V8)
AB24
TVSS
AE26
GPIO0_D3_d
AB23
GPIO0_D4_d
AD25
GPIO0_D5_d
AC24
GPIO0_D6_d
PMU PLL
V21
PMUPLL_AVDD_0V9
Y21
PMUPLL_AVDD_1V8
V20
PMUPLL_AVSS
SYS PLL
P11
SYSPLL_AVDD_0V9
N10
SYSPLL_AVDD_1V8
N11
SYSPLL_AVSS
RK3568
BGA636_19R00X19R00X1R20
Operating Voltage=3.3V Only
PMUIO2 Domain
Operating Voltage=1.8V/3.3V
CLK32K_IN I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA I2C2_SCL_M0 I2C2_SDA_M0 PWM0_M0
PWM1_M0 PWM2_M0 PWM3_IR PWM4 PWM5 PWM6 PWM7_IR HDMITX_CEC_M1
PMUIO1/2/OSC Domain Logic Power
Operating Voltage=0.9V
SDMMC0_DET SDMMC0_PWREN
/ SATA_CP_DET /
SATA_MP_SWITCH SATA_CP_POD
/GPU_PWREN
/
CLK32K_OUT0
CAN0_TX_M0
/ /
CAN0_RX_M0 SPI0_CLK_M0
/
SPI0_MOSI_M0
/ /
CPUAVS
GPUAVS
/
NPUAVS
/
EDP_HPDIN_M1
/ /
VOP_PWM_M0 SPI0_CS1_M0
/
SPI0_MISO_M0
/
SPI0_CS0_M0
/
TSADC_SHUT_M0 PMIC_SLEEP
/
PCIE30X1_CLKREQn_M0
/
PCIE20_CLKREQn_M0
/
PCIE30X2_CLKREQn_M0
PCIE30X2_BUTTONRSTn
/
/
PCIE30X1_BUTTONRSTn PCIE20_BUTTONRSTn
/
PCIE20_WAKEn_M0
/
/
UART0_RX UART0_TX
/
PCIE30X1_WAKEn_M0
/ / /
PCIE30X1_PERSTn_M0
/
UART0_RTSn PCIE30X2_WAKEn_M0
// //PCIE30X2_PERSTn_M0
UART0_CTSNPWM0_M1
/
/
TSADC_SHUT_ORG
/
TSADC_SHUT_M1
FLASH_VOL_SEL
/ /
MCU_JTAG_TDO MCU_JTAG_TCK
/
PWM1_M1
/ /PCIE20_PERSTn_M0
PWM2_M1
/
MCU_JTAG_TDI MCU_JTAG_TMS MCU_JTAG_TRSTn
/
UART2_RX_M0 UART2_TX_M0
PMU_VDD_LOGIC_0V9
/REFCLK_OUT
GPIO0_A0_d
/
GPIO0_A1_z
/
GPIO0_A2_d GPIO0_A3_u
/
GPIO0_A4_u
/
GPIO0_A5_d
/
GPIO0_A6_d
/
GPIO0_A7_u
/
GPIO0_B0_u
/
GPIO0_B1_u
/
GPIO0_B2_u GPIO0_B3_u
/
GPIO0_B4_u
/
GPIO0_B5_u
/
GPIO0_B6_u
/
GPIO0_B7_d
/
GPIO0_C0_d
/
GPIO0_C1_d
/
GPIO0_C2_d
/
GPIO0_C3_d
/
GPIO0_C4_d
/
GPIO0_C5_d
/
GPIO0_C6_d
/
GPIO0_C7_d
/
GPIO0_D0_u
/
GPIO0_D1_u
NPOR_u
PMUIO1
PMUIO2
AH27
AG27 AG26 AG28 AA22 Y22 AF25 AE24
AG25
Y20
AD23 AF24 AB21 AG24 AB20 AC22 AA20 AH26
AD22 AF23 AG23 AE23 AD21 AC21 AD20 AH25
AC20 AH24
W19
V19
C1200
12
100nF
X5R 10V C0201
REFCLKOUT TSADC_SHUT_M0
VCC3V3_PMU VCC3V3_PMU
C1203
12
100nF
X5R 10V C0201
GPIO0_C5
VCC3V3_PMU
C1210
12
100nF
X5R 10V C0201
VDDA0V9_PMU
C1213
12
100nF
X5R 10V C0201
R1201 0R
R1203 0R
PMIC_SLEEP_H PMIC_INT_L SDMMC0_DET_L USB_OTG_PWREN_H_GPIO0_A5 USB_HOST_PWREN_H_GPIO0_A6
FLASH_VOL_SEL
DVP_PWREN0_H_GPIO0_B0 I2C0_SCL_PMIC I2C0_SDA_PMIC I2C1_SCL_TP I2C1_SDA_TP TP_INT_L_GPIO0_B5 TP_RST_L_GPIO0_B6 Working_LEDEN_H_GPIO0_B7
VGA_HPDIN_GPIO0_C0 WIFI_PWREN_L_GPIO0_C1 PWM3_IR LCD0_BL_PWM4 LCD1_BL_PWM5
4G_PWREN_H_GPIO0_C6 LCD0_PWREN_H_GPIO0_C7
UART2_RX_M0_DEBUG UART2_TX_M0_DEBUG
C1214
12
1uF
X5R 10V C0402
Reset Key Control Path
TSADC_SHUT Control Path
RK809-5 Control Path
RESETn
5%
1 2
1 2
R0402
R0402
TSADC_SHUT_M0
5%
REFCLK_OUT
Default:24MHz
Note:
If PMUIO2 domain power voltage is adjusted, the software DTS configuration must be updated synchronously, otherwise the IO may be damaged!
If the PMUIO2 hardware has been modified to
1.8V power supply, and the corresponding DTS must be modified to 1.8V configuration, otherwise the IO function of PMUIO2 will be abnormally.
The PMUIO2 hardware has been modified to
3.3V power supply, if the software DTS configuration is still 1.8V configuration, the IO of PMUIO2 will be damaged!
RK3568
TSADC_SHUT
RK809-5
RESETB
I2C0_SCL_PMIC I2C0_SDA_PMIC
I2C1_SCL_TP I2C1_SDA_TP
nPOR
12
R1204
2.2K
5% R0402
12
R1206
2.2K
5% R0402
12
VCC3V3_PMU
12
R1205
2.2K
5% R0402
R1207
2.2K
5% R0402
Reset Key
If a board needs to be compatible with two voltage choices, recommended to enable BOM_ID
Option
Default
QSGMII_PWREN_H_GPIO0_C5LCD1_PWREN_H_GPIO0_C5
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
12.RK3568_OSC/PLL/PMUIO
12.RK3568_OSC/PLL/PMUIO
12.RK3568_OSC/PLL/PMUIO
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Designed by:
2
Designed by:
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
1
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
13 72
Sheet: of
13 72
Sheet: of
13 72
A A
Note:
Caps of between dashed green lines and U1000 should be placed under the U1000 package. Other caps should be placed close to the U1000 package
GPIO0_C5 GPIO0_C5
Rockchip Confidential
5
4
3
Page 14
5
4
3
2
1
RK3568_I(VCCIO2 Domain)
U1000I
eMMC_D0/FLASH_D0
VCCIO2 Domain
Operating Voltage=1.8V/3.3V
FLASH_D0
FSPI_CS1n
FSPI_D2 FSPI_CLK FSPI_D0 FSPI_D1 FSPI_CS0n FSPI_D3
/ /
FLASH_D1 FLASH_D2
/
FLASH_D3
/
FLASH_D4
/
FLASH_D5
/
FLASH_D6
/ /
FLASH_D7
/
FLASH_WRn
FLASH_DQS
/
FLASH_CLE
/
FLASH_WPn/
/
FLASH_ALE
/ /
FLASH_RDY FLASH_RDn/
/
FLASH_CS0n
/
FLASH_CS1n
EMMC_D0 EMMC_D1
D D
C C
EMMC_D2 EMMC_D3
EMMC_D5 EMMC_D6 EMMC_D7
EMMC_CLKOUT
EMMC_DATA_STROBE
EMMC_RSTn
Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7_u: L:VCCIO2 must supply 3.3V H:VCCIO2 must supply 1.8V
RK3568
BGA636_19R00X19R00X1R20
/
/
GPIO1_B4_u
/
GPIO1_B5_u
/
GPIO1_B6_u
/
GPIO1_B7_u
/EMMC_D4
GPIO1_C0_u
/
GPIO1_C1_u
/
GPIO1_C2_u
/
GPIO1_C3_u
/EMMC_CMD
GPIO1_C4_u
/
GPIO1_C5_d
/
GPIO1_C6_d
/
GPIO1_C7_d
/
GPIO1_D0_d
/
GPIO1_D1_u
/
GPIO1_D2_u
/
GPIO1_D3_u
/
GPIO1_D4_u
VCCIO2
A24 C21 B24 D21 A25 E21 E22 B25
B22
eMMC_CLKOUT/FLASH_DQS_SOC
A23
A26
F20
FSPI_CLK/FLASH_ALE_SOC
A22 C24 D23 C23 A27
VCCIO_FLASH
H18
eMMC_D0/FLASH_D0 eMMC_D1/FLASH_D1 eMMC_D2/FLASH_D2 eMMC_D3/FLASH_D3 eMMC_D4/FLASH_D4 eMMC_D5/FLASH_D5 eMMC_D6/FLASH_D6 eMMC_D7/FLASH_D7
eMMC_CMD/FLASH_WRn
R1300 22R
1 2
R1301 22R
1 2
R0402
R0402
5%
eMMC_CLKOUT/FLASH_DQS
eMMC_DATA_STROBE/FLASH_CLE
eMMC_RSTn/FSPI_D2/FLASH_WPn
5%
FSPI_CLK/FLASH_ALE FSPI_D0/FLASH_RDY FSPI_D1/FLASH_RDn FSPI_CS0n/FLASH_CS0n FSPI_D3/FLASH_CS1n
Note:
“FLASH_VOL_SEL” status and VCCIO_FLASH power supply voltage must match
C1300
12
100nF
otherwise the IO function of VCCIO2 will be abnormally
X5R
or
10V
the IO of VCCIO2 will be damaged!
C0201
When VCCIO2 voltage is connected to 1.8V, FLASH_VOL_SEL must be high When VCCIO2 voltage is connected to 3.3V, FLASH_VOL_SEL must be low If VCCIO2 power supply voltage and FLASH_VOL_SEL fails to meet the above relationship, its function will be abnormally(for example, it cannot be started normally) or IO will be damaged.
Layout note:
Test point must be placed on the line, and no branch can be added
FSPI_CLK/FLASH_ALE
Note:
Reserve TestPoint for put the system into Maskrom mode to update the firmware When writing mismatched firmware or other conditions result in boot failure, use this test point
Except in this case, please use Recovery Key Put the system into loader mode to update the firmware
TP1300 TP_0.7 TP1301 TP_0.7
TP1302 TP_0.7 TP1303 TP_0.7
Note:
For eMMC or Nand Flash: If eMMC_D0/FLASH_D0=0V at after power on and reset, then system will enter into Maskrom mode.
Note:
For SPI Flash: If FSPI_CLK=0V at after power on and reset, then system will enter into Maskrom mode.
RK3568_J(VCCIO3 Domain)
U1000J
VCCIO3 Domain
Operating Voltage=1.8V/3.3V
/
UART2_TX_M1
/ SDMMC0_D1 SDMMC0_D2 SDMMC0_D3 /
SDMMC0_CMD//
SDMMC0_CLK UART5_TX_M0
B B
RK3568
BGA636_19R00X19R00X1R20
UART2_RX_M1 ARMJTAG_TCK
/
/
ARMJTAG_TMS
PWM10_M1
/
TEST_CLKOUT
UART6_TX_M1SDMMC0_D0 UART6_RX_M1/
/
UART5_CTSn_M0/ UART5_RTSn_M0
/
UART5_RX_M0
/
/
PWM8_M1
/
PWM9_M1
/
CAN0_TX_M1
CAN0_RX_M1/
/
GPIO1_D5_u
/
GPIO1_D6_u GPIO1_D7_u
/
GPIO2_A0_u
/
GPIO2_A1_u
/
GPIO2_A2_d
VCCIO3
GPIO1_D5
J25
GPIO1_D6
J24
GPIO1_D7
H26
GPIO2_A0
J23
GPIO2_A1
H27
GPIO2_A2
H28
VCCIO_SD
L22
C1301
12
100nF
X5R 10V C0201
Note:
Caps of between dashed green lines and U1000 should be placed under the U1000 package
A A
Rockchip Confidential
5
4
Default
SDMMC0&JTAG UART&CAN&JTAG
GPIO1_D5 GPIO1_D6 GPIO1_D7 GPIO2_A0
GPIO2_A1
GPIO2_A2
R1304 22R
1 2
R0402
SDMMC0_D0 SDMMC0_D1 SDMMC0_D2/ARMJTAG_TCK SDMMC0_D3/ARMJTAG_TMS
SDMMC0_CMD
5%
SDMMC0_CLK
Note:
If VCCIO3 domain power voltage is adjusted, the software DTS configuration must be updated synchronously, otherwise the IO may be damaged!
If the VCCIO3 hardware has been modified to
1.8V power supply, and the corresponding DTS must be modified to 1.8V configuration, otherwise the IO function of VCCIO3 will be abnormally.
The VCCIO3 hardware has been modified to
3.3V power supply, if the software DTS configuration is still 1.8V configuration, the IO of VCCIO3 will be damaged!
If a board needs to be compatible with two voltage choices, recommended to enable BOM_ID
3
Option
GPIO1_D5 GPIO1_D6 GPIO1_D7 GPIO2_A0
GPIO2_A1
GPIO2_A2
UART6_TX_M1 UART6_RX_M1
CAN0_TX_M1
CAN0_RX_M1
R1302 22R
1 2
R1303 22R
1 2
2
R04025%
TP1304 TP_0.7
R04025%
TP1305 TP_0.7
For ARM JTAG
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
13.RK3568_Flash/SD Controller
13.RK3568_Flash/SD Controller
13.RK3568_Flash/SD Controller
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Zhangdz
Designed by:
Zhangdz
Designed by:
Zhangdz
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
14 72
Sheet: of
14 72
Sheet: of
14 72
Page 15
5
4
3
2
1
RK3568_U(USB3.0/SATA/QSGMII/PCIe2.0 x1)
U1000U
USB3.0
OTG0_HS/FS/LS
D D
(USB Download)
USB3.0
HOST1_HS/FS/LS
USB3.0
OTG0/HOST1_ HS/FS/LS Power
USB3_OTG0_DP USB3_OTG0_DM
USB3_OTG0_VBUSDET
USB3_OTG0_ID
USB3_HOST1_DP USB3_HOST1_DM
USB3_AVDD_0V9
USB3_AVDD_1V8
USB3_AVDD_3V3
MULTI_PHY0/1/2
USB3.0 OTG0_SS and SATA0 Mux
C C
MULTI PHY0
USB3.0 HOST1_SS and SATA1 and QSGMII_M0 Mux
USB3_HOST1_SSTXP/SATA1_TXP/QSGMII_TXP_M0 USB3_HOST1_SSTXN/SATA1_TXN/QSGMII_TXN_M0
USB3_HOST1_SSRXP/SATA1_RXP/QSGMII_RXP_M0 USB3_HOST1_SSRXN/SATA1_RXN/QSGMII_RXN_M0
MULTI PHY1
PCIe2.0 and SATA2 and QSGMII_M1 Mux
B B
MULTI PHY2
MULTI_PHY REFCLK
RK3568
BGA636_19R00X19R00X1R20
A A
USB3_OTG0_SSTXP/SATA0_TXP USB3_OTG0_SSTXN/SATA0_TXN
USB3_OTG0_SSRXP/SATA0_RXP USB3_OTG0_SSRXN/SATA0_RXN
PCIE20_TXP/SATA2_TXP/QSGMII_TXP_M1 PCIE20_TXN/SATA2_TXN/QSGMII_TXN_M1
PCIE20_RXP/SATA2_RXP/QSGMII_RXP_M1 PCIE20_RXN/SATA2_RXN/QSGMII_RXN_M1
PCIE20_REFCLKP PCIE20_REFCLKN
MULTI_PHY0_REFCLKP MULTI_PHY0_REFCLKN
MULTI_PHY1_REFCLKP MULTI_PHY1_REFCLKN
MULTI_PHY_AVDD_0V9_1 MULTI_PHY_AVDD_0V9_2
MULTI_PHY_AVDD_1V8
Note:
Caps of between dashed green lines and U1000 should be placed under the U1000 package. Other caps should be placed close to the U1000 package
Rockchip Confidential
5
Diff 90 Ohm ±10%
P27 P28
M24
L23
Diff 90 Ohm ±10%
P24 P25
P22
P23
M23
USB3_OTG0_SSTXP/SATA0_TXP
T28
USB3_OTG0_SSTXN/SATA0_TXN
T27
USB3_OTG0_SSRXP/SATA0_RXP
R28
USB3_OTG0_SSRXN/SATA0_RXN
R27
Default
VCC_3V3
12
USB3_OTG0_DP USB3_OTG0_DM
USB3_OTG0_ID
USB3_HOST1_DP USB3_HOST1_DM
USB_AVDD_1V8
12
C1401 100nF
X5R 10V C0201
USB_AVDD_0V9
12
C1403
C1402
100nF
100nF
X5R
X5R
10V
10V
C0201
C0201
Diff 90 Ohm ±10%
USB3_OTG0_SSTXP USB3_OTG0_SSTXN
USB3_OTG0_SSRXP USB3_OTG0_SSRXN
Diff 90 Ohm ±10%
C1400
12
100nF
X5R 10V C0402
Option
USB3_OTG0_VBUSDET
USB3_OTG0_SSTXP/SATA0_TXP USB3_OTG0_SSTXN/SATA0_TXN
USB3_OTG0_SSRXP/SATA0_RXP USB3_OTG0_SSRXN/SATA0_RXN
Option
USB3 OTG0 SATA3.0 Port0
12
C1408 100nF
X5R 10V C0201
Diff 90 Ohm ±10%
USB3_HOST1_SSTXP USB3_HOST1_SSTXN
USB3_HOST1_SSRXP USB3_HOST1_SSRXN
Diff 90 Ohm ±10%
Diff 85 Ohm ±10%
PCIE20_TXP PCIE20_TXN
PCIE20_RXP PCIE20_RXN
Diff 85 Ohm ±10%
PCIE20_REFCLKP PCIE20_REFCLKN
Diff 100 Ohm ±10%
VDDA_0V9
12
C1409
4.7uF
X5R
6.3V C0402
VCCA_1V8
12
USB3_HOST1_SSTXP/SATA1_TXP USB3_HOST1_SSTXN/SATA1_TXN
USB3_HOST1_SSRXP/SATA1_RXP USB3_HOST1_SSRXN/SATA1_RXN
Option
Option
PCIE20_TXP/SATA2_TXP PCIE20_TXN/SATA2_TXN
PCIE20_RXP/SATA2_RXP PCIE20_RXN/SATA2_RXN
Default
Option
PCIE20_TXP/SATA2_TXP PCIE20_TXN/SATA2_TXN
PCIE20_RXP/SATA2_RXP PCIE20_RXN/SATA2_RXN
Option2
QSGMII M1
C1410
PCIE20_TXP/SATA2_TXP
4.7uF
X5R
PCIE20_TXN/SATA2_TXN
6.3V C0402
PCIE20_RXP/SATA2_RXP PCIE20_RXN/SATA2_RXN
Option3
USB3_HOST1_SSTXP/SATA1_TXP
V28
USB3_HOST1_SSTXN/SATA1_TXN
V27
USB3_HOST1_SSRXP/SATA1_RXP
U28
USB3_HOST1_SSRXN/SATA1_RXN
U27
Default
USB3 HOST1 SATA3.0 Port1
PCIE20_TXP/SATA2_TXP
W27
PCIE20_TXN/SATA2_TXN
W28
PCIE20_RXP/SATA2_RXP
Y27
PCIE20_RXN/SATA2_RXN
Y28
V24 V25
Option1
PCIe2.0 SATA3.0 Port2
R24 R25
Note:
In case of multiplexing,
U25
impedance control
U24
Diff 90 Ohm ±10%
R20 R21
R22
12
C1407 100nF
X5R 10V C0201
SGMII M1
QSGMII can choose: QSGMII_TXP_M0/QSGMII_TXN_M0 QSGMII_RXP_M0/QSGMII_RXN_M0 or QSGMII_TXP_M1/QSGMII_TXN_M1 QSGMII_RXP_M1/QSGMII_RXN_M1
See "07.UART Map/GMAC0/1 Path Map" GMAC0/1 Path Map
4
Diff 100 Ohm ±10%
SATA0_TXP SATA0_TXN
SATA0_RXP SATA0_RXN
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
SATA1_TXP SATA1_TXN
SATA1_RXP SATA1_RXN
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
SATA2_TXP SATA2_TXN
SATA2_RXP SATA2_RXN
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
QSGMII_TXP_M1 QSGMII_TXN_M1
QSGMII_RXP_M1 QSGMII_RXN_M1
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
SGMII_TXP_M1 SGMII_TXN_M1
SGMII_RXP_M1 SGMII_RXN_M1
Diff 100 Ohm ±10%
SGMII can choose: SGMII_TXP_M0/SGMII_TXN_M0 SGMII_RXP_M0/SGMII_RXN_M0 or SGMII_TXP_M1/SGMII_TXN_M1 SGMII_RXP_M1/SGMII_RXN_M1
3
RK3568_V(USB2.0 HOST)
U1000V
USB2.0 HOST
USB2_HOST2_DP USB2_HOST2_DM
USB2_HOST3_DP USB2_HOST3_DM
USB2_AVDD_0V9
USB2_AVDD_1V8
USB2_AVDD_3V3
RK3568
BGA636_19R00X19R00X1R20
R2 R1
T2 T1
R8
P9
P10
Diff 90 Ohm ±10%
Diff 90 Ohm ±10%
VCC_3V3
C1404
12
100nF
X5R 10V C0201
USB2_HOST2_DP USB2_HOST2_DM
USB2_HOST3_DP USB2_HOST3_DM
USB_AVDD_1V8
12
USB_AVDD_0V9
C1405 100nF
X5R 10V C0201
C1406
12
100nF
X5R 10V C0201
RK3568_W(PCIe3.0 x2)
U1000W
PCIe3.0 x 2
PCIE30_REFCLKP_IN PCIE30_REFCLKN_IN
PCIE30_RESREF
PCIE30_AVDD_0V9_1 PCIE30_AVDD_0V9_2
PCIE30_AVDD_1V8
RK3568
BGA636_19R00X19R00X1R20
PCIE30_TX0P PCIE30_TX0N
PCIE30_TX1P PCIE30_TX1N
PCIE30_RX0P PCIE30_RX0N
PCIE30_RX1P PCIE30_RX1N
AA28 AA27
AB28 AB27
AC28 AC27
AD28 AD27
Y25 AA25
U19
U21 U20
U22
Diff 85 Ohm ±10%
Diff 85 Ohm ±10%
Diff 85 Ohm ±10%
Diff 85 Ohm ±10%
Diff 100 Ohm ±10%
PCIE30_RESREF
C1411
12
100nF
X5R 10V C0201
2
R1400 200R
1 2
VDDA_0V9
C1412 100nF
X5R 10V C0201
C1413
12
4.7uF
X5R
6.3V C0402
12
PCIE30_TX0P PCIE30_TX0N
PCIE30_TX1P PCIE30_TX1N
PCIE30_RX0P PCIE30_RX0N
PCIE30_RX1P PCIE30_RX1N
PCIE30_REFCLKP_IN PCIE30_REFCLKN_IN
1%
R0201
VCCA_1V8
12
C1414
4.7uF
X5R
6.3V C0402
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
14.RK3568_USB/PCIe/SATA PHY
14.RK3568_USB/PCIe/SATA PHY
14.RK3568_USB/PCIe/SATA PHY
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Zhangdz
Designed by:
Zhangdz
Designed by:
Zhangdz
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
15 72
Sheet: of
15 72
Sheet: of
15 72
Page 16
5
RK3568_K(VCCIO4 Domain)
U1000K
VCCIO4 Domain
Operating Voltage=1.8V/3.3V
D D
SDMMC1_D0 SDMMC1_D1 SDMMC1_D2 SDMMC1_D3
SDMMC1_CMD
SDMMC1_CLK
SDMMC1_PWREN SDMMC1_DET
I2S2_SCLK_RX_M0 I2S2_LRCK_RX_M0 I2S2_MCLK_M0
I2S2_SCLK_TX_M0 I2S2_LRCK_TX_M0 I2S2_SDO_M0 I2S2_SDI_M0
CLK32K_OUT1
C C
RK3568
BGA636_19R00X19R00X1R20
GMAC0_RXD2
/
GMAC0_RXD3 GMAC0_RXCLK
/
GMAC0_TXD2
/
GMAC0_TXD3
/
/
GMAC0_TXCLK
I2C4_SDA_M1
/
I2C4_SCL_M1
/
GMAC0_TXD0 GMAC0_TXD1 GMAC0_TXEN GMAC0_RXD0
/
GMAC0_RXD1 GMAC0_RXDV_CRS ETH0_REFCLKO_25M
/
GMAC0_MCLKINOUT
/
GMAC0_MDC
/
/
GMAC0_MDIO
/
GMAC0_RXER
/
UART6_RX_M0 UART6_TX_M0
/ /
UART7_RX_M0
/
UART7_TX_M0
UART9_RX_M0
/
//UART9_TX_M0
UART8_RTSn_M0/ UART8_CTSn_M0
/
/
UART1_RX_M0
/
UART1_TX_M0 UART1_RTSn_M0
/ /
UART1_CTSn_M0
UART6_RTSn_M0
/
UART6_CTSn_M0 /
/ /
UART7_RTSn_M0
/
UART7_CTSn_M0 UART9_RTSn_M0
/
UART9_CTSn_M0
/ /
UART8_TX_M0
UART8_RX_M0
/
CAN2_RX_M1
/
CAN2_TX_M1
/
/
SPI1_CLK_M0 SPI1_MISO_M0
/
SPI1_MOSI_M0
/
SPI1_CS0_M0/ SPI2_CLK_M0
/
/
SPI2_MISO_M0
/
SPI2_MOSI_M0 SPI2_CS0_M0
/ /
SPI2_CS1_M0
SPI1_CS1_M0
/
/
GPIO2_A3_u
/
GPIO2_A4_u
/
GPIO2_A5_u
/
GPIO2_A6_u
/
GPIO2_A7_u
/
GPIO2_B0_d
/
GPIO2_B1_d
/
GPIO2_B2_u
/
GPIO2_B3_u
/
GPIO2_B4_u
/
GPIO2_B5_u
/
GPIO2_B6_u
/
GPIO2_B7_d
/
GPIO2_C0_d
/
GPIO2_C1_d
/
GPIO2_C2_d
/
GPIO2_C3_d
/
GPIO2_C4_d
/
GPIO2_C5_d
/
GPIO2_C6_d
RK3568_N(VCCIO7 Domain) RK3568_O(SARADC/OTP)
U1000N
VCCIO7 Domain
Operating Voltage=1.8V/3.3V
I2S3_MCLK_M1
PWM14_M1 PWM15_IR_M1 EDP_HPDIN_M0 PWM12_M1 PWM13_M1 /
B B
HDMITX_SCL HDMITX_SDA HDMITX_CEC_M0
RK3568
BGA636_19R00X19R00X1R20
A A
/
SPI3_CLK_M1
SPI3_MOSI_M1
SPDIF_TX_M2
/ SATA2_ACT_LED /
SPI3_MISO_M1
SPI3_CS0_M1
/
I2C5_SCL_M1
I2C5_SDA_M1/
/
SPI3_CS1_M1
//CAN1_RX_M1 /
CAN1_TX_M1 / /
SATA1_ACT_LED /
SATA0_ACT_LED /
/
PCIE30X2_CLKREQn_M2 PCIE30X2_WAKEn_M2
/
PCIE30X2_PERSTn_M2
/
UART9_TX_M1 UART9_RX_M1
Note:
If VCCIO7 domain power voltage is adjusted, the software D TS configuration must be updated synchronously, otherwise the IO may be damaged!
If the VCCIO7 hardware has been modified to 1.8V power supply, and the c orresponding DTS must be modified to 1.8V configuration, otherwise the IO function of VCCIO7 will be abnormally.
The VCCIO7 hardware has been modified to 3.3V power supply, if the s oftware DTS configuration is still 1.8V configuration, the IO of VCCIO7 will be dama ged!
/
I2S3_SCLK_M1
/ //
I2S3_LRCK_M1 I2S3_SDO_M1
/
I2S3_SDI_M1/
VCCIO4
4
Note:
If VCCIO4 domain power voltage is adjusted, the software D TS configuration must be updated synchronously, otherwise the IO may be damaged! If the VCCIO4 hardware has been modified to 1.8V power supply, and the c orresponding DTS must be modified to 1.8V configuration, otherwise the IO function of VCCIO4 will be abnormally. The VCCIO4 hardware has been modified to 3.3V power supply, if the s oftware DTS configuration is still 1.8V configuration, the IO of VCCIO4 will be damaged!
Default
WIFI+BT+PCM RGMII0
GPIO2_A3
E27
GPIO2_A4
E28
GPIO2_A5
B28
GPIO2_A6
C27
GPIO2_A7
C28
GPIO2_B0
D27
GPIO2_B1
D26
GPIO2_B2
E25
GPIO2_B3
F28
GPIO2_B4
G27
GPIO2_B5
G28
GPIO2_B6
F27
GPIO2_B7
H25
GPIO2_C0
F24
GPIO2_C1
G23
GPIO2_C2
F25
GPIO2_C3
H24
GPIO2_C4
H23
GPIO2_C5
F26
GPIO2_C6
E26
VCCIO4
J21
12
Note:
When use HDMI, HDMITX_SCL/SDA cannot be shared with other devices
/
GPIO4_C2_d
/
GPIO4_C3_d
/
GPIO4_C4_d
/
GPIO4_C5_d
/
GPIO4_C6_d
/
GPIO4_C7_u
/
GPIO4_D0_u
/
GPIO4_D1_u
GPIO4_D2_d
VCCIO7
GPIO2_A3 GPIO2_A4 GPIO2_A5 GPIO2_A6
GPIO2_A7
GPIO2_B0
R1502 22R
GPIO2_B1 GPIO2_B2
GPIO2_B3 GPIO2_B4 GPIO2_B5 GPIO2_B6
GPIO2_B7 GPIO2_C0 GPIO2_C1
GPIO2_C2 GPIO2_C3 GPIO2_C4 GPIO2_C5
GPIO2_C6
VCCIO4
C1500 100nF
X5R
If a board needs to be compatible
10V C0201
with two voltage choices, recommended to enable BOM_ID
AF8 AA11 AH7
GPIO4_C5
AD8
GPIO4_C6
AE8
AG8 AG7 AH6
AB9
VCC_3V3 VCCA_1V8
V12
12
1 2
R1508 0R
1 2
R1510 0R
1 2
4G_DISABLE_GPIO4_C2 HDMIRX_INT_L_GPIO4_C3 SATA2_ACT_LED
HDMITX_SCL HDMITX_SDA HDMITX_CEC_M0
HDMIRX_RST_L_GPIO4_D2
If a board needs to be compatible with two
C1509
voltage choices,
100nF
recommended to enable BOM_ID
X5R 10V C0201
R0402
R0402
R0402
5%
5%
5%
SDMMC1_D0 SDMMC1_D1 SDMMC1_D2 SDMMC1_D3
SDMMC1_CMD
3
SDMMC1_CLK
WIFI_REG_ON_H_GPIO2_B1 WIFI_WAKE_HOST_H_GPIO2_B2
UART1_RX_M0 UART1_TX_M0 UART1_RTSn_M0 UART1_CTSn_M0
BT_REG_ON_H_GPIO2_B7 BT_WAKE_HOST_H_GPIO2_C0 HOST_WAKE_BT_H_GPIO2_C1
SOC_PCM_CLK SOC_PCM_SYNC SOC_PCM_OUT SOC_PCM_IN
CLK32K_OUT1_WIFI
VCCIO_WL
U1000O
SARADC
Recovery/
OTP
RK3568
BGA636_19R00X19R00X1R20
Option
SARADC_VIN0
SARADC_VIN1
SARADC_VIN2
SARADC_VIN3
SARADC_VIN4
SARADC_VIN5
SARADC_VIN6
SARADC_VIN7
SARADC_AVDD_1V8
OTP_VCC18
2
GPIO2_A3 GPIO2_A4 GPIO2_A5 GPIO2_A6
R1500 22R
GPIO2_A7
GPIO2_B0
GPIO2_B3 GPIO2_B4 GPIO2_B5 GPIO2_B6
GPIO2_B7 GPIO2_C0 GPIO2_C1
GPIO2_C2 GPIO2_C3 GPIO2_C4 GPIO2_C5
VCCIO4
If a board needs to be compatible with two voltage choices, recommended to enable BOM_ID
1 2
R1501 22R
1 2
R1503 22R
1 2
R1504 22R
1 2
R1505 22R
1 2
R1506 22R
1 2
R1507 22R
1 2
R1513 0R
1 2
V1.1
R1509 0R
1 2
R1511 0R
1 2
R0402
R0402
R0402
5%
5%
5%DNP
R04025%
R04025%
R04025%
R04025% R04025% R04025%
R04025%
GMAC0_RXD2 GMAC0_RXD3 GMAC0_RXCLK GMAC0_TXD2
GMAC0_TXD3
GMAC0_TXCLK
GMAC0_TXD0 GMAC0_TXD1 GMAC0_TXEN GMAC0_RXD0
GMAC0_RXD1 GMAC0_RXDV_CRS ETH0_REFCLKO_25M
GMAC0_MCLKINOUT
GMAC0_MDC GMAC0_MDIO GMAC0_RXER
VCC_1V8
VCC_3V3
Note:
If Ethernet PHY uses other models, please note whether the default pull-up and pull-down of GPIO affect Ethernet PHY function
At present, TXEN will be affected if it defaults to high level need to add a 4.7K resistance to ground
Note:
According to the actual choice of mounted Cannot be mounted at the same time
Default:1.8V Select the voltage according to the application
RTL8201F/YT8512C only support 3.3V IO VCCIO4 must be changed to 3.3V power supply
Note:
Must be mounted
SARADC_VIN0_KEY/RECOVERY SARADC_VIN0_KEY/RECOVERY
B27
SARADC_VIN1_HW_ID
C26
SARADC_VIN2_HP_HOOK
D24
SARADC_VIN3_BOM_ID
E23
SARADC_VIN4
G21
SARADC_VIN5
F22
SARADC_VIN6
G20
SARADC_VIN7
F21
H22
H20
12
VCC_1V8
12
C1510 100nF
X5R 10V C0201
C1511 100nF
X5R 10V C0201
C1501 1nF
1 2
C1502 1nF
1 2
C1503 1nF
1 2
C1504 1nF
1 2
C1505 1nF
1 2
C1506 1nF
1 2
C1507 1nF
1 2
C1508 1nF
1 2
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
X5R 50V
X5R 50V
X5R 50V
X5R 50V
X5R 50V
X5R 50V
X5R 50V
X5R 50V
SARADC_VIN0_KEY/RECOVERY
Note:
If there is no Key requirement, two test points must be reserved to facilitate firmware update
It is suggested to reserve a Key to facilitate the development debug
If SARADC_VIN0=0V at after power on and reset, then system will enter into loader mode.
SARADC_VIN0_KEY/RECOVERY
SARADC_VIN1_HW_ID SARADC_VIN2_HP_HOOK SARADC_VIN3_BOM_ID
SARADC_VIN4 SARADC_VIN5 SARADC_VIN6 SARADC_VIN7
1
GMAC0_TXEN
12
R1515
4.7K
5% R0402
DNP
VCCA_1V8
12
R1512 10K
1% R0402
TP1501 TP_0.7
TP1502 TP_0.7
Rockchip Confidential
5
Default
GPIO4_C5 GPIO4_C6
UART9_TX_M1 UART9_RX_M1
4
Option
GPIO4_C5 GPIO4_C6
SATA1_ACT_LED SATA0_ACT_LED
Note:
Caps of between dashed green lines and U1000 should be placed under the U1000 package
3
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
15.RK3568_SARADC/GPIO
15.RK3568_SARADC/GPIO
15.RK3568_SARADC/GPIO
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Designed by:
2
Designed by:
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
1
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
16 72
Sheet: of
16 72
Sheet: of
16 72
Page 17
5
4
3
2
1
RK3568_P(MIPI_CSI_RX)
U1000P
MIPI CSI RX
D D
RK3568
BGA636_19R00X19R00X1R20
MIPI_CSI_RX_D0P MIPI_CSI_RX_D0N
MIPI_CSI_RX_D1P MIPI_CSI_RX_D1N
MIPI_CSI_RX_D2P MIPI_CSI_RX_D2N
MIPI_CSI_RX_D3P MIPI_CSI_RX_D3N
MIPI_CSI_RX_CLK0P MIPI_CSI_RX_CLK0N
MIPI_CSI_RX_CLK1P MIPI_CSI_RX_CLK1N
MIPI_CSI_RX_AVDD_0V9
MIPI_CSI_RX_AVDD_1V8
AG12 AH12
AG11 AH11
AE11 AD11
AD9 AE9
AG10 AH10
AG9 AH9
W14
Y14
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
MIPI_AVDD_1V8
12
C1600 100nF
X5R 10V C0201
MIPI_AVDD_0V9
12
C1601 100nF
X5R 10V C0201
MIPI_CSI_RX_D0P MIPI_CSI_RX_D0N
MIPI_CSI_RX_D1P MIPI_CSI_RX_D1N
MIPI_CSI_RX_D2P MIPI_CSI_RX_D2N
MIPI_CSI_RX_D3P MIPI_CSI_RX_D3N
MIPI_CSI_RX_CLK0P MIPI_CSI_RX_CLK0N
MIPI_CSI_RX_CLK1P MIPI_CSI_RX_CLK1N
Option1
Option2
Sensor1 x4Lane
x2Lane
Sensor1
+
Sensor2
x2Lane
MIPI_CSI_RX_D0-3
MIPI_CSI_RX_CLK0
MIPI_CSI_RX_D0-1
MIPI_CSI_RX_CLK0
MIPI_CSI_RX_D2-3
MIPI_CSI_RX_CLK1
RK3568_M(VCCIO6 Domain)
U1000M
VCCIO6 Domain
C C
Operating Voltage=1.8V/3.3V
/
EBC_SDDO0
SDMMC2_D0_M0
CIF_D0 CIF_D1 CIF_D2 CIF_D3 CIF_D4 CIF_D5 CIF_D6
CIF_D8 CIF_D9 CIF_D10 CIF_D11 CIF_D12 UART7_TX_M2 CIF_D13 CIF_D14 CIF_D15
ISP_FLASHTRIGOUT
CAM_CLKOUT0 CAM_CLKOUT1
ISP_PRELIGHT_TRIG
I2C4_SCL_M0
I2C2_SDA_M1 I2C2_SCL_M1 /
CIF_HREF CIF_VSYNC
CIF_CLKOUT
CIF_CLKIN
B B
RK3568
BGA636_19R00X19R00X1R20
Note:
Caps of between dashed green lines and U1000 should be placed under the U1000 package. Other caps should be placed close to the U1000 package
A A
/
/
EBC_SDDO1
SDMMC2_D1_M0
/
SDMMC2_D2_M0
/
/
EBC_SDDO2
SDMMC2_D3_M0
EBC_SDDO3
/
/
/ /
EBC_SDDO4
SDMMC2_CMD_M0
/
EBC_SDDO5
SDMMC2_CLK_M0
/ / I2S1_SDI2_M1
EBC_SDDO6
SDMMC2_DET_M0
/ /
EBC_SDDO7
/
SDMMC2_PWREN_M0
GMAC1_TXD2_M1
/
/
EBC_SDDO8
/
EBC_SDDO9
GMAC1_TXD3_M1
/
EBC_SDDO10
GMAC1_TXCLK_M1
/
/
EBC_SDDO11
GMAC1_RXD2_M1
/
/
/
/
EBC_SDDO12
GMAC1_RXD3_M1
/
EBC_SDDO13
GMAC1_RXCLK_M1
/
GMAC1_TXD0_M1
/ /
EBC_SDDO14
/
/
GMAC1_TXD1_M1
/
EBC_SDDO15
GMAC1_TXEN_M1
EBC_SDCE0
/
/
/
/
EBC_SDCE1
GMAC1_RXD0_M1
/
/
GMAC1_RXD1_M1
EBC_SDCE2
/
EBC_SDCE3
GMAC1_RXDV_CRS_M1
/
/
GMAC1_RXER_M1I2C4_SDA_M0 ETH1_REFCLKO_25M_M1
EBC_GDOE
/
/
CAN2_RX_M0
EBC_GDSP
/
/
CAN2_TX_M0
/
/
EBC_SDSHR
GMAC1_MDC_M1
EBC_SDLE
/
/
GMAC1_MDIO_M1
/
/
EBC_SDOE
EBC_GDCLK
/
GMAC1_MCLKINOUT_M1
/
/
EBC_SDCLK
/
I2S1_MCLK_M1 I2S1_SCLK_TX_M1
/ /
I2S1_LRCK_TX_M1 I2S1_SDO0_M1
/ VOP_BT656_D3_M1
I2S1_SDI0_M1
/ /
I2S1_SDI1_M1
/
I2S1_SDI3_M1
/
/ /
UART1_RX_M1
/
UART7_RX_M2
/ /
UART9_TX_M2
/
UART9_RX_M2
/
SPI3_CS0_M0
SPI3_CS1_M0
/
SPI3_MISO_M0
/
SPI3_MOSI_M0
//
SPI3_CLK_M0
/
/
ISP_FLASH_TRIGIN
/
UART1_RTSn_M1
/
PWM11_IR_M1
UART1_CTSn_M1
/
/
VOP_BT656_D0_M1 / VOP_BT656_D1_M1 /
VOP_BT656_D2_M1 /
VOP_BT656_D4_M1
/ /
VOP_BT656_D5_M1
VOP_BT656_D6_M1
/
VOP_BT656_D7_M1CIF_D7
/
/UART1_TX_M1
PDM_CLK0_M1
PDM_SDI0_M1
/
PDM_CLK1_M1
/
PDM_SDI1_M1
/ /
PDM_SDI2_M1
PDM_SDI3_M1
/
I2S2_LRCK_TX_M1
I2S2_LRCK_RX_M1
/
I2S1_SCLK_RX_M1
/
I2S1_LRCK_RX_M1
/
I2S1_SDO1_M1
/
I2S1_SDO2_M1
/
/
I2S2_SDI_M1EBC_VCOM /
I2S2_SDO_M1
/
VOP_BT656_CLK_M1 /
I2S1_SDO3_M1
/
I2S2_MCLK_M1
I2S2_SCLK_TX_M1
/
I2S2_SCLK_RX_M1
/
AC5
/
GPIO3_C6_d
AA6
/
GPIO3_C7_d
AB5
/
GPIO3_D0_d
AB1
/
GPIO3_D1_d
Y7
/
GPIO3_D2_d
AC1
/
GPIO3_D3_d
AA1
/
GPIO3_D4_d
AA5
/
GPIO3_D5_d
Y6
/
GPIO3_D6_d
Y5
/
GPIO3_D7_d
AA3
/
GPIO4_A0_d
AA2
/
GPIO4_A1_d
Y4
/
GPIO4_A2_d
Y3
/
GPIO4_A3_d
Y2
/
GPIO4_A4_d
Y1
/
GPIO4_A5_d
W2
/
GPIO4_A6_d
W1
/
GPIO4_A7_d
V7
/
GPIO4_B0_d
V2
/
GPIO4_B1_d
V4
/
GPIO4_B2_d
V1
/
GPIO4_B3_d
V6
/
GPIO4_B4_d
V5
GPIO4_B5_d
U5
/
GPIO4_B6_d
U4
/
GPIO4_B7_d
U3
GPIO4_C0_d
/
U2
/
GPIO4_C1_d
R9
VCCIO6_1
U9 C1602
VCCIO6_2
Note:
If VCCIO6 domain power voltage is adjusted, the software DTS configuration must be updated synchronously, otherwise the IO may be damaged!
If the VCCIO6 hardware has been modified to
1.8V power supply, and the corresponding DTS must be modified to 1.8V configuration, otherwise the IO function of VCCIO6 will be abnormally.
The VCCIO6 hardware has been modified to
3.3V power supply, if the software DTS configuration is still 1.8V configuration, the IO of VCCIO6 will be damaged!
Note:
Camera MCLK can select the following clock: 1:CAM_CLKOUT0 2:CAM_CLKOUT1 3:CIF_CLKOUT 4:REFCLK_OUT(24MHz)
LCD_EN_H_GPIO3_C6 LCD_RST_L_GPIO3_C7 HDMIRX_DET_L_GPIO3_D0
MIPI_CAM1_RST_L_GPIO3_D2 MIPI_CAM1_PDN_L_GPIO3_D3 MIPI_CAM0_RST_L_GPIO3_D4 MIPI_CAM0_PDN_L_GPIO3_D5
GMAC1_TXD2_M1_SOC GMAC1_TXD3_M1_SOC GMAC1_TXCLK_M1_SOC
GMAC1_TXD0_M1_SOC GMAC1_TXD1_M1_SOC
GMAC1_TXEN_M1_SOC
GMAC1_RXER_M1/GPIO4_B2 ETH1_REFCLKO_25M_M1_SOC
V1.1
CIF_CLKOUT_SOC
C1603
12
12
100nF
1uF
X5R
X5R
10V
6.3V
C0201
C0402
R1600 22R R04025%1 2 R1601 22R R04025%1 2 R1602 22R R04025%1 2
R1603 22R R04025%1 2 R1604 22R R04025%1 2
R1605 22R R04025%1 2
R1608 22R R04025%1 2
R1611 0R R04025%1 2
R1609 22R R04025%1 2
R1610 0R
R0402
5%1 2
VCC_1V8VCCIO6
GMAC1_TXD2_M1 GMAC1_TXD3_M1 GMAC1_TXCLK_M1 GMAC1_RXD2_M1 GMAC1_RXD3_M1 GMAC1_RXCLK_M1 GMAC1_TXD0_M1 GMAC1_TXD1_M1
GMAC1_TXEN_M1
GMAC1_RXD0_M1 GMAC1_RXD1_M1
GMAC1_RXDV_CRS_M1
TP1600 TP_0.7
ETH1_REFCLKO_25M_M1
I2C2_SDA_M1
I2C2_SCL_M1
GMAC1_MDC_M1
GMAC1_MDIO_M1
CIF_CLKOUT
GMAC1_MCLKINOUT_M1
Note:
According to the actual choice of mounted Cannot be mounted at the same time
Default:1.8V Select the voltage according to the application
If the IO domain is to be used as FEPHY, since some FEPHY only support 3.3V IO, it is recommended to reallocate GPIO to reduce the cost of level conversion
If a board needs to be compatible with two voltage choices, recommended to enable BOM_ID
I2C2_SDA_M1 I2C2_SCL_M1
VCCIO6
12
R1606
2.2K
5% R0402
12
R1607
2.2K
5% R0402
Attention to the voltage matching
Rockchip Confidential
5
4
3
Mode
CIF_D0
CIF_D1
CIF_D2
CIF_D3
CIF_D4
CIF_D5
CIF_D6
CIF_D7
CIF_D8
CIF_D9
CIF_D10
CIF_D11
CIF_D12
CIF_D13
CIF_D14
CIF_D15
Support BT601 YCbCr 422 8bit input Support BT656 YCbCr 422 8bit input Support RAW 8/10/12bit input Support BT1120 YCbCr 422 8/10/12/16bit input, single/dual-edge sampling Support 2/4 mixed BT656/BT1120 YCbCr 422 8bit input
BT1120 16bit Mode: Default: D0-D7 <--> Y0-Y7 , D8-D15 <--> C0-C7 Swap ON: D0-D7 <--> C0-C7 , D8-D15 <--> Y0-Y7
GMAC
GMACx_TXD0
GMACx_TXD1
GMACx_TXD2
GMACx_TXD3
GMACx_TXEN
GMACx_TXCLK
GMACx_RXD0
GMACx_RXD1
GMACx_RXD2
GMACx_RXD3
GMACx_RXDV
GMACx_RXCLK
GMACx_RXER
GMACx_MDC
GMACx_MDIO
ETHx_REFCLKO_25M
GMACx_MCLKINOUT
GPIO
GPIO
16bit
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
12bit
--
--
--
--
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
Direction GEPHY
------>
------>
------>
------>
------>
------> <-----­<-----­<-----­<-----­<-----­<------
------> <----->
------> <------
------> <------
2
10bit
--
--
--
--
--
--
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
PHYx_TXD0
PHYx_TXD1
PHYx_TXD2
PHYx_TXD3
PHYx_TXEN
PHYx_TXCLK
PHYx_RXD0
PHYx_RXD1
PHYx_RXD2
PHYx_RXD3
PHYx_RXDV
PHYx_RXCLK
PHYx_MDC
PHYx_MDIO
PHYx OSC
PHYx_CLKOUT125(Option)
PHYx_RSTn
PHYx_INT/PMEB
8bit
--
--
--
--
--
--
--
--
D0
D1
D2
D3
D4
D5
D6
D7
GMAC Direction FEPHY
GMACx_TXD0
GMACx_TXD1
GMACx_TXEN
GMACx_RXD0
GMACx_RXD1
GMACx_RXDV
GMACx_RXER
GMACx_MDC
GMACx_MDIO
ETHx_REFCLKO_25M
GMACx_MCLKINOUT
GPIO
GPIO
------>
------>
------>
<-----­<------
<------
<------
------> <----->
------> <----->
------> <------
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
16.RK3568_VI Interface
16.RK3568_VI Interface
16.RK3568_VI Interface
Date:
Wednesday, J une 16, 2021
Date:
Wednesday, J une 16, 2021
Date:
Wednesday, J une 16, 2021
Designed by:
Zhangdz
Designed by:
Zhangdz
Designed by:
Zhangdz
1
PHYx_TXD0
PHYx_TXD1
PHYx_TXEN
PHYx_RXD0
PHYx_RXD1
PHYx_CRS_DV
PHYx_RXER
PHYx_MDC
PHYx_MDIO
PHYx OSC
PHYx_TXC
PHYx_RSTn
PHYx_INT/PMEB
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Default
Default
Default
Reviewed by:
Reviewed by:
Reviewed by:
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
Sheet: of
Sheet: of
17 72
17 72
17 72
Page 18
5
4
3
2
1
RK3568_S(MIPI_DSI_TX1)RK3568_R(MIPI_DSI_TX0/LVDS_TX0)
U1000R
D D
RK3568
BGA636_19R00X19R00X1R20
C C
MIPI_DSI_TX0_D0P/LVDS_TX0_D0P MIPI_DSI_TX0_D0N/LVDS_TX0_D0N
MIPI_DSI_TX0_D1P/LVDS_TX0_D1P MIPI_DSI_TX0_D1N/LVDS_TX0_D1N
MIPI_DSI_TX0_D2P/LVDS_TX0_D2P MIPI_DSI_TX0_D2N/LVDS_TX0_D2N
MIPI_DSI_TX0_D3P/LVDS_TX0_D3P MIPI_DSI_TX0_D3N/LVDS_TX0_D3N
MIPI_DSI_TX0_CLKP/LVDS_TX0_CLKP MIPI_DSI_TX0_CLKN/LVDS_TX0_CLKN
MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9
MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8
MIPI DSI TX0/LVDS TX0
AH17 AG17
AH16 AG16
AH14 AG14
AH13 AG13
AH15 AG15
W16
Y17
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
MIPI_AVDD_1V8
12
C1700 100nF
X5R 10V C0201
MIPI_AVDD_0V9
12
C1701 100nF
X5R 10V C0201
MIPI_DSI_TX0_D0P/LVDS_TX0_D0P MIPI_DSI_TX0_D0N/LVDS_TX0_D0N
MIPI_DSI_TX0_D1P/LVDS_TX0_D1P MIPI_DSI_TX0_D1N/LVDS_TX0_D1N
MIPI_DSI_TX0_D2P/LVDS_TX0_D2P MIPI_DSI_TX0_D2N/LVDS_TX0_D2N
MIPI_DSI_TX0_D3P/LVDS_TX0_D3P MIPI_DSI_TX0_D3N/LVDS_TX0_D3N
MIPI_DSI_TX0_CLKP/LVDS_TX0_CLKP MIPI_DSI_TX0_CLKN/LVDS_TX0_CLKN
RK3568_T(eDP TX)
U1000T
eDP_TX
eDP_TX_D0P eDP_TX_D0N
eDP_TX_D1P
B B
RK3568
BGA636_19R00X19R00X1R20
A A
eDP_TX_D1N
eDP_TX_D2P eDP_TX_D2N
eDP_TX_D3P eDP_TX_D3N
eDP_TX_AUXP eDP_TX_AUXN
eDP_TX_AVDD_0V9
eDP_TX_AVDD_1V8
EDP_TXD0P EDP_TXD0N
EDP_TXD1P EDP_TXD1N
EDP_TXD2P EDP_TXD2N
EDP_TXD3P EDP_TXD3N
C1704 100nF
1 2
C1705 100nF
1 2
C1706 100nF
1 2
C1709 100nF
1 2
C1707 100nF
1 2
C1708 100nF
1 2
C1710 100nF
1 2
C1711 100nF
1 2
12
12
C1713
100nF
X5R
10V
C0201
C1714 100nF
X5R 10V C0201
J28 K27
K28 L27
L28 M27
M28 N27
L25 M25
M20
M22
C0201 X5R 10V C0201 X5R 10V
C0201 X5R 10V C0201 X5R 10V
C0201 X5R 10V C0201 X5R 10V
C0201 X5R 10V C0201 X5R 10V
VCCA1V8_IMAGE
Note:
Caps of between dashed green lines and U1000 should be placed under the U1000 package. Other caps should be placed close to the U1000 package
Rockchip Confidential
5
VDDA0V9_IMAGE
12
C1715 1uF
X5R 10V C0402
Diff 100 Ohm ±10% Diff 100 Ohm ±10%
EDP_TX_D0P EDP_TX_D0N
EDP_TX_D1P EDP_TX_D1N
EDP_TX_D2P EDP_TX_D2N
EDP_TX_D3P EDP_TX_D3N
EDP_TX_AUXP EDP_TX_AUXN
12
C1716 1uF
X5R 10V C0402
4
U1000S
MIPI DSI TX1
RK3568
BGA636_19R00X19R00X1R20
MIPI_DSI_TX1_D0P MIPI_DSI_TX1_D0N
MIPI_DSI_TX1_D1P MIPI_DSI_TX1_D1N
MIPI_DSI_TX1_D2P MIPI_DSI_TX1_D2N
MIPI_DSI_TX1_D3P MIPI_DSI_TX1_D3N
MIPI_DSI_TX1_CLKP MIPI_DSI_TX1_CLKN
MIPI_DSI_TX1_AVDD_0V9
MIPI_DSI_TX1_AVDD_1V8
AD18 AE18
AD17 AC17
AD14 AC14
AD12 AE12
AD15 AE15
W15
MIPI_AVDD_1V8
Y15
RK3568_Q(HDMI2.0 TX)
3
U1000Q
HDMI2.0 TX
RK3568
BGA636_19R00X19R00X1R20
HDMI_TX_D2P HDMI_TX_D2N
HDMI_TX_D1P HDMI_TX_D1N
HDMI_TX_D0P HDMI_TX_D0N
HDMI_TX_CLKP HDMI_TX_CLKN
HDMI_TX_HPDIN
HDMI_TX_REXT
HDMI_TX_AVDD_0V9_1 HDMI_TX_AVDD_0V9_2
HDMI_TX_AVDD_1V8
AG22 AH22
AG21 AH21
AG20 AH20
AH19 AG19
Note:
If common mode inductors are needed, it is recommended to keep 2.2ohm in series to improve the antistatic ability
AB18
AA18
V17 V18
W18
Diff 100 Ohm ±10% Diff 100 Ohm ±10%
HDMI_TX2P HDMI_TX2N
HDMI_TX1P HDMI_TX1N
HDMI_TX0P HDMI_TX0N
HDMI_TXCLKP HDMI_TXCLKN
HDMI_TX_REXT
12
C1717 100nF
X5R 10V C0201
2
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
Diff 100 Ohm ±10%
MIPI_AVDD_0V9
12
12
R1702 2.2R R1703 2.2R
R1700 2.2R R1701 2.2R
R1704 2.2R R1705 2.2R
R1706 2.2R
L1700 NC
R1707 2.2R
R1708 1.62K
12
C1702 100nF
X5R 10V C0201
1 2 1 2
1 2 1 2
1 2 1 2
1 2
2
4
1 2
1 2
VDDA0V9_IMAGE
C1718 100nF
X5R 10V C0201
C1703 100nF
X5R 10V C0201
1
RP2_0405
3
R0201
12
C1719
4.7uF
X5R
6.3V C0402
MIPI_DSI_TX1_D0P MIPI_DSI_TX1_D0N
MIPI_DSI_TX1_D1P MIPI_DSI_TX1_D1N
MIPI_DSI_TX1_D2P MIPI_DSI_TX1_D2N
MIPI_DSI_TX1_D3P MIPI_DSI_TX1_D3N
MIPI_DSI_TX1_CLKP MIPI_DSI_TX1_CLKN
R04025% R04025%
R04025% R04025%
R04025% R04025%
R04025%
R04025%
1%
VCCA1V8_IMAGE
12
C1712 100nF
X5R 10V C0201
12
C1720
4.7uF
X5R
6.3V C0402
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
17.RK3568_VO Interface_1
17.RK3568_VO Interface_1
17.RK3568_VO Interface_1
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Zhangdz
Designed by:
Zhangdz
Designed by:
Zhangdz
HDMI_TX2P_PORT HDMI_TX2N_PORT
HDMI_TX1P_PORT HDMI_TX1N_PORT
HDMI_TX0P_PORT HDMI_TX0N_PORT
HDMI_TXCLKP_PORT HDMI_TXCLKN_PORT
HDMI_TX_HPDIN
Reviewed by:
Reviewed by:
Reviewed by:
1
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
18 72
Sheet: of
18 72
Sheet: of
Default
Default
Default
18 72
Page 19
5
4
RK3568_L(VCCIO5 Domain)
3
2
1
VCC_3V3
R1800 10K
5% R0402
12
VCC_3V3
R1804
2.2K
5% R0402
12
12
R1801 10K
5% R0402
od
R1805
2.2K
5% R0402
U1000L
D D
VCCIO5 Domain
12
Operating Voltage=1.8V/3.3V
LCDC_D0 LCDC_D1 LCDC_D2 LCDC_D3 LCDC_D4 LCDC_D5 LCDC_D6 LCDC_D7
LCDC_CLK
LCDC_D8 LCDC_D9
LCDC_D11 LCDC_D12
C C
B B
LCDC_D13 LCDC_D14
LCDC_D16 LCDC_D17 LCDC_D18 LCDC_D19 LCDC_D20 LCDC_D21 LCDC_D22
LCDC_HSYNC LCDC_VSYNC / LCDC_DEN
PWM14_M0 PWM15_IR_M0
RK3568
BGA636_19R00X19R00X1R20
VOP_BT656_D0_M0
/ /
VOP_BT656_D1_M0
/
VOP_BT656_D2_M0 VOP_BT656_D3_M0
/
VOP_BT656_D4_M0
/ SPI2_CS1_M1 /
VOP_BT656_D5_M0 VOP_BT656_D6_M0
/
VOP_BT656_D7_M0
/
VOP_BT656_CLK_M0
/
VOP_BT1120_D0
/
VOP_BT1120_D1 VOP_BT1120_D2
/ /
VOP_BT1120_D3 VOP_BT1120_D4
/
VOP_BT1120_CLK
/ /
VOP_BT1120_D5
/
VOP_BT1120_D7 VOP_BT1120_D8
/
VOP_BT1120_D9
/ /
VOP_BT1120_D10 / /
VOP_BT1120_D12 /
PWM12_M0
/
VOP_BT1120_D13 /
VOP_BT1120_D14 /
VOP_BT1120_D15
VOP_PWM_M1
/
SPDIF_TX_M1 /
/
SPI0_MISO_M1 SPI0_MOSI_M1
/
SPI0_CS0_M1
/
SPI0_CLK_M1
/ / /
SPI2_CS0_M1
/
SPI2_MOSI_M1 SPI2_MISO_M1
/
SPI2_CLK_M1
/
SPI1_CS0_M1
/ /
GMAC1_TXD2_M0 GMAC1_TXD3_M0
/
GMAC1_RXD2_M0
/ /
GMAC1_RXD3_M0 GMAC1_TXCLK_M0
/
GMAC1_RXCLK_M0
/ // VOP_BT1120_D6 /ETH1_REFCLKO_25M_M0 SDMMC2_PWREN_M1LCDC_D15 /
/
GMAC1_RXD0_M0
/
GMAC1_RXD1_M0 GMAC1_RXDV_CRS_M0
/
GMAC1_RXER_M0
/ /
GMAC1_TXD0_M0 GMAC1_TXD1_M0
/ /
GMAC1_TXEN_M0
/
SPI1_MOSI_M1
/
SPI1_MISO_M1 SPI1_CLK_M1
/
GMAC1_MDC_M0
/ /
GMAC1_MDIO_M0
PCIE20_CLKREQn_M1
/
PCIE20_WAKEn_M1
/ /
PCIE30X1_CLKREQn_M1
/
PCIE30X1_WAKEn_M1
/
PCIE30X2_CLKREQn_M1
/
PCIE30X2_WAKEn_M1 PCIE30X2_PERSTn_M1
/
UART8_TX_M1
/
/
UART8_RX_M1
/
PCIE30X1_PERSTn_M1
/
I2S3_MCLK_M0 I2S3_SCLK_M0LCDC_D10
/
I2S3_LRCK_M0
/
I2S3_SDO_M0
/
I2S3_SDI_M0
/
UART4_RX_M1 UART4_TX_M1
/
I2C5_SCL_M0
/
I2C5_SDA_M0
/ /
I2C3_SCL_M1VOP_BT1120_D11 I2C3_SDA_M1
/ /
UART3_TX_M1
/ / PDM_SDI3_M2UART3_RX_M1PWM13_M0LCDC_D23 // / GMAC1_MCLKINOUT_M0
PCIE20_PERSTn_M1
/
UART5_TX_M1 UART5_RX_M1
/
/
UART7_TX_M1 UART7_RX_M1
/
I2S1_MCLK_M2
/ /
I2S1_SCLK_TX_M2 I2S1_LRCK_TX_M2
/ /
I2S1_SDI0_M2
/
I2S1_SDI1_M2 I2S1_SDI2_M2
/ /
I2S1_SDI3_M2 I2S1_SDO0_M2
/
/
I2S1_SDO1_M2
/
SDMMC2_D0_M1 SDMMC2_D1_M1
/
SDMMC2_D2_M1
/
SDMMC2_D3_M1
/
SDMMC2_CMD_M1
/ //
SDMMC2_CLK_M1
/
SDMMC2_DET_M1
PWM8_M0
/
PWM9_M0
/
PDM_SDI0_M2
/
PDM_SDI1_M2
/ /
PWM10_M0 PWM11_IR_M0
/
PDM_SDI2_M2
/
/
I2S1_SDO2_M2 I2S1_SDO3_M2
/
I2S1_SCLK_RX_M2
/
PDM_CLK1_M2//
/
I2S1_LRCK_RX_M2/
If a board needs to be compatible with two voltage choices,
/
GPIO2_D0_d
/
GPIO2_D1_d
/
GPIO2_D2_d
/
GPIO2_D3_d
/
GPIO2_D4_d
/
GPIO2_D5_d
/
GPIO2_D6_d
/
GPIO2_D7_d
/
GPIO3_A0_d
/
GPIO3_A1_d
/
GPIO3_A2_d
/
GPIO3_A3_d
/
GPIO3_A4_d
/
GPIO3_A5_d
/
GPIO3_A6_d
/
GPIO3_A7_d GPIO3_B0_d
/
GPIO3_B1_d
/
GPIO3_B2_d
/
GPIO3_B3_d
/
GPIO3_B4_d
/
GPIO3_B5_d
/
GPIO3_B6_d
/
GPIO3_B7_d GPIO3_C0_d
/
GPIO3_C1_d
/
GPIO3_C2_d
/
GPIO3_C3_d
GPIO3_C4_d
/
GPIO3_C5_d
VCCIO5_1 VCCIO5_2
AG6 AD7 AC8 AC7 AF5 AF6 AD6 AH5
AH4
AB8 AE5 AG4 AF4 AH3 AG3 AH2 AG2
AG1 AF2 AF1 AE1 AE2 AE3 AD4 AD2
AD1 AA7 AC4
AC3 AC2
V10 V11
I2S3_MCLK_M0 I2S3_SCLK_M0_SOC I2S3_LRCK_M0_SOC I2S3_SDO_M0
GPIO3_B6 GPIO3_B7 GPIO3_C0
GPIO3_C4 GPIO3_C5
VCC_3V3
C1800
12
100nF
X5R 10V C0201
recommended to enable BOM_ID
PCIE20_CLKREQn_M1 PCIE20_WAKEn_M1 PCIE30X1_CLKREQn_M1 PCIE30X1_WAKEn_M1 PCIE30X2_CLKREQn_M1 PCIE30X2_WAKEn_M1 PCIE30X2_PERSTn_M1 PCIE30X2_PRSNT_L_GPIO2_D7
PCIE30X1_PRSNT_L_GPIO3_A0
PCIE30X1_PERSTn_M1
R1802 22R R04025%
1 2
R1803 22R R04025%
1 2
I2S3_SDI_M0 GMAC1_INT/PMEB_GPIO3_A7 GMAC1_RSTn_GPIO3_B0
UART4_RX_M1 UART4_TX_M1 I2C5_SCL_M0 I2C5_SDA_M0 RS485_DIR_GPIO3_B5
PCIE20_PERSTn_M1 HP_DET_L_GPIO3_C2 SPK_CTL_H_GPIO3_C3
TP1801 TP_0.7
Note:
If VCCIO5 domain power voltage is adjusted, the software DTS configuration must be updated synchronously, otherwise the IO may be damaged!
If the VCCIO5 hardware has been modified to 1.8V power supply, and the corresponding DTS must be modified to 1.8V configuration, otherwise the IO function of VCCIO5 will be abnormally.
The VCCIO5 hardware has been modified to 3.3V power supply, if the software DTS configuration is still 1.8V configuration, the IO of VCCIO5 will be damaged!
GMAC0_INT/PMEB_GPIO3_C0
GMAC1_INT/PMEB_GPIO3_A7
TP1800 TP_0.7
I2S3_SCLK_M0 I2S3_LRCK_M0
I2C5_SCL_M0 I2C5_SDA_M0
Default
GPIO3_B6 GPIO3_B6
A A
Note:
Caps of between dashed green lines and U1000 should be placed under the U1000 package
Default
GPIO3_B7 GPIO3_C0
PCIE20_PRSNT_L_GPIO3_B6 PCIE_ETH_ISOLATE_L_GPIO3_B6
UART3_TX_M1 UART3_RX_M1
Rockchip Confidential
5
4
PCIe EthernetPCIe slot
QSGMII/SGMII
GPIO3_C4 GPIO3_C5
GAMC1_MDIO_M0
Option Option
Option
3
GPIO3_B7 GPIO3_C0
GMAC0_RSTn_GPIO3_B7 GMAC0_INT/PMEB_GPIO3_C0
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
18.RK3568_VO Interface_2
18.RK3568_VO Interface_2
18.RK3568_VO Interface_2
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
Zhangdz
Default UART7
GPIO3_C4 GPIO3_C5
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
Sheet: of
1
UART7_TX_M1GMAC1_MDC_M0 UART7_RX_M1
V1.1
V1.1
V1.1
19 72
19 72
19 72
Page 20
5
4
3
2
1
RK3568_H(VCCIO1 Domain)
U1000H
D D
VCCIO1 Domain
Operating Voltage=1.8V/3.3V
ACODEC_ADC_DATA
CAN1_RX_M0
UART3_RX_M0
I2C3_SDA_M0 I2C3_SCL_M0
I2S1_MCLK_M0
I2S1_SCLK_RX_M0
I2S1_LRCK_TX_M0 I2S1_LRCK_RX_M0
I2S1_SDO0_M0 I2S1_SDO1_M0 I2S1_SDO2_M0
C C
I2S1_SDO3_M0
RK3568
BGA636_19R00X19R00X1R20
/
UART3_TX_M0
/
UART3_RTSn_M0
/
/I2S1_SCLK_TX_M0
UART3_CTSn_M0
/
UART4_RX_M0
/
UART4_RTSn_M0
/
UART4_TX_M0
UART4_CTSn_M0
/ / I2S1_SDI3_M0
I2S1_SDI2_M0
/
I2S1_SDI1_M0
/
I2S1_SDI0_M0
/
PDM_CLK1_M0
/
PDM_CLK0_M0
/
PDM_SDI3_M0 PDM_SDI2_M0
/ /
PDM_SDI1_M0
/
PDM_SDI0_M0
/ / CAN1_TX_M0
SCR_CLK
/
/ SCR_IO
/
SCR_RST
SCR_DET
/
PCIE30X1_PERSTn_M2
/
PCIE30X1_WAKEn_M2/
/
PCIE30X1_CLKREQn_M2
/
PCIE20_CLKREQn_M2 PCIE20_WAKEn_M2
//PCIE20_PERSTn_M2
AUDIOPWM_LOUT_P AUDIOPWM_LOUT_N
/
/ SPDIF_TX_M0
AUDIOPWM_ROUT_P/
AUDIOPWM_ROUT_N/
// /
ACODEC_ADC_CLK
ACODEC_DAC_CLK/
ACODEC_DAC_SYNC
//ACODEC_DAC_DATAL /
ACODEC_DAC_DATAR
/
ACODEC_ADC_SYNC
/
GPIO1_A0_u
/
GPIO1_A1_u
/
GPIO1_A2_d
/
GPIO1_A3_d
/
GPIO1_A4_d
/
GPIO1_A5_d
/
GPIO1_A6_d
/
GPIO1_A7_d
/
GPIO1_B0_d
/
GPIO1_B1_d
/
GPIO1_B2_d
/
GPIO1_B3_d
VCCIO1
D18 E18
I2S1_MCLK_M0_SOC
A19
I2S1_SCLK_TX_M0_SOC
B19
PDM_CLK1_M0_SOC
F18
I2S1_LRCK_TX_M0_SOC
A20
PDM_CLK0_M0_SOC
C20
B20 D20 E20 A21 B21
VCCIO_ACODEC
H17
12
C1900 100nF
X5R 10V C0201
I2C3_SDA_M0 I2C3_SCL_M0
R1902 22R R04025%
1 2
R1903 22R R04025%
1 2
R1904 22R R04025%
1 2
R1905 22R R04025%
1 2
R1906 22R R04025%
1 2
I2S1_SDO0_M0_RK809 PDM_SDI3_M0_ADC PDM_SDI2_M0_ADC PDM_SDI1_M0_ADC I2S1_SDI0_M0/PDM_SDI0_M0_RK809
Default 3.3V
If a board needs to be compatible with two voltage choices, recommended to enable BOM_ID
I2C3_SDA_M0 I2C3_SCL_M0
VCCIO_ACODEC
12
12
R1900
R1901
2.2K
2.2K
5%
5%
R0402
R0402
I2S1_MCLK_M0_RK809
I2S1_SCLK_TX_M0_RK809 PDM_CLK1_M0_ADC
I2S1_LRCK_TX_M0_RK809 PDM_CLK0_M0_RK809
Note:
If VCCIO1 domain power voltage is adjusted, the software DTS configuration must be updated synchronously,
B B
otherwise the IO may be damaged!
If the VCCIO1 hardware has been modified to
1.8V power supply, and the corresponding DTS must be modified to 1.8V configuration, otherwise the IO function of VCCIO1 will be abnormally.
The VCCIO1 hardware has been modified to
3.3V power supply, if the software DTS configuration is still 1.8V configuration, the IO of VCCIO1 will be damaged!
A A
Note:
Caps of between dashed green lines and U1000 should be placed under the U1000 package
Rockchip Confidential
5
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
4
3
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
19.RK3568_Audio Interface
19.RK3568_Audio Interface
19.RK3568_Audio Interface
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
Zhangdz
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
Sheet: of
1
V1.1
V1.1
V1.1
20 72
20 72
20 72
Page 21
5
12V/3A DCIN
J2000
4
DC-0007-5P
D D
DC3_DC_0007_5P
VCC12V_DC_IN
1 2 3
5
12
C2002 100nF
X5R 50V C0603
Note:
With SATA,PCIe, the current is estimated according to the actual number of SATA,PCIe
VCC12V_DCIN
1 2
12
F2000
R2000
JK-SMD200L
2R
F8050
5% R1210
C2004
12
2.2uF
X5R 25V C1206
1 2
D2000 SS32
DO_214AC
DNP
12
C2000
12
+
100uF
SVPF 25V E_E7
C2003 10uF
X5R 25V C1206
4
12
C2001
12
100nF
R2001
X5R
DNP
25V C0402
R0603
3
2
1
VCC3V3_SYS
VCC12V_DCIN VCC3V3_SYS
4.5V<VIN<18V
C2007
C2006
12
12
C C
10uF
X5R 25V C1206
100nF
X5R 25V C0402
1 2
R2002
5%
100K
R0402
>8V---> ON VENH min=1.5V
12
R2004 24K
5% R0402
C2012
12
100nF
X5R 10V
C0402
U2000
5
VIN
2
GND
4
EN
FB/OUT
SY8113B/SM8103ADC
SOT_23_6
6
LX
1
BS
3
C2005 100nF
1 2
X5R 25V
C0402
FB=0.6V
L2000
4.7uH
IND_606045
12
C2008 22pF
C0G 50V C0402
R2003 232K
1% R0402
12
R2005
49.9K
1% R0402
12
VCC5V0_SYS
VCC12V_DCIN VCC5V0_SYS
4.5V<VIN<18V
C2018
C2017
12
12
B B
10uF
X5R 25V C1206
100nF
X5R 25V C0402
EXT_EN
1 2
R2008
5%
10K
R0402
U2001
5
VIN
2
GND
4
EN
FB/OUT
SY8113B/SM8103ADC
SOT_23_6
6
LX
1
BS
3
C2016 100nF
1 2
X5R 25V
C0402
FB=0.6V
L2001
6.8uH
IND_606045
12
C2019 22pF
C0G 50V C0402
R2009 232K
1% R0402
12
R2011 30K
1% R0402
12
VCC5V0_USB
VCC12V_DCIN VCC5V0_USB
4.5V<VIN<18V
C2025
C2024
12
12
A A
10uF
X5R 25V C1206
100nF
X5R 25V C0402
EXT_EN
VCC_3V3
1 2
R2014
5%
10K
R0402
DNP
1 2
R2016
5%
10K
R0402
12
R2017 51K
5% R0402
DNP
U2002
5
VIN
2
GND
4
EN
FB/OUT
SY8113B/SM8103ADC
SOT_23_6
6
LX
1
BS
3
C2023 100nF
1 2
X5R 25V
C0402
FB=0.6V
L2002
6.8uH
IND_606045
12
R2015
C2026
12
22pF
C0G 50V C0402
232K
1% R0402
12
R2018 30K
1% R0402
Default 3.39V
C2009
12
120uF
+
SVPF 20V E_C6
Default 5.2V
C2020
12
120uF
+
SVPF 20V E_C6
Default 5.2V
C2027
12
120uF
+
SVPF 20V E_C6
C2010 22uF
X5R 10V C0805
C2021 22uF
X5R 10V C0805
C2028 22uF
X5R 10V C0805
C2011
12
100nF
X5R 10V
C0402
VCC5V0_SYS VCC_5V0
C2013
12
10uF
X5R 10V
VCC_3V3
C0603
R2012 27K
R0402
C2022
12
100nF
X5R 10V
C0402
C2029
12
100nF
X5R 10V
C0402
R2006 0R
C2014
12
100nF
X5R 10V
C0402
DNP
DNP
1 2
5%
1 2
12
R2007 100K
5% R0402
DNP
1
12
R2013 51K
5% R0402
DNP
2 3
1
12
R2010 10K
5% R0402
DNP
Q2001 S8050
SOT_23
2 3
DNP
R06035%
Q2000 WPM3407-3/TR
SOT_23
DNP
C2015
12
22uF
X5R 10V C0805
EXT_EN
12
12
12
Rockchip Confidential
5
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
20.Power_DC IN
20.Power_DC IN
20.Power_DC IN
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Designed by:
4
3
2
Designed by:
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
1
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
21 72
Sheet: of
21 72
Sheet: of
21 72
Page 22
5
I2C0_SCL_PMIC I2C0_SDA_PMIC PMIC_INT_L PMIC_SLEEP_H
RK809_32KOUT_WIFI
RESETn
RK809_PWRON
D D
PMIC RK809 DCDC
VDD_LOGIC
C2110
R2100
12
100nF
X5R 10V C0402
VDD_LOGIC
C C
VDD_GPU
Feedback from RK3568
VDD_GPU
C2122
12
100nF
X5R 10V C0402
Feedback from RK3568
Pin
12
12
100R
5% R0402
R2102
12
12
100R
5% R0402
I2S1_MCLK_M0_RK809 I2S1_SCLK_TX_M0_RK809 I2S1_LRCK_TX_M0_RK809
I2S1_SDO0_M0_RK809
I2S1_SDI0_M0/PDM_SDI0_M0_RK809
PDM_CLK0_M0_RK809
EXT_EN
C2106 22uF
12
C2112
C2111
12
22uF
22uF
X5R
X5R
6.3V
6.3V C0603
C0603
C2123
C2124
12
22uF
22uF
X5R
X5R
6.3V
6.3V
C0603
C0603
OUTVDD
C0603
VCC3V3_SYS
X5R 6.3V
L2100 470nH
IND_252010 DCR<50mohm
ON 0.9V
VCC3V3_SYS
L2102 470nH
IND_252010 DCR<50mohm
ON 0.9V
11
12
SW1
13
10
9
SW2
8
U2100A
VCC1
SW1
FB1
VCC2
SW2
FB2
RK809-5
QFN68_7R00X7R00X0R80_T
BUCK1/BUCK2
100R
RK3568
FB
4
HPL_OUT HP_SNS HPR_OUT
SPKN_OUT SPKP_OUT
MIC1_INP MIC1_INN
BUCK1 BUCK4
2.5A 1.5A
0.5-2.4V 0.5-3.4V
BUCK2
2.5A 1.5A
0.5-2.4V
BUCK3
0.5-2.4V
FB3=0.8V
VCC4
VCC3
VBUCK3
3
PMIC RK809 LDO
VCC3V3_SYS
12
VCC3V3_SYS
12
VCC3V3_SYS
12
VCC3V3_SYS
12
VCC3V3_SYS
12
R2101 100R
5% R0402
VDD_NPU
12
VCC_DDR
12
VDD
RK3568
C2115 100nF
X5R 10V C0402
VDD_NPU
C2126 10uF
X5R 10V C0603
62K 1%
47K 1%
110K 1%
82K 1%DDR3L 1.35V
68K 1%
OUT
100R
FB
C2107 10uF
1 2
SW4
IND_252010 DCR<50mohm
C2120 10uF
1 2
SW3
IND_252010
12
R2103 62K
1% R0402
12
R2104 120K
1% R0402
BUCK4
DCR<50mohm
X5R 10V C0603
12
C0603
DDR4
LPDDR4/4x
DDR3
LPDDR3
C2114
C2113
12
22uF
22uF
X5R
X5R
6.3V
6.3V C0603
C0603
Feedback from RK3568
X5R 10V
12
Default DDR4
12
C2125 22uF
X5R
6.3V C0603
1.21V
1.11V
1.53V
1.25V
VCC3V3_SYS
66
65
SW4
FB4
SW3
FB3
64
24
25
26
27
OFF 0.9V
FB=0.8V
L2101 470nH
VCC3V3_SYS
L2103 470nH
U2100B
400mA LDO:
22 23
VCC5
C2100 1uF
X5R
6.3V C0402
30 28
VCC6
C2105 1uF
X5R
6.3V C0402
4 3
VCC7
C2117 1uF
X5R 10V C0402
57
VCC8
C2127 1uF
X5R
6.3V
VCC8\9:
C0402
2.7V-5.5V
54
VCC9
C2131
RK809-5
10uF
QFN68_7R00X7R00X0R80_T
X5R 10V C0603
C2132 1uF
C2133 1uF
C2134 1uF
C2135 1uF
400mA@Vin>3V 200mA@Vin>2V
12
C0402
12
C0402
12
C0402
12
C0402
2
LDO1 400mA
LDO2 400mA
Low noise
LDO3 100mA
Codec vddio
LDO4 400mA
LDO5 400mA
LDO6 400mA
LDO7 400mA
LDO8 400mA
LDO9 400mA
2.1A SWOUT2
2.1A SWOUT1
BUCK5
1.5V-3.6V
2.5A
X5R 6.3V
X5R 6.3V
X5R 6.3V
X5R 6.3V
SW5
FB5
VDDA_0V9
VCCA_1V8
VDDA0V9_IMAGE
VCCA1V8_IMAGE
Default ON/OFF
OFF 0.9V
C2101 1uF
1 2
ON 0.9V
C2102 1uF
21
20
29
31
5
6
58
55
53
SW5
59
R2105 DNP
1 2
ON 0.9V
C2103 1uF
1 2
OFF 3.3V
C2104 4.7uF
1 2
ON 3.3V
C2108 1uF
1 2
ON 3.3V
C2109 1uF
1 2
ON 1.8V
C2116 1uF
1 2
ON 1.8V
C2118 1uF
1 2
OFF 1.8V
C2119 1uF
1 2
ON 3.3V
C2121 1uF
1 2
ON 3.3V
C2128 10uF
1 2
ON 1.8V
L2104 470nH
IND_252010
12
FB2100 120R-100MHz
1 2
FB2101 120R-100MHz
1 2
FB2102 120R-100MHz
1 2
FB2103 120R-100MHz
1 2
DCR<50mohm
R0402
1
C0402X5R 6.3V
C0402X5R 6.3V
C0402X5R 6.3V
C0402X5R 6.3V
C0402X5R 6.3V
C0402X5R 6.3V
C0402X5R 6.3V
C0402X5R 6.3V
C0402X5R 6.3V
C0402X5R 6.3V
C0603X5R 10V
VCC_1V8
C2130
C2129
12
12
R2106 0R
L06030.030ohm
L06030.030ohm
L06030.030ohm
L06030.030ohm
22uF
X5R
6.3V C0603
22uF
X5R
6.3V C0603
12
R0402
VDDA0V9_IMAGE
VDDA_0V9
VDDA0V9_PMU
VCCIO_ACODEC
VCCIO_SD
VCC3V3_PMU
VCCA_1V8
VCCA1V8_PMU
VCCA1V8_IMAGE
VCC3V3_SD
VCC_3V3
5%
USB_AVDD_0V9
USB_AVDD_1V8
MIPI_AVDD_0V9
MIPI_AVDD_1V8
PMIC RK809 Managerment PMIC RK809 CODEC
3
C2151 100nF
X5R 10V C0402
U2100C
46
VREF
47
GNDREF
69
ePAD
50
XIN
51
XOUT
2
SDA
1
SCL
7
INT
49
SLEEP
68
CLK32K
67
RESETB
RK809-5
QFN68_7R00X7R00X0R80_T
Gas Gauge
30K
VCC_RTC
BATDIV
EXT_EN
X5R 10V
C0G 50V
Y2100
32.768KHz
C0G 50V
5%
5%
5%
5%
RK809_VREF
12
SDA_809
SCL_809
PMIC_INT_L
PMIC_SLEEP_H
RK809_CLK32KOUTRK809_32KOUT_WIFI
RESETn
12
C2136 1uF
12
B B
A A
Note:
If the external RTC IC is used, Can choose not mounted
C2138 22pF
C2144 22pF
I2C0_SDA_PMIC
I2C0_SCL_PMIC
VCC3V3_PMU
R2107 22R
1 2
R2108 22R
1 2
R2110 0R
1 2
R2112 10K
1 2
C0402
12
C0402
CRY2_6R90X1R40X1R30
12
C0402
R0402
R0402
R0402
R0402
Rockchip Confidential
5
4
SNSP
SNSN
PWRON
VCC3V3_SYS
C2139 1uF
45
56
62
63
60
61
VDC
52
EXT_EN
RK809_VDC
RK809_PWRON
12
C2152 100nF
X5R 10V C0402
1 2
1.2V
C0402
12
C2149 100nF
X5R 10V C0402
X5R 10V
VCC12V_DCIN
12
12
R2109 100K
5% R0402
R2111 11K
5% R0402
3
VCC5V0_SYS
FB2104 120R-100MHz
1 2
C2140 10uF
C2137 4.7uF
C2141 1uF
C2143 2.2uF
C2145 1uF
C2146 1uF
X5R 10V
12
C0603
X5R 10V
12
C0603
X5R 6.3V
12
C0402
X5R 10V
12
C0402
X5R 6.3V
12
C0402
X5R 6.3V
12
C0402
I2S1_MCLK_M0_RK809
I2S1_SCLK_TX_M0_RK809
I2S1_LRCK_TX_M0_RK809
I2S1_SDO0_M0_RK809
I2S1_SDI0_M0/PDM_SDI0_M0_RK809
PDM_CLK0_M0_RK809
L0603 2A
V1.1
VCC_CPVDD
VCC_CPVSS
VCC_1P8D
VCC_1P8A
U2100D
33
VCC_SPK_HP
36
CPn
37
CPp
38
VCC_CPVDD
35
VCC_CPVSS
48
VCC_1P8D
Power from VCC_RTC
44
VCC_1P8A
16
MCLK
15
BCLK
14
LRCLK
17
SDI
18
SDO/PDMDATA
19
PDMCLK
RK809-5
QFN68_7R00X7R00X0R80_T
Note:
If RK809-5 codec is not used, then Pin 14,15,16,17,19,40 Tie VSS Pin 18,36,37,38,35,39,41,34,32,43,42 Leave floating
2
IO Power =LDO4
HPL_OUT
HP_SNS
HPR_OUT
SPK_OUTn
SPK_OUTp
MIC1p
MIC_L
MIC1n
MIC_R
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
HPL_OUT
39
HP_SNS
40
HPR_OUT
41
34
32
43
42
FB2105
SPKN
180R-100M
L0603
FB2106
SPKP
180R-100M
L0603
C2148 100nF
C2150
12
27pF
C0G 50V C0402
C2153 100nF
C2154
12
27pF
C0G 50V C0402
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
21.Power_PMIC
21.Power_PMIC
21.Power_PMIC
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
1
1 2
1.5A
1 2
1.5A
12
X5R 10V C0402
12
X5R 10V C0402
Default
Default
Default
C2142 680pF
C0G 50V
1 2
C0402
SPKN_OUT
SPKP_OUT
C2147
12
680pF
C0G 50V C0402
MIC1_INP
MIC1_INN
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
22 72
Sheet: of
22 72
Sheet: of
22 72
Page 23
5
I2C0_SCL_PMIC I2C0_SDA_PMIC RTCIC_32KOUT PMIC_SLEEP_H VDD_CPU_COM
RTCIC_INT_L_GPIO0_D3
I2C5_SCL_M0
I2C5_SDA_M0
4
LCD0_PWREN_H_GPIO0_C7 LCD1_PWREN_H_GPIO0_C5
3
2
1
VDD_CPU
D D
VCC3V3_PMU VCC5V0_SYS
12
C2204 1uF
X5R 10V C0402
V1.1
VDD_CPU
C2205
12
VDD_CPU_COM
C2206
12
22uF
22uF
X5R
X5R
6.3V
6.3V
C0603
C0603
Feedback from RK3568
OUT
100R
FB
12
C2207 22uF
X5R
6.3V C0603
C2208
12
22uF
X5R
6.3V C0603
DNP
VDD
RK3568
12
12
R2200 51K
5% R0402
C2210
12
100nF
X5R 10V C0402
DNP
C2201 22uF
X5R 10V C0805
12
C2202 22uF
X5R 10V C0805
PMIC_SLEEP_H I2C0_SDA_PMIC I2C0_SCL_PMIC
U2200
D1
VIN
D2
VIN
E1
VIN
E2
VIN
A2
EN
A1
VSEL
B1
SDA
A3
SCL
B4
AGND
TCS4525_WT
CSP20_1R96X1R56X0R66
SW_1 SW_2 SW_3 SW_4 VOUT
GND GND GND GND GND GND
/RK860
D3
L2200
D4
0.24uH
E3
IND_252012
E4 A4
B2 B3 C1 C2 C3 C4
R2201
12
100R
5% R0402
V1.1
C C
RTC IC
Note:
The power off hold time scheme is required, It is recommended to use external RTC IC
But, it will not support the timing poweron function
C2200 12pF
Y2200
32.768KHz
CRY2_6R90X1R40X1R30
C2203 DNP
RTCIC_INT_L_GPIO0_D3
--Option
C0G 50V
12
C0402
C0402
VCCA1V8_PMU
12
DNP
1 2
R2203 10K
5% R0402
12
VCC_RTC
3
U2201
1
OSCI
OSCO
CLKOUT
INT
VSS4SDA
VDD
SCL
2
3
HYM8563TS
TSSOP8_3R10X3R10X1R10
8
7
6
5
RTCIC_32KOUT
I2C5_SCL_M0
I2C5_SDA_M0
C2209 100nF
VCC3V3_SYS
2
3
1
D2200 BAT54C
SOT_23
1 2
C0402
R2202 10K
X5R 10V
1 2
J2200
1
1
2
2
CR1220-3V
BAT_CR1220
+
-
R0402
5%DNP
VCC_3V3
Address:Read A3H,Write A2H
DCDC
VCC3V3_LCD0VCC3V3_SYS VCC3V3_LCD1VCC3V3_SYS
2 3
12
12
1 2
5%
C2212 100nF
X5R 10V
C0402
R2204 100K
Q2200
1
5%
WPM2015-3/TR
R0402
SOT_23
12
R2206 10K
R0402 5%
Q2202
1
2 3
S8050
SOT_23
12
R2210 51K
R0402 5%
C2213
12
10uF
X5R 10V C0603
C2214
12
10uF
X5R 10V C0603
R2209 10K
R0402
12
1 2
5%
C2215 100nF
X5R 10V
C0402
C2211
12
10uF
X5R 10V C0603
B B
LCD0_PWREN_H_GPIO0_C7 LCD1_PWREN_H_GPIO0_C5
R2208 10K
R0402
2 3
12
R2205 100K
Q2201
1
5%
WPM2015-3/TR
R0402
SOT_23
12
R2207 10K
R0402 5%
Q2203
1
12
R2211 51K
R0402 5%
2 3
S8050
SOT_23
C2216
12
10uF
X5R 10V C0603
According to the actual product assigned to the LCM
A A
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
22.Power_Ext Discrete/RTC IC
22.Power_Ext Discrete/RTC IC
22.Power_Ext Discrete/RTC IC
Rockchip Confidential
5
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Designed by:
4
3
2
Designed by:
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
1
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
23 72
Sheet: of
23 72
Sheet: of
23 72
Page 24
5
4
3
2
1
FLASH_VOL_SEL
Flash Power Manage
VCCIO2 domain voltage: Recommend voltage value
FLASH_VOL_SEL state decided to VCCIO2 domain IO driven by default
(VCCIO_FLASH)
D D
eMMC
Nand flash
SPI flash
1.8V
Default 3.3V, Optional 1.8V
Default 1.8V, Optional 3.3V
FLASH_VOL_SEL --> Logic=H
FLASH_VOL_SEL --> Logic=L(Default)
FLASH_VOL_SEL --> Logic=H(Default)
Note:
According to the actual choice of mounted Cannot be mounted at the same time
VCC_3V3
C C
R2300 0R
1 2
VCC_1V8
R2302 0R
1 2
1
C2300
12
1uF
X5R
6.3V C0402
B B
DNP
DNP
1 2
R2304 10K
5%
R0402
12
C2302 DNP
C0402
2
3
5%DNP
R0402
5%
R0402
U2300
IN
GND
EN
PT5108E23E-18
DNP
SOT_23_5
OUT
VCCIO_FLASHVCC_3V3
5
C2301
12
4.7uF
4
BP
12
C2303 DNP
C0402
X5R
6.3V C0603
FLASH_VOL_SEL
VCC3V3_PMU
12
R2301 10K
5% R0402
12
R2303
2.2K
5% R0402
DNP
Note: FLASH_VOL_SEL state decided to VCCIO2 domain IO driven by default Logic=L:3.3V IO driven Logic=H:1.8V IO driven
When VCCIO2 voltage is connected to 1.8V, FLASH_VOL_SEL must be high When VCCIO2 voltage is connected to 3.3V, FLASH_VOL_SEL must be low If VCCIO2 power supply voltage and FLASH_VOL_SEL fails to meet the above relationship, its function will be abnormally(for example, it cannot be started normally) or IO will be damaged.
A A
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Rockchip Confidential
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Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
4
3
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
23.Power_Flash Power Manage
23.Power_Flash Power Manage
23.Power_Flash Power Manage
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Default
Default
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
24 72
Sheet: of
24 72
Sheet: of
24 72
Page 25
5
USB3_OTG0_DP USB3_OTG0_DM
USB3_OTG0_VBUSDET USB3_OTG0_ID
USB3_OTG0_SSTXP USB3_OTG0_SSTXN
USB3_OTG0_SSRXP USB3_OTG0_SSRXN
D D
C C
B B
USB3_HOST1_DP USB3_HOST1_DM
USB3_HOST1_SSTXP USB3_HOST1_SSTXN
USB3_HOST1_SSRXP USB3_HOST1_SSRXN
USB2_HOST2_DP USB2_HOST2_DM
USB2_HOST3_DP USB2_HOST3_DM
USB_OTG_PWREN_H_GPIO0_A5
USB_HOST_PWREN_H_GPIO0_A6
USB_OTG_PWREN_H_GPIO0_A5
USB_HOST_PWREN_H_GPIO0_A6
USB3_OTG0_VBUSDET
USB3_OTG0_ID USB3_OTG0ID
VCC5V0_USB
R2505 0R
C2502 1uF
12
X5R 10V C0402
C2505 1uF
12
X5R 10V C0402
12
VCC5V0_USB
12
5
4
R2511 DNP
R0402
R2515 0R
5
4
R2517 DNP
R0402
R2500 10K
12
R2501 15K
5% R0402
R2504 100R
U2500
VOUT
IN
GND
OCB
EN
SY6280AAC/TCS9163
SOT_23_5
U2501
VOUT
IN
GND
OCB
EN
SY6280AAC/TCS9163
SOT_23_5
4
5%1 2
VCC5V0_USB_OTG0
R0402
5%1 2
12
R0402
D2502 ESD5451N
ESD0402
VCC5V0_USB_OTG0
5%DNP1 2
R0805
1
2
3
5%DNP1 2 R2513 0R R02015%1 2
R0805
1
2
3
12
C2503
+
120uF
SVPF 20V
12
12
E_C6
R2512
4.7K
It can be configured
5%
according to the actual needs
R0402
VCC5V0_USB_HOST1
12
C2506
+
120uF
SVPF 20V E_C6
R2518
4.7K
It can be configured
5%
according to the actual needs
R0402
12
12
R2506
C2504
10K
100nF
5%
X5R
R0402
10V
DNP
C0402
12
12
C2507
R2516
100nF
10K
X5R
5%
10V
R0402
C0402
DNP
3
USB3_OTG0_SSRXN USB3_OTG0_SSRXP
USB3_OTG0_SSTXN USB3_OTG0_SSTXP
Note: The ESD of USB3.0 signal cannot be change at will If it needs to be change, the same specification must be selected.
R2502 0R R02015%1 2 R2503 0R R02015%1 2
C2500 100nF C2501
Cj<=0.4pF
USB3_OTG0_DP
USB3_OTG0_DM
Note:
If common mode inductors are needed, it is recommended to keep 2.2ohm in series to improve the antistatic ability
Note: The ESD of USB3.0 signal cannot be change at will If it needs to be change, the same specification must be selected.
R2508 2.2R
R2509 2.2R
USB3_HOST1_SSRXN USB3_HOST1_SSRXP
USB3_HOST1_SSTXN USB3_HOST1_SSTXP
R0402
R0402
R2507 0R
5%1 2
5%1 2
R2510 0R
R2514 0R R02015%1 2
C2508 100nF C2509
Cj<=0.4pF
USB3_HOST1_DP
R2520 2.2R
USB3_HOST1_DM
R2521 2.2R
Note:
If common mode inductors are needed, it is recommended to keep 2.2ohm in series to improve the antistatic ability
R0402
R0402
5%1 2
5%1 2
R2519 0R
2
4
R2522 0R
1 2 1 2
2
4
1 2 1 2
10V
100nF
10V
10V
100nF
10V
C0201
C0201
C0201
C0201
R0402
L2501 NC
RP2_040513
R0402
X5R
X5R
R0402
L2500 NC
RP2_040513
R0402
X5R
X5R
5%1 2
5%1 2
D2500 ESD5311X
ESD0402
D2503
ESD5311X
ESD0402
5%1 2
5%1 2
D2507 ESD5311X
ESD0402
D2509
ESD5311X
ESD0402
2
1 2
1 2
12
12
D2505 ESD5341N
ESD0402
1 2
USB3_OTG0DP
USB3_OTG0DM
12
D2506 ESD5341N
ESD0402
1 2
1 2
12
12
D2511 ESD5341N
ESD0402
1 2
USB3_HOST1DP
USB3_HOST1DM
12
D2512 ESD5341N
ESD0402
D2501 ESD5311X
ESD0402
D2504 ESD5311X
ESD0402
D2508 ESD5311X
ESD0402
D2510 ESD5311X
ESD0402
USB3_OTG0SSRXN USB3_OTG0SSRXP
USB3_OTG0DP USB3_OTG0DM
USB3_OTG0SSTXN USB3_OTG0SSTXP
VCC5V0_USB_OTG0
USB3_HOST1SSRXN USB3_HOST1SSRXP
USB3_HOST1DP USB3_HOST1DM
USB3_HOST1SSTXN USB3_HOST1SSTXP
VCC5V0_USB_HOST1
USB3_OTG0ID USB3_OTG0DP USB3_OTG0DM
VCC5V0_USB_OTG0
USB3_HOST1DP
USB3_HOST1DM
VCC5V0_USB_HOST1
5
RX-
4
GND1
6
RX+
3
D+
7
GND2
2
D-
8
TX-
1
VBUS
9
TX+
5
RX-
4
GND1
6
RX+
3
D+
7
GND2
2
D-
8
TX-
1
VBUS
9
TX+
11
G2
G1
J2500
10
USB30_AF_SMT_THF
USB30_AF_SMT_THF
7
5
GND
G16G2
4
ID
3
DP
2
DM
1
VUSB
9
J2501 USB20_micro
USB20Micro5_MU05_10MGF_T
11
G2
G1
J2502
10
USB30_AF_SMT_THF
USB30_AF_SMT_THF
6
G2
4
GND
3
D+
2
D-
1
5V
G1
J2503
5
USB20_TPYEA_01
USB20A4_USB_AF_01_001
1
Default
USB3.0 OTG0
And SATA0 Option
G38G4
USB2.0 OTG0 Option With USB ID
Default
USB3.0 HOST1
And SATA1 Option
USB2.0 HOST1 Option
6
R0805
R0805
VCC5V0_USB_HOST2
5%DNP1 2
1
2
3
5%DNP1 2
1
2
3
12
C2511
+
120uF
SVPF 20V E_C6
12
R2529
4.7K
It can be configured
5%
according to the actual needs
R0402
VCC5V0_USB_HOST3VCC5V0_USB
12
C2514
+
120uF
SVPF 20V E_C6
12
R2536
4.7K
It can be configured
5%
according to the actual needs
R0402
12
12
R2524
C2512
10K
100nF
5%
X5R
R0402
10V
DNP
C0402
12
12
C2515
R2533
100nF
10K
X5R
5%
10V
R0402
C0402
DNP
USB2_HOST2_DP
R2526 2.2R
R2527 2.2R
Note:
If common mode inductors are needed, it is recommended to keep 2.2ohm in series to improve the antistatic ability
USB2_HOST3_DP USB2_HOST3DP
R2532 2.2R
USB2_HOST3_DM
R2534 2.2R
Note:
If common mode inductors are needed, it is recommended to keep 2.2ohm in series to improve the antistatic ability
R0402
R0402
R0402
R0402
5%1 2
5%1 2
5%1 2
5%1 2
R2525 0R
2
4
R2528 0R
R2531 0R
2
4
R2535 0R
R0402
L2502 NC
RP2_040513
R0402
R0402
L2503 NC
RP2_040513
R0402
5%1 2
5%1 2
5%1 2
5%1 2
D2513 ESD5341N
ESD0402
D2515 ESD5341N
ESD0402
USB2_HOST2DP
USB2_HOST2DMUSB2_HOST2_DM
12
12
D2514 ESD5341N
ESD0402
12
12
D2516 ESD5341N
ESD0402
VCC5V0_USB_HOST2
USB2_HOST3DM
VCC5V0_USB_HOST3
VCC5V0_USB
R2523 0R
C2510 1uF
12
X5R 10V C0402
USB_HOST_PWREN_H_GPIO0_A6
A A
C2513 1uF
12
X5R 10V C0402
USB_HOST_PWREN_H_GPIO0_A6
U2502
5
VOUT
IN
GND
4
OCB
EN
SY6280AAC/TCS9163
SOT_23_5
R2530 0R
U2503
5
VOUT
IN
GND
4
OCB
EN
2.4V
SY6280AAC/TCS9163
SOT_23_5
Rockchip Confidential
5
4
3
2
4
3
2
1
4
3
2
1
GND
D+
D-
5V
GND
D+
D-
5V
G2
G1
J2504
5
USB20_TPYEA_01
USB20A4_USB_AF_01_001
6
G2
G1
J2505
5
USB20_TPYEA_01
USB20A4_USB_AF_01_001
USB2.0 HOST2
USB2.0 HOST3
And 4G module Option
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
Rockchip Electronics Co., Ltd
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
25.USB2/USB3 Port
25.USB2/USB3 Port
25.USB2/USB3 Port
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Zhangdz
Zhangdz
Zhangdz
1
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
Sheet: of
Sheet: of
25 72
25 72
25 72
Page 26
5
DDR3_DQ0 DDR3_DQ1 DDR3_DQ2 DDR3_DQ3 DDR3_DQ4 DDR3_DQ5 DDR3_DQ6 DDR3_DQ7
DDR3_DM0
DDR3_DQS0P
D D
C C
B B
A A
DDR3_DQS0N
DDR3_DQ8 DDR3_DQ9 DDR3_DQ10 DDR3_DQ11 DDR3_DQ12 DDR3_DQ13 DDR3_DQ14 DDR3_DQ15
DDR3_DM1
DDR3_DQS1P DDR3_DQS1N
DDR3_DQ16 DDR3_DQ17 DDR3_DQ18 DDR3_DQ19 DDR3_DQ20 DDR3_DQ21 DDR3_DQ22 DDR3_DQ23
DDR3_DM2
DDR3_DQS2P DDR3_DQS2N
DDR3_DQ24 DDR3_DQ25 DDR3_DQ26 DDR3_DQ27 DDR3_DQ28 DDR3_DQ29 DDR3_DQ30 DDR3_DQ31
DDR3_DM3
DDR3_DQS3P DDR3_DQS3N
DDR3_A9 DDR3_A2 DDR3_A4 DDR3_A3
DDR3_BA1 DDR3_A11 DDR3_A13 DDR3_A8
DDR3_A6 DDR3_A5 DDR3_A10 DDR3_A7
DDR3_BA2 DDR3_A14 DDR3_A15 DDR3_A0
DDR3_RASn DDR3_CASn DDR3_A1 DDR3_A12
DDR3_WEn DDR3_BA0 DDR3_CKE
DDR3_CLKP DDR3_CLKN
DDR3_ODT1 DDR3_CS1n DDR3_ODT0 DDR3_CS0n
DDR3_RESETn
DDRPHY_VREFOUT
DDR3_DQ0 DDR3_DQ6 DDR3_DQ1 DDR3_DQ7 DDR3_DQ2 DDR3_DQ4 DDR3_DQ3 DDR3_DQ5
DDR3_DQS0P DDR3_DQS0N
DDR3_DM0
DDR3_DQ10 DDR3_DQ12 DDR3_DQ11 DDR3_DQ14 DDR3_DQ8 DDR3_DQ13 DDR3_DQ9 DDR3_DQ15
DDR3_DQS1P DDR3_DQS1N
DDR3_DM1
VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDRVCC_DDR
12
VCC_DDR
12
VCC_DDR
12
R3100 240R
1% R0402
C3109 10uF
C0603 X5R
6.3V
C3131 10uF
C0603 X5R
6.3V
U3100 DDR3_16bit
FBGA96_14R00X11R00X1R20
DDR3 x16bit
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
F3
DQSL
G3
DQSL
E7
DML
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
C7
DQSU
B7
DQSU
D3
DMU
H1
VREFDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VDDQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
VSSQ
L8
ZQ0
L9
ZQ1
C3111
C3110
12
12
12
10uF
C0603 X5R
6.3V
C3132 10uF
C0603 X5R
6.3V
100nF
C0402 X5R 10V
C3133
12
100nF
C0402 X5R 10V
AP/A10
BC/A12
VREFCA
12
12
CKE0 CKE1 ODT0 ODT1
RESET
C3112 100nF
C0402 X5R 10V
C3134 100nF
C0402 X5R 10V
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7 R7
A11
N7 T3
A13
T7
A14
M7
A15
M2
BA0
N8
BA1
M3
BA2
J3
RAS
K3
CAS
L3
WE
J7
CK
K7
CK
K9 J9 K1 J1 L2
CS0
L1
CS1
M8
R9
VDD
R1
VDD
N9
VDD
N1
VDD
K8
VDD
K2
VDD
G7
VDD
D9
VDD
B2
VDD
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
T2
12
C3113
12
100nF
C0402 X5R 10V
C3135
12
100nF
C0402 X5R 10V
Rockchip Confidential
5
4
DDR3_A0 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A4 DDR3_A5 DDR3_A6 DDR3_A7 DDR3_A8 DDR3_A9 DDR3_A10 DDR3_A11 DDR3_A12 DDR3_A13 DDR3_A14 DDR3_A15
DDR3_BA0 DDR3_BA1 DDR3_BA2
DDR3_RASn DDR3_CASn DDR3_WEn
DDR3_CLKP DDR3_CLKN
DDR3_CKE
DDR3_ODT0
DDR3_CS0n
DDR3_RESETn DDR3_RESETn
C3100 1nF
C0402 X5R 50V
DNP
C3114
12
100nF
C0402 X5R 10V
C3136
12
100nF
C0402 X5R 10V
DDR3_DQ24 DDR3_DQ31 DDR3_DQ25 DDR3_DQ30 DDR3_DQ26 DDR3_DQ29 DDR3_DQ27 DDR3_DQ28
DDR3_DQS3P DDR3_DQS3N
DDR3_DM3
DDR3_DQ17 DDR3_DQ23 DDR3_DQ16 DDR3_DQ21 DDR3_DQ18 DDR3_DQ22 DDR3_DQ19 DDR3_DQ20
DDR3_DQS2P DDR3_DQS2N
DDR3_DM2
12
R3101 240R
1% R0402
C3115 100nF
C0402 X5R 10V
C3137 100nF
C0402 X5R 10V
C3116
12
100nF
C0402 X5R 10V
C3138
12
100nF
C0402 X5R 10V
12
12
4
U3101 DDR3_16bit
FBGA96_14R00X11R00X1R20
DDR3 x16bit
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
F3
DQSL
G3
DQSL
E7
DML
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
C7
DQSU
B7
DQSU
D3
DMU
H1
VREFDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VDDQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
VSSQ
L8
ZQ0
L9
ZQ1
VCC_DDR
C3117 100nF
C0402 X5R 10V
C3139 100nF
C0402 X5R 10V
12
VCC_DDR
12
12
12
C3118 10uF
C0603 X5R
6.3V
C3140 10uF
C0603 X5R
6.3V
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
AP/A10
A11
BC/A12
A13 A14 A15
BA0 BA1 BA2
RAS CAS
WE
CK CK
CKE0 CKE1 ODT0 ODT1
CS0 CS1
VREFCA
VDD VDD VDD VDD VDD VDD VDD VDD VDD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
RESET
For better EMI.Place close to CLKP/N signal terminal.
DDR3_CLKP
DDR3_CLKN
C3119
12
10uF
C0603 X5R
6.3V
C3141
12
10uF
C0603 X5R
6.3V
DDR3_A0
N3
DDR3_A1
P7
DDR3_A2
P3
DDR3_A3
N2
DDR3_A4
P8
DDR3_A5
P2
DDR3_A6
R8
DDR3_A7
R2
DDR3_A8
T8
DDR3_A9
R3
DDR3_A10
L7
DDR3_A11
R7
DDR3_A12
N7
DDR3_A13
T3
DDR3_A14
T7
DDR3_A15
M7
DDR3_BA0
M2
DDR3_BA1
N8
DDR3_BA2
M3
DDR3_RASn
J3
DDR3_CASn
K3
DDR3_WEn
L3
DDR3_CLKP
J7
DDR3_CLKN
K7
DDR3_CKE
K9 J9
DDR3_ODT0
K1 J1
DDR3_CS0n
L2 L1
M8
R9 R1 N9 N1 K8 K2 G7 D9 B2
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
T2
C3101
12
1nF
C0402 X5R 50V
DNP
C3120
12
100nF
C0402 X5R 10V
C3142
12
100nF
C0402 X5R 10V
3
R3105 49.9R
R3107 49.9R
C3121
12
100nF
C0402 X5R 10V
C3143
12
100nF
C0402 X5R 10V
3
1 2
1 2
C3122
12
100nF
C0402 X5R 10V
C3144
12
100nF
C0402 X5R 10V
R0402
R0402
12
12
DDR3_DQ6 DDR3_DQ0 DDR3_DQ7 DDR3_DQ1 DDR3_DQ5 DDR3_DQ3 DDR3_DQ4 DDR3_DQ2
DDR3_DQS0P DDR3_DQS0N
DDR3_DM0
DDR3_DQ12 DDR3_DQ10 DDR3_DQ14 DDR3_DQ11 DDR3_DQ15 DDR3_DQ9 DDR3_DQ13 DDR3_DQ8
DDR3_DQS1P DDR3_DQS1N
DDR3_DM1
VREF_DDR_DQ VREF_DDR_CA VREF_DDR_DQ VREF_DDR_CAVREF_DDR_CAVREF_DDR_CAVREF_DDR_DQ VREF_DDR_DQ
1%
1%
C3123 100nF
C0402 X5R 10V
C3145 100nF
C0402 X5R 10V
12
12
12
U3102 DDR3_16bit
FBGA96_14R00X11R00X1R20
DDR3 x16bit
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
F3
DQSL
G3
DQSL
E7
DML
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
C7
DQSU
B7
DQSU
D3
DMU
H1
VREFDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VDDQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
VSSQ
L8
ZQ0
L9
1 2
12
12
C3125 100nF
C0402 X5R 10V
C3147 100nF
C0402 X5R 10V
ZQ1
12
12
R3102 240R
1% R0402
C3104 100pF
C0402 C0G 50V
C3124 100nF
C0402 X5R 10V
C3146 100nF
C0402 X5R 10V
C3126 100nF
C0402 X5R 10V
C3148 100nF
C0402 X5R 10V
2
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
AP/A10
R7
A11
N7
BC/A12
T3
A13
T7
A14
M7
A15
M2
BA0
N8
BA1
M3
BA2
J3
RAS
K3
CAS
L3
WE
J7
CK
K7
CK
K9
CKE0
J9
CKE1
K1
ODT0
J1
ODT1
L2
CS0
L1
CS1
M8
VREFCA
R9
VDD
R1
VDD
N9
VDD
N1
VDD
K8
VDD
K2
VDD
G7
VDD
D9
VDD
B2
VDD
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
T2
RESET
VCC_DDR
VCC_DDR
VCC_DDR
DDRPHY_VREFOUT
Notes: Close to SOC
2
U3103 DDR3_16bit
FBGA96_14R00X11R00X1R20
DDR3_A0 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A4 DDR3_A5 DDR3_A6 DDR3_A7 DDR3_A8 DDR3_A9 DDR3_A10 DDR3_A11 DDR3_A12 DDR3_A13 DDR3_A14 DDR3_A15
DDR3_BA0 DDR3_BA1 DDR3_BA2
DDR3_RASn DDR3_CASn DDR3_WEn
DDR3_CLKP DDR3_CLKN
DDR3_CKE
DDR3_ODT1
DDR3_CS1n
DDR3_RESETn DDR3_RESETn
C3102
12
1nF
C0402 X5R 50V
DNP
R3104 1K
R3108 1K
C3149
12
1nF
X5R 50V
C0402
C3150
12
1nF
X5R 50V
C0402
1 2
1 2
R3109 0R
1 2
DDR3_DQ31 DDR3_DQ24 DDR3_DQ30 DDR3_DQ25 DDR3_DQ28 DDR3_DQ27 DDR3_DQ29 DDR3_DQ26
DDR3_DQS3P DDR3_DQS3N
DDR3_DM3
DDR3_DQ23 DDR3_DQ17 DDR3_DQ21 DDR3_DQ16 DDR3_DQ20 DDR3_DQ19 DDR3_DQ22 DDR3_DQ18
DDR3_DQS2P DDR3_DQS2N
DDR3_DM2
12
R0402
R0402
R0402
R3103 240R
1% R0402
1%
1%DNP
5%
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
F3
DQSL
G3
DQSL
E7
DML
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
C7
DQSU
B7
DQSU
D3
DMU
H1
VREFDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VDDQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
VSSQ
L8
ZQ0
L9
ZQ1
VREF_DDR_CA
12
12
R3106 1K
R0402 1%
VREF_DDR_DQ
12
12
R3110 1K
1% R0402
DNP
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
31.DRAM-DDR3_4X16Bit_96P
31.DRAM-DDR3_4X16Bit_96P
31.DRAM-DDR3_4X16Bit_96P
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Zhangdz
Designed by:
Zhangdz
Designed by:
Zhangdz
1
DDR3 x16bit
AP/A10
BC/A12
VREFCA
RESET
C3106
C3105
12
1nF
1nF
C0402
C0402
X5R
X5R
50V
50V
C3127
C3128
12
1nF
1nF
C0402
C0402
X5R
X5R
50V
50V
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Reviewed by:
Reviewed by:
Reviewed by:
1
CKE0 CKE1 ODT0 ODT1
A11
A13 A14 A15
BA0 BA1 BA2
RAS CAS
CS0 CS1
VDD VDD VDD VDD VDD VDD VDD VDD VDD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Default
Default
Default
DDR3_A0
N3
A0
DDR3_A1
P7
A1
DDR3_A2
P3
A2
DDR3_A3
N2
A3
DDR3_A4
P8
A4
DDR3_A5
P2
A5
DDR3_A6
R8
A6
DDR3_A7
R2
A7
DDR3_A8
T8
A8
DDR3_A9
R3
A9
DDR3_A10
L7
DDR3_A11
R7
DDR3_A12
N7
DDR3_A13
T3
DDR3_A14
T7
DDR3_A15
M7
DDR3_BA0
M2
DDR3_BA1
N8
DDR3_BA2
M3
DDR3_RASn
J3
DDR3_CASn
K3
DDR3_WEn
L3
WE
DDR3_CLKP
J7
CK
DDR3_CLKN
K7
CK
DDR3_CKE
K9 J9
DDR3_ODT1
K1 J1
DDR3_CS1n
L2 L1
M8
R9 R1 N9 N1 K8 K2 G7 D9 B2
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
T2
C3103
12
1nF
C0402 X5R 50V
DNP
C3108
C3107
12
12
12
1nF
C0402 X5R 50V
C3129 1nF
C0402 X5R 50V
1nF
C0402 X5R 50V
C3130
12
1nF
C0402 X5R 50V
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Sheet: of
V1.1
V1.1
V1.1
26 72
26 72
26 72
Page 27
5
DDR3_DQ0 DDR3_DQ1 DDR3_DQ2 DDR3_DQ3 DDR3_DQ4 DDR3_DQ5 DDR3_DQ6 DDR3_DQ7
DDR3_DM0
DDR3_DQS0P DDR3_DQS0N
DDR3_DQ8 DDR3_DQ9
D D
C C
B B
A A
DDR3_DQ10 DDR3_DQ11 DDR3_DQ12 DDR3_DQ13 DDR3_DQ14 DDR3_DQ15
DDR3_DM1
DDR3_DQS1P DDR3_DQS1N
DDR3_DQ16 DDR3_DQ17 DDR3_DQ18 DDR3_DQ19 DDR3_DQ20 DDR3_DQ21 DDR3_DQ22 DDR3_DQ23
DDR3_DM2
DDR3_DQS2P DDR3_DQS2N
DDR3_DQ24 DDR3_DQ25 DDR3_DQ26 DDR3_DQ27 DDR3_DQ28 DDR3_DQ29 DDR3_DQ30 DDR3_DQ31
DDR3_DM3
DDR3_DQS3P DDR3_DQS3N
DDR3_ECC_DQ0 DDR3_ECC_DQ1 DDR3_ECC_DQ2 DDR3_ECC_DQ3 DDR3_ECC_DQ4 DDR3_ECC_DQ5 DDR3_ECC_DQ6 DDR3_ECC_DQ7
DDR3_ECC_DM
DDR3_ECC_DQSP DDR3_ECC_DQSN
DDR3_A9 DDR3_A2 DDR3_A4 DDR3_A3
DDR3_BA1 DDR3_A11 DDR3_A13 DDR3_A8
DDR3_A6 DDR3_A5 DDR3_A10 DDR3_A7
DDR3_BA2 DDR3_A14 DDR3_A15 DDR3_A0
DDR3_RASn DDR3_CASn DDR3_A1 DDR3_A12
DDR3_WEn DDR3_BA0 DDR3_CKE
DDR3_CLKP DDR3_CLKN
DDR3_ODT1 DDR3_CS1n DDR3_ODT0 DDR3_CS0n
DDR3_RESETn
DDRPHY_VREFOUT
Rockchip Confidential
DDR3_DQ0 DDR3_DQ7 DDR3_DQ1 DDR3_DQ6 DDR3_DQ2 DDR3_DQ5 DDR3_DQ3 DDR3_DQ4
DDR3_DQS0P DDR3_DQS0N
DDR3_DM0
DDR3_DQ11 DDR3_DQ12 DDR3_DQ10 DDR3_DQ14 DDR3_DQ8 DDR3_DQ13 DDR3_DQ9 DDR3_DQ15
DDR3_DQS1P DDR3_DQS1N
DDR3_DM1
VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDRVCC_DDR
DDR3_ECC_DQ4 DDR3_ECC_DQ1 DDR3_ECC_DQ3 DDR3_ECC_DQ6 DDR3_ECC_DQ0 DDR3_ECC_DQ7 DDR3_ECC_DQ5 DDR3_ECC_DQ2
DDR3_ECC_DQSP DDR3_ECC_DQSN
DDR3_ECC_DM
R3210
1 2
VCC_DDR VCC_DDR
0R R04025%
R3212
1 2
0R R04025%
R3214
1 2
VCC_DDR
0R R04025%
VREF_DDR_DQ VREF_DDR_CA VREF_DDR_DQ VREF_DDR_CA
5
12
R3202 240R
1% R0402
12
R3220 240R
1% R0402
U3200 DDR3_16bit
FBGA96_14R00X11R00X1R20
DDR3 x16bit
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
F3
DQSL
G3
DQSL
E7
DML
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
C7
DQSU
B7
DQSU
D3
DMU
H1
VREFDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VDDQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
VSSQ
L8
ZQ0
L9
ZQ1
U3204 DDR3_16bit
FBGA96_14R00X11R00X1R20
DDR3 x16bit
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
F3
DQSL
G3
DQSL
E7
DML
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
C7
DQSU
B7
DQSU
D3
DMU
H1
VREFDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VDDQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
VSSQ
L8
ZQ0
L9
ZQ1
DDR3_A0
N3
A0
DDR3_A1
P7
A1
DDR3_A2
P3
A2
DDR3_A3
N2
A3
DDR3_A4
P8
A4
DDR3_A5
P2
A5
DDR3_A6
R8
A6
DDR3_A7
R2
A7
DDR3_A8
T8
A8
DDR3_A9
R3
A9
DDR3_A10
L7
AP/A10
DDR3_A11
R7
A11
DDR3_A12
N7
BC/A12
DDR3_A13
T3
A13
DDR3_A14
T7
A14
DDR3_A15
M7
A15
DDR3_BA0
M2
BA0
DDR3_BA1
N8
BA1
DDR3_BA2
M3
BA2
DDR3_RASn
J3
RAS
DDR3_CASn
K3
CAS
DDR3_WEn
L3
WE
DDR3_CLKP
J7
CK
DDR3_CLKN
K7
CK
DDR3_CKE
K9
CKE0
J9
CKE1
DDR3_ODT0
K1
ODT0
J1
ODT1
DDR3_CS0n
L2
CS0
L1
CS1
M8
VREFCA
R9
VDD
R1
VDD
N9
VDD
N1
VDD
K8
VDD
K2
VDD
G7
VDD
D9
VDD
B2
VDD
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
DDR3_RESETn DDR3_RESETn DDR3_RESETn DDR3_RESETn
T2
RESET
C3216
12
1nF
C0402 X5R 50V
DNP
DDR3_A0
N3
A0
DDR3_A1
P7
A1
DDR3_A2
P3
A2
DDR3_A3
N2
A3
DDR3_A4
P8
A4
DDR3_A5
P2
A5
DDR3_A6
R8
A6
DDR3_A7
R2
A7
DDR3_A8
T8
A8
DDR3_A9
R3
A9
DDR3_A10
L7
AP/A10
DDR3_A11
R7
A11
DDR3_A12
N7
BC/A12
DDR3_A13
T3
A13
DDR3_A14
T7
A14
DDR3_A15
M7
A15
DDR3_BA0
M2
BA0
DDR3_BA1
N8
BA1
DDR3_BA2
M3
BA2
DDR3_RASn
J3
RAS
DDR3_CASn
K3
CAS
DDR3_WEn
L3
WE
DDR3_CLKP
J7
CK
DDR3_CLKN
K7
CK
DDR3_CKE
K9
CKE0
J9
CKE1
DDR3_ODT0
K1
ODT0
J1
ODT1
DDR3_CS0n
L2
CS0
L1
CS1
M8
VREFCA
R9
VDD
R1
VDD
N9
VDD
N1
VDD
K8
VDD
K2
VDD
G7
VDD
D9
VDD
B2
VDD
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
DDR3_RESETn DDR3_RESETn
T2
RESET
C3281
12
1nF
C0402 X5R 50V
DNP
CS0 ECC
VCC_DDR VCC_DDR VCC_DDRVCC_DDR
VCC_DDR
DDR3_DQ24 DDR3_DQ31 DDR3_DQ25 DDR3_DQ30 DDR3_DQ26 DDR3_DQ29 DDR3_DQ27 DDR3_DQ28
DDR3_DQS3P DDR3_DQS3N
DDR3_DM3
DDR3_DQ17 DDR3_DQ23 DDR3_DQ16 DDR3_DQ21 DDR3_DQ18 DDR3_DQ22 DDR3_DQ19 DDR3_DQ20
DDR3_DQS2P DDR3_DQS2N
DDR3_DM2
CS1 ECC
DDR3_ECC_DQ1 DDR3_ECC_DQ4 DDR3_ECC_DQ6 DDR3_ECC_DQ3 DDR3_ECC_DQ2 DDR3_ECC_DQ5 DDR3_ECC_DQ7 DDR3_ECC_DQ0
DDR3_ECC_DQSP DDR3_ECC_DQSN
DDR3_ECC_DM
12
R3203 240R
1% R0402
R3211
1 2
0R R04025%
R3213
1 2
0R R04025%
R3215
1 2
0R R04025%
12
R3221 240R
1% R0402
4
U3201 DDR3_16bit
FBGA96_14R00X11R00X1R20
DDR3 x16bit
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
F3
DQSL
G3
DQSL
E7
DML
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
C7
DQSU
B7
DQSU
D3
DMU
H1
VREFDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VDDQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
VSSQ
L8
ZQ0
L9
ZQ1
U3205 DDR3_16bit
FBGA96_14R00X11R00X1R20
DDR3 x16bit
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
F3
DQSL
G3
DQSL
E7
DML
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
C7
DQSU
B7
DQSU
D3
DMU
H1
VREFDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VDDQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
VSSQ
L8
ZQ0
L9
ZQ1
4
AP/A10
BC/A12
VREFCA
RESET
AP/A10
BC/A12
VREFCA
RESET
CS0 CS1
DDR3_A0
N3
A0
DDR3_A1
P7
A1
DDR3_A2
P3
A2
DDR3_A3
N2
A3
DDR3_A4
P8
A4
DDR3_A5
P2
A5
DDR3_A6
R8
A6
DDR3_A7
R2
A7
DDR3_A8
T8
A8
DDR3_A9
R3
A9
DDR3_A10
L7
DDR3_A11
R7
A11
DDR3_A12
N7
DDR3_A13
T3
A13
DDR3_A14
T7
A14
DDR3_A15
M7
A15
DDR3_BA0
M2
BA0
DDR3_BA1
N8
BA1
DDR3_BA2
M3
BA2
DDR3_RASn
J3
RAS
DDR3_CASn
K3
CAS
DDR3_WEn
L3
WE
DDR3_CLKP
J7
CK
DDR3_CLKN
K7
CK
DDR3_CKE
K9
CKE0
J9
CKE1
DDR3_ODT0
K1
ODT0
J1
ODT1
DDR3_CS0n
L2
CS0
L1
CS1
M8
R9
VDD
R1
VDD
N9
VDD
N1
VDD
K8
VDD
K2
VDD
G7
VDD
D9
VDD
B2
VDD
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
T2
C3217
12
1nF
C0402 X5R 50V
DNP
DDR3_A0
N3
A0
DDR3_A1
P7
A1
DDR3_A2
P3
A2
DDR3_A3
N2
A3
DDR3_A4
P8
A4
DDR3_A5
P2
A5
DDR3_A6
R8
A6
DDR3_A7
R2
A7
DDR3_A8
T8
A8
DDR3_A9
R3
A9
DDR3_A10
L7
DDR3_A11
R7
A11
DDR3_A12
N7
DDR3_A13
T3
A13
DDR3_A14
T7
A14
DDR3_A15
M7
A15
DDR3_BA0
M2
BA0
DDR3_BA1
N8
BA1
DDR3_BA2
M3
BA2
DDR3_RASn
J3
RAS
DDR3_CASn
K3
CAS
DDR3_WEn
L3
WE
DDR3_CLKP
J7
CK
DDR3_CLKN
K7
CK
DDR3_CKE
K9
CKE0
J9
CKE1
DDR3_ODT1
K1
ODT0
J1
ODT1
DDR3_CS1n
L2
CS0
L1
CS1
M8
R9
VDD
R1
VDD
N9
VDD
N1
VDD
K8
VDD
K2
VDD
G7
VDD
D9
VDD
B2
VDD
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
T2
C3282
12
1nF
C0402 X5R 50V
DNP
DDR3_DQ7 DDR3_DQ0 DDR3_DQ6 DDR3_DQ1 DDR3_DQ4 DDR3_DQ3 DDR3_DQ5 DDR3_DQ2
DDR3_DQS0P DDR3_DQS0N
DDR3_DM0
DDR3_DQ12 DDR3_DQ11 DDR3_DQ14 DDR3_DQ10 DDR3_DQ15 DDR3_DQ9
DDR3_DQ13
DDR3_DQ8
DDR3_DQS1P DDR3_DQS1N
DDR3_DM1
VREF_DDR_DQ VREF_DDR_CA VREF_DDR_DQ VREF_DDR_CAVREF_DDR_CAVREF_DDR_CAVREF_DDR_DQ VREF_DDR_DQ
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
12
R3204 240R
1% R0402
C3220
12
10uF
C0603 X5R
6.3V
C3231
12
10uF
C0603 X5R
6.3V
C3247
12
10uF
C0603 X5R
6.3V
C3257
12
10uF
C0603 X5R
6.3V
C3272
12
10uF
C0603 X5R
6.3V
C3283
12
10uF
C0603 X5R
6.3V
U3202 DDR3_16bit
FBGA96_14R00X11R00X1R20
DDR3 x16bit
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
F3
DQSL
G3
DQSL
E7
DML
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
C7
DQSU
B7
DQSU
D3
DMU
H1
VREFDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VDDQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
VSSQ
L8
ZQ0
L9
ZQ1
C3221
C3222
12
12
10uF
100nF
C0603
C0402
X5R
X5R
6.3V
10V
C3233
C3232
12
12
100nF
10uF
C0402
C0603
X5R
X5R
10V
6.3V
C3249
C3248
12
12
100nF
10uF
C0402
C0603
X5R
X5R
10V
6.3V
C3258
C3259
12
12
10uF
100nF
C0603
C0402
X5R
X5R
6.3V
10V
C3273
C3274
12
12
10uF
100nF
C0603
C0402
X5R
X5R
6.3V
10V
C3285
C3284
12
12
100nF
10uF
C0402
C0603
X5R
X5R
10V
6.3V
3
U3203 DDR3_16bit
FBGA96_14R00X11R00X1R20
R3205 240R
1% R0402
C3228
12
100nF
C0402 X5R 10V
C3239
12
100nF
C0402 X5R 10V
C3255
12
100nF
C0402 X5R 10V
C3265
12
100nF
C0402 X5R 10V
C3280
12
100nF
C0402 X5R 10V
C3291
12
100nF
C0402 X5R 10V
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
F3
DQSL
G3
DQSL
E7
DML
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
C7
DQSU
B7
DQSU
D3
DMU
H1
VREFDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VDDQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
VSSQ
L8
ZQ0
L9
ZQ1
DDR3 x16bit
Notes: Close to SOC
DDR3_A0
N3
A0
DDR3_A1
P7
A1
DDR3_A2
P3
A2
DDR3_A3
N2
A3
DDR3_A4
P8
A4
DDR3_A5
P2
A5
DDR3_A6
R8
A6
DDR3_A7
R2
A7
DDR3_A8
T8
A8
DDR3_A9
R3
A9
DDR3_A10
L7
AP/A10
DDR3_A11
R7
A11
DDR3_A12
N7
BC/A12
DDR3_A13
T3
A13
DDR3_A14
T7
A14
DDR3_A15
M7
A15
DDR3_BA0
M2
BA0
DDR3_BA1
N8
BA1
DDR3_BA2
M3
BA2
DDR3_RASn
J3
RAS
DDR3_CASn
K3
CAS
DDR3_WEn
L3
WE
DDR3_CLKP
J7
CK
DDR3_CLKN
K7
CK
DDR3_CKE
K9
CKE0
J9
CKE1
DDR3_ODT1
K1
ODT0
J1
ODT1
DDR3_CS1n
L2
CS0
L1
CS1
M8
VREFCA
R9
VDD
R1
VDD
N9
VDD
N1
VDD
K8
VDD
K2
VDD
G7
VDD
D9
VDD
B2
VDD
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
T2
RESET
C3218
12
1nF
C0402 X5R 50V
DNP
C3224
C3223
12
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
C3234
C3235
12
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
C3250
C3251
12
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
C3261
C3260
12
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
C3276
C3275
12
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
C3287
C3286
12
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
3
DDR3_DQ31 DDR3_DQ24 DDR3_DQ30 DDR3_DQ25 DDR3_DQ28 DDR3_DQ27 DDR3_DQ29 DDR3_DQ26
DDR3_DQS3P DDR3_DQS3N
DDR3_DM3
DDR3_DQ23 DDR3_DQ17 DDR3_DQ21 DDR3_DQ16 DDR3_DQ20 DDR3_DQ19 DDR3_DQ22 DDR3_DQ18
DDR3_DQS2P DDR3_DQS2N
DDR3_DM2
12
C3225
C3226
12
100nF
C0402 X5R 10V
C3236
12
100nF
C0402 X5R 10V
C3252
12
100nF
C0402 X5R 10V
C3262
12
100nF
C0402 X5R 10V
C3277
12
100nF
C0402 X5R 10V
C3288
12
100nF
C0402 X5R 10V
C3227
12
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
C3238
C3237
12
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
C3254
C3253
12
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
C3264
C3263
12
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
C3279
C3278
12
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
C3289
C3290
12
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
2
DDR3_A0
N3
A0
DDR3_A1
P7
A1
DDR3_A2
P3
A2
DDR3_A3
N2
A3
DDR3_A4
P8
A4
DDR3_A5
P2
A5
DDR3_A6
R8
A6
DDR3_A7
R2
A7
DDR3_A8
T8
A8
DDR3_A9
R3
A9
DDR3_A10
L7
AP/A10
DDR3_A11
R7
A11
DDR3_A12
N7
BC/A12
DDR3_A13
T3
A13
DDR3_A14
T7
A14
DDR3_A15
M7
A15
DDR3_BA0
M2
BA0
DDR3_BA1
N8
BA1
DDR3_BA2
M3
BA2
DDR3_RASn
J3
RAS
DDR3_CASn
K3
CAS
DDR3_WEn
L3
WE
DDR3_CLKP
J7
CK
DDR3_CLKN
K7
CK
DDR3_CKE
K9
CKE0
J9
CKE1
DDR3_ODT1
K1
ODT0
J1
ODT1
DDR3_CS1n
L2
CS0
L1
CS1
M8
VREFCA
R9
VDD
R1
VDD
N9
VDD
N1
VDD
K8
VDD
K2
VDD
G7
VDD
D9
VDD
B2
VDD
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
T2
RESET
C3219
12
1nF
C0402 X5R 50V
DNP
VCC_DDR
VCC_DDR
12
12
C3229 10uF
R3207
X5R
100K
6.3V
1%
C0603
R0402
12
C3243
R3209
12
100nF
100K
X5R
1%
10V
R0402
C0402
VCC_DDR VCC_DDR
C3256
12
1nF
X5R 50V
VCC_DDR
2
C0402
C3266
12
1nF
X5R 25V
C0201
12
R3219 1K
R0402 1%
12
R3222 1K
R0402 1%
R3217 0R
VREF_DDR_CA
C3292
12
1nF
C0402 X5R 50V
DDRPHY_VREFOUT
12
12
C3293 1nF
C0402 X5R 50V
C3230 100nF
X5R 10V
C0402
DDR3_ODT0 DDR3_ODT1 DDR3_CASn DDR3_RASn
DDR3_CS0n DDR3_CS1n DDR3_WEn DDR3_CKE
DDR3_BA0 DDR3_A15 DDR3_BA2 DDR3_A10
DDR3_A3 DDR3_BA1 DDR3_A0 DDR3_A12
DDR3_A5 DDR3_A11 DDR3_A2 DDR3_A1
DDR3_A13 DDR3_A4 DDR3_A9 DDR3_A14
DDR3_A6 DDR3_A7 DDR3_A8
DDR3_CLKP DDR3_CLKN
DDR3_CLKP DDR3_CLKN
Notes: Close to SOC
R0402
C3294
12
1nF
C0402 X5R 50V
RP3200 39R RP4_0408
4 5 3
6
2
7
1
8
RP3201 39R RP4_0408
1
8
2
7
3
6
4 5
RP3202 39R RP4_0408
4 5 3
6
2
7
1
8
RP3203 39R RP4_0408
1
8
2
7
3
6
4 5
RP3204 39R RP4_0408
4 5 3
6
2
7
1
8
RP3205 39R RP4_0408
1
8
2
7
3
6
4 5
RP3206 39R RP4_0408
4 5 3
6
2
7
1
8
R3200 51R R04025%1 2 R3201 51R R04025%1 2
C1110
12
2pF
C0201 C0G 50V
DNP
U3206 RT9199PSP/RT9045
NCT3101S/UR6517/UR6515C/RT9173CPSP/RT9173DPSP
1
2
3
4
DDR_VTT
VREF_DDR_DQ
5%12
12
C3295
12
1nF
C0402 X5R 50V
VIN
GND
REFEN
VOUT
12
C3267 1nF
C0402 X5R 50V
C3244 22uF
X5R
6.3V C0603
12
NC8
NC7
VCNTL
NC5
EPAD
SOP8_5R00X4R00X1R75_T
9
12
12
C3245 100nF
X5R 10V
C0402
C3268
12
12
1nF
C0402 X5R 50V
C3296
C3298
12
1nF
1nF
C0402
C0402
X5R
X5R
50V
50V
C3269 1nF
C0402 X5R 50V
C3246 10nF
X5R 25V
C0402
8
7
6
5
12
NCT3101S_2A
上下电阻为
UR6515C_2A UR6517_1.8A
上下电阻为
C3270 1nF
C0402 X5R 50V
1
DDR_VTT
C3200
C3201
12
12
10uF
1uF
X5R
X5R
6.3V
6.3V
C0603
C0402
C3205
C3204
12
12
1uF
4.7uF
X5R
X5R
6.3V
6.3V
C0402
C0603
C3209
C3208
12
12
1uF
10uF
X5R
X5R
6.3V
6.3V
C0402
C0603
C3212
C3213
12
12
4.7uF
1uF
X5R
X5R
6.3V
6.3V
C0603
C0402
VCC5V0_SYS
12
C3240 10uF
X5R 10V C0805
C3271
12
1nF
C0402 X5R 50V
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
12
12
C3242
C3241
10uF
100nF
X5R
X5R
10V
10V
C0805
C0402
1K-5K (2K 1%)
100K 1%
12
R3216 1K
1% R0402
DNP
12
R3218
C3297
12
1K
1nF
1%
C0402
R0402
X5R
DNP
50V
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
32.DRAM-DDR3_4X16+ECC_2X16_96P
32.DRAM-DDR3_4X16+ECC_2X16_96P
32.DRAM-DDR3_4X16+ECC_2X16_96P
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
1
C3202
C3203
12
12
100nF
10nF
X5R
X5R
10V
25V
C0402
C0402
C3206
C3207
12
12
100nF
10nF
X5R
X5R
10V
25V
C0402
C0402
C3210
C3211
12
12
100nF
10nF
X5R
X5R
10V
25V
C0402
C0402
C3215
C3214
12
12
10nF
100nF
X5R
X5R
25V
10V
C0402
C0402
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
27 72
Sheet: of
27 72
Sheet: of
Default
Default
Default
27 72
Page 28
5
DDR4_DQL0_A DDR4_DQL2_A DDR4_DQL4_A DDR4_DQL6_A DDR4_DQL7_A DDR4_DQL5_A DDR4_DQL3_A DDR4_DQL1_A DDR4_DML_A DDR4_DQSL_P_A DDR4_DQSL_N_A
D D
C C
B B
A A
DDR4_DQU3_A DDR4_DQU1_A DDR4_DQU7_A DDR4_DQU5_A DDR4_DQU2_A DDR4_DQU4_A DDR4_DQU6_A DDR4_DQU0_A DDR4_DMU_A DDR4_DQSU_P_A DDR4_DQSU_N_A
DDR4_DQU7_B DDR4_DQU5_B DDR4_DQU3_B DDR4_DQU1_B DDR4_DQU0_B DDR4_DQU6_B DDR4_DQU4_B DDR4_DQU2_B DDR4_DMU_B DDR4_DQSU_P_B DDR4_DQSU_N_B
DDR4_DQL0_B DDR4_DQL2_B DDR4_DQL4_B DDR4_DQL6_B DDR4_DQL7_B DDR4_DQL5_B DDR4_DQL1_B DDR4_DQL3_B DDR4_DML_B DDR4_DQSL_P_B DDR4_DQSL_N_B
DDR4_A0 DDR4_A1 DDR4_A2 DDR4_A3 DDR4_A4 DDR4_A5 DDR4_A6 DDR4_A7 DDR4_A8 DDR4_A9 DDR4_A10 DDR4_A11 DDR4_A12 DDR4_A13 DDR4_A14_WEn DDR4_A15_CASn DDR4_A16_RASn
DDR4_ACTn DDR4_BA0 DDR4_BA1 DDR4_BG0 DDR4_BG1
DDR4_CKE
DDR4_CLKP DDR4_CLKN
DDR4_CS0n DDR4_ODT0
DDR4_RESETn
DDRPHY_VREFOUT
VCC_DDR VCC3V3_SYS
C3308
12
VCC_DDR
12
C3307 10uF
X5R
6.3V C0603
C3331 1uF
X5R
6.3V
C0402
12
12
10uF
X5R
6.3V C0603
C3332 100nF
X5R 10V
C0402
C3309
12
10uF
X5R
6.3V C0603
C3333
12
100nF
X5R 10V
C0402
DDR4_DQU0_A DDR4_DQU1_A DDR4_DQU2_A DDR4_DQU3_A DDR4_DQU5_B DDR4_DQU4_A DDR4_DQU5_A DDR4_DQU6_A DDR4_DQU7_A
DDR4_DMU_A
DDR4_DQSU_P_A DDR4_DQSU_N_A
DDR4_DQL0_A DDR4_DQL1_A DDR4_DQL2_A DDR4_DQL3_A DDR4_DQL4_A DDR4_DQL5_A DDR4_DQL6_A DDR4_DQL7_A
DDR4_DML_A
DDR4_DQSL_P_A DDR4_DQSL_N_A
12
R3313 240R
1% R0402
VCC_DDR
VCC25_DDR
C3311
C3310
12
12
12
5
1uF
X5R
6.3V
C0402
C3334 100nF
X5R 10V
C0402
DNP
100nF
X5R 10V
C0402
C3335
12
100nF
X5R 10V
C0402
U3300
A3
DQU0
B8
DQU1
C3
DQU2
C7
DQU3
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
E2
DMU_n/DBIU_n
B7
DQSU_P
A7
DQSU_N
G2
DQL0
F7
DQL1
H3
DQL2
H7
DQL3
H2
DQL4
H8
DQL5
J3
DQL6
J7
DQL7
E7
DML_n/DBIL_n
G3
DQSL_P
F3
DQSL_N
F9
ZQ
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
B1
VPP1
R9
VPP2
DDR4_16bit_SDP
FBGA96_14R00X11R00X1R20
DDR4_BG1 DDR4_BG1/VSS
R3320 0R
Notes: Close to DRAM
Notes: When use DDP DDR4 SDRAM, DDR4 SDRAM' M9 pin connect to DDR_BG1 net of SOC; DDR4 SDRAM' T7 pin connect to GND; DDR4 SDRAM' E9 pin connect to GND by 240ohm resistor
C3313
C3312
12
12
12
100nF
X5R 10V
C0402
C3336 100nF
X5R 10V
C0402
100nF
X5R 10V
C0402
C3337
12
100nF
X5R 10V
C0402
A10/AP
A12/BC_n
WE_n/A14 CAS_n/A15 RAS_n/A16
ACT_n
RESET_n ALERT_n
VREFCA
C3314
12
100nF
X5R 10V
C0402
C3338
12
100nF
X5R 10V
C0402
A11
A13
BA0 BA1
BG0
CK_P CK_N
CKE
CS_n
ODT
PAR TEN
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS
12
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
NC
R0402
12
12
P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8 L2 M8 L8
N2 N8
M2
K7 K8
K2 L7 K3 L3
P1 P9 T3 N9
T7
M1
A2 A8 C9 D2 D8 E3 E8 F1 H1 H9 B2 E1 E9 G8 K1 K9 M9 N1 T1
C3315 100nF
X5R 10V
C0402
C3339 100nF
X5R 10V
C0402
5%DNP
4
DDR4_A0 DDR4_A1 DDR4_A2 DDR4_A3 DDR4_A4 DDR4_A5 DDR4_A6 DDR4_A7 DDR4_A8 DDR4_A9 DDR4_A10 DDR4_A11 DDR4_A12 DDR4_A13 DDR4_A14_WEn DDR4_A15_CASn DDR4_A16_RASn
DDR4_BA0 DDR4_BA1
DDR4_BG0
DDR4_CLKP_A DDR4_CLKN_A
DDR4_CKE_A DDR4_CS0n_A DDR4_ODT0_A DDR4_ACTn
DDR4_RESETn
R3315 0R
1 2
VREF_DDR4_CA
R3317 0R
1 2
12
R3319 0R
5% R0402
C3316
12
12
100nF
X5R 10V
C0402
C3340
12
12
100nF
X5R 10V
C0402
DNP
4
3
DDR4P216SD6
DDR4_CLKP
R3300 49.9R
DDR4_CLKN
5%
DDR4_CLKP_A
DDR4_CLKN_A DDR4_CLKN_B
DDR4_CKE_A DDR4_CKE_B
DDR4_CS0n_A DDR4_CS0n_B
DDR4_ODT0_A DDR4_ODT0_B
C3302
1 2
1nF
DNP
DDR4_BG1/VSS
C3317
C3318
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3342
C3341
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
X5R 50V
C0402
R04025%DNP
R04025%
12
C3319 100nF
X5R 10V
C0402
12
C3343 100nF
X5R 10V
C0402
R3302 0R
1 2
R3304 0R
1 2
R3306 0R
1 2
R3308 0R
1 2
R3310 0R
1 2
C3321
C3320
12
12
100nF
X5R 10V
C0402
12
C3344 100nF
X5R 10V
C0402
100nF
X5R 10V
C0402
12
C3345 100nF
X5R 10V
C0402
DDR4_CLKP
R0201
5%
DDR4_CLKN
R0201
5%
DDR4_CKE
R0201
5%
DDR4_CS0n
R0201
5%
DDR4_ODT0
R0201
Notes: Close to SOC
DDRPHY_VREFOUT
VCC3V3_PMU
3
1 2
R3301 49.9R
1 2
R3303 0R
1 2
R3305 0R
1 2
R3307 0R
1 2
R3309 0R
1 2
R3311 0R
1 2
VCC_DDR
C3303
12
1nF
X5R 50V
C0402
R3322 0R
C3304
12
1nF
X5R 50V
C0402
C3322
12
1uF
X5R 10V C0402
R0201
R0201
R0201
R0201
R0201
R0201
R0201
1 2
R3325
5%
51K
R0402
1%
1%
5%
5%
5%
5%
5%
12
C3300
1 2
100pF
X5R 25V DNP
C0201
DDR4_CLKP_B
VREF_DDR4_CA
5%
R0402
12
C3329 100nF
X5R 10V
C0402
DNP
C3305
12
1nF
X5R 50V
C0402
U3302 PT5108E23E-25
1
IN
2
GND
3
EN
SOT_23_5
2
DDR4_DQU0_B DDR4_DQU1_B DDR4_DQU2_B DDR4_DQU3_B DDR4_DQU4_B
DDR4_DQU6_B DDR4_DQU7_B
DDR4_DMU_B
DDR4_DQSU_P_B DDR4_DQSU_N_B
DDR4_DQL0_B DDR4_DQL1_B DDR4_DQL2_B DDR4_DQL3_B DDR4_DQL4_B DDR4_DQL5_B DDR4_DQL6_B DDR4_DQL7_B
DDR4_DML_B
DDR4_DQSL_P_B DDR4_DQSL_N_B
12
VCC_DDR
VCC25_DDR
C3306
12
1nF
X5R 50V
C0402
OUT
BP
R3312 240R
1% R0402
5
4
A3 B8 C3 C7 C2 C8 D3 D7
E2
B7 A7
G2 F7 H3 H7 H2 H8 J3 J7
E7
G3 F3
F9
A1 A9 C1 D9 F2 F8 G1 G9 J2 J8
B3 B9 D1 G7 J1 J9 L1 L9 R1 T9
B1 R9
VCC_DDR
12
12
12
12
C3330 DNP
C0402
U3301
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
DMU_n/DBIU_n
DQSU_P DQSU_N
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DML_n/DBIL_n
DQSL_P DQSL_N
ZQ
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VPP1 VPP2
DDR4_16bit_SDP
FBGA96_14R00X11R00X1R20
R3321 1K
1% R0402
DNP
R3323 1K
1% R0402
DNP
C3323
4.7uF
X5R
6.3V
C0402
Rockchip Confidential
2
VCC25_DDR
12
C3324
4.7uF
X5R
6.3V
C0402
A10/AP
A12/BC_n
WE_n/A14 CAS_n/A15 RAS_n/A16
CK_P CK_N
CS_n
ACT_n
RESET_n ALERT_n
VREFCA
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
12
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3 T2
A11
M7 T8
A13
L2 M8 L8
N2
BA0
N8
BA1
M2
BG0
K7 K8
K2
CKE
L7 K3
ODT
L3
P1 P9 T3
PAR
N9
TEN
T7
NC
M1
A2 A8 C9 D2 D8 E3 E8 F1 H1 H9 B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
12
C3325
C3326
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
33.DRAM-DDR4_2x16bit_96P
33.DRAM-DDR4_2x16bit_96P
33.DRAM-DDR4_2x16bit_96P
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Zhangdz
Designed by:
Zhangdz
Designed by:
Zhangdz
DDR4_A0 DDR4_A1 DDR4_A2 DDR4_A3 DDR4_A4 DDR4_A5 DDR4_A6 DDR4_A7 DDR4_A8 DDR4_A9 DDR4_A10 DDR4_A11 DDR4_A12 DDR4_A13 DDR4_A14_WEn DDR4_A15_CASn DDR4_A16_RASn
DDR4_BA0 DDR4_BA1
DDR4_BG0
DDR4_CLKP_B DDR4_CLKN_B
DDR4_CKE_B DDR4_CS0n_B DDR4_ODT0_B DDR4_ACTn
DDR4_RESETn
R3314 0R
1 2
VREF_DDR4_CA
R3316 0R
1 2
12
R3318 0R
5% R0402
12
C3327 100nF
X5R 10V
C0402
Reviewed by:
Reviewed by:
Reviewed by:
1
1 2
C3328 100nF
X5R 10V
C0402
Default
Default
Default
DNP
X5R 50V
C0402
R04025%DNP
R04025%
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Sheet: of
V1.1
V1.1
V1.1
28 72
28 72
28 72
C3301 1nF
DDR4_BG1/VSS
12
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
1
Page 29
DDR4_DQL0_A DDR4_DQL2_A DDR4_DQL4_A DDR4_DQL6_A DDR4_DQL7_A DDR4_DQL5_A DDR4_DQL3_A DDR4_DQL1_A DDR4_DML_A DDR4_DQSL_P_A DDR4_DQSL_N_A
DDR4_DQU3_A DDR4_DQU1_A DDR4_DQU7_A DDR4_DQU5_A DDR4_DQU2_A DDR4_DQU4_A
D D
C C
B B
DDR4_DQU6_A DDR4_DQU0_A DDR4_DMU_A DDR4_DQSU_P_A DDR4_DQSU_N_A
DDR4_DQU7_B DDR4_DQU5_B DDR4_DQU3_B DDR4_DQU1_B DDR4_DQU0_B DDR4_DQU6_B DDR4_DQU4_B DDR4_DQU2_B DDR4_DMU_B DDR4_DQSU_P_B DDR4_DQSU_N_B
DDR4_DQL0_B DDR4_DQL2_B DDR4_DQL4_B DDR4_DQL6_B DDR4_DQL7_B DDR4_DQL5_B DDR4_DQL1_B DDR4_DQL3_B DDR4_DML_B DDR4_DQSL_P_B DDR4_DQSL_N_B
DDR4_A0 DDR4_A1 DDR4_A2 DDR4_A3 DDR4_A4 DDR4_A5 DDR4_A6 DDR4_A7 DDR4_A8 DDR4_A9 DDR4_A10 DDR4_A11 DDR4_A12 DDR4_A13 DDR4_A14_WEn DDR4_A15_CASn DDR4_A16_RASn
DDR4_ACTn
DDR4_BA0 DDR4_BA1
DDR4_BG0 DDR4_BG1
DDR4_CKE
DDR4_CLKP DDR4_CLKN
DDR4_CS0n DDR4_CS1n DDR4_ODT0 DDR4_ODT1
DDR4_RESETn
DDRPHY_VREFOUT
DDRPHY_VREFOUT
Notes: Close to SOC
5
A3 B8 C3 C7 C2 C8 D3 D7
E2
B7 A7
G2 F7 H3 H7 H2 H8 J3 J7
E7
G3 F3
F9
R3400 240R
1% R0402
A1 A9 C1 D9 F2 F8 G1 G9 J2 J8
B3 B9 D1 G7 J1 J9 L1 L9 R1 T9
B1 R9
R3419 0R
R3415 0R
U3400
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
DMU_n/DBIU_n
DQSU_P DQSU_N
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DML_n/DBIL_n
DQSL_P DQSL_N
ZQ
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VPP1 VPP2
DDR4_16bit
FBGA96_14R00X11R00X1R20
12
DNP
R0402
5%12
R0402
DDR4_DQU0_A DDR4_DQU1_A DDR4_DQU2_A DDR4_DQU3_A DDR4_DQU4_A DDR4_DQU5_A DDR4_DQU6_A DDR4_DQU7_A
DDR4_DQSU_P_A DDR4_DQSU_N_A
DDR4_DQL0_A DDR4_DQL1_A DDR4_DQL2_A DDR4_DQL3_A DDR4_DQL4_A DDR4_DQL5_A DDR4_DQL6_A DDR4_DQL7_A
DDR4_DML_A
DDR4_DQSL_P_A DDR4_DQSL_N_A
12
VCC_DDR
VCC25_DDR
DDR4_BG1 DDR4_BG1//VSS
Notes: Close to DRAM
VCC_DDR
C3482
12
1nF
X5R 50V
C0402
C3483
12
1nF
X5R 50V
C0402
A10/AP
A12/BC_n
WE_n/A14 CAS_n/A15 RAS_n/A16
ACT_n
RESET_n ALERT_n
VREFCA
5%
VCC_DDR
12
12
DDR4_A0
P3
A0
DDR4_A1
P7
A1
DDR4_A2
R3
A2
DDR4_A3
N7
A3
DDR4_A4
N3
A4
DDR4_A5
P8
A5
DDR4_A6
P2
A6
DDR4_A7
R8
A7
DDR4_A8
R2
A8
DDR4_A9
R7
A9
DDR4_A10
M3
DDR4_A11
T2
A11
DDR4_A12
M7
DDR4_A13
T8
A13
DDR4_A14_WEn
L2
DDR4_A15_CASn
M8
DDR4_A16_RASn
L8
DDR4_BA0
N2
BA0
DDR4_BA1
N8
BA1
DDR4_BG0
M2
BG0
DDR4_0_CLKP
K7
CK_P
DDR4_0_CLKN
K8
CK_N
DDR4_CKE
K2
CKE
DDR4_CS0n
L7
CS_n
DDR4_ODT0
K3
ODT
DDR4_ACTn
L3
P1 P9 T3
PAR
N9
TEN
T7
NC
M1
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
12
R3418 0R
5% R0402
R3414 1K
1% R0402
DNP
R3416 1K
1% R0402
DNP
C3400
1 2
1nF C0402
DNP
R3404 0R R02015%DNP1 2
VREF_DDR4_CA
R3408 0R R04025%1 2
DDR4_BG1//VSS
Notes: When use 16Gbit/32Gbit DDR4 SDRAM, DDR4 SDRAM' M9 pin connect to DDR_BG1 net of SOC; DDR4 SDRAM' T7 pin connect to GND; DDR4 SDRAM' E9 pin connect to GND by 240ohm resistor
VREF_DDR4_CA
C3405
C3406
12
1nF
X5R 50V
C0402
C3407
12
12
1nF
1nF
X5R
X5R
50V
50V
C0402
C0402
X5R 50V
12
C3408 1nF
X5R 50V
C0402
4
DDR4_DQU0_B DDR4_DQU1_B DDR4_DQU2_B DDR4_DQU3_B DDR4_DQU4_B DDR4_DQU5_B DDR4_DQU6_B DDR4_DQU7_B
DDR4_DMU_BDDR4_DMU_A
DDR4_DQSU_P_B DDR4_DQSU_N_B
DDR4_DQL0_B DDR4_DQL1_B DDR4_DQL2_B DDR4_DQL3_B DDR4_DQL4_B DDR4_DQL5_B DDR4_DQL6_B DDR4_DQL7_B
DDR4_DML_B
DDR4_DQSL_P_B DDR4_DQSL_N_B
12
VCC_DDR
VCC25_DDR
R3401 240R
1% R0402
VCC3V3_PMU
A3 B8 C3 C7 C2 C8 D3 D7
E2
B7 A7
G2 F7 H3 H7 H2 H8 J3 J7
E7
G3 F3
F9
A1 A9 C1 D9 F2 F8 G1 G9 J2 J8
B3 B9 D1 G7 J1 J9 L1 L9 R1 T9
B1 R9
U3401
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
DMU_n/DBIU_n
A10/AP DQSU_P DQSU_N
A12/BC_n
DQL0
WE_n/A14
DQL1
CAS_n/A15
DQL2
RAS_n/A16 DQL3 DQL4 DQL5 DQL6 DQL7
DML_n/DBIL_n
DQSL_P DQSL_N
ZQ
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VPP1 VPP2
DDR4_16bit
FBGA96_14R00X11R00X1R20
VCC3V3_SYS
ACT_n
RESET_n ALERT_n
VREFCA
C3409
12
1uF
X5R 10V C0402
R3417 10K
3
R3402 240R
1% R0402
DDR4_CLKP
DDR4_CLKN
DDR4_CLKP
DDR4_CLKN
A3 B8 C3 C7 C2 C8 D3 D7
E2
B7 A7
G2 F7 H3 H7 H2 H8 J3 J7
E7
G3 F3
F9
A1 A9 C1 D9 F2 F8 G1 G9 J2 J8
B3 B9 D1 G7 J1 J9 L1 L9 R1 T9
B1 R9
R3421 22R
R3420 22R
R3423 22R
R3422 22R
12
12
C3414 100nF
X5R 10V
C0402
U3402
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
DMU_n/DBIU_n
A10/AP DQSU_P DQSU_N
A12/BC_n
DQL0
WE_n/A14
DQL1
CAS_n/A15
DQL2
RAS_n/A16 DQL3 DQL4 DQL5 DQL6 DQL7
DML_n/DBIL_n
DQSL_P DQSL_N
ZQ
RESET_n ALERT_n
VDDQ VDDQ
VREFCA
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VPP1 VPP2
DDR4_16bit
FBGA96_14R00X11R00X1R20
12
C3416
C3415
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
DDR4_A0
P3
A0
DDR4_A1
P7
A1
DDR4_A2
R3
A2
DDR4_A3
N7
A3
DDR4_A4
N3
A4
DDR4_A5
P8
A5
DDR4_A6
P2
A6
DDR4_A7
R8
A7
DDR4_A8
R2
A8
DDR4_A9
R7
A9
DDR4_A10
M3
DDR4_A11
T2
A11
DDR4_A12
M7
DDR4_A13
T8
A13
DDR4_A14_WEn
L2
DDR4_A15_CASn
M8
DDR4_A16_RASn
L8
DDR4_BA0
N2
BA0
DDR4_BA1
N8
BA1
DDR4_BG0
M2
BG0
DDR4_1_CLKP
K7
CK_P
DDR4_1_CLKN
K8
CK_N
DDR4_CKE
K2
CKE
DDR4_CS0n
L7
CS_n
DDR4_ODT0
K3
ODT
DDR4_ACTn
L3
DDR4_RESETnDDR4_RESETn
P1 P9 T3
PAR
N9
TEN
R3405 0R R02015%DNP1 2
T7
NC
M1
VREF_DDR4_CA
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
B2
VSS
E1
VSS
R3409 0R R04025%1 2
E9
VSS
G8
VSS
K1
VSS
K9
VSS VSS VSS VSS
R0402
DDR4_BG1//VSS
M9 N1 T1
1
2
5%1 2
12
C3421 DNP
C0402
DDR4P416DD6
C3401
1 2
1nF C0402
DNP
U3404 PT5108E23E-25
5
IN
OUT
GND
4
EN3BP
SOT_23_5
X5R 50V
DDR4_CLKP
DDR4_CLKN
12
C3420 DNP
C0402
R3412 49.9R
R3413 49.9R
VCC25_DDR
12
12
C3410
C3484
4.7uF
4.7uF
X5R
X5R
6.3V
6.3V
C0402
C0402
DDR4_DQU1_A DDR4_DQU0_A DDR4_DQU3_A DDR4_DQU2_A DDR4_DQU5_A DDR4_DQU4_A DDR4_DQU7_A DDR4_DQU6_A
DDR4_DMU_A
DDR4_DQSU_P_A DDR4_DQSU_N_A
DDR4_DQL1_A DDR4_DQL0_A DDR4_DQL3_A DDR4_DQL2_A DDR4_DQL5_A DDR4_DQL4_A DDR4_DQL7_A DDR4_DQL6_A
DDR4_DML_A
DDR4_DQSL_P_A DDR4_DQSL_N_A
12
VCC_DDR
VCC25_DDR VCC25_DDR
1%1 2
R0201
1%1 2
R0201
C3404
12
100pF
C0G 50V
C0201
DNP
12
C3411
4.7uF
X5R
6.3V
C0402
12
12
C3413
C3412
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
ACT_n
R0201
R0201
R0201
R0201
2
R3403 240R
1% R0402
U3403
A3
DQU0
B8
DQU1
C3
DQU2
C7
DQU3
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
E2
DMU_n/DBIU_n
B7
DQSU_P
A7
DQSU_N
G2
DQL0
F7
DQL1
H3
DQL2
H7
DQL3
H2
DQL4
H8
DQL5
J3
DQL6
J7
DQL7
E7
DML_n/DBIL_n
G3
DQSL_P
F3
DQSL_N
F9
ZQ
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
B1
VPP1
R9
VPP2
DDR4_16bit
FBGA96_14R00X11R00X1R20
CAS_n/A15 RAS_n/A16
DDR4_A0
P3
A0
DDR4_A1
P7
A1
DDR4_A2
R3
A2
DDR4_A3
N7
A3
DDR4_A4
N3
A4
DDR4_A5
P8
A5
DDR4_A6
P2
A6
DDR4_A7
R8
A7
DDR4_A8
R2
A8
DDR4_A9
R7
A9
DDR4_A10
M3
DDR4_A11
T2
A11
DDR4_A12
M7
DDR4_A13
T8
A13
DDR4_A14_WEn
L2
DDR4_A15_CASn
M8
DDR4_A16_RASn
L8
DDR4_BA0
N2
BA0
DDR4_BA1
N8
BA1
DDR4_BG0
M2
BG0
DDR4_0_CLKP
K7
CK_P
DDR4_0_CLKN
K8
CK_N
DDR4_CKE
K2
CKE
DDR4_CS1n
L7
CS_n
DDR4_ODT1
K3
ODT
DDR4_ACTn
L3
DDR4_RESETn
P1 P9 T3
PAR
N9
TEN
T7
NC
M1
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
DDR4_0_CLKP
1%1 2
DDR4_0_CLKN
1%1 2
DDR4_1_CLKP
1%1 2
DDR4_1_CLKN
1%1 2
12
12
C3417 100nF
X5R 10V
C0402
C3402
1 2
1nF C0402
DNP
R3406 0R R02015%DNP1 2
VREF_DDR4_CA
R3410 0R R04025%1 2
DDR4_BG1//VSS DDR4_BG1//VSS
12
C3418
C3419
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
X5R 50V
DDR4_DQU1_B DDR4_DQU0_B DDR4_DQU3_B DDR4_DQU2_B DDR4_DQU5_B DDR4_DQU4_B DDR4_DQU7_B DDR4_DQU6_B
DDR4_DMU_B
DDR4_DQSU_P_B DDR4_DQSU_N_B
DDR4_DQL1_B DDR4_DQL0_B DDR4_DQL3_B DDR4_DQL2_B DDR4_DQL5_B DDR4_DQL4_B DDR4_DQL7_B DDR4_DQL6_B
DDR4_DML_B
DDR4_DQSL_P_B DDR4_DQSL_N_B
12
VCC_DDR
A10/AP
A12/BC_n
WE_n/A14
ACT_n
RESET_n ALERT_n
VREFCA
1
DDR4_A0
P3
A0
DDR4_A1
P7
A1
DDR4_A2
R3
A2
DDR4_A3
N7
A3
DDR4_A4
N3
A4
DDR4_A5
P8
A5
DDR4_A6
P2
A6
DDR4_A7
R8
A7
DDR4_A8
R2
A8
DDR4_A9
R7
A9
DDR4_A10
M3
DDR4_A11
T2
A11
DDR4_A12
M7
DDR4_A13
T8
A13
DDR4_A14_WEn
L2
DDR4_A15_CASn
M8
DDR4_A16_RASn
L8
DDR4_BA0
N2
BA0
DDR4_BA1
N8
BA1
DDR4_BG0
M2
BG0
DDR4_1_CLKP
K7
CK_P
DDR4_1_CLKN
K8
CK_N
DDR4_CKE
K2
CKE
DDR4_CS1n
L7
CS_n
DDR4_ODT1
K3
ODT
DDR4_ACTn
L3
DDR4_RESETn
P1 P9 T3
PAR
N9
TEN
T7
NC
M1
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
C3403 1nF C0402
R3407 0R R02015%DNP1 2
VREF_DDR4_CA
R3411 0R R04025%1 2
1 2
DNP
X5R 50V
VCC_DDR
C3424
C3423
C3422
12
22uF
X5R
6.3V C0603
A A
VCC_DDR
C3452
12
22uF
X5R
6.3V C0603
12
12
10uF
10uF
X5R
X5R
10V
10V
C0603
C0603
C3453
C3454
12
12
10uF
10uF
X5R
X5R
10V
10V
C0603
C0603
C3426
C3425
12
100nF
X5R 10V
C0402
C3455
12
100nF
X5R 10V
C0402
C3427
C3428
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3457
C3456
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3429
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3459
C3458
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3431
C3430
12
100nF
X5R 10V
C0402
C3460
12
100nF
X5R 10V
C0402
C3432
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3461
C3462
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3434
C3433
12
100nF
X5R 10V
C0402
C3463
12
100nF
X5R 10V
C0402
C3435
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3465
C3464
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3437
C3436
12
100nF
X5R 10V
C0402
C3466
12
100nF
X5R 10V
C0402
C3438
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3467
C3468
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3440
C3439
12
1nF
X5R 50V C0402
C3469
12
1nF
X5R 50V C0402
C3441
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3471
C3470
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
Rockchip Confidential
5
4
C3443
C3444
C3442
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3472
C3473
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
3
C3445
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3474
C3475
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3447
C3446
12
100nF
X5R 10V
C0402
C3476
12
100nF
X5R 10V
C0402
C3448
12
100nF
X5R 10V
C0402
C3477
12
100nF
X5R 10V
C0402
C3449
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3478
C3479
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3451
C3450
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3481
C3480
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
2
Designed by:
Rockchip Electronics Co., Ltd
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
34.DRAM-DDR4_4x16Bit_96P
34.DRAM-DDR4_4x16Bit_96P
34.DRAM-DDR4_4x16Bit_96P
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Zhangdz
Zhangdz
Zhangdz
1
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
Sheet: of
Sheet: of
29 72
29 72
29 72
Page 30
DDR4_DQL0_A DDR4_DQL2_A DDR4_DQL4_A DDR4_DQL6_A DDR4_DQL7_A DDR4_DQL5_A DDR4_DQL3_A DDR4_DQL1_A DDR4_DML_A DDR4_DQSL_P_A DDR4_DQSL_N_A
DDR4_DQU3_A DDR4_DQU1_A DDR4_DQU7_A DDR4_DQU5_A DDR4_DQU2_A DDR4_DQU4_A
D D
C C
B B
DDR4_DQU6_A DDR4_DQU0_A DDR4_DMU_A DDR4_DQSU_P_A DDR4_DQSU_N_A
DDR4_DQU7_B DDR4_DQU5_B DDR4_DQU3_B DDR4_DQU1_B DDR4_DQU0_B DDR4_DQU6_B DDR4_DQU4_B DDR4_DQU2_B DDR4_DMU_B DDR4_DQSU_P_B DDR4_DQSU_N_B
DDR4_DQL0_B DDR4_DQL2_B DDR4_DQL4_B DDR4_DQL6_B DDR4_DQL7_B DDR4_DQL5_B DDR4_DQL1_B DDR4_DQL3_B DDR4_DML_B DDR4_DQSL_P_B DDR4_DQSL_N_B
DDR4_ECC_DQ0 DDR4_ECC_DQ1 DDR4_ECC_DQ2 DDR4_ECC_DQ3 DDR4_ECC_DQ4 DDR4_ECC_DQ5 DDR4_ECC_DQ6 DDR4_ECC_DQ7 DDR4_ECC_DM DDR4_ECC_DQS_P DDR4_ECC_DQS_N
DDR4_A0 DDR4_A1 DDR4_A2 DDR4_A3 DDR4_A4 DDR4_A5 DDR4_A6 DDR4_A7 DDR4_A8 DDR4_A9 DDR4_A10 DDR4_A11 DDR4_A12 DDR4_A13 DDR4_A14_WEn DDR4_A15_CASn DDR4_A16_RASn DDR4_ACTn DDR4_BA0 DDR4_BA1 DDR4_BG0 DDR4_BG1 DDR4_CKE
DDR4_CLKP DDR4_CLKN
DDR4_CS0n
DDR4_ODT0
DDR4_RESETn
DDRPHY_VREFOUT
5
DDR4_DQU0_A DDR4_DQU1_A DDR4_DQU2_A DDR4_DQU3_A DDR4_DQU4_A DDR4_DQU5_A DDR4_DQU6_A DDR4_DQU7_A
DDR4_DQSU_P_A DDR4_DQSU_N_A
DDR4_DQL0_A DDR4_DQL1_A DDR4_DQL2_A DDR4_DQL3_A DDR4_DQL4_A DDR4_DQL5_A DDR4_DQL6_A DDR4_DQL7_A
DDR4_DML_A
DDR4_DQSL_P_A DDR4_DQSL_N_A
12
VCC_DDR
VCC25_DDR VCC25_DDR
U3500
A3
DQU0
B8
DQU1
C3
DQU2
C7
DQU3
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
E2
DMU_n/DBIU_n
B7
DQSU_P
A7
DQSU_N
A12/BC_n
DQL0
WE_n/A14
DQL1
CAS_n/A15
DQL2
RAS_n/A16 DQL3 DQL4 DQL5 DQL6 DQL7
DML_n/DBIL_n
DQSL_P DQSL_N
ZQ
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VPP1 VPP2
DDR4_16bit
FBGA96_14R00X11R00X1R20
Notes: When use 16Gbit/32Gbit DDR4 SDRAM, DDR4 SDRAM' M9 pin connect to DDR_BG1 net of SOC; DDR4 SDRAM' T7 pin connect to GND; DDR4 SDRAM' E9 pin connect to GND by 240ohm resistor
R3530 0R
R3500 240R
1% R0402
G2 F7 H3 H7 H2 H8 J3 J7
E7
G3 F3
F9
A1 A9 C1 D9 F2 F8 G1 G9 J2 J8
B3 B9 D1 G7 J1 J9 L1 L9 R1 T9
B1 R9
DDR4_BG1
A10/AP
ACT_n
RESET_n ALERT_n
VREFCA
DNP
DDR4_A0
P3
A0
DDR4_A1
P7
A1
DDR4_A2
R3
A2
DDR4_A3
N7
A3
DDR4_A4
N3
A4
DDR4_A5
P8
A5
DDR4_A6
P2
A6
DDR4_A7
R8
A7
DDR4_A8
R2
A8
DDR4_A9
R7
A9
DDR4_A10
M3
DDR4_A11
T2
A11
DDR4_A12
M7
DDR4_A13
T8
A13
DDR4_A14_WEn
L2
DDR4_A15_CASn
M8
DDR4_A16_RASn
L8
DDR4_BA0
N2
BA0
DDR4_BA1
N8
BA1
DDR4_BG0
M2
BG0
DDR4_CLKP
K7
CK_P
DDR4_CLKN
K8
CK_N
DDR4_CKE
K2
CKE
DDR4_CS0n
L7
CS_n
DDR4_ODT0
K3
ODT
DDR4_ACTn
L3
P1 P9 T3
PAR
N9
TEN
T7
NC
M1
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
12
R0402
R3524 0R R04025%DNP1 2
VREF_DDR4_CA
R3525 0R R04025%1 2
5%
12
R3531 0R
5% R0402
C3500
1 2
1nF C0402
DNP
DDR4_BG1/VSS_M9
12
12
R3533
R3532
0R
0R
5%
5%
R0402
R0402
X5R 50V
4
DDR4_DQU0_B DDR4_DQU1_B DDR4_DQU2_B DDR4_DQU3_B DDR4_DQU4_B DDR4_DQU5_B DDR4_DQU6_B DDR4_DQU7_B
DDR4_DMU_BDDR4_DMU_A
DDR4_DQSU_P_B DDR4_DQSU_N_B
DDR4_DQL0_B DDR4_DQL1_B DDR4_DQL2_B DDR4_DQL3_B DDR4_DQL4_B DDR4_DQL5_B DDR4_DQL6_B DDR4_DQL7_B
DDR4_DML_B
DDR4_DQSL_P_B DDR4_DQSL_N_B
12
R3501 240R
1% R0402
VCC_DDR
U3501
A3
DQU0
B8
DQU1
C3
DQU2
C7
DQU3
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
E2
DMU_n/DBIU_n
B7
DQSU_P
A7
DQSU_N
G2
DQL0
F7
DQL1
H3
DQL2
H7
DQL3
H2
DQL4
H8
DQL5
J3
DQL6
J7
DQL7
E7
DML_n/DBIL_n
G3
DQSL_P
F3
DQSL_N
F9
ZQ
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
B1
VPP1
R9
VPP2
DDR4_16bit
FBGA96_14R00X11R00X1R20
DDRPHY_VREFOUT
3
DDR4_A0
P3
A0
DDR4_A1
P7
A1
DDR4_A2
R3
A2
DDR4_A3
N7
A3
DDR4_A4
N3
A4
DDR4_A5
P8
A5
DDR4_A6
P2
A6
DDR4_A7
R8
A7
DDR4_A8
R2
A8
DDR4_A9
R7
A9
DDR4_A10
M3
A10/AP
DDR4_A11
T2
A11
DDR4_A12
M7
A12/BC_n
WE_n/A14 CAS_n/A15 RAS_n/A16
DDR4_A13
T8
A13
DDR4_A14_WEn
L2
DDR4_A15_CASn
M8
DDR4_A16_RASn
L8
DDR4_BA0
N2
BA0
DDR4_BA1
N8
BA1
DDR4_BG0
M2
BG0
DDR4_CLKP
K7
CK_P
DDR4_CLKN
K8
CK_N
DDR4_CKE_1
K2
CKE
L7
CS_n
K3
ODT
L3
ACT_n
P1
RESET_n
P9
ALERT_n
T3
PAR
N9
TEN
T7
NC
M1
VREFCA
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
VCC_DDR VCC_DDR
DDR4_CS0n_1 DDR4_ODT0_1 DDR4_ACTn
DDR4_RESETnDDR4_RESETn
C3522
12
1nF
X5R 50V
C0402
C3523
12
1nF
X5R 50V
C0402
R3502 49.9R R0201 R3503 49.9R R0201 R3504 49.9R R0201
C3501 1nF C0402
R3526 0R R04025%DNP1 2
VREF_DDR4_CA
R3527 0R R04025%1 2
R3514 0R
VCC_DDR
1 2 1 2 1 2
1 2
DNP
1% 1% 1%
X5R 50V
R0402
R3508 0R R04025%1 2
R3509 0R R04025%1 2 R3507 0R R04025%1 2
DDR4_CKE DDR4_CS0n DDR4_ODT0
VREF_DDR4_CA
5%12
12
C3524 1nF
X5R 50V
C0402
VCC_DDR
VCC25_DDR
C3525
12
1nF
X5R 50V
C0402
DDR4_ECC_DQ0 DDR4_ECC_DQ1 DDR4_ECC_DQ2 DDR4_ECC_DQ3 DDR4_ECC_DQ4 DDR4_ECC_DQ5 DDR4_ECC_DQ6 DDR4_ECC_DQ7
DDR4_ECC_DM
DDR4_ECC_DQS_P DDR4_ECC_DQS_N
12
R3512 240R
1% R0402
C3526
12
1nF
X5R 50V
C0402
U3504
A3
DQU0
B8
DQU1
C3
DQU2
C7
DQU3
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
E2
DMU_n/DBIU_n
B7
DQSU_P
A7
DQSU_N
G2
DQL0
F7
DQL1
H3
DQL2
H7
DQL3
H2
DQL4
H8
DQL5
J3
DQL6
J7
DQL7
E7
DML_n/DBIL_n
G3
DQSL_P
F3
DQSL_N
F9
ZQ
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
B1
VPP1
R9
VPP2
DDR4_16bit
FBGA96_14R00X11R00X1R20
ECC
12
R3513 1K
1% R0402
DNP
12
R3515 1K
1% R0402
DNP
A10/AP
A12/BC_n
WE_n/A14 CAS_n/A15 RAS_n/A16
ACT_n
RESET_n ALERT_n
VREFCA
2
DDR4_A0
P3
A0
DDR4_A1
P7
A1
DDR4_A2
R3
A2
DDR4_A3
N7
A3
DDR4_A4
N3
A4
DDR4_A5
P8
A5
DDR4_A6
P2
A6
DDR4_A7
R8
A7
DDR4_A8
R2
A8
DDR4_A9
R7
A9
DDR4_A10
M3
DDR4_A11
T2
A11
DDR4_A12
M7
DDR4_A13
T8
A13
DDR4_A14_WEn
L2
DDR4_A15_CASn
M8
DDR4_A16_RASn
L8
DDR4_BA0
N2
BA0
DDR4_BA1
N8
BA1
DDR4_BG0
M2
BG0
DDR4_CLKP
K7
CK_P
DDR4_CLKN
K8
CK_N
DDR4_CKE
K2
CKE
DDR4_CS0n
L7
CS_n
DDR4_ODT0
K3
ODT
DDR4_ACTn
L3
DDR4_RESETn
C3513
X5R 50V
P1 P9 T3
PAR
N9
TEN
T7
NC
M1
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
1nF C0402
R3528 0R R04025%DNP1 2
VREF_DDR4_CA
R3529 0R R04025%1 2
DDR4_BG1/VSS_M9DDR4_BG1/VSS_M9DDR4_BG1/VSS_M9
VCC_DDR VCC_DDR
12
12
1 2
R3517 100K
R0402
R3518 100K
R0402
DNP
12
C3547 10uF
X5R
1%
6.3V C0603
C3553
12
1%
100nF
X5R 10V
C0402
DDR4_A1 DDR4_A9 DDR4_A13 DDR4_A7
DDR4_A2 DDR4_A11 DDR4_A8 DDR4_A6
DDR4_CKE DDR4_A16_RASn DDR4_CS0n DDR4_A15_CASn
DDR4_A5 DDR4_A3 DDR4_BA1 DDR4_A12
DDR4_BG0 DDR4_ACTn DDR4_A14_WEn DDR4_ODT0
DDR4_A0 DDR4_BA0 DDR4_A10 DDR4_A4
DDR4_CLKP DDR4_CLKN
DDR4_BG1/VSS_M9
DDR4_CLKP DDR4_CLKN
Notes: Close to SOC
12
C3548 100nF
X5R 10V
C0402
12
C3529 22uF
X5R
6.3V C0603
R3521 39R R04025%1 2 R3522 39R R04025%1 2
R3523 39R R04025%
U3507 UR6517/NCT3101S
1
VIN
2
GND
3
REFEN
4
VOUT
12
C3554 22uF
X5R
6.3V C0603
RP3500 39R RP4_0408
4 5 3
6
2
7
1
8
RP3501 39R RP4_0408
1
8
2
7
3
6
4 5
RP3502 39R RP4_0408
4 5 3
6
2
7
1
8
RP3503 39R RP4_0408
1
8
2
7
3
6
4 5
RP3504 39R RP4_0408
1
8
2
7
3
6
4 5
RP3505 39R RP4_0408
4 5 3
6
2
7
1
8
1 2
DNP
C1111
12
2pF
C0201 C0G 50V
V1.1
8
NC8
7
NC7
6
VCNTL
5
NC5
EPAD
SOP8_5R00X4R00X1R75_T
9
DDR_VTT
12
12
C3556
C3555
10nF
100nF
X5R
X5R
25V
10V
C0402
C0402
Notes: Need support DDR4 Requirement
12
C3551 10uF
X5R 10V C0805
DDR_VTT
12
12
12
12
VCC5V0_SYS
12
C3504 10uF
X5R 10V C0603
C3509 10uF
X5R 10V C0603
C3514 10uF
X5R 10V C0603
C3518 10uF
X5R 10V C0603
C3552 100nF
X5R 10V
C0402
1
12
12
12
12
NCT3101S_2A
上下电阻为
UR6517_1.8A
上下电阻为
C3505 1uF
X5R 10V
C0402
C3510 1uF
X5R 10V
C0402
C3515 1uF
X5R 10V
C0402
C3519 1uF
X5R 10V
C0402
C3506
12
100nF
X5R 10V C0402
C3511
12
100nF
X5R 10V C0402
C3516
12
100nF
X5R 10V C0402
C3520
12
100nF
X5R 10V C0402
1K-5K (2K 1%)
100K 1%
C3507
12
10nF
X5R 25V C0402
C3512
12
10nF
X5R 25V C0402
C3517
12
10nF
X5R 25V C0402
C3521
12
10nF
X5R 25V C0402
VCC3V3_SYS
C3530
12
1uF
X5R 10V C0402
R3516 10K
VCC3V3_PMU
VCC_DDR
C3558
C3557
12
12
10uF
10uF
X5R
X5R
10V
6.3V C0603
VCC_DDR
C0603
C3588
C3587
12
12
22uF
22uF
X5R
X5R
6.3V
6.3V C0603
C0603
A A
Rockchip Confidential
C3560
C3559
12
10uF
X5R 10V C0603
C3589
12
10uF
X5R
6.3V
C0603
C3561
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3590
C3591
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
5
C3563
C3562
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3592
C3593
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3565
C3564
12
100nF
X5R 10V
C0402
C3594
12
22uF
X5R
6.3V C0603
C3566
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3595
C3596
12
12
10uF
10uF
X5R
X5R
10V
10V
C0603
C0603
C3568
C3569
C3567
12
12
100nF
1uF
X5R
X5R
10V
6.3V
C0402
C0402
C3597
C3598
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3570
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3599
C3527
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
4
R0402
C3571
12
12
100nF
X5R 10V
C0402
C3528
12
100nF
X5R 10V C0402
C3572 100nF
X5R 10V
C0402
U3506 PT5108E23E-25
1
2
5%1 2
12
C3550 DNP
C0402
C3573
12
100nF
X5R 10V
C0402
IN
GND
EN3BP
SOT_23_5
C3574
12
100nF
X5R 10V
C0402
5
OUT
4
12
C3575
12
100nF
X5R 10V
C0402
12
C3549 DNP
C0402
C3576 100nF
X5R 10V
C0402
VCC25_DDR
12
12
C3532
C3531
4.7uF
4.7uF
X5R
X5R
6.3V
6.3V
C0402
C0402
C3577
C3578
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
3
12
12
C3533 100nF
X5R 10V
C0402
C3579
12
100nF
X5R 10V
C0402
12
C3534 100nF
X5R 10V
C0402
C3580
12
100nF
X5R 10V
C0402
12
C3535
C3536
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3582
C3581
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
12
12
C3538
C3537
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C3583
C3584
12
12
1uF
100nF
X5R
X5R
6.3V
10V
C0402
C0402
C3586
C3585
12
100nF
X5R 10V
C0402
C3502
12
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
2
Designed by:
Rockchip Electronics Co., Ltd
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
35.DRAM-DDR4_96P_2X16+ECC_1X16
35.DRAM-DDR4_96P_2X16+ECC_1X16
35.DRAM-DDR4_96P_2X16+ECC_1X16
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
1
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Sheet: of
Default
Default
Default
V1.1
V1.1
V1.1
30 72
30 72
30 72
Page 31
5
J12
K2
LPDDR3_D0 LPDDR3_D1 LPDDR3_D2
VCC_DDR
LPDDR3_D3 LPDDR3_D4 LPDDR3_D5 LPDDR3_D6 LPDDR3_D7 LPDDR3_D8
LPDDR3_D9 LPDDR3_D10 LPDDR3_D11 LPDDR3_D12 LPDDR3_D13 LPDDR3_D14 LPDDR3_D15 LPDDR3_D16 LPDDR3_D17 LPDDR3_D18 LPDDR3_D19 LPDDR3_D20 LPDDR3_D21 LPDDR3_D22 LPDDR3_D23 LPDDR3_D24 LPDDR3_D25 LPDDR3_D26 LPDDR3_D27 LPDDR3_D28 LPDDR3_D29 LPDDR3_D30 LPDDR3_D31
LPDDR3_DQS0P LPDDR3_DQS0N LPDDR3_DQS1P LPDDR3_DQS1N LPDDR3_DQS2P LPDDR3_DQS2N LPDDR3_DQS3P LPDDR3_DQS3N
LPDDR3_DM0 LPDDR3_DM1 LPDDR3_DM2 LPDDR3_DM3
D D
C C
B B
P9
N9 N10 N11
M8
M9 M10 M11 F11 F10
F9
F8 E11 E10
E9
D9
T8
T9 T10 T11
R8
R9 R10 R11 C11 C10
C9
C8 B11 B10
B9
B8
L10 L11 G10 G11 P10 P11 D10 D11
L8
G8
P8
D8
DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_D16/NC DDR_D17/NC DDR_D18/NC DDR_D19/NC DDR_D20/NC DDR_D21/NC DDR_D22/NC DDR_D23/NC DDR_D24/NC DDR_D25/NC DDR_D26/NC DDR_D27/NC DDR_D28/NC DDR_D29/NC DDR_D30/NC DDR_D31/NC
DDR_DQS0 DDR_DQS0n DDR_DQS1 DDR_DQS1n DDR_DQS2 DDR_DQS2n DDR_DQS3 DDR_DQS3n
DDR_DM0 DDR_DM1 DDR_DM2/NC DDR_DM3/NC
VDDCA1M2VDDCA2L2VDDCA3H3VDDCA4G2VDDCA5
VSS1B2VSS2B5VSS3C5VSS4E4VSS5E5VSS6F5VSS7H2VSS8
VDD2_1U9VDD2_2U8VDD2_3P6VDD2_4P5VDD2_5P4VDD2_6L5VDD2_7
F2
VSS9
VSS10L6VSS11M5VSS12N4VSS13N5VSS14R4VSS15R5VSS16T2VSS17T3VSS18T4VSS19T5VSSQ1B6VSSQ2
VDD2_8K6VDD2_9K5VDD2_10J6VDD2_11J5VDD2_12
H12
K12
VDD2_17
VDD2_16
VDD2_15
VDD2_13H6VDD2_14
D5
D6
G5
H5
4
B12
D12
F12
VSSQ3C6VSSQ4
VSSQ5E6VSSQ6F6VSSQ7
VSSQ8G6VSSQ9
U3600 LP3S_B178
FBGA178_13R00X11R50X1R20
VDD2_20
VDD2_19
VDD2_18
A8
A9
D4
VDDQ_6
VDDQ_5
VDDQ_4N8VDDQ_3
VDDQ_2
VDDQ_1
K11
L12
N12
R12
U11
3
G9
H10
K10
M12
P12
T12
VSSQ10
VSSQ11
VSSQ12L9VSSQ13M6VSSQ14
VSSQ15N6VSSQ16
VSSQ17R6VSSQ18T6VSSQ19
VSSCA1C3VSSCA2D3VSSCA3F4VSSCA4G3VSSCA5G4VSSCA6J4VSSCA7M4VSSCA8
VDDQ_16
VDDQ_15E8VDDQ_14
VDDQ_13
VDDQ_12H8VDDQ_11
VDDQ_10
VDDQ_9J9VDDQ_8
VDDQ_7
H9
K8
H11
J10
A11
C12
E12
G12
P3
R2
DDR_A0
P2
DDR_A1
N2
DDR_A2
N3
DDR_A3
M3
DDR_A4
F3
DDR_A5
E3
DDR_A6
E2
DDR_A7
D2
DDR_A8
C2
DDR_A9
J3
DDR_CLK
J2
DDR_CLKn
L3
DDR_CS0
L4
DDR_CS1
K3
DDR_CKE0
K4
DDR_CKE1
J8
DDR_ODT
B3
DDR_ZQ0
B4
DDR_ZQ1
A1
NU1
A2
NU2
A12
NU3
A13
NU4
B1
NU5
B13
NU6
T1
NU7
T13
NU8
U1
NU9
U2
NU10
U12
NU11
U13
NU12
C4
NC1
K9
NC2
R3
NC3
U10
H4
J11
VCC1V8_DDR
DDR_VREFCA
DDR_VREFDQ
VDD1_1A3VDD1_2A4VDDQ_17
VDD1_3
VDD1_4
VDD1_5
VDD1_6U3VDD1_7U4VDD1_8U5VDD1_9U6VDD1_10
A5
A6
A10
12
R3602 240R
1% R0402
DDR_VREFCA
DDR_VREFDQVCC_DDR
LPDDR3_A0 LPDDR3_A1 LPDDR3_A2 LPDDR3_A3 LPDDR3_A4 LPDDR3_A5 LPDDR3_A6 LPDDR3_A7 LPDDR3_A8 LPDDR3_A9
LPDDR3_CLKP LPDDR3_CLKN
LPDDR3_CS0n LPDDR3_CS1n
LPDDR3_CKE
LPDDR3_ODT0
12
R3603 240R
1% R0402
VCC_DDR VCC_DDR
12
R3604 1K
R0402 1%
12
C3601
12
1nF
R3606
X5R
1K
50V
R0402
C0402
1%
C3603
12
1nF
X5R 50V C0402
LPDDR3_CLKP LPDDR3_CLKN
R3608 0R
1 2
2
R0402
1 2
1 2
12
R3605
DNP
768R
R0402 1%
12
R3607
DNP
1K
R0402 1%
5%
R3600
49.9R
R0402
R3601
49.9R
R0402
1%
1%
12
VCC_DDR
12
12
C3600 100pF
C0G 50V
C0402
DNP
C3602 1nF
X5R 50V
C0402
C3604 1nF
X5R 50V
C0402
1
DDRPHY_VREFOUT
VCC1V8_DDR
C3631
4.7uF
X5R
6.3V
C0402
Notes: Close to SOC
C3633
C3632
12
12
100nF
C0402 X5R 10V
100nF
C0402 X5R 10V
12
C3634
C3635
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
36.DRAM-LPDDR3_1X32bit_178P
36.DRAM-LPDDR3_1X32bit_178P
36.DRAM-LPDDR3_1X32bit_178P
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Zhangdz
Designed by:
Zhangdz
Designed by:
Zhangdz
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
1
C3637
C3636
12
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
31 72
Sheet: of
31 72
Sheet: of
31 72
C3605
C3606
12
12
10uF
X5R
6.3V C0603
VCC_DDR
C3615
12
12
10uF
X5R
6.3V
A A
C0603
10uF
X5R
6.3V C0603
C3616 10uF
X5R
6.3V C0603
C3607
12
12
1uF
C0402 X5R 10V
C3617
12
12
1uF
C0402 X5R 10V
C3608 1uF
C0402 X5R 10V
C3618 1uF
C0402 X5R 10V
C3609
12
12
100nF
C0402 X5R 10V
C3619
12
12
100nF
C0402 X5R 10V
C3610 100nF
C0402 X5R 10V
C3620 100nF
C0402 X5R 10V
C3611 100nF
C0402 X5R 10V
C3621 100nF
C0402 X5R 10V
C3612
12
100nF
C0402 X5R 10V
C3622
12
100nF
C0402 X5R 10V
12
12
C3613 100nF
C0402 X5R 10V
C3623 100nF
C0402 X5R 10V
C3614
12
100nF
C0402 X5R 10V
VCC3V3_SYS
C3624
12
12
100nF
C0402 X5R 10V
C3625 100nF
C0402 X5R 10V
C3626 100nF
C0402 X5R 10V
12
12
C3627 100nF
C0402 X5R 10V
VCC3V3_PMU
C3628
12
100nF
C0402 X5R 10V
R3610 10K
1 2
C3629
12
1uF
X5R 10V C0402
DNP
R0402
VCCA1V8_PMU
R3609 0R
1 2
U3601 PT5108E23E-18
1
IN
GND
EN
SOT_23_5
DNP
OUT
BP
2
3
12
C3638 DNP
C0402
5%DNP
5%
R0402
5
C3630
12
12
4.7uF
C3639 DNP
C0402
X5R
6.3V
C0402
4
12
12
12
Rockchip Confidential
5
4
3
2
Page 32
5
4
3
2
1
U3800A
LPDDR4_DQ0_A LPDDR4_DQ1_A LPDDR4_DQ2_A LPDDR4_DQ3_A LPDDR4_DQ4_A LPDDR4_DQ5_A LPDDR4_DQ6_A
D D
C C
VCC0V6_DDR
12
12
R3800
R3801
240R
240R
R0402
R0402
1%
1%
VCC_DDR
C3801
12
B B
22uF
X5R
6.3V C0603
12
C3802 10uF
X5R
6.3V C0603
C3803
12
10uF
X5R
6.3V C0603
LPDDR4_DQ7_A
LPDDR4_DQS0P_A LPDDR4_DQS0N_A
LPDDR4_DM0_A
LPDDR4_DQ8_A
LPDDR4_DQ9_A LPDDR4_DQ10_A LPDDR4_DQ11_A LPDDR4_DQ12_A LPDDR4_DQ13_A LPDDR4_DQ14_A LPDDR4_DQ15_A
LPDDR4_DQS1P_A LPDDR4_DQS1N_A
LPDDR4_DM1_A
LPDDR4_A0_A LPDDR4_A1_A LPDDR4_A2_A LPDDR4_A3_A LPDDR4_A4_A LPDDR4_A5_A
LPDDR4_CLKP_A LPDDR4_CLKN_A
LPDDR4_CKE0_A LPDDR4_CKE1_A
LPDDR4_CS0n_A LPDDR4_CS1n_A
LPDDR4_ODT0_CA_A
C3804
12
1uF
C0402 X5R 10V
C3805 100nF
C0402 X5R 10V
C3806
12
100nF
C0402 X5R 10V
12
B2
DQ0_a
C2
DQ1_a
E2
DQ2_a
F2
DQ3_a
F4
DQ4_a
E4
DQ5_a
C4
DQ6_a
B4
DQ7_a
D3
DQS0_t_a
E3
DQS0_c_a
C3
DMI0_a
B11
DQ8_a
C11
DQ9_a
E11
DQ10_a
F11
DQ11_a
F9
DQ12_a
E9
DQ13_a
C9
DQ14_a
B9
DQ15_a
D10
DQS1_t_a
E10
DQS1_c_a
C10
DMI1_a
H2
CA0_a
J2
CA1_a
H9
CA2_a
H10
CA3_a
H11
CA4_a
J11
CA5_a
J8
CK_t_a
J9
CK_c_a
J4
CKE0_a
J5
CKE1_a
K8
CKE2_a_NC
H4
CS0_a
H3
CS1_a
K5
CS2_a_NC
G2
ODT_CA_a
A5
ZQ0
A8
ZQ1
G11
ZQ2_NC
LPDDR4_200P
BGA200_15R00X10R00X0R90
C3807 100nF
C0402 X5R 10V
C3808
12
100nF
C0402 X5R 10V
12
CH BCH A
C3809
12
100nF
C0402 X5R 10V
DQ0_b DQ1_b DQ2_b DQ3_b DQ4_b DQ5_b DQ6_b DQ7_b
DQS0_t_b DQS0_c_b
DMI0_b
DQ8_b
DQ9_b DQ10_b DQ11_b DQ12_b DQ13_b DQ14_b DQ15_b
DQS1_t_b DQS1_c_b
DMI1_b
CA0_b
CA1_b
CA2_b
CA3_b
CA4_b
CA5_B
CK_t_b CK_c_b
CKE0_b CKE1_b
CKE2_b_NC
CS0_b
CS1_b
CS2_b_NC
ODT_CA_b
RESET_n
C3810
12
100nF
C0402 X5R 10V
AA2 Y2 V2 U2 U4 V4 Y4 AA4
W3 V3
Y3
AA11 Y11 V11 U11 U9 V9 Y9 AA9
W10 V10
Y10
R2 P2 R9 R10 R11 P11
P8 P9
P4 P5 N8
R4 R3 N5
T2
T11
C3811
12
12
100nF
C0402 X5R 10V
12
C3812 100nF
C0402 X5R 10V
C3800 1nF
C0402 X5R 50V
DNP
LPDDR4_DQ0_B LPDDR4_DQ1_B LPDDR4_DQ2_B LPDDR4_DQ3_B LPDDR4_DQ4_B LPDDR4_DQ5_B LPDDR4_DQ6_B LPDDR4_DQ7_B
LPDDR4_DQS0P_B LPDDR4_DQS0N_B
LPDDR4_DM0_B
LPDDR4_DQ8_B LPDDR4_DQ9_B LPDDR4_DQ10_B LPDDR4_DQ11_B LPDDR4_DQ12_B LPDDR4_DQ13_B LPDDR4_DQ14_B LPDDR4_DQ15_B
LPDDR4_DQS1P_B LPDDR4_DQS1N_B
LPDDR4_DM1_B
LPDDR4_A0_B LPDDR4_A1_B LPDDR4_A2_B LPDDR4_A3_B LPDDR4_A4_B LPDDR4_A5_B
LPDDR4_CLKP_B LPDDR4_CLKN_B
LPDDR4_CKE0_B LPDDR4_CKE1_B
LPDDR4_CS0n_B LPDDR4_CS1n_B
LPDDR4_ODT0_CA_B
LPDDR4_RESETn
C3813
12
100nF
C0402 X5R 10V
C3818
C3814 100nF
C0402 X5R 10V
C3815
12
12
100nF
C0402 X5R 10V
12
C3816 100nF
C0402 X5R 10V
C3817
12
12
100nF
C0402 X5R 10V
100nF
C0402 X5R 10V
C3819 100nF
C0402 X5R 10V
C3820
12
12
100nF
C0402 X5R 10V
12
C3821 100nF
C0402 X5R 10V
12
VCC1V8_DDR
VCC0V6_DDR
C3822 100nF
C0402 X5R 10V
VCC_DDR
U3800B
F1
VDD1_1
F12
VDD1_2
G4
VDD1_3
G9
VDD1_4
T4
VDD1_5
T9
VDD1_6
U1
VDD1_7
U12
VDD1_8
A4
VDD2_1
A9
VDD2_2
F5
VDD2_3
F8
VDD2_4
H1
VDD2_5
H5
VDD2_6
H8
VDD2_7
H12
VDD2_8
K1
VDD2_9
K3
VDD2_10
K10
VDD2_11
K12
VDD2_12
N1
VDD2_13
N3
VDD2_14
N10
VDD2_15
N12
VDD2_16
R1
VDD2_17
R5
VDD2_18
R8
VDD2_19
R12
VDD2_20
U5
VDD2_21
U8
VDD2_22
AB4
VDD2_23
AB9
VDD2_24
B3
VDDQ_1
B5
VDDQ_2
B8
VDDQ_3
B10
VDDQ_4
D1
VDDQ_5
D5
VDDQ_6
D8
VDDQ_7
D12
VDDQ_8
F3
VDDQ_9
F10
VDDQ_10
U3
VDDQ_11
U10
VDDQ_12
W1
VDDQ_13
W5
VDDQ_14
W8
VDDQ_15
W12
VDDQ_16
AA3
VDDQ_17
AA5
VDDQ_18
AA8
VDDQ_19
AA10
VDDQ_20
A1
DNU_1
A2
DNU_2
A11
DNU_3
A12
DNU_4
B1
DNU_5
B12
DNU_6
LPDDR4_200P
BGA200_15R00X10R00X0R90
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8
VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58
DNU_7
DNU_8
DNU_9 DNU_10 DNU_11 DNU_12
A3 A10 C1 C5 C8 C12 D2 D4 D9 D11 E1 E5 E8 E12 G1 G3 G5 G8 G10 G12 J1 J3 J10 J12 K2 K4 K9 K11 N2 N4 N9 N11 P1 P3 P10 P12 T1 T3 T5 T8 T10 T12 V1 V5 V8 V12 W2 W4 W9 W11 Y1 Y5 Y8 Y12 AB3 AB5 AB8 AB10
AA1 AA12 AB1 AB2 AB11 AB12
VCC0V6_DDR
VCC1V8_DDR
C3830
C3831
C3829
C3828
12
22uF
X5R
6.3V C0603
VCC3V3_SYS VCC0V6_DDR VCC_DDR
VCC1V8_DDR
12
A A
C3855 10uF
X5R 10V C0603
12
12
10uF
X5R
6.3V C0603
R3806 100K
R0402
10uF
X5R
6.3V C0603
1 2
5%
12
1uF
C0402 X5R 10V
12
C3856 100nF
X5R 10V C0402
C3832
12
4
2
1
C3833
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
ETA3409A/TCS42 01:1.0uH/2A SY8089AAAC:2.2 uH/2A
U3801
LX
VIN
GND
EN
FB/OUT
SY8089AAC
/ETA3409 A/TCS4201
SOT_23_5
12
3
5
C3834 100nF
C0402 X5R 10V
L3800
2.2uH
IND_404026
FB=0.6V
C3835
C3836
12
12
100nF
C0402 X5R 10V
12
100nF
C0402 X5R 10V
C3857 100pF
C0G 50V C0402
C3837
12
12
100nF
C0402 X5R 10V
12
12
R3807 2K
1% R0402
R3809 100K
1% R0402
C3858
12
22uF
X5R
6.3V C0603
Rockchip Confidential
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4
C3838 100nF
C0402 X5R 10V
C3839
12
12
100nF
C0402 X5R 10V
C3859
12
100nF
X5R 10V
C0402
Default Option
LPDDR4x =0.6V
C3840 100nF
C0402 X5R 10V
12
C3860 10uF
X5R 10V C0603
R3804
C3841
12
100nF
C0402 X5R 10V
12
DNP
1 2
5%
0R
R0603
LPDDR4 =1.1V
C3842 100nF
C0402 X5R 10V
C3843 100nF
C0402 X5R 10V
3
C3844
12
12
100nF
C0402 X5R 10V
12
C3845 100nF
C0402 X5R 10V
C3846
12
100nF
C0402 X5R 10V
VCC3V3_SYS
VCC3V3_PMU
C3854
12
100nF
C0402 X5R 10V
VCCA1V8_PMU
R3802 0R
1 2
U3802
1
12
C3853 DNP
C0402
IN
2
GND
EN3BP
PT5108E23E-18
SOT_23_5
DNP
2
C3827
12
1uF
X5R 10V C0402
DNP
DNP
1 2
R3808
5%
10K
R0402
5
OUT
4
5%
R0402
C3847
12
C3852 DNP
C0402
4.7uF
X5R
6.3V
C0402
12
C3823
C3824
12
12
12
Project:
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File:
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Date:
Date:
Date:
Designed by:
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Designed by:
100nF
10uF
C0402
X5R
X5R
6.3V 10V
C0603
C3848
C3849
12
100nF
10uF
C0402
X5R
X5R
6.3V 10V
C0603
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
38.DRAM-LPDDR4X_1X32bit_200P
38.DRAM-LPDDR4X_1X32bit_200P
38.DRAM-LPDDR4X_1X32bit_200P
Wednesday, June 16, 2021
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Wednesday, June 16, 2021
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C3825
12
12
Reviewed by:
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C3826
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
C3850
C3851
12
100nF
100nF
C0402
C0402
X5R
X5R
10V
10V
Rockchip Electronics Co., Ltd
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Default
Default
Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
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32 72
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32 72
Page 33
5
eMMC Flash
eMMC_D0/FLASH_D0 eMMC_D1/FLASH_D1 eMMC_D2/FLASH_D2
D D
eMMC_D3/FLASH_D3 eMMC_D4/FLASH_D4 eMMC_D5/FLASH_D5 eMMC_D6/FLASH_D6 eMMC_D7/FLASH_D7
eMMC_CMD/FLASH_WRn
eMMC_CLKOUT/FLASH_DQS
eMMC_DATA_STROBE/FLASH_CLE
eMMC_RSTn/FSPI_D2/FLASH_WPn
Note:
No need to double layout with Nand Flash, 0R resistor can be omitted
C C
VCCIO_FLASH
R4004 10K R04025%@eMMC
1 2
R4005 10K R04025%@eMMC
1 2
R4006 10K R04025%@eMMC
B B
1 2
C4008 2.2uF C0402
12
X5R 10V
@eMMC
eMMC_D0/FLASH_D0 eMMC_D1/FLASH_D1 eMMC_D2/FLASH_D2 eMMC_D3/FLASH_D3 eMMC_D4/FLASH_D4 eMMC_D5/FLASH_D5 eMMC_D6/FLASH_D6 eMMC_D7/FLASH_D7
eMMC_CMD
eMMC_CLKOUT
eMMC_RSTn
eMMC_DATA_STROBE
C4009
12
100nF
C0402 X5R 10V
@eMMC
Note:
If Flash is compatible, please notice
A A
when eMMC is used, the option is that @eMMC is mounted, @Nand is not mounted,@SPI Flash is not mounted when Nand is used, the option is that @Nand is mounted, @eMMC is not mounted,@SPI Flash is not mounted when SPI Flash is used, the option is that SPI Flash is mounted, @eMMC is not mounted,@Nand is not mounted
Rockchip Confidential
5
4
R4002 0R
1 2
Place at branch point and FLASH_CLE Signal
eMMC_CLKOUT/FLASH_DQS eMMC_CLKOUT
eMMC_CMD/FLASH_WRn eMMC_CMD
U4000A
A3
DATA0
A4
DATA1
A5
DATA2
B2
DATA3
B3
DATA4
B4
DATA5
B5
DATA6
B6
DATA7
M5
CMD
M6
CLK
K5
RST_n
C2
VDDi
H5
12
R4007 47K
R0402 5%
DNP
4
Data Strobe
E9
VSF1
E10
VSF2
F10
VSF3
K10
VSF4
EMMC_B153_2L
BGA153_13RX11R5X0R9_2L
R4003 0R
1 2
Place at branch point and FLASH_DQS Signal
R4000 0R
1 2
Place at branch point and FSPI_D2/FLASH_WPn Signal
R4001 0R
1 2
Place at branch point and FLASH_WRn Signal
C6
VCCQ1
M4
VCCQ2
N4
VCCQ3
P3
VCCQ4
P5
VCCQ5
E6
VCC1
F5
VCC2
J10
VCC3
K9
VCC4
J5
VSS1
A6
VSS2
C4
VSS3
E7
VSS4
G5
VSS5
H10
VSS6
K8
VSSQ1
N2
VSSQ2
N5
VSSQ3
P4
VSSQ4
P6
VSSQ5
@eMMC
R0402
R0402
R0402
R0402
12
3
5%DNP
5%DNP
C4000 100nF
X5R 10V C0402
@eMMC
3
eMMC_DATA_STROBEeMMC_DATA_STROBE/FLASH_CLE
5%@eMMC
eMMC_RSTneMMC_RSTn/FSPI_D2/FLASH_WPn
5%@eMMC
C4001
12
100nF
X5R 10V C0402
@eMMC
C4005
12
100nF
X5R 10V C0402
@eMMC
12
12
C4002 100nF
X5R 10V C0402
@eMMC
C4006 100nF
X5R 10V C0402
@eMMC
12
VCC_3V3
12
VCCIO_FLASH
C4003 100nF
X5R 10V C0402
@eMMC
C4007
4.7uF
X5R
6.3V
C0603
@eMMC
12
C4004
4.7uF
X5R
6.3V
C0603
@eMMC
2
A7
E8
E5
RFU1
RFU2
G10
RFU3
RFU4G3RFU5
@eMMC
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U4000B
A2
NC2
A8
NC8
A9
NC9
A10
NC10
A11
NC11
A12
NC12
A13
NC13
A14
NC14
B1
NC15
B7
NC21
B8
NC22
B9
NC23
B10
NC24
B11
NC25
B12
NC26
B13
NC27
B14
NC28
C1
NC29
C3
NC31
C7
NC35
C8
NC36
C9
NC37
C10
NC38
C11
NC39
C12
NC40
C13
NC41
C14
NC42
D1
NC43
D2
NC44
D3
NC45
D4
NC46
D12
NC54
D13
NC55
D14
NC56
E1
NC57
E2
NC58
E3
NC59
E12
NC68
E13
NC69
E14
NC70
F1
NC71
F2
NC72
F3
NC73
F12
NC82
F13
NC83
F14
NC84
G1
NC85
G2
NC86
G12
NC96
G13
NC97
G14
NC98
EMMC_B153_2L
BGA153_13RX11R5X0R9_2L
Project:
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File:
File:
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Date:
Date:
Date:
Designed by:
Designed by:
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
40.Flash-eMMC Flash
40.Flash-eMMC Flash
40.Flash-eMMC Flash
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
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Zhangdz
RFU6K6RFU7
K7
P7
P10
RFU8
Default
Default
Default
RFU9
1
1
NC196 NC195 NC194 NC193 NC191 NC190 NC184 NC183
NC182 NC181 NC180 NC179 NC178 NC177 NC176 NC175 NC174 NC171 NC169
NC168 NC167 NC166 NC165 NC164 NC163 NC162 NC161 NC157 NC156 NC155
NC154 NC153 NC152 NC143 NC142 NC141
NC140 NC139 NC138 NC129 NC128 NC127
NC126 NC125 NC124 NC115 NC114 NC113
NC112 NC111 NC110 NC101 NC100
NC99
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Sheet: of
P14 P13 P12 P11 P9 P8 P2 P1
N14 N13 N12 N11 N10 N9 N8 N7 N6 N3 N1
M14 M13 M12 M11 M10 M9 M8 M7 M3 M2 M1
L14 L13 L12 L3 L2 L1
K14 K13 K12 K3 K2 K1
J14 J13 J12 J3 J2 J1
H14 H13 H12 H3 H2 H1
V1.1
V1.1
V1.1
33 72
33 72
33 72
Page 34
5
4
3
2
1
Nand Flash
eMMC_D0/FLASH_D0 eMMC_D1/FLASH_D1 eMMC_D2/FLASH_D2 eMMC_D3/FLASH_D3 eMMC_D4/FLASH_D4
D D
C C
B B
eMMC_D5/FLASH_D5 eMMC_D6/FLASH_D6 eMMC_D7/FLASH_D7
eMMC_CMD/FLASH_WRn
eMMC_CLKOUT/FLASH_DQS
eMMC_DATA_STROBE/FLASH_CLE
eMMC_RSTn/FSPI_D2/FLASH_WPn FSPI_CLK/FLASH_ALE FSPI_D0/FLASH_RDY FSPI_D1/FLASH_RDn FSPI_CS0n/FLASH_CS0n FSPI_D3/FLASH_CS1n
VCCIO_FLASH
R4104 4.7K
1 2
R4105 4.7K
1 2
R4106 4.7K
1 2
eMMC_DATA_STROBE/FLASH_CLE FLASH_CLE
eMMC_CLKOUT/FLASH_DQS FLASH_DQS
eMMC_CMD/FLASH_WRn FLASH_WRn
Note:
No need to double layout with eMMC, 0R resistor can be omitted
VCC_3V3
FSPI_D0/FLASH_RDY
5%@Nand
R0402
R0402
R0402
FSPI_D1/FLASH_RDn FSPI_CS0n/FLASH_CS0n
5%@Nand
FSPI_D3/FLASH_CS1n
5%@Nand
VCC_3V3 VCC_3V3
FLASH_CLE FSPI_CLK/FLASH_ALE FLASH_WRn eMMC_RSTn/FSPI_D2/FLASH_WPn
VCC_3V3
R4100 0R
1 2
@Nand
Place at branch point and eMMC_DATA_STROBE Signal
R4101 0R
1 2
@Nand
Place at branch point and eMMC_CLKOUT Signal
R4102 0R
1 2
@Nand
Place at branch point and eMMC_CMD Signal
U4100
1
VCC1
2
VSS1
3
NC1
4
R/B1
5
R/B2
6
R/B3
7
R/B4
8
RE
9
CE0
10
CE1
11
NC2
12
VCC2
13
VSS2
14
CE2
15
CE3
16
CLE
17
ALE
18
WE
19
WP
20
NC3
21
NC4
22
NC5
23
VSS3
24
VCC3
NAND_FLASH
TSOP48_18R40X12R10X1R20
@Nand
VCC_3V3
R0402
R0402
R0402
VSSQ4 VCCQ4
VSSQ3 VCCQ3 VCCQ5
VCCQ2 VSSQ2
VCCQ1 VSSQ1
VSS5 NC13
I/O7 I/O6 I/O5 I/O4
VCC4 VSS4
DQS
I/O3 I/O2 I/O1 I/O0
NC6
VSS6
5%
5%
5%
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VCCIO_FLASH
eMMC_D7/FLASH_D7 eMMC_D6/FLASH_D6 eMMC_D5/FLASH_D5 eMMC_D4/FLASH_D4
FLASH_DQS
eMMC_D3/FLASH_D3 eMMC_D2/FLASH_D2 eMMC_D1/FLASH_D1 eMMC_D0/FLASH_D0
VCCIO_FLASH
R4103 0R
1 2
R4107 0R
1 2
@Nand
R0402
R0402
5%DNP
5%
Note:
If use SLC Nand, This Resistance is DNP
R4108 0R
1 2
R0402
5%DNP
Note:
If use Toshiba and Sandisk DDR mode, VCCQ1 and VCCQ4 must be connected to VCCIO_FLASH
V1.1
C4100
12
1uF
X5R
6.3V
C0402
@Nand
Note:
A A
If Flash is compatible, please notice
12
C4101 100nF
C0402 X5R 10V
@Nand
12
C4102 100nF
C0402 X5R 10V
@Nand
when eMMC is used, the option is that @eMMC is mounted, @Nand is not mounted,@SPI Flash is not mounted when Nand is used, the option is that @Nand is mounted, @eMMC is not mounted,@SPI Flash is not mounted when SPI Flash is used, the option is that SPI Flash is mounted, @eMMC is not mounted,@Nand is not mounted
Rockchip Confidential
5
4
C4103
12
1uF
X5R
6.3V
C0402
@Nand
3
12
C4104 100nF
C0402 X5R 10V
@Nand
Rockchip Electronics Co., Ltd
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Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
41.Flash-Nand Flash(Option)
41.Flash-Nand Flash(Option)
41.Flash-Nand Flash(Option)
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
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1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
34 72
Sheet: of
34 72
Sheet: of
34 72
Page 35
5
4
3
2
1
MicroSD Card
SDMMC0_D0 SDMMC0_D1 SDMMC0_D2/ARMJTAG_TCK
D D
SDMMC0_D3/ARMJTAG_TMS
SDMMC0_CMD
SDMMC0_CLK
SDMMC0_DET_L
13
C C
VCC3V3_SD
SDMMC0_D2/ARMJTAG_TCK SDMMC0_D3/ARMJTAG_TMS SDMMC0_CMD
1 2 1 2 1 2
SDMMC0_CLK
SDMMC0_D0 SDMMC0_D1 SDMMC0_DET_L
C4200
12
10uF
X5R 10V C0603
B B
Close to MicroSD Card
12
C4201 100nF
X5R 10V
C0402
12
R4206 10K
5% R0402
DNP
1 2 1 2 1 2
R4200 22R R04025% R4201 22R R04025% R4202 22R R04025%
R4203 22R R04025% R4204 22R R04025% R4205 100R R04025%
12
D4205 ESD5341N
ESD0402
12
D4206 ESD5341N
ESD0402
12
D4200 ESD5341N
ESD0402
12
D4201 ESD5341N
ESD0402
12
D4202 ESD5341N
ESD0402
12
D4203 ESD5341N
ESD0402
12
D4204 ESD5341N
ESD0402
1 2 3 4 5 6 7 8 9
DATA2 CD/DATA3 CMD VDD CLK VSS DATA0 DATA1 CD
G4
G1
10
12
G3
J4200 TFP09-2-12B
TF9_TFP09-2-12B
G2
11
MicroSD Card
A A
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Project:
Project:
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Project:
File:
File:
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Date:
Date:
Date:
Designed by:
Designed by:
4
3
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
42.Flash-MicroSD Card
42.Flash-MicroSD Card
42.Flash-MicroSD Card
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Default
Default
Zhangdz
Zhangdz
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Reviewed by:
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Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
35 72
Sheet: of
35 72
Sheet: of
35 72
Page 36
5
4
3
2
1
SPI Flash
FSPI_CLK/FLASH_ALE
D D
FSPI_D0/FLASH_RDY FSPI_D1/FLASH_RDn eMMC_RSTn/FSPI_D2/FLASH_WPn FSPI_D3/FLASH_CS1n
FSPI_CS0n/FLASH_CS0n
U4300 W25Q256JWEIQ
FSPI_CS0n/FLASH_CS0n
FSPI_D1/FLASH_RDn
eMMC_RSTn/FSPI_D2/FLASH_WPn FSPI_CLK/FLASH_ALE
C C
WSON8_8R00X6R00X0R80_T
1
CS
DO(D1)2HOLD(D3)
3
WP(D2)
4
VSS
EPAD
9
@SPI Flash
VCC
CLK
DI(D0)
8
FSPI_D3/FLASH_CS1n
7
6
FSPI_D0/FLASH_RDY
5
12
VCCIO_FLASH
C4300 100nF
C0402 X5R 10V
@SPI Flash
C4301
12
1uF
X5R
6.3V
C0402
@SPI Flash
Note:
Default: 1.8V
Support: 1bit SPI NOR or SPI NAND 4bit SPI NOR or SPI NAND
VCCIO_FLASH VCCIO_FLASH
B B
12
R4300 10K
5% R0402
eMMC_RSTn/FSPI_D2/FLASH_WPn FSPI_D3/FLASH_CS1n
@SPI Flash
12
R4301 10K
5% R0402
@SPI Flash
Note:
If Flash is compatible, please notice when eMMC is used, the option is that @eMMC is mounted, @Nand is not mounted,@SPI Flash is not mounted when Nand is used, the option is that @Nand is mounted, @eMMC is not mounted,@SPI Flash is not mounted when SPI Flash is used, the option is that SPI Flash is mounted, @eMMC is not mounted,@Nand is not mounted
A A
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Project:
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4
3
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
43.Flash-SPI FLASH(Option)
43.Flash-SPI FLASH(Option)
43.Flash-SPI FLASH(Option)
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Default
Default
Zhangdz
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Reviewed by:
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Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
36 72
Sheet: of
36 72
Sheet: of
36 72
Page 37
5
DVP_PWREN0_H_GPIO0_B0 HDMIRX_PWREN_H_GPIO0_D6
4
Camera0 Power supply
3
Camera1 Power supply
2
Note:
When the binocular camera is used, If separate control is required, separate power supply is recommended
1
VCC3V3_SYS VDD1V2_DVDD_DVP0 VCC3V3_SYS VDD1V2_DVDD_DVP1
D D
12
C4500 10uF
X5R
6.3V C0603
DNP
DVP_PWREN0_H_GPIO0_B0 HDMIRX_PWREN_H_GPIO0_D6
VCC3V3_SYS
C4510
12
1uF
C C
B B
X5R
6.3V C0402
DVP_PWREN0_H_GPIO0_B0
VCC3V3_SYS
C4524
12
1uF
X5R
6.3V C0402
DVP_PWREN0_H_GPIO0_B0
DNP
1 2
R4500
5%
10K
R0402
1 2
R4506
5%
10K
R0402
1 2
R4512
5%
10K
R0402
12
12
12
C4508 100nF
X5R 10V C0402
DNP
C4518 100nF
X5R 10V C0402
C4532 100nF
X5R 10V C0402
DNP
U4500
4
VIN
2
GND
1
EN
SY8089AAC
SOT_23_5
U4502
1
IN
2
GND
EN3ADJ
LP3983S/TCS2196
SOT_23_5
U4504
1
IN
2
GND
EN3BP
PT5108E23E-18
SOT_23_5
FB/OUT
LX
DNP
OUT
OUT
L4500
3
DNP
2.2uH
IND_404026
5
Default=1.2V
5
12
R4507 200K
1%
4
R0402
FB=0.8V
12
R4510 390K
1% R0402
5
12
C4520 DNP
C0402
4
12
C4530 DNP
C0402
12
12
VDD1V2_DVDD_DVP0
12
C4511 22pF
C0G 50V C0402
C4501 100pF
C0G 50V C0402
DNP
R4501 150K
1% R0402
DNP
12
R4504 150K
1% R0402
DNP
C4512
12
10uF
X5R 10V C0603
DVDD_DVP0=1.2V
DVDD_DVP0=1.5V
VCC1V8_DOVDD_DVP0
12
C4521 DNP
C0402
C4525
12
4.7uF
X5R
6.3V C0603
Default=1.2V
C4502 22uF
X5R
6.3V C0603
DNP
C4503
12
100nF
X5R 10V
C0402
DNP
12
DVDD_DVP0=1.2V
DVDD_DVP0=1.5V
Note:
According to camera model, DCDC power supply is recommended if the DVDD current exceeds 100mA
390K 1%
220K 1%
Default
Option
150K 1%
100K 1%
Default
12
C4504 10uF
X5R
6.3V C0603
DNP
VCC3V3_SYS
C4514
12
1uF
X5R
6.3V C0402
HDMIRX_PWREN_H_GPIO0_D6
VCC3V3_SYS
C4527
12
1uF
X5R
6.3V C0402
HDMIRX_PWREN_H_GPIO0_D6
DNP
1 2
R4502
5%
10K
R0402
1 2
R4508
5%
10K
R0402
1 2
R4513
5%
10K
R0402
U4501
4
VIN
2
GND
1
EN
12
C4509
SY8089AAC
SOT_23_5
100nF
X5R 10V C0402
DNP
U4503
1
IN
2
GND
EN3ADJ
C4519
12
100nF
LP3983S/TCS2196
X5R
SOT_23_5 10V C0402
U4505
1
IN
2
GND
3
EN
C4533
12
PT5108E23E-18
100nF
SOT_23_5
X5R 10V C0402
DNP
VEN min=1.5V
FB/OUT
LX
DNP
OUT
OUT
BP
L4501
3
DNP
2.2uH
IND_404026
5
Default=1.2V
5
12
R4509 200K
1%
4
R0402
FB=0.8V
12
R4511 390K
1% R0402
5
12
C4522 DNP
C0402
4
12
C4531 DNP
C0402
12
12
VDD1V2_DVDD_DVP1
12
C4515 22pF
C0G 50V C0402
C4505 100pF
C0G 50V C0402
DNP
R4503 150K
1% R0402
DNP
12
R4505 150K
1% R0402
DNP
C4516
12
10uF
X5R 10V C0603
DVDD_DVP1=1.2V
DVDD_DVP1=1.5V
VCC1V8_DOVDD_DVP1
12
C4523 DNP
C0402
C4528
12
4.7uF
X5R
6.3V C0603
Default=1.2V
12
22uF
X5R
6.3V C0603
DNP
100nF
X5R 10V
C0402
DNP
C4507
C4506
12
DVDD_DVP0=1.2V
DVDD_DVP0=1.5V
Note:
According to camera model, DCDC power supply is recommended if the DVDD current exceeds 100mA
390K 1%
220K 1%
Default
Option
150K 1%
100K 1%
Default
VCC5V0_SYS
C4535
12
1uF
X5R 10V C0402
DVP_PWREN0_H_GPIO0_B0
1 2
R4514
5%
100K
R0402
U4506
1
IN
2
GND
EN3BP
C4549
12
PT5108E23E-28
100nF
SOT_23_5
X5R 10V C0402
5
OUT
4
12
12
12
C4534 DNP
C0402
C4548 DNP
C0402
C4536 DNP
C0402
FB4500 180R-100M
C4537
12
4.7uF
X5R
6.3V C0603
1 2
VCC2V8_AVDD_DVP0 VCC2V8_AVDD_DVP1VCC2V8_DVP1
L0603 1.5A
C4539
12
10uF
X5R 10V C0603
VCC5V0_SYSVCC2V8_DVP0
C4541
12
1uF
X5R 10V C0402
HDMIRX_PWREN_H_GPIO0_D6
1 2
R4515
5%
100K
R0402
U4507
1
IN
2
GND
3
EN
C4551
12
100nF
PT5108E23E-28
X5R
SOT_23_5 10V C0402
5
OUT
4
BP
12
12
12
C4542 DNP
C0402
C4550 DNP
C0402
C4543 DNP
C0402
FB4501 180R-100M
C4544
12
4.7uF
X5R
6.3V C0603
1 2
L0603 1.5A
C4546
12
10uF
X5R 10V C0603
Note:
Adjust the power on sequence according to the camera model
A A
Rockchip Confidential
eg:GC8034
Power on Sequence
1.8V-->1.2V-->2.8V--->MCLK-->PWDN--->RST
5
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
45.VI-Camera_Power
45.VI-Camera_Power
45.VI-Camera_Power
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Designed by:
4
3
2
Designed by:
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
1
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
37 72
Sheet: of
37 72
Sheet: of
37 72
Page 38
5
4
Camera0:MIPI_CSI_RX 4Lanes
3
2
1
MIPI_CSI_RX_D0P MIPI_CSI_RX_D0N
D D
C C
MIPI_CSI_RX_D1P MIPI_CSI_RX_D1N
MIPI_CSI_RX_D2P MIPI_CSI_RX_D2N
MIPI_CSI_RX_D3P MIPI_CSI_RX_D3N
MIPI_CSI_RX_CLK0P MIPI_CSI_RX_CLK0N
CIF_CLKOUT
I2C2_SDA_M1
I2C2_SCL_M1
MIPI_CAM0_PDN_L_GPIO3_D5
MIPI_CAM0_RST_L_GPIO3_D4
12
MIPI_CSI_RX_D0P MIPI_CSI_RX_D0N
MIPI_CSI_RX_D2P MIPI_CSI_RX_D2N
MIPI_CSI_RX_D3P MIPI_CSI_RX_D3N
CIF_CLKOUT MIPI_CSI_X4_RST
C4701
MIPI_CAM0_PDN_L_GPIO3_D5
DNP
C0402
Note:
J4700 AXT530124
CNN30M_0R40_V_SMT
1
GND_1
2
RDP0
3
RDN0
4
GND_4
5
RDP2
6
RDN2
7
GND_7
8
RDP3
9
RDN3
10
GND_10
11
MCLK
12
RESET
13
GND_13
14
PWDN GND_1515GND_16
G_3131G_3232G_3333G_34
RCN RCP
GND_28
RDP1 RDN1
GND_25
DOVDD1.8V
GND_23
DVDD1.5V
SIO_D SIO_C
GND_19
AVDD2.8V
34
VCC1V8_DOVDD_DVP0
30 29 28 27 26 25 24 23 22 21 20 19 18
AF
17 16
MIPI_CSI_RX_CLK0N MIPI_CSI_RX_CLK0P
MIPI_CSI_RX_D1P MIPI_CSI_RX_D1N
I2C2_SDA_M1 I2C2_SCL_M1
VCC1V8_DOVDD_DVP0
VDD1V2_DVDD_DVP0
VCC2V8_DVP0 VCC2V8_AVDD_DVP0
C4700
12
100nF
X5R 10V C0402
VDD1V2_DVDD_DVP0
C4702
12
10uF
X5R 10V C0603
VCC2V8_AVDD_DVP0
12
C4703 100nF
X5R 10V C0402
VCC2V8_DVP0
Camera MCLK can select the following clock: 1:CAM_CLKOUT0 2:CAM_CLKOUT1 3:CIF_CLKOUT 4:REFCLK_OUT(24MHz)
Attention to the voltage matching
R4701 0R
1 2
B B
VCC1V8_DOVDD_DVP0
12
R4700 51K
DNP
5% R0402
MIPI_CSI_X4_RSTMIPI_CAM0_RST_L_GPIO3_D4
5%
R0402
12
C4708 100nF
X5R 10V C0402
12
C4704
4.7uF
X5R
6.3V C0603
12
C4705 100nF
X5R 10V C0402
Close to FPC Connector
12
C4706 10uF
X5R 10V C0603
12
C4707 100nF
X5R 10V C0402
A A
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Rockchip Confidential
5
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
4
3
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
47.VI-Camera_MIPI_CSI_1x 4Lanes
47.VI-Camera_MIPI_CSI_1x 4Lanes
47.VI-Camera_MIPI_CSI_1x 4Lanes
1
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Sheet: of
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
V1.1
V1.1
V1.1
38 72
38 72
38 72
Page 39
5
4
3
2
1
MIPI_CSI_RX_D0P MIPI_CSI_RX_D0N
MIPI_CSI_RX_D1P MIPI_CSI_RX_D1N
MIPI_CSI_RX_D2P MIPI_CSI_RX_D2N
D D
C C
MIPI_CSI_RX_D3P MIPI_CSI_RX_D3N
MIPI_CSI_RX_CLK0P MIPI_CSI_RX_CLK0N
MIPI_CSI_RX_CLK1P MIPI_CSI_RX_CLK1N
CIF_CLKOUT
REFCLK_OUT
MIPI_CAM0_PDN_L_GPIO3_D5 MIPI_CAM0_RST_L_GPIO3_D4
MIPI_CAM1_RST_L_GPIO3_D2 MIPI_CAM1_PDN_L_GPIO3_D3
I2C2_SDA_M1
I2C2_SCL_M1
I2C3_SCL_M0 I2C3_SDA_M0
C4803
12
DNP
C0402
VCC1V8_DOVDD_DVP0
Camera0:MIPI_CSI_RX 2Lanes
J4800 AXT530124
CNN30M_0R40_V_SMT
MIPI_CSI_RX_D0P MIPI_CSI_RX_D0N
CIF_CLKOUT MIPI_CAM_X2_RST0
MIPI_CAM0_PDN_L_GPIO3_D5
R4800
1 2
1 2
51K
R0402
R4801 0R
R0402
1
GND_1
2
RDP0
3
RDN0
4
GND_4
5
RDP2
6
RDN2
7
GND_7
8
RDP3
9
RDN3
10
GND_10
11
MCLK
12
RESET
13
GND_13
14
PWDN GND_1515GND_16
5%DNP
MIPI_CAM_X2_RST0MIPI_CAM0_RST_L_GPIO3_D4
5%
C4808
12
100nF
X5R 10V C0402
GND_28
GND_25
DOVDD1.8V
GND_23
DVDD1.5V
GND_19
AVDD2.8V
G_3131G_3232G_3333G_34
RDP1 RDN1
SIO_D SIO_C
34
30
RCN
29
RCP
28 27 26 25 24 23 22 21 20 19 18
AF
17 16
Note:
Camera MCLK can select the following clock: 1:CAM_CLKOUT0 2:CAM_CLKOUT1 3:CIF_CLKOUT 4:REFCLK_OUT(24MHz)
MIPI_CSI_RX_CLK0N MIPI_CSI_RX_CLK0P
MIPI_CSI_RX_D1P MIPI_CSI_RX_D1N
I2C2_SDA_M1 I2C2_SCL_M1
VCC1V8_DOVDD_DVP0
VDD1V2_DVDD_DVP0
VCC2V8_DVP0
VCC2V8_AVDD_DVP0
VDD1V2_DVDD_DVP0VCC1V8_DOVDD_DVP0
C4800
12
100nF
X5R 10V C0402
VCC2V8_AVDD_DVP0 VCC2V8_DVP0
12
C4804
4.7uF
X5R
6.3V C0603
12
C4805 100nF
X5R 10V C0402
12
12
C4801 10uF
X5R 10V C0603
C4806 10uF
X5R 10V C0603
Close to FPC Connector
12
12
C4802 100nF
X5R 10V C0402
C4807 100nF
X5R 10V C0402
Attention to the voltage matching
VCC1V8_DOVDD_DVP1
12
Q4800 2SK3018
1
SOT_323
I2C3_SDA_M0 I2C_SDA_MIPI1
B B
I2C2_SDA_M1
I2C3_SCL_M0 I2C_SCL_MIPI1
I2C2_SCL_M1
REFCLK_OUT
3
1 2
VCC1V8_DOVDD_DVP1
3
1 2
1 2
2
1
2
DNP
Q4801 2SK3018
SOT_323
DNP
3.3Vpp
A A
R4802 10K
5% R0402
DNP
R4803
Note:
0R
5%
R0402
If the two camera have the same address, the I2C bus needs to be separated
12
R4804 10K
5% R0402
DNP
R4805 0R
5%
R0402
R4806 100R
R0402
12
5%
R4808 120R
5% R0402
MIPI_CAM_MCLK1
C4816
12
DNP
C0402
Rockchip Confidential
5
Camera1:MIPI_CSI_RX 2Lanes
J4801 AXT530124
MIPI_CSI_RX_D2P MIPI_CSI_RX_D2N
MIPI_CAM_MCLK1 MIPI_CAM_X2_RST1
MIPI_CAM1_PDN_L_GPIO3_D3
VCC1V8_DOVDD_DVP1
4
1 2
1 2
CNN30M_0R40_V_SMT
1
GND_1
2
RDP0
3
RDN0
4
GND_4
5
RDP2
6
RDN2
7
GND_7
8
RDP3
9
RDN3
10
GND_10
11
MCLK
12
RESET
13
GND_13
14
PWDN GND_1515GND_16
G_3131G_3232G_3333G_34
R4807 51K
5%DNP
R0402
R4809 0R
R0402
MIPI_CAM_X2_RST1MIPI_CAM1_RST_L_GPIO3_D2
5%
C4817
12
100nF
X5R 10V C0402
RCN RCP
GND_28
RDP1 RDN1
GND_25
DOVDD1.8V
GND_23
DVDD1.5V
SIO_D SIO_C
GND_19
AVDD2.8V
34
30 29 28 27 26 25 24 23 22 21 20 19 18
AF
17 16
Note:
Camera MCLK can select the following clock: 1:CAM_CLKOUT0 2:CAM_CLKOUT1 3:CIF_CLKOUT 4:REFCLK_OUT(24MHz)
Attention to the voltage matching
3
V1.1
MIPI_CSI_RX_CLK1N MIPI_CSI_RX_CLK1P
MIPI_CSI_RX_D3P MIPI_CSI_RX_D3N
I2C_SDA_MIPI1 I2C_SCL_MIPI1
VCC1V8_DOVDD_DVP1
VDD1V2_DVDD_DVP1
VCC2V8_DVP1 VCC2V8_AVDD_DVP1
2
VDD1V2_DVDD_DVP1VCC1V8_DOVDD_DVP1
C4809
12
100nF
X5R 10V C0402
VCC2V8_AVDD_DVP1 VCC2V8_DVP1
12
C4812
4.7uF
X5R
6.3V C0603
12
C4813 100nF
X5R 10V C0402
12
12
C4810 10uF
X5R 10V C0603
C4814 10uF
X5R 10V C0603
Close to FPC Connector
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
File:
File:
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Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
48.VI-Camera_MIPI_CSI_2x 2Lanes
48.VI-Camera_MIPI_CSI_2x 2Lanes
48.VI-Camera_MIPI_CSI_2x 2Lanes
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Default
Default
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
Default
12
12
1
C4811 100nF
X5R 10V C0402
C4815 100nF
X5R 10V C0402
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
Sheet: of
Sheet: of
39 72
39 72
39 72
Page 40
5
4
3
2
1
MIPI_CSI_RX_D0P MIPI_CSI_RX_D0N
MIPI_CSI_RX_D1P MIPI_CSI_RX_D1N
MIPI_CSI_RX_D2P MIPI_CSI_RX_D2N
MIPI_CSI_RX_D3P MIPI_CSI_RX_D3N
MIPI_CSI_RX_CLK0P
C4902
12
18pF
C0G 50V
C0402
DNP
REFCLK_OUT
VCC3V3_HDMI_RX
12
R4921 10K
R0402 5%
DNP
12
R4922 10K
R0402 5%
MIPI_CSI_RX_CLK0N
HDMIRX_INT_L_GPIO4_C3
HDMIRX_RST_L_GPIO4_D2
I2S3_SCLK_M0 I2S3_LRCK_M0
I2S3_SDI_M0
I2C3_SCL_M0 I2C3_SDA_M0
REFCLK_OUT
HDMIRX_PWREN_H_GPIO0_D6
HDMIRX_DET_L_GPIO3_D0
1
X1
GND2X2
Y4900 24MHz
CRY4_3R20X2R50X0R80
C4904 100pF
RK628D_I2CSEL
I2C address configuration:
I2C_SEL
HDMIRX_RST_L_GPIO4_D2
RK628D_I2CSEL HDMIRX_INT_L_GPIO4_C3
4
GND
3
DNP
C0402
0
VCCIO7
3.3V
VCCIO5
3.3V
VCCIO_ACODEC
3.3V
PMUIO1
3.3V
1.8V
VCCIO6
1.8V
C4901
12
100nF
X5R 10V C0402
C4903
12
18pF
C0G 50V
C0402
DNP
C0G 50V1 2
TP4901 TP_0.7
12
R4919 100R
R0402 5%
I2C_ADDR
7'b1010000
7'b10100011
D D
C C
B B
HDMI1.4 RX
21
G120G2
Utility
Type A
CLKN
CLK_G
CLKP
D0_G
D1_G
D2_G
G322G4
23
U4902E
H4
RESETN_u
C7
GPIO3_B3_d
J3
GPIO3_B4/INT_d
L9
OSC_OUT
M9
OSC_IN
J8
EFUSE_VDD_2V5
H7
GPIO1_A0/TEST_CLKO_d
D7
TEST_d
F7
GND22
G4
GND23
G5
GND24
G6
GND25
G7
GND26
G8
GND27
H6
GND28
RK628D
BGA144_8R00X8R00X1R15
C4912
12
100nF
X5R 10V C0402
VCC5V_HDMIRX_PORT
19
HPD
18
+5V
17
GND
16
SDA
15
SCL
14 13
CEC
12 11 10 9
D0N
8 7
D0P
6
D1N
5 4
D1P
3
D2N
2 1
D2P
J4900 HDMI_TYPE_A
HDMIA19_HDMI_01A
GPIO0_A4/I2S_D0_M0_d GPIO0_A5/I2S_D1_M0_d GPIO0_A6/I2S_D2_M0_d GPIO0_A7/I2S_D3_M0_d
GPIO0_A3/I2S_LRCK_M0_d
GPIO0_A2/I2S_SCK_M0_d
GPIO0_B4/I2C_SCL_u GPIO1_B5/I2C_SDA_u
PLL_AVDD_3V3
PLL_AVDD_1V1
VCC3V3_HDMI_RXVCCA3V3_HDMIRX VDDA1V1_HDMIRX VDD1V1_HDMI_RX
C4913
12
100nF
X5R 10V C0402
C4900 100nF C0402
HDMI_RXCLKN_PORT HDMI_RXCLKP_PORT
HDMI_RX0N_PORT HDMI_RX0P_PORT
HDMI_RX1N_PORT HDMI_RX1P_PORT
HDMI_RX2N_PORT HDMI_RX2P_PORT
K2 H3 H2 H1 J1 J2
L3 K3
M10
J7
H5
VCCIO1
E9
DVDD_1
D8
DVDD_2
A1
GND12
A12
GND13
M1
GND14
M12
GND15
E5
GND16
E6
GND17
E7
GND18
F4
GND19
F5
GND20
F6
GND21
C4914
12
100nF
X5R 10V C0402
X5R 10V1 2
U4900 ESD5344D
SON10_2R50X1R00X0R50
1
IO1
2
IO2 GND3GND
4
IO3
5
IO4
1
IO1
2
IO2 GND3GND
4
IO3
5
IO4
U4901 ESD5344D
SON10_2R50X1R00X0R50
Cj<=0.4pF
I2S3_SDI_M0
I2S3_LRCK_M0 I2S3_SCLK_M0
I2C3_SCL_M0 I2C3_SDA_M0
VCCA3V3_HDMIRX
VDDA1V1_HDMIRX
VCC3V3_HDMI_RX
VDD1V1_HDMI_RX
C4915
12
100nF
X5R 10V C0402
HDMI_RX_HPDOUT_PORT
HDMI_RXDDC_SDA_PORT HDMI_RXDDC_SCL_PORT
NC_10
NC_9
NC_7 NC_6
NC_10
NC_9
NC_7 NC_6
C4916
12
100nF
X5R 10V C0402
9 8 7 6
10 9 8 7 6
12
C4917 1uF
X5R
6.3V C0402
HDMI_RXCLKP_PORT
HDMI_RX0N_PORT HDMI_RX0P_PORT
HDMI_RX1N_PORT HDMI_RX1P_PORT
HDMI_RX2N_PORT HDMI_RX2P_PORT
U4902D
RK628D
BGA144_8R00X8R00X1R15
HDMI RX
HDMI_RX_CEC_PORT HDMIRX_DET_L_GPIO3_D0
HDMI_RXCLKN_PORT
10
12
12
ED4901
ED4900
ESD5341N
ESD5341N
ESD0402
ESD0402
HDMIRX_CLKN HDMIRX_CLKP
GPIO1_B1/HDMIRX_SDA_M0_u GPIO1_B2/HDMIRX_SCL_M0_u GPIO1_B3/HDMIRX_CEC_M0_u GPIO1_B0/HDMIRX_HPD_M0_d
HDMIRX_EXTR
HDMIRX_DVDD_1V1_1 HDMIRX_DVDD_1V1_2
HDMIRX_AVDD_3V3
HDMIRX_D2N HDMIRX_D2P HDMIRX_D1N HDMIRX_D1P HDMIRX_D0N HDMIRX_D0P
GND28 GND29
GND11 GND10
12
12
ED4903
ED4902
ESD5341N
ESD5341N
ESD0402
ESD0402
HDMI_RX2N
H11 H12 J11 J12 K11 K12 L11 L12
L10 M11
M8 L8 K9 K8
G9
H9 J9
J10
H10 K10
R4913 2.2R R04025%1 2
HDMI_RX2P
R4907 2.2R R04025%1 2
HDMI_RX1N
R4905 2.2R R04025%1 2
HDMI_RX1P
R4908 2.2R R04025%1 2
HDMI_RX0N
R4909 2.2R R04025%1 2R4906 22R R04025%DNP1 2
HDMI_RX0P
R4910 2.2R R04025%1 2
HDMI_RXCLKN
R4914 2.2R R04025%1 2
HDMI_RXCLKP
R4911 2.2R R04025%1 2
HDMI_RXDDC_SDA HDMI_RXDDC_SDA_PORT
R4912 22R R04025%1 2
HDMI_RXDDC_SCL
R4915 22R R04025%1 2
HDMI_RX_CEC HDMI_RX_CEC_PORT
R4916 22R R04025%1 2
HDMI_RX_HPDOUT HDMI_RX_HPDOUT_PORT
R4917 22R R04025%1 2
R4918 2K R04021%1 2
C4905
C4906
12
12
1uF
100nF
X5R
X5R
6.3V
10V
C0402
C0402
VCC5V_HDMIRX_PORT
HDMI_RXDDC_SDA_PORT HDMI_RXDDC_SCL_PORT
HDMI_RX_CEC_PORT
C4907
12
12
1uF
X5R
6.3V C0402
C4908 100nF
X5R 10V C0402
12
12
D4900 B5819WS
SOD_323
12
R4901
R4900
10K
10K
R0402
R0402
5%
5%
VCC3V3_HDMI_RX
12
D4901 B5819WS
SOD_323
12
R4904 27K
R0402 5%
HDMI_RX2N_PORT HDMI_RX2P_PORT HDMI_RX1N_PORT HDMI_RX1P_PORT HDMI_RX0N_PORT HDMI_RX0P_PORT HDMI_RXCLKN_PORT HDMI_RXCLKP_PORT
HDMI_RXDDC_SCL_PORT
VDDA1V1_HDMIRX
VCCA3V3_HDMIRX
VCC5V_HDMIRX_PORT
R4902
1 2
10K
5%
R0402
HDMIRX_DET_L--->SOC---->SOC I2C--->RK628D--->HDMI_RX_HPDOUT
HDMIRX_DET_L=Low ---> HDMI_RX_HPDOUT=High
U4902A
GVI/LVDS/MIPI OUT
Support MIPI_CSI_TX
GVI/LVDS/MIPI_TX0P
Port0
GVI/LVDS/MIPI_TX0N GVI/LVDS/MIPI_TX1P GVI/LVDS/MIPI_TX1N GVI/LVDS/MIPI_TX2P GVI/LVDS/MIPI_TX2N GVI/LVDS/MIPI_TX3P GVI/LVDS/MIPI_TX3N GVI/LVDS/MIPI_TX4P GVI/LVDS/MIPI_TX4N
UnSupport MIPI_CSI_TX
GVI/LVDS/MIPI_TX5P
Port1
GVI/LVDS/MIPI_TX5N GVI/LVDS/MIPI_TX6P GVI/LVDS/MIPI_TX6N GVI/LVDS/MIPI_TX7P GVI/LVDS/MIPI_TX7N GVI/LVDS/MIPI_TX8P GVI/LVDS/MIPI_TX8N GVI/LVDS/MIPI_TX9P GVI/LVDS/MIPI_TX9N
GPIO3_B1/GVI_HPD_u
GPIO3_B2/GVI_LOCK_u
GVI/LVDS/MIPI_REXT
GVI/LVDS/MIPI_PLL_AVDD_3V3
GVI/LVDS/MIPI_AVDD_3V3_1 GVI/LVDS/MIPI_AVDD_3V3_2
GVI/LVDS/MIPI_AVDD_1V1_1 GVI/LVDS/MIPI_AVDD_1V1_2 GVI/LVDS/MIPI_AVDD_1V1_3 GVI/LVDS/MIPI_AVDD_1V1_4
RK628D
BGA144_8R00X8R00X1R15
12
GND5 GND4 GND3 GND2 GND1
R4903 51K
R0402 5%
1
G2 G1 F2 F1 E2 E1 D2 D1 C2 C1
A2 B2 A3 B3 A4 B4 A5 B5 A6 B6
A7 B7
B1
C3
D5 E4
D4 E3 C5 F3
C6 D6 C4 G3 D3
Q4900 S8050
SOT_23
2 3
MIPI to SOC
MIPI_CSI_RX_D0P MIPI_CSI_RX_D0N MIPI_CSI_RX_D1P MIPI_CSI_RX_D1N MIPI_CSI_RX_CLK0P MIPI_CSI_RX_CLK0N MIPI_CSI_RX_D2P MIPI_CSI_RX_D2N MIPI_CSI_RX_D3P MIPI_CSI_RX_D3N
R4920 4.02K R04021%1 2
12
12
Description:
LVDS/MIPI/GVI Signal relations hip:
Port MIPI_DSI_TX Mode
Port0
Port1
C4909
C4910
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
C4919
C4918
12
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
Note:
RK3568 is in sleep state. To support the insertion of HDMI RX interrupt wake-up, GPIO needs to be assigned to PMUIO0 or PMUIO1 or PMUIO2 domain
PIN
LVDS Mode GVI Mode MIPI_CSI_TX
G2
LVDS0_D0P
G1
LVDS0_D0N
F2
LVDS0_D1P
F1
LVDS0_D1N
ODD
E2
LVDS0_CLKP
E1
LVDS0_CLKN
D2
LVDS0_D2P
D1
LVDS0_D2N
C2
LVDS0_D3P
C1
LVDS0_D3N
A2
LVDS1_D0P
B2
LVDS1_D0N
A3
LVDS1_D1P
EVEN
B3
LVDS1_D1N
A4
LVDS1_CLKP
B4
LVDS1_CLKN
A5
LVDS1_D2P
B5
LVDS1_D2N
A6
LVDS1_D3P
B6
LVDS1_D3N
C4911
12
1uF
X5R
6.3V C0402
C4920
C4921
12
12
100nF
1uF
X5R
X5R
10V
6.3V
C0402
C0402
Left
Right
VCCA3V3_HDMIRX
VDDA1V1_HDMIRX
DSI0_D0P DSI0_D0N DSI0_D1P DSI0_D1N DSI0_CLKP DSI0_CLKN DSI0_D2P DSI0_D2N DSI0_D3P DSI0_D3N
DSI1_D0P DSI1_D0N DSI1_D1P DSI1_D1N DSI1_CLKP DSI1_CLKN DSI1_D2P DSI1_D2N DSI1_D3P DSI1_D3N
GVI_D0P GVI_D0N GVI_D1P GVI_D1N
GVI_D2P GVI_D2N GVI_D3P GVI_D3N
GVI_D4P GVI_D4N GVI_D5P GVI_D5N
GVI_D6P GVI_D6N GVI_D7P GVI_D7N
CSI0_D0P CSI0_D0N CSI0_D1P CSI0_D1N CSI0_CLKP CSI0_CLKN CSI0_D2P CSI0_D2N CSI0_D3P CSI0_D3N
NC
U4902B
VCC_3V3
R4923 0R
C4923
C4922
12
12
100nF
10uF
X5R
X5R
10V
6.3V
C0402
C0603
A A
HDMIRX_PWREN_H_GPIO0_D6
Rockchip Confidential
R4929 10K
R0402
1 2
5%
5
5%DNP1 2
R0402
12
R4924 100K
R0402 5%
1
12
R4930 51K
R0402 5%
VCC3V3_HDMI_RX VDD1V1_HDMI_RX VDDA1V1_HDMIRXVCC3V3_SYS VCC3V3_HDMI_RX
2 3
Q4901
1
WPM2015-3/TR
SOT_23
12
R4927 10K
R0402 5%
Q4902 S8050
SOT_23
2 3
C4924
12
10uF
X5R
6.3V C0603
HDMI2MIPI single Port 1080P
VCC3V3_HDMI_RX=110mA
VCC1V1_HDMI_RX=175mA
FB4901
1 2
120R-100MHz
L0603
VCCA3V3_HDMIRX
C4925
12
4.7uF
X5R
6.3V C0603
U4903
4
VIN
12
C4926
1 2
10uF
R4925
X5R
10K
10V
R0402
C0603
4
2
GND
1
EN
12
C4931 100nF
X5R 10V C0402
SY8089AAC
/ETA3409A/TCS4201
SOT_23_5
5%
FB/OUT
3
LX
5
ETA3409A/TCS4201:1.0uH/2A SY8089AAAC:2.2uH/2A
L4900
2.2uH
IND_404026
12
C4927 100pF
C0G 50V C0402
FB4900
1 2
120R-100MHz
12
C4928
R4926
12
10uF
100K
X5R
1%
6.3V
R0402
C0603
12
R4928 120K
1% R0402
3
L0603
C4929
12
100nF
X5R 10V
C0402
C4930
12
4.7uF
X5R
6.3V C0603
RGB/BT1120 IN&OUT
RK628D
BGA144_8R00X8R00X1R15
GPIO3_A0/VOP_DEN_u GPIO3_A1/VOP_HSYNC_u GPIO3_A3/VOP_VSYNC_u
GPIO2_B2/VOP_D10_u
GPIO2_B3/VOP_D11_u
GPIO2_B4/VOP_D12_u
GPIO2_B5/VOP_D13_u
GPIO2_B6/VOP_D14_u
GPIO2_B7/VOP_D15_u
GPIO2_C0/VOP_D16_u
GPIO2_C1/VOP_D17_u
GPIO2_C2/VOP_D18_u
GPIO2_C3/VOP_D19_u
GPIO2_C4/VOP_D20_u
GPIO2_C5/VOP_D21_u
GPIO2_C6/VOP_D22_u
GPIO2_C7/VOP_D23_u
2
GPIO2_A0/VOP_D0_u GPIO2_A1/VOP_D1_u GPIO2_A2/VOP_D2_u GPIO2_A3/VOP_D3_u GPIO2_A4/VOP_D4_u GPIO2_A5/VOP_D5_u GPIO2_A6/VOP_D6_u GPIO2_A7/VOP_D7_u GPIO2_B0/VOP_D8_u GPIO2_B1/VOP_D9_u
VOP_DCLK_u
GPIO1_A1_d
VCCIO2_1 VCCIO2_2
A9 B9 A8 B8
G10 G11 G12 F9 F12 F11 F10 E10 E12 E11 D10 D11 C11 D12 C12 B12 B11 A11 C10 B10 A10 D9 C9 C8 H8
E8 F8
U4902C
HDMI OUT
RK628D
BGA144_8R00X8R00X1R15
HDMITX_D2N HDMITX_D2P HDMITX_D1N HDMITX_D1P HDMITX_D0N
HDMITX_D0P HDMITX_CLKN HDMITX_CLKP
GPIO0_B1/HDMITX_SDA_u GPIO0_B2/HDMITX_SCL_u GPIO0_B3/HDMITX_CEC_u GPIO0_B0/HDMITX_HPD_d
HDMITX_EXTR
HDMITX_DVDD_1V1_2 HDMITX_DVDD_1V1_3 HDMITX_DVDD_1V1_1
HDMITX_AVDD_3V3
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
L7 M7 L6 M6 L5 M5 L4 M4
K1 L1 M2 L2
M3
J4 J5 J6
K4
K7
GND9
K6
GND8
K5
GND7
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
49.VI-HDMI1.4 RX(To MIPICSI RX)
49.VI-HDMI1.4 RX(To MIPICSI RX)
49.VI-HDMI1.4 RX(To MIPICSI RX)
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Zhangdz
Zhangdz
Zhangdz
1
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
Sheet: of
Sheet: of
40 72
40 72
40 72
Page 41
5
4
3
2
1
HDMI2.0 TX
HDMI_TX2P_PORT HDMI_TX2N_PORT HDMI_TX1P_PORT
D D
HDMI TX DDC
C C
HDMI_TX1N_PORT HDMI_TX0P_PORT HDMI_TX0N_PORT HDMI_TXCLKP_PORT HDMI_TXCLKN_PORT
HDMITX_SCL
HDMITX_SDA
HDMITX_CEC_M0 HDMI_TX_HPDIN
VCC_3V3
12
R5000 10K
5% R0402
2
VCC_3V3
1
Q5000 2SK3018
SOT_323
3
VCC_5V0
12
12
D5000 B5819WS
SOD_323
R5001
1.8K
5% R0402
HDMI_TX2P_PORT HDMI_TX2N_PORT
HDMI_TX1P_PORT HDMI_TX1N_PORT
HDMI_TX0P_PORT HDMI_TX0N_PORT
HDMI_TXCLKP_PORT HDMI_TXCLKN_PORT
HDMI_TX_CEC_PORT HDMI_TXDDC_SCL_PORT HDMI_TXDDC_SDA_PORT
HDMI_TX_HPD_PORT
HDMI_TXDDC_SCL_PORTHDMITX_SCL
Cj<=0.4pF
U5000 ESD5344D
SON10_2R50X1R00X0R50
1
IO1
2
IO2
3
GND
4
IO3
5
IO4
1
IO1
2
IO2
3
GND
4
IO3
5
IO4
U5001 ESD5344D SON10_2R50X1R00X0R50
12
ED5000 ESD5341N
ESD0402
NC_10
NC_9
GND NC_7 NC_6
NC_10
NC_9
GND NC_7 NC_6
12
ED5001
ESD5341N
ESD0402
10 9 8 7 6
10 9 8 7 6
12
ED5002 ESD5341N
ESD0402
HDMI_TX2P_PORT HDMI_TX2N_PORT
HDMI_TX1P_PORT HDMI_TX1N_PORT
HDMI_TX0P_PORT HDMI_TX0N_PORT
HDMI_TXCLKP_PORT HDMI_TXCLKN_PORT
VCC5V_HDMI_TX
12
ED5003 ESD5341N
ESD0402
12
10 11 12 13 14 15 16 17 18 19
C5000 1uF
X5R 10V
C0402
1 2 3 4 5 6 7 8 9
23
D2P D2_G D2N D1P D1_G D1N D0P D0_G D0N CLKP CLK_G CLKN CEC Utility SCL SDA GND +5V HPD
G322G4
Type A
G120G2
J5000
21
HDMI_TYPE_A
HDMIA19_HDMI_01A
12
R5002
Q5001
10K
2SK3018
1
5%
SOT_323
R0402
12
R5006 27K
5% R0402
2
VCC_5V0
2
B B
VCC_3V3
A A
HDMITX_CEC_M0 HDMI_TX_CEC_PORT
Rockchip Confidential
5
3
1
Q5002 2SK3018
SOT_323
3
12
R5003
1.8K
5% R0402
HDMI_TXDDC_SDA_PORTHDMITX_SDA
VCC_5V0
HDMI TX HPDHDMI TX CEC
HDMI_TX_HPDIN HDMI_TX_HPD_PORT
4
R5005 1K
1 2
3
R0402
5%
12
R5007 100K
5% R0402
2
D5001 B5819W
1 2
R5004 0R
1 2
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
50.VO-HDMI2.0 TX
50.VO-HDMI2.0 TX
50.VO-HDMI2.0 TX
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
Zhangdz
VCC5V_HDMI_TX
SOD_123
5%DNP
R0402
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
Sheet: of
1
V1.1
V1.1
V1.1
41 72
41 72
41 72
Page 42
5
4
3
2
1
1
VDD1
2
VDD2
3
VDD3
4
NC1
5
GND1
6
BIST
7
NC2
8
NC3
9
GND2
10
NC4
11
NC5
12
GND3
13
NC6
14
NC7
15
GND4
16
NC8
17
NC9
18
GND5
19
MIPI_2N
20
MIPI_2P
21
GND6
22
MIPI_1N
23
MIPI_1P
24
GND7
25
MIPI_CLKN
26
MIPI_CLKP
27
GND8
28
MIPI_0N
29
MIPI_0P
30
GND9
31
MIPI_3N
32
MIPI_3P
33
GND10
34
FB1
35
FB2
36
FB3
37
FB4
38
FB5
39
PWM_IN
40
PWM_OUT
41
CABC_EN
42
NC21
43
VLED1
44
VLED2
45
VLED3
GND2546GND26
LCD5200 LTL089CL02-W02
FH26-45S-03SHW
47
1
VDD1
2
VDD2
3
VDD3
4
NC1
5
GND1
6
BIST
7
NC2
8
NC3
9
GND2
10
NC4
11
NC5
12
GND3
13
NC6
14
NC7
15
GND4
16
NC8
17
NC9
18
GND5
19
MIPI_2N
20
MIPI_2P
21
GND6
22
MIPI_1N
23
MIPI_1P
24
GND7
25
MIPI_CLKN
26
MIPI_CLKP
27
GND8
28
MIPI_0N
29
MIPI_0P
30
GND9
31
MIPI_3N
32
MIPI_3P
33
GND10
34
FB1
35
FB2
36
FB3
37
FB4
38
FB5
39
PWM_IN
40
PWM_OUT
41
CABC_EN
42
NC21
43
VLED1
44
VLED2
45
VLED3
2
GND2546GND26
47
LCD5201 LTL089CL02-W02
FH26-45S-03SHW
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
52.VO-LCM_MIPI_DSI_TX0/TX1
52.VO-LCM_MIPI_DSI_TX0/TX1
52.VO-LCM_MIPI_DSI_TX0/TX1
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Zhangdz
Designed by:
Zhangdz
Designed by:
Zhangdz
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
42 72
Sheet: of
42 72
Sheet: of
42 72
1 2
1 2
1 2
1 2
VCC3V3_LCD0
R0402
VCC_LED0_K
R0402
VCC_LED0_A
VCC3V3_LCD1
R0402
VCC_LED1_K
R0402
VCC_LED1_A
5%DNP
5%DNP
5%DNP
5%DNP
MIPI_DSI_TX0_D0P/LVDS_TX0_D0P
Single-MIPI0 LCM
MIPI_DSI_TX0_D0N/LVDS_TX0_D0N
MIPI_DSI_TX0_D1P/LVDS_TX0_D1P MIPI_DSI_TX0_D1N/LVDS_TX0_D1N
MIPI_DSI_TX0_D2P/LVDS_TX0_D2P
D D
C C
B B
A A
MIPI_DSI_TX0_D2N/LVDS_TX0_D2N
MIPI_DSI_TX0_D3P/LVDS_TX0_D3P MIPI_DSI_TX0_D3N/LVDS_TX0_D3N
MIPI_DSI_TX0_CLKP/LVDS_TX0_CLKP MIPI_DSI_TX0_CLKN/LVDS_TX0_CLKN
LCD0_BL_PWM4
MIPI_DSI_TX1_D0P MIPI_DSI_TX1_D0N
MIPI_DSI_TX1_D1P MIPI_DSI_TX1_D1N
MIPI_DSI_TX1_D2P MIPI_DSI_TX1_D2N
MIPI_DSI_TX1_D3P MIPI_DSI_TX1_D3N
MIPI_DSI_TX1_CLKP MIPI_DSI_TX1_CLKN
LCD1_BL_PWM5
VCC5V0_SYS
12
LCD0_BL_PWM4
MIPI0_LCM_PWMOUT
R5201 0R
1 2
R5203 0R
1 2
Single- MIPI1 LCM
VCC5V0_SYS
12
LCD1_BL_PWM5
MIPI1_LCM_PWMOUT
R5208 0R
1 2
R5210 0R
1 2
C5203 10uF
X5R 10V C0603
C5209 10uF
X5R 10V C0603
R0402
R0402
R0402
R0402
L5200
4.7uH
IND_404030
0.06ohm
C5204
12
100nF
X5R 10V C0402
5%
5%DNP
C5210
12
100nF
X5R 10V C0402
5%
5%DNP
12
R5204 100K
5% R0402
12
R5211 100K
5% R0402
U5200 SY7203DBC
DFN10_3R00X3R00X0R80_T
7
IN
LX1 LX2
1
NC1
OVP
3
NC2
NC3 NC4
EN9FB
GND2
11
L5201
4.7uH
IND_404030
0.06ohm
U5201 SY7203DBC
DFN10_3R00X3R00X0R80_T
7
IN
LX1 LX2
1
NC1
OVP
3
NC2
NC3 NC4
EN9FB
GND2
11
D5200 SS34
DO_214AC
1 2
4 5
8 6 10 2
12
Adjust the value of resistance according to used LCD.
D5201 SS34
DO_214AC
1 2
4 5
8 6 10 2
12
Adjust the value of resistance according to used LCD.
R5205 2R
R1206 5%
DNP
R5212 2R
R1206 5%
DNP
VCC3V3_LCD0
VCC_LED0_K
12
R5206
5.1R
5% R1206
VCC3V3_LCD1
VCC_LED1_A
VCC_LED1_K
12
R5213
5.1R
5% R1206
C5200
12
10uF
X5R
6.3V C0603
VCC_LED0_A
C5205
12
2.2uF
X5R 50V C0805
C5206
12
10uF
X5R
6.3V C0603
C5211
12
2.2uF
X5R 50V C0805
C5201
12
10uF
X5R
6.3V C0603
C5207
12
10uF
X5R
6.3V C0603
C5202
12
100nF
X5R 10V C0402
C5208
12
100nF
X5R 10V C0402
VCC3V3_LCD0
LCD0_BL_PWM4 MIPI0_LCM_PWMOUT
VCC3V3_LCD1
LCD1_BL_PWM5 MIPI1_LCM_PWMOUT
R5200 10K
MIPI_DSI_TX0_D2N/LVDS_TX0_D2N MIPI_DSI_TX0_D2P/LVDS_TX0_D2P
MIPI_DSI_TX0_D1N/LVDS_TX0_D1N MIPI_DSI_TX0_D1P/LVDS_TX0_D1P
MIPI_DSI_TX0_CLKN/LVDS_TX0_CLKN MIPI_DSI_TX0_CLKP/LVDS_TX0_CLKP
MIPI_DSI_TX0_D0N/LVDS_TX0_D0N MIPI_DSI_TX0_D0P/LVDS_TX0_D0P
MIPI_DSI_TX0_D3N/LVDS_TX0_D3N MIPI_DSI_TX0_D3P/LVDS_TX0_D3P
R5202 0R
R5207 10K
MIPI_DSI_TX1_D2N MIPI_DSI_TX1_D2P
MIPI_DSI_TX1_D1N MIPI_DSI_TX1_D1P
MIPI_DSI_TX1_CLKN MIPI_DSI_TX1_CLKP
MIPI_DSI_TX1_D0N MIPI_DSI_TX1_D0P
MIPI_DSI_TX1_D3N MIPI_DSI_TX1_D3P
R5209 0R
Rockchip Confidential
5
4
3
Page 43
5
Dual-MIPI LCM
MIPI_DSI_TX0_D0P/LVDS_TX0_D0P MIPI_DSI_TX0_D0N/LVDS_TX0_D0N
D D
C C
MIPI_DSI_TX0_D1P/LVDS_TX0_D1P MIPI_DSI_TX0_D1N/LVDS_TX0_D1N
MIPI_DSI_TX0_D2P/LVDS_TX0_D2P MIPI_DSI_TX0_D2N/LVDS_TX0_D2N
MIPI_DSI_TX0_D3P/LVDS_TX0_D3P MIPI_DSI_TX0_D3N/LVDS_TX0_D3N
MIPI_DSI_TX0_CLKP/LVDS_TX0_CLKP MIPI_DSI_TX0_CLKN/LVDS_TX0_CLKN
MIPI_DSI_TX1_D0P MIPI_DSI_TX1_D0N
MIPI_DSI_TX1_D1P MIPI_DSI_TX1_D1N
MIPI_DSI_TX1_D2P MIPI_DSI_TX1_D2N
MIPI_DSI_TX1_D3P MIPI_DSI_TX1_D3N
MIPI_DSI_TX1_CLKP MIPI_DSI_TX1_CLKN
VCCA1V8_IMAGE
LCD0_BL_PWM4
LCD_EN_H_GPIO3_C6 LCD_RST_L_GPIO3_C7
VCC5V0_SYS
B B
12
LCD0_BL_PWM4
VCCIO6 Default:1.8v
12
C5306 100nF
X5R 10V C0402
C5305 10uF
X5R 10V C0603
L5300
4.7uH
IND_404030
0.06ohm
U5300 SY7203DBC
DFN10_3R00X3R00X0R80_T
7
IN
1
NC1
3
NC2
9
EN
12
R5305 100K
5% R0402
A A
Rockchip Confidential
5
4
R5300 0R
R5301 0R
R5303 0R
4
LX1
5
LX2
8
OVP
6
NC3
10
NC4
2
FB
GND2
11
Adjust the value of resistance according to used LCD.
4
1 2
1 2
1 2
D5300 SS34
DO_214AC
1 2
12
R5306 2R
R1206 5%
DNP
R0402
R0402
R0402
12
5%
R5307
5.1R
5% R1206
VCC3V3_LCD0
C5300
12
10uF
X5R
6.3V C0603
VCC1V8_LCD
C5303
12
4.7uF
X5R
6.3V C0402
5%
12
R5302 DNP
R0402
5%
12
R5304 DNP
R0402
VCC_LED_A
C5307
12
2.2uF
X5R 50V C0805
VCC_LED_K
3
12
C5301 10uF
X5R
6.3V C0603
12
C5302 100nF
X5R 10V C0402
VCC_LED_K
VCC_LED_A
C5304
12
100nF
X5R 10V C0402
LCD_EN_HLCD_EN_H_GPIO3_C6
LCD_RST_LLCD_RST_L_GPIO3_C7
TP5300 TP5301
MIPI_DSI_TX1_D2P MIPI_DSI_TX1_D2N
MIPI_DSI_TX1_D1P MIPI_DSI_TX1_D1N
MIPI_DSI_TX1_CLKP MIPI_DSI_TX1_CLKN
MIPI_DSI_TX1_D0P MIPI_DSI_TX1_D0N
MIPI_DSI_TX1_D3P MIPI_DSI_TX1_D3N
LCD_EN_H
MIPI_PWM_OUT
VCC3V3_LCD0
VCC1V8_LCD
TP5302
LCD_RST_L
MIPI_DSI_TX0_D2P/LVDS_TX0_D2P MIPI_DSI_TX0_D2N/LVDS_TX0_D2N
MIPI_DSI_TX0_D1P/LVDS_TX0_D1P MIPI_DSI_TX0_D1N/LVDS_TX0_D1N
MIPI_DSI_TX0_CLKP/LVDS_TX0_CLKP MIPI_DSI_TX0_CLKN/LVDS_TX0_CLKN
MIPI_DSI_TX0_D0P/LVDS_TX0_D0P MIPI_DSI_TX0_D0N/LVDS_TX0_D0N
MIPI_DSI_TX0_D3P/LVDS_TX0_D3P MIPI_DSI_TX0_D3N/LVDS_TX0_D3N
2
J5300 LCD_DualMIPI-61P
FH36W-61S-03SHW
1
GND1
2
GND2
3
GND3
4
VLED_GND1
5
VLED_GND2
6
VLED_GND3
7
VLED_GND4
8
VLED_GND5
9
VLED_GND6
10
VLED2
11
VLED4
12
NC1
13
GND5
14
PWM
15
TE
16
GND6
17
DSI_R_2P
18
DSI_R_2N
19
GND7
20
DSI_R_1P
21
DSI_R_1N
22
GND8
23
DSI_R_CLKP
24
DSI_R_CLKN
25
GND9
26
DSI_R_0P
27
DSI_R_0N
28
GND10
29
DSI_R_3P
30
DSI_R_3N
31
GND11
32
EN
33
NC6
34
VBAT1
35
VBAT2
36
VBAT3
37
VBAT4
38
NC5
39
VDDIO1
40
VDDIO2
41
GND12
42
DBIST(GND)
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
TE_S GND13 RESET GND14 DSI_L_2P DSI_L_2N GND15 DSI_L_1P DSI_L_1N GND16 DSI_L_CLKP DSI_L_CLKN GND17 DSI_L_0P DSI_L_0N GND18 DSI_L_3P DSI_L_3N GND19
GND53 GND54
LCD_CON : Dual MIPI
A1 A2
1
Left and Right support redistribution
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
3
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
53.VO-LCM_Dual MIPI_DSI TX
53.VO-LCM_Dual MIPI_DSI TX
53.VO-LCM_Dual MIPI_DSI TX
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Default
Default
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
43 72
Sheet: of
43 72
Sheet: of
43 72
Page 44
5
4
3
2
1
Single-LVDS LCM
MIPI_DSI_TX0_D0P/LVDS_TX0_D0P MIPI_DSI_TX0_D0N/LVDS_TX0_D0N
D D
C C
MIPI_DSI_TX0_D1P/LVDS_TX0_D1P MIPI_DSI_TX0_D1N/LVDS_TX0_D1N
MIPI_DSI_TX0_D2P/LVDS_TX0_D2P MIPI_DSI_TX0_D2N/LVDS_TX0_D2N
MIPI_DSI_TX0_D3P/LVDS_TX0_D3P MIPI_DSI_TX0_D3N/LVDS_TX0_D3N
MIPI_DSI_TX0_CLKP/LVDS_TX0_CLKP MIPI_DSI_TX0_CLKN/LVDS_TX0_CLKN
LCD0_BL_PWM4
VCC3V3_LCD0
C5402
12
10uF
X5R
6.3V C0603
12
C5400 10uF
X5R
6.3V C0603
12
C5401 100nF
X5R 10V C0402
LCD0_BL_PWM4 LVDS_LCM_PWMOUT
VCC3V3_LCD0
MIPI_DSI_TX0_D0N/LVDS_TX0_D0N MIPI_DSI_TX0_D0P/LVDS_TX0_D0P
MIPI_DSI_TX0_D1N/LVDS_TX0_D1N MIPI_DSI_TX0_D1P/LVDS_TX0_D1P
MIPI_DSI_TX0_D2N/LVDS_TX0_D2N MIPI_DSI_TX0_D2P/LVDS_TX0_D2P
MIPI_DSI_TX0_CLKN/LVDS_TX0_CLKN MIPI_DSI_TX0_CLKP/LVDS_TX0_CLKP
MIPI_DSI_TX0_D3N/LVDS_TX0_D3N MIPI_DSI_TX0_D3P/LVDS_TX0_D3P
R5400 0R
1 2
R0402
5%DNP
VCC_LED_K
L5400
VCC5V0_SYS
B B
R0402
R0402
12
5%
5%DNP
C5404 100nF
X5R 10V C0402
12
R5403 100K
5% R0402
C5403
12
10uF
X5R 10V C0603
LCD0_BL_PWM4
LVDS_LCM_PWMOUT
A A
R5401 0R
1 2
R5402 0R
1 2
4.7uH
IND_404030
0.06ohm
U5400 SY7203DBC
DFN10_3R00X3R00X0R80_T
7
IN
1
NC1
3
NC2
9
EN
LX1 LX2
OVP NC3 NC4
4 5
8 6 10 2
FB
GND2
11
D5400 SS34
DO_214AC
1 2
VCC_LED_A
12
VCC_LED_K
R5404 2R
R1206 5%
DNP
12
R5405
5.1R
5% R1206
12
Adjust the value of resistance according to used LCD.
C5405
2.2uF
X5R 50V C0805
VCC_LED_A
Rockchip Confidential
5
4
3
2
LCD5400 B101EW04
FPC40-0R5A
1
NC1
2
AVDD1
3
AVDD2
4
NC2
5
I2C_CLK_EDID
6
I2C_SDA_EDID
7
NC3
8
RIN0-
9
RIN0+
10
GND1
11
RIN1-
12
RIN1+
13
GND2
14
RIN2-
15
RIN2+
16
GND3
17
CLKIN-
18
CLKIN+
19
GND4
20
RIN3-
21
RIN3+
22
GND5
23
NC4
24
NC5
25
GND6
26
NC6
27
Color_EN
28
CABC_EN
29
LED_PWM(I)
30
LED_PWM(O)
31
NC7
32
VLED_GND1
33
VLED_GND2
34
VLED_GND3
35
VLED_GND4
36
VLED_GND5
37
VLED_GND6
38
NC8
39
VLED1
40
VLED2
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
54.VO-LCM_LVDS TX
54.VO-LCM_LVDS TX
54.VO-LCM_LVDS TX
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Default
Default
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
44 72
Sheet: of
44 72
Sheet: of
44 72
Page 45
5
4
3
2
1
Single-eDP LCM
Note:
For EDP displays with edp1.2a or above,
EDP_TX_D0P EDP_TX_D0N
EDP_TX_D1P
D D
EDP_TX_D1N
EDP_TX_D2P EDP_TX_D2N
EDP_TX_D3P EDP_TX_D3N
EDP_TX_AUXP EDP_TX_AUXN
LCD0_BL_PWM4
C C
VCC3V3_LCD0
C5600
12
10uF
X5R
6.3V C0603
12
C5602 100nF
X5R 10V C0402
C0402
C5601
12
10uF
X5R
6.3V C0603
C5603 100nF
1 2
VCC3V3_LCD0
X5R 10V
12
R5601 100K
DNP
5% R0402
VCC_LED_K
VCC_LED_A
J5600 eDP_Flex
52
AJ752-B-S-51
1
GND_1
3
GND_2
5
VIN_2
7
EDPTX_AUXP EDPTX_AUXN
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
9
VIN_4 AUX_P GND_3 NC_1 GND_4 NC_2 GND_5 NC_3 GND_6 NC_4 GND_7 GND_8 LEDC5B LEDC3B LEDC1B LEDC6A LEDC4A LEDC2A GND_9 LEDA2_1 NC_6 LEDA1_1 GND_10
PAD_2
GND_11
LANE0_N LANE0_P LANE1_N LANE1_P LANE2_N LANE2_P LANE3_N LANE3_P
GND_12 LEDC6B LEDC4B LEDC2B GND_13 LEDC5A LEDC3A LEDC1A
LEDA2_2 LEDA1_2
HPD VIN_1 VIN_3
AUX_N
NC_5
NC_7
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
TP5600
VCC3V3_LCD0
EDP_TX_D0N EDP_TX_D0P EDP_TX_D1N EDP_TX_D1P EDP_TX_D2N EDP_TX_D2P EDP_TX_D3N EDP_TX_D3P
VCC_LED_K
VCC_LED_A
PAD_1
53
the bias resistors R5600 and R5601 of aux are not mounted.
VCC3V3_LCD0
12
R5600 100K
DNP
5% R0402
C5604 100nF
1 2
C0402
X5R 10V
EDP_TX_AUXNEDP_TX_AUXP
L5600
B B
VCC5V0_SYS
C5605
12
10uF
X5R 10V C0603
12
C5606 100nF
X5R 10V C0402
LCD0_BL_PWM4
12
R5602 100K
A A
5% R0402
4.7uH
IND_404030
0.06ohm
U5600 SY7203DBC
DFN10_3R00X3R00X0R80_T
7
IN
1
NC1
3
NC2
9
EN
LX1 LX2
OVP NC3 NC4
4 5
8 6 10 2
FB
GND2
11
Rockchip Confidential
5
4
3
D5600 SS34
DO_214AC
1 2
VCC_LED_A
12
VCC_LED_K
12
Adjust the value of resistance according to used LCD.
R5603 2R
R1206 5%
DNP
12
R5604
5.1R
5% R1206
C5607
2.2uF
X5R 50V C0805
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
56.VO-LCM_eDP TX
56.VO-LCM_eDP TX
56.VO-LCM_eDP TX
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Default
Default
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
45 72
Sheet: of
45 72
Sheet: of
45 72
Page 46
5
4
3
2
1
Touch Panel connector
I2C1_SCL_TP I2C1_SDA_TP TP_INT_L_GPIO0_B5
D D
TP_RST_L_GPIO0_B6
I2C1_SDA_TP I2C1_SCL_TP TP_RST_L_GPIO0_B6 TP_INT_L_GPIO0_B5
R5800 22R R04025%
1 2
R5801 22R R04025%
1 2
R5802 22R R04025%
1 2
R5803 22R R04025%
1 2
I2C_SDA_TP I2C_SCL_TP TP_RST TP_INT
VCC3V3_TP
C C
13
GND13
1
GND1
2
NC2
3
NC3
4
NC4
5
NC5
6
GND6
7
SDA
8
SCL
9
/SD
10
INT
11
VDD11
12
VDD12
GND14
J5800 Touch_screen
FPC12P_05MM
I2C_SDA_TP
I2C_SCL_TP
TP_RST
TP_INT
ED5800 ESD5341N
1 2
ED5801 ESD5341N
1 2
ED5802 ESD5341N
1 2
ED5803 ESD5341N
1 2
ESD0402
ESD0402
ESD0402
ESD0402
14
VCC3V3_TPVCC3V3_PMU
R5804 0R
1 2
VCC_3V3
B B
A A
R5805 0R
1 2
Rockchip Confidential
5
4
R0402
R0402
5%
C5800
12
4.7uF
5%DNP
6.3V X5R C0402
12
C5801 100nF
C0402 X5R 10V
Rockchip Electronics Co., Ltd
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Rockchip Electronics Co., Ltd
Project:
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2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
58.TP Connector_COF
58.TP Connector_COF
58.TP Connector_COF
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Default
Default
Zhangdz
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Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
46 72
Sheet: of
46 72
Sheet: of
46 72
Page 47
5
VGA OUT
Default:RTD2166
CH7517,IT6516:Can also support
EDP_TX_D0P EDP_TX_D0N
EDP_TX_D1P EDP_TX_D1N
EDP_TX_AUXP
D D
EDP_TX_AUXN
VGA_HPDIN_GPIO0_C0
VGA_PWREN_H_GPIO0_D5
I2C5_SCL_M0
I2C5_SDA_M0
PMUIO2
3.3V
1.8V
EDP_TX_AUXP EDP_TX_AUXN
EDP_TX_D0P EDP_TX_D0N EDP_TX_D1P EDP_TX_D1N
I2C5_SDA_M0 I2C5_SCL_M0
VGA_HPDIN_GPIO0_C0
R5903 0R R5904 0R
C5906 100nF
1 2
C5908 100nF
1 2
1 2 1 2
Power Sequence:
5v-->3.3v-->1.2v
C C
VCC_5V0
2 3
1
12
R5919 10K
R0402 5%
Q5901 S8050
SOT_23
2 3
Q5902 WPM2015-3/TR
1
SOT_23
12
R5924 10K
5% R0402
Q5903 S8050
SOT_23
2 3
R04025%DNP
Q5900 WPM2015-3/TR
SOT_23
R04025%DNP
VCC5V0_VGA
12
VCC3V3_VGA
12
C5924 10uF
X5R 10V C0603
C5917
4.7uF
X5R 10V C0603
R5913 0R
C5916
12
100nF
X5R 10V
C0402
1 2
R5922 0R
C5923
12
100nF
X5R 10V
C0402
12
1 2
12
R5917 100K
R0402 5%
1
12
R5921 51K
R0402 5%
1 2
12
R5923 100K
5% R0402
1
R5926 51K
5% R0402
2 3
VCC5V0_SYS
C5915
12
10uF
X5R 10V C0603
VGA_PWREN_H_GPIO0_D5
B B
VGA_PWREN_H_GPIO0_D5
A A
VCC3V3_SYS
12
C5922 10uF
X5R 10V C0603
R5925 10K
R0402
R5920 10K
R0402
5%
VCC_3V3
1 2
5%
Rockchip Confidential
5
4
TP5900 TP_0.7
VCCA3V3_RTD
C0402X5R 10V C0402X5R 10V
VDD1V2_RTD_VCCK
VDD1V2_RTD_VCCK
550mW
FB5903
1 2
120R-100MHz
L0603
FB5905
1 2
120R-100MHz
L0603
4
TP5901 TP_0.7
R04025%DNP R04025%DNP
12
DP_TX_AUXP DP_TX_AUXN
C5913 100nF
X5R 10V C0402
R5902
4.7K
5% R0402
SMB_SDA SMB_SCL
30
31
32
HPD
EXT1.2V_CTRL
POL29POL1/SPI_CEB10GPI1/SPI_CLK11GPI2/SPI_SI12GPI3/SPI_SO13VCC_3314VGA_SCL15VGA_SDA
VCC3V3_VGA
12
26
27
28
SMB_SDA29SMB_SCL
LDO_RSTB
EXT_CLK_IN
VCC3V3_VGA
3
C5900
12
100nF
X5R 10V C0402
VCCK_1225PVCC_33
GREEN_P
BLUE_P
VDD_DAC_33
HVSYNC_PWR
16
12
21
D5909 BAV99
SOT_23
RED_P
HSYNC VSYNC
33
VGA_SDA
VGA_SCL
C5920 100nF
X5R 10V C0402
VCC3V3_VGA
12
12
R5901
R5900
4.7K
4.7K
5%
5%
R0402
R0402
DNP
DNP
12
R5906 100K
5% R0402
U5900
DNP
1
AVCC_33
2
AUX_P
3
AUX_N
4
AVCC_12
5
LANE0_P
6
LANE0_N
7
LANE1_P
8
LANE1_N
VCC3V3_VGA
12
R5911
4.7K
5% R0402
12
R5916
4.7K
5% R0402
TP5902TP_0.7 TP5903TP_0.7 TP5904TP_0.7
VCC5V0_VGA VCC5V0_VGA VCC5V0_VGA
21
D5908 BAV99
3
SOT_23
BAT54S
VCCA3V3_RTD_DAC
C5925
4.7uF
X5R
6.3V C0603
C5928
4.7uF
X5R
6.3V C0603
C5926
12
100nF
X5R 10V C0402
C5929
12
100nF
X5R 10V C0402
12
VCCA3V3_RTD
12
3
VDD1V2_RTD_VCCK
C5901
12
4.7uF
X5R
6.3V C0603
24
GND
23 22 21 20 19 18 17
12
EPAD
RTD2166
QFN32_4R00X4R00X0R90_T
R5914 47R
R5915 47R
VGA_B_CONVGA_G_CONVGA_R_CON
3
C5902
12
100nF
X5R 10V C0402
VGA_R VGA_G VGA_B
VGA_HSYNC VGA_VSYNC
C5909
C5910
12
100nF
4.7uF
X5R
X5R
10V
10V
C0402
C0603
1 2
1 2
3
R0402
R0402
21
D5910 BAV99
SOT_23
D5911 B5819W
1 2
12
5%
5%
12
16
SOD_123
VCCA3V3_RTD_DAC
12
D5902 B5819WS
SOD_323
12
R5910
R5909
2.2K
2.2K
5%
5%
R0402
R0402
C5919
C5918
12
18pF
18pF
C0G
C0G
50V
50V
C0402
C0402
DNP
DNP
G16
VCC5V0_VGA_CONVCC5V0_VGA
VCC5V0_VGA
VGA_DDC_SDA
VGA_DDC_SCL
12
12
C5930 1uF
X5R 10V C0402
D5905 ESD5341N
ESD0402
5
15
VGA_DDC_SCL
2
1
BLM18BB220SN1D
12
12
12
1 2
1 2
G6
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FB5900
1 2
26R-100M
L0603
C5903 2pF
C0G 50V
C0402
FB5901
1 2
26R-100M
L0603
C5905 2pF
C0G 50V
C0402
FB5902
1 2
26R-100M
L0603
C5911 2pF
C0G 50V
C0402
5%
R0402
5%
R0402
G17
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
59.VO-VGA Output(eDP To VGA)
59.VO-VGA Output(eDP To VGA)
59.VO-VGA Output(eDP To VGA)
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
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C5904
12
2pF
C0G 50V
C0402
C5907
12
2pF
C0G 50V
C0402
C5912
12
2pF
C0G 50V
C0402
VGA_HSYNC_CON
C5914
12
2pF
C0G 50V
C0402
C5921
12
2pF
C0G 50V
C0402
J5900 VGA_DB15
DSUB15B
VGA_CHASSIS_GNDVGA_CHASSIS_GND
17
C5927
12
100nF
X5R 50V C0603
Rockchip Electronics Co., Ltd
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Rockchip Electronics Co., Ltd
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Default
Default
Default
1
12
D5900 ESD5341N
ESD0402
12
D5901 ESD5341N
ESD0402
12
D5903 ESD5341N
ESD0402
12
D5904 ESD5341N
ESD0402
12
D5907 ESD5341N
ESD0402
12
FB5904 120R-100MHz
25% 2A L0603
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
47 72
Sheet: of
47 72
Sheet: of
47 72
VGA_R VGA_R_CON
12
R5905 75R
1% R0402
VGA_G VGA_G_CON
12
R5907 75R
1% R0402
VGA_B VGA_B_CON
12
R5908 75R
1% R0402
VGA_HSYNC
R5912 47R
12
D5906 ESD5341N
ESD0402
4
G5
ID1
G10
VS
SCL
10
14
VGA_VSYNC_CON
2
VGA_VSYNC VGA_VSYNC_CON
R5918 47R
VGA_B_CON
VGA_G_CON
VGA_R_CON
1
2
3
B
NC
HS
8
9
13
VGA_HSYNC_CON
12
C5931 100nF
X5R 10V C0402
R
G
G7
G8
ID0
SDA
6
7
11
12
VGA_DDC_SDA
Page 48
5
SDIO WIFI/BT MODULE
SDMMC1_D0 SDMMC1_D1 SDMMC1_D2 SDMMC1_D3
SDMMC1_CMD
SDMMC1_CLK
WIFI_REG_ON_H_GPIO2_B1
VCC3V3_SYS
12
C6008 1uF
X5R 10V C0402
DNP
WIFI_WAKE_HOST_H_GPIO2_B2
UART1_RX_M0 UART1_TX_M0 UART1_RTSn_M0 UART1_CTSn_M0
BT_REG_ON_H_GPIO2_B7 BT_WAKE_HOST_H_GPIO2_C0 HOST_WAKE_BT_H_GPIO2_C1
SOC_PCM_CLK SOC_PCM_SYNC SOC_PCM_OUT SOC_PCM_IN
CLK32K_OUT1_WIFI
RK809_32KOUT_WIFI
RTCIC_32KOUT
WIFI_PWREN_L_GPIO0_C1
C6009
12
100nF
X5R 10V
C0402
DNP
WIFI_PWREN_L_GPIO0_C1
D D
C C
And Giga PHY0 Option Close to Module
5%DNP
VCCIO_WL
R6000 10K
1 2
R6005 10K
1 2
R0402
R0402
5%DNP
SDMMC1_D0
SDMMC1_D1
SDMMC1_D2
SDMMC1_D3
SDMMC1_CMD
Note:
If ultra low standby power consumption is required, please contact RK to reallocate GPIO and Power
VCCIO_WL
C6006 22uF
X5R
6.3V C0603
5%DNP
R0402
5%
R0402
12
Note:
The maximum peak current is 600mA
C6007
12
Close to WIFI module
100nF
X5R 10V C0402
VCC_3V3
VCC_1V8
If a board needs to be compatible with two voltage choices, recommended to enable BOM_ID
R6011 0R
1 2
2 3
12
R6012 100K
5% R0402
DNP
1
12
R6014 10K
5% R0402
DNP
Q6000 WPM2026-3/TR
SOT_23
DNP
R6008 0R
1 2
R6009 0R
1 2
VBAT_WL_1T1R
5%
R0603
12
For RTL8821CS
B B
Yes
WIFI
acb/g/n
5GHz
YesYes
Yes
No
No
YesYes
Yes
BT
4.2
4.2/4.0
5.0/4.2
No 1.8-3.3V NoNo No NoYes No No
Yes No
No
NoYes
No
4.0
4.2
YesYes 4.2Yes Yes Module
Yes
OPTION
a
AW-CM256SM Yes
AP6236/AP6212 1.71-3.6V
AP6256/AP6255
RTL8189ETV Module F89FTSM12-W3
RTL8723BS Module F23BDSM23-W2
A A
Module 6223A-SRD
QCA9377 Module 8223A-SR
RTL8821CS Module 6221A-SRC
No
Yes
No
Yes Yes Yes 4.2 Module
Rockchip Confidential
5
4
5%
R6001 0R
1 2
R6002 0R
1 2
R6003 0R
1 2
R6004 0R
1 2
R6006 0R
1 2
R0402
R0402
R0402
R0402
R0402
5%
5%
5%
5%
WIFI1T1R_D0
WIFI1T1R_D1
WIFI1T1R_D2
WIFI1T1R_D3
WIFI1T1R_CMD
Note:
According to the actual choice of mounted Cannot be mounted at the same time
C6005
Please choose IO voltage values
1uF
according to the real mounted module
X5R 10V
and modify the corresponding
C0402
software configuration.
VCCIO_WL
RK809_32KOUT_WIFI
RTCIC_32KOUT
CLK32K_OUT1_WIFI
Note:
If an external RTC IC is required, it is recommended to use the output of the RTC IC
Crystals
37.4MHz
R6016 0R
1 2
R6017 0R
1 2
R6018 0R
1 2
VDDIO
1.71-3.6V
26MHz
37.4MHz
Module Integrated
Module Integrated
Module Integrated
Integrated
Integrated
4
1.71-3.6V
1.62-3.6V
1.62-3.6VRTL8723DS
1.7-3.45V No No No
1.7-3.45V No No No No
5%
R0402
5%DNP
R0402
5%DNP
R0402
Option1
Yes Yes
Yes Yes
Yes Yes
No
No
Note: Adjusted the load capacitance according to the crystal specification.
C6001 22pF
C0402
C6004 22pF
C0402
Option1
Using RTL8189ETV/FTV modules please notice WIFI REG ON is on pin12 or pin34, choose according to the actual condition.
WIFI_REG_ON_H_GPIO2_B1
Option4
12
R6015 10K
5% R0402
WIFIBT_32KIN_1T1R
12
12
C6012
R6019
DNP
DNP
C0402
R0402
Option2 Option3
Yes@SDIO2.0 No@SDIO3.0
Yes@SDIO2.0 No@SDIO3.0
No No
No NoNo
3
C0G 50V
C0G 50V
No
3
12
CRY4_3R20X2R50X0R80
12
VCCIO_WL
12
Y6000
3
GND
X2
4
X1
GND
37.4MHz
R6010 0R
WIFI_WAKE_HOST_H_GPIO2_B2 WIFI1T1R_D2 WIFI1T1R_D3 WIFI1T1R_CMD SDMMC1_CLK WIFI1T1R_D0 WIFI1T1R_D1
C6010 1uF
X5R 10V C0402
C6011
12
100nF
X5R 10V C0402
Option4
Yes
Yes
Yes
No
No
No
Yes
2
WIFI1T1R_XTAL_IN
2
R6007 0R
1
±10ppm
1 2
R0402
1 2
5%
R0402
12 13 14 15 16 17 18 19 20 21 22
5%
U6000
WIFI1T1R_XTAL_OUT
WL_REG_ON WL_HOST_WAKE SDIO_DATA_2 SDIO_DATA_3 SDIO_DATA_CMD SDIO_DATA_CLK SDIO_DATA_0 SDIO_DATA_1 GND3 VIN_LDO_OUT VDDIO
Option2
L6000
4.7uH
IND_303012
1A_DCR<=80mohm
C6013
12
4.7uF
VCCIO_WL
12
10V X5R C0603
R6021
4.7K
5% R0402
DNP
SOC_PCM_IN
WIFIBT_32KIN_1T1R SOC_PCM_IN SOC_PCM_CLK SOC_PCM_OUT SOC_PCM_SYNC
For RTL8723DS
Note: Yes: option circuit be mounted No: option circuit not be mounted
2
50 Ohm RF trace
VBAT_WL_1T1R
8
9
10
11
VBAT
XTAL_IN
XTAL_OUT
AP6256 MODULE
MD44_AP6XXX
LPO
VIN_LDO
24
23
BT_WAKE_HOST_H_GPIO2_C0
HOST_WAKE_BT_H_GPIO2_C1
6
7
BT_HOST_WAKE
BT_VIO/N_HOST_WAKE
PCM_OUT25PCM_CLK26PCM_IN27PCM_SYNC
C6000
12
C6002 DNP
C0402
2
1
4
5
GND23GND1
FM_RX
N_WAKE
BT_WAKE
WL_BT_ANT
TCXO_IN
GND533GND4
GPS_RF
VDD_TCXO
30
31
28
32
29
12
R6020 0R
5% R0402
DNP
Option3
BT_REG_ON_H_GPIO2_B7
WIFI_REG_ON_H_GPIO2_B1
Using RTL8189ET V/FTV modules,please notice WIFI REG ON is on pin12 or pin 34, choose according to th e actual condit ion.
10pF
C0402
1 2
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12
C6003 DNP
C0402
N_VDDSWP_IN
N_VDDSWP_OUT
N_VDDSWPIO
UART_CTS_N
UART_RXD UART_TXD
UART_RTS_N
TX1 TX2
N_REG_PU
N_I2C_SCL
GND6
N_I2C_SDA
BT_RST_N
R6022 0R
1 2
DNP
R6023 0R
1 2
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
60.WIFI/BT-SDMMC1_1T1R + UART
60.WIFI/BT-SDMMC1_1T1R + UART
60.WIFI/BT-SDMMC1_1T1R + UART
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Reviewed by:
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Zhangdz
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Zhangdz
1
ANT6000
1
ANT
ANT_JACK
ANT_JACK
2
GND1
3
GND2
47 46 45
UART1_RTSn_M0
44
UART1_TX_M0
43
UART1_RX_M0
42
UART1_CTSn_M0
41 40 39 38 37 36 35 34
12
R6013 10K
5% R0402
DNP
For RTL8723DS
5%
R0402
5%
R0402
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
Sheet: of
Sheet: of
Default
Default
Default
1
48 72
48 72
48 72
Page 49
5
SDIO WIFI/BT MODULE-2T2R
SDMMC1_D0 SDMMC1_D1 SDMMC1_D2 SDMMC1_D3
SDMMC1_CMD
SDMMC1_CLK
D D
C C
WIFI_REG_ON_H_GPIO2_B1 WIFI_WAKE_HOST_H_GPIO2_B2
UART1_RX_M0 UART1_TX_M0 UART1_RTSn_M0 UART1_CTSn_M0
BT_REG_ON_H_GPIO2_B7 BT_WAKE_HOST_H_GPIO2_C0 HOST_WAKE_BT_H_GPIO2_C1
SOC_PCM_CLK SOC_PCM_SYNC SOC_PCM_OUT SOC_PCM_IN
CLK32K_OUT1_WIFI
RK809_32KOUT_WIFI
RTCIC_32KOUT
WIFI_PWREN_L_GPIO0_C1
And Giga PHY0 Option Close to Module
R6200 10K
VCCIO_WL
1 2
R6205 10K
1 2
Note:
If ultra low standby power consumption is required, please contact RK to reallocate GPIO and Power
VCCIO_WL
VCC_3V3
VCC_1V8
R6211 0R
1 2
R6213 0R
1 2
R0402
R0402
5%DNP
5%
12
Note:
B B
According to the actual choice of mounted Cannot be mounted at the same time
Please choose IO voltage values according to the real mounted module and modify the corresponding software configuration.
If a board needs to be compatible with two voltage choices, recommended to enable BOM_ID
C6212 1uF
X5R 10V C0402
R0402
R0402
4
5%DNP
SDMMC1_D0
SDMMC1_D1
SDMMC1_D2
SDMMC1_D3
5%DNP
SDMMC1_CMD
VCCIO_WL
12
R6212 10K
5% R0402
12
R6214 10K
5% R0402
DNP
For AP6398S
5%
R6201 0R
1 2
R6202 0R
1 2
R6203 0R
1 2
R6204 0R
1 2
R6206 0R
1 2
Note: Adjusted the load capacitance according to the crystal specification.
C6209 22pF
C0402
C6210 22pF
C0402
Option1
SDIO voltage select: 0: 3.3V 1:1.8V
R0402
R0402
R0402
R0402
R0402
12
C0G 50V
12
C0G 50V
WIFI2T2R_D0
5%
WIFI2T2R_D1
5%
WIFI2T2R_D2
5%
WIFI2T2R_D3
5%
WIFI2T2R_CMD
Y6200
3
GND
X2
4
X1
GND
37.4MHz
CRY4_3R20X2R50X0R80
Note:
If an external RTC IC is required, it is recommended to use the output of the RTC IC
R6219 0R
RTCIC_32KOUT
CLK32K_OUT1_WIFI
1 2
R6220 0R
1 2
R6221 0R
1 2
3
R6207 0R
1 2
2
1
WIFI_REG_ON_H_GPIO2_B1 WIFI_WAKE_HOST_H_GPIO2_B2 WIFI2T2R_CMD SDMMC1_CLK WIFI2T2R_D3 WIFI2T2R_D2 WIFI2T2R_D0 WIFI2T2R_D1
SDIO_VSEL
VCCIO_WL
12
R6217 10K
5% R0402
5%
R0402
5%DNP
R0402
5%DNP
R0402
5%
R0402
L6200
4.7uH
IND_303012
1A_DCR<=80mohm
Option2
ANT1GND12GND2
1 2
C6203
12
10pF
C0G 50V C0402
1 2
3
ANT6200 ANT_JACK
ANT_JACK
C6200 DNP
C0402
C6206 DNP
C0402
2
ANT1GND12GND2
ANT6201 ANT_JACK
3
ANT_JACK
C6201 DNP
1 2
C0402
C6204
12
10pF
C0G 50V C0402
C6207 DNP
1 2
C0402
ANT1GND12GND2
1 2
12
1 2
C6205 10pF
C0G 50V C0402
DNP
1
3
ANT6202 ANT_JACK
ANT_JACK
DNP
C6202 DNP
C0402
C6208 DNP
C0402
For AP6398SR3
50 Ohm RF trace
2
8
9
U6200
12
NC/NC/PCIE_PREST_L
13
XTAL_OUT
14
XTAL_IN
15
WL_REG_ON
16
WL_HOST_WAKE
17
SDIO_DATA_CMD
18
SDIO_DATA_CLK
19
SDIO_DATA_3
20
SDIO_DATA_2
21
SDIO_DATA_0/HUSB_DP
22
SDIO_DATA_1/HUSB_DM
23
GND_10
24
NC/SDIO_VSEL/PCIE_PME_L
25
VIN_LDO
C6211
12
4.7uF
10V X5R C0603
SOC_PCM_SYNC SOC_PCM_OUT SOC_PCM_IN SOC_PCM_CLK
WIFIBT_32KIN_2T2RRK809_32KOUT_WIFI
11
GND_7
GND_810GND_9
WL_ANT1
AP6398S
MD50_AP6XXX_13RX15RX1R5
VIN_LDO_OUT26PCM_SYNC27PCM_IN
PCM_OUT
28
29
12
R6222 DNP
R0402
1
5
7
GND_23GND_1
GND_34GND_4
GND_56GND_6
WL/BT_ANT0
GPIO8_9/NC_BT_ANT/NC
GPIO4/NC/PCIE_TDN
GPIO5/WL_UART_RX/PCIE_RDP
NC/WL_UART_TX/PCIE_RDN
NC/NC/PCIE_CLKREQ_L
NC/NC/PCIE_REFCLK_P
PCM_CLK
30
VBAT
NC/NC/PCIE_REFCLK_N33LPO
VDDIO
GND_11
35
36
31
34
32
VCCIO_WL
C6215
12
100nF
X5R 10V C0402
12
C6218 DNP
C0402
BT_HOST_WAKE
BT_WAKE
NC/GND/PCIE_TDP
UART_CTS_N UART_RTS_N
UART_RXD UART_TXD
GND_12
BT_REG_ON
C6216
12
100nF
X5R 10V C0402
50 49 48 47 46 45 44 43 42 41 40 39 38 37
VBAT_WL_2T2R
C6217
12
22uF
X5R
6.3V C0603
BT_WAKE_HOST_H_GPIO2_C0 HOST_WAKE_BT_H_GPIO2_C1
R6208 0R
1 2
Only AP6398S
UART1_RTSn_M0 BT_UART_CTSN UART1_TX_M0 UART1_RX_M0
BT_REG_ON_H_GPIO2_B7
R6209 0R
R6215 0R
1 2
23
Q6200 WPM2026-3/TR
1
SOT_23
DNP
12
R6218 10K
5% R0402
DNP
WIFI_PWREN_L_GPIO0_C1
R0402
1 2
5%
5%
UART1_CTSn_M0
R0402
12
R6210 10K
5% R0402
DNP
VCC3V3_SYS
5%
R0603
12
C6213
12
100nF
X5R 10V
C0402
DNP
R6216 100K
5% R0402
DNP
C6214
12
1uF
X5R 10V C0402
DNP
Option3
Yes
WIFI
acb/g/n
5GHz
5.0
4.1
YesYes
Yes Module
4.1
BT
Crystals
37.4MHz
VDDIO
1.71-3.6V Yes YesYesYes Yes
37.4MHz
Integrated
4
1.71-3.6VRTL8822BS
Option1
Option2 Option3
Yes Yes
No No No
3
Yes
Yes
Note: Yes: option circuit be mounted No: option circuit not be mounted
2
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
62.WIFI/BT-SDMMC1_2T2R + UART
62.WIFI/BT-SDMMC1_2T2R + UART
62.WIFI/BT-SDMMC1_2T2R + UART
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Designed by:
Designed by:
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
49 72
Sheet: of
49 72
Sheet: of
Default
Default
Default
1
49 72
OPTION
A A
AP6398S Yes
AP6356S 1.71-3.6V
Module
a
Yes Yes Yes
Yes
Rockchip Confidential
5
Page 50
5
4
3
2
1
PCIe WIFI6/BT MODULE-2T2R
C6400 DNP
C0402
C6404 DNP
C0402
V1.1
ANT6400 ANT_JACK
ANT_JACK
WIFI_REG_ON_H_GPIO2_B1 WIFI_WAKE_HOST_H_GPIO2_B2
UART1_RX_M0 UART1_TX_M0 UART1_RTSn_M0
D D
C C
PCIE20_CLKREQn_M1 PCIE20_CLKREQn_1V8
B B
PCIE20_WAKEn_M1 PCIE20_WAKEn_1V8
PCIE20_PERSTn_M1
A A
UART1_CTSn_M0
BT_REG_ON_H_GPIO2_B7 BT_WAKE_HOST_H_GPIO2_C0 HOST_WAKE_BT_H_GPIO2_C1
SOC_PCM_CLK SOC_PCM_SYNC SOC_PCM_OUT SOC_PCM_IN
CLK32K_OUT1_WIFI RK809_32KOUT_WIFI RTCIC_32KOUT
C6407 22pF
C0402
C6409 22pF
C0402
12
C0G 50V
12
C0G 50V
3
3
R6407 10K
Y6400
3
4
CRY4_3R20X2R50X0R80
1
VCCIO_WL
1
X2
GND
37.4MHz
Q6400 2SK3018
SOT_323
2
Q6401 2SK3018
SOT_323
2
1 2
GND
X1
VCCIO_WLVCCIO_WL
VCCIO_WL
Note: Adjusted the load capacitance according to the crystal specification.
2
1
12
12
12
Note:
If ultra low standby power consumption is required, please contact RK to reallocate GPIO and Power
PCIE20_TXP PCIE20_TXN PCIE20_RXP PCIE20_RXN PCIE20_REFCLKP PCIE20_REFCLKN
PCIE20_CLKREQn_M1
PCIE20_WAKEn_M1
PCIE20_PERSTn_M1
PCIE20_PERSTn_1V8
R6402 0R
1 2
R6403 10K
5% R0402
R6405 10K
5% R0402
PCIE20_PERSTn_1V8
5%
R0402
R6408 12K
5% R0402
RK809_32KOUT_WIFI
RTCIC_32KOUT
CLK32K_OUT1_WIFI
5%
R0402
R6410 0R
R6411 0R
R6412 0R
WIFI_REG_ON_H_GPIO2_B1 WIFI_WAKE_HOST_H_GPIO2_B2
SOC_PCM_IN SOC_PCM_OUT SOC_PCM_SYNC SOC_PCM_CLK
PCIE20_WAKEn_1V8
1 2
1 2
1 2
R0402
R0402
R0402
VCCIO_WL
12
5%
5%DNP
5%DNP
12
R6409 10K
5% R0402
U6400
12
PCIE_PERST_L
13
XTAL_IN
14
XTAL_OUT
15
WL_REG_ON
16
WL_HOST_WAKE/WL_GPIO_0
17
NC1
18
NC2
19
BT_PCM_OUT
20
BT_PCM_IN
21
BT_PCM_SYNC
22
BT_PCM_CLK
23
GND10
24
PCIE_PME_L
25
CBUCK_0P9
C6413
4.7uF
10V X5R C0603
L6400 2.2uH
IND_303015
1A_DCR<=80mohm
L6401 2.2uH
IND_303015
1A_DCR<=80mohm
PCIE_WIFIBT_32KIN
Rockchip Confidential
5
4
3
12
12
11
CSR_VLX26GND1127ASR_VLX
12
12
9
GND810GND9
28
12
R6413 DNP
R0402
ANT1GND12GND2
R6400 0R
5% R0402
8
7
GND7
WL_ANT1
ABUCK_1P12
30
29
C6418
4.7uF
10V X5R C0603
ANT1GND12GND2
ANT6401
3
12
3
1 2
R6401 0R
5% R0402
1 2
ANT_JACK
ANT_JACK
C6401 DNP
C0402
C6405 DNP
C0402
50 Ohm RF trace
2
1
5
GND23GND1
GND34GND4
GND56GND6
WL_ANT0
BT_HOST_WAKE
BT_WAKE
NC4 PCIE_TX_P PCIE_TX_N PCIE_RX_P PCIE_RX_N
BT_UART_CTS_N BT_UART_RTS_N
BT_UART_RXD BT_UART_TXD
GND14
BT_REG_ON
PCIE_CLKREQ_L
GND13
32
C6421 DNP
C0402
PCIE_RCLK_P
VBAT
PCIE_RCLK_N33LPO
VDDIO
35
36
34
PCIE_REFCLKP PCIE_REFCLKN
AP6275P/AP6275PR3
MD50_AP6XXX_13RX15RX1R5
1 2 1 2
GND12
31
12
BT_WAKE_HOST_H_GPIO2_C0
50
HOST_WAKE_BT_H_GPIO2_C1
49 48
PCIE_TDP
47
PCIE_TDN
46
PCIE_RDP
45
PCIE_RDN
44
UART1_RTSn_M0
43
UART1_CTSn_M0
42
UART1_TX_M0
41
UART1_RX_M0
40 39
BT_REG_ON_H_GPIO2_B7
38
PCIE20_CLKREQn_1V8
37
C6419 100pF C0201 X5R 25V 100pF C0201 X5R 25V C6420
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
2
Designed by:
C6408 100nF C0201 X5R 10V
1 2
C6410 100nF C0201 X5R 10V
1 2
C6411 100nF C0201 X5R 10V
1 2
C6412 100nF C0201 X5R 10V
1 2
VCC3V3_PCIEWL_VBAT
VCCIO_WL
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
64.WIFI6/BT-PCIe_2T2R + UART
64.WIFI6/BT-PCIe_2T2R + UART
64.WIFI6/BT-PCIe_2T2R + UART
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
Zhangdz
ANT1GND12GND2
12
C6414
12
100nF
X5R 10V C0402
C6416
12
100nF
X5R 10V C0402
PCIE20_REFCLKP PCIE20_REFCLKN
Reviewed by:
Reviewed by:
Reviewed by:
ANT6402 ANT_JACK
3
ANT_JACK
C6402
C6403 10pF
C0G 50V C0402
DNP
C0402
C6406 DNP
C0402
1 2
1 2
For AP6275PR3
PCIE20_RXP PCIE20_RXN PCIE20_TXP PCIE20_TXN
R6404
1 2
C6415
12
22uF
X5R 10V C0805
1 2
C6417
12
4.7uF
10V X5R C0603
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Default
Default
Default
0R
R0603
Max:1.2A
R6406 0R
R0402
Max:0.3A
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Sheet: of
1
VCC3V3_SYS
5%
VCC_1V8
5%
V1.1
V1.1
V1.1
50 72
50 72
50 72
Page 51
5
FE PHY0
And SDIO WIFI Option
GMAC0_TXD0 GMAC0_TXD1
GMAC0_TXEN
D D
GMAC0_RXD0 GMAC0_RXD1
GMAC0_RXDV_CRS
GMAC0_RXER
GMAC0_MCLKINOUT
GMAC0_MDC
GMAC0_MDIO
ETH0_REFCLKO_25M
GMAC0_RSTn_GPIO3_B7
Option
FEPHY0_CKXTAL1_I
C6500
12
18pF
C0G 50V C0402
DNP
Default
ETH0_REFCLKO_25M FEPHY0_CKXTAL2_O/I
Default:
Refclk:MAC output,PHY input
Y6500
1
X1
GND
GND2X2
DNP
25MHz
CRY4_3R20X2R50X0R80
R6504 0R
1 2
R6505 0R
1 2
R6506 0R
1 2
R6511 0R
1 2
12
C6506 DNP
C0402
Note:
RTL8201F/YT8512C only support 3.3V IO VCCIO4 must be changed to 3.3V power supply
C C
R6516 0R
1 2
R6519 0R
1 2
B B
VCC3V3_FEPHY0
GMAC0_RSTn_GPIO3_B7
PHYRSTB is 3.3V IO
VCC3V3_FEPHY0
VCC3V3_FEPHY0
A A
GMAC0_RXDV_CRS GMAC0_RXER
Note:
If GMAC0_RXDV_CRS has pull-up resistance by default, then 4.7K pull-down resistance is required
VCCA3V3_FEPHY0VCC_3V3
5%
R0402
VCC3V3_FEPHY0
5%
R0402
R6527 10K
1 2
R6528 0R
1 2
R6529 10K
1 2
R6531 1.8K
1 2
R6532 22R
1 2
R6533 22R
1 2
For YT8512C
5
Close to PIN7,30
12
C6507
4.7uF
X5R
6.3V C0402
12
C6511
4.7uF
X5R
6.3V C0402
Close to PIN14
5%DNP
FEPHY0_TXD3
R0402
GMAC0_TXEN
5%
FEPHY0_RSTn
R0402
5%DNP
R0402
GMAC0_MDC
5%
GMAC0_MDIO
R0402
FEPHY0_LED0/PHYAD0/PMEB FEPHY0_LED1/PHYAD1
R0402
5%
FEPHY0_CRS_DV
5%
FEPHY0_RXER/FXEN
R0402
12
C6508 100nF
X5R 10V
C0402
12
C6512 100nF
X5R 10V
C0402
FEPHY0_TXC
GMAC0_TXD0 GMAC0_TXD1
12
C6514 100nF
X5R 10V C0402
12
C6509 100nF
X5R 10V
C0402
U6501
17 18 19 20 21 22 23 24
12
R6534
4.7K
5% R0402
DNP
4
4
3
C6501
12
18pF
C0G 50V C0402
DNP
5%DNP
R0402
5%
R0402
5%
R0402
5%
R0402
R6512 4.7K
R6518 4.7K
R6522 4.7K
VCC3V3_FEPHY0
16
TXD1 TXD2 TXD3 TXEN PHYRSTB MDC MDIO LED0/PHYAD0/PMEB
FEPHY0_DVDD100UT
12
12
C6517 100nF
X5R 10V C0402
4
FEPHY0_MDI0P
FEPHY0_CKXTAL2_O/I
FEPHY0_CKXTAL1_I
FEPHY0_CKXTAL1_I
FEPHY0_TXCGMAC0_MCLKINOUT
5%DNP
12
R0402
RTL8201F/YT8512C: Pull Low for RMII REF_CLK Output mode Pull High for RMII REF_CLK Input mode(default)
FEPHY0_MDI0N
FEPHY0_MDI1P FEPHY0_MDI1N
FEPHY0_RXD3/CLK_CTL
FEPHY0_RXDV
Pull High for RMII mode(default)
5%
12
Pull Low for UTP Mode(default) Pull High for Fiber Mode
12
Pull Low for LED0 Mode(default) Pull High for WOL Mode WOL:Wake-on-LAN
10
11
12
13
14
15
RXC
TXC
TXD0
DVDD33
RXD2/INTB
RXD3/CLK_CTL
LED1/PHYAD125CRS/CRS_DV26COL27RXER/FXEN28DVDD10OUT29AVDD33_230CKXTAL1/I31CKXTAL2/O/EXT_I32E-Pad
C6518 1uF
X5R
6.3V C0402
DNP
FEPHY0_RXER/FXEN
R0402
5%
FEPHY0_RXD1
R0402
FEPHY0_RXD3/CLK_CTL FEPHY0_RXD2/INT
FEPHY0_RXD1 FEPHY0_RXD0
RXD09RXD1
RXDV
AVDD33_1
MDI1­MDI1+ MDI0­MDI0+
AVDD100UT
RSET
RTL8201F/YT8512C
QFN32_5R00X5R00X1R00_T
33
FEPHY0_CKXTAL2_O/I FEPHY0_CKXTAL1_I
VCCA3V3_FEPHY0
R6524 10K
R6525 22R R6526 22R
FEPHY0_RXDV
8 7
FEPHY0_MDI1N
6
FEPHY0_MDI1P
5
FEPHY0_MDI0N
4
FEPHY0_MDI0P
3
FEPHY0_AVDD100UT
2
FEPHY0_RSEL
1
1 2
1 2 1 2
3
12
5%
5% 5%
C6515 100nF
X5R 10V C0402
3
R0402
R0402
R0402
R0402
12
R0402
12
R0402
12
R0402
VCC3V3_FEPHY0
GMAC0_RXD1 GMAC0_RXD0
12
R6501 0R
1 2
R6500 0R
1 2
R6502 0R
1 2
R6503 0R
1 2
R6513 4.7K
R6517 4.7K
R6523 4.7K
R0402
R0402
R0402
VCCA3V3_FEPHY0
12
R6530
2.49K
1% R0402
C6516 1uF
X5R
6.3V C0402
DNP
5% 5%
5% 5%
5%
5%
5%DNP
12
ED6500 UDD32C03L01
SOD_323
DNP
12
ED6501 UDD32C03L01
SOD_323
DNP
VCC3V3_FEPHY0
VCC3V3_FEPHY0
VCC3V3_FEPHY0
2
High-tension
FEPHY0_MCT1
FEPHY0_MCT2
R6507 75R
5% R0805
D6501 BS3500NCF
SMB_F
DNP
LED6501 LED_GREEN
LED0603
Net_Link_LED
area
FEPHY0_A+ FEPHY0_A-
FEPHY0_B+ FEPHY0_B-
12
12
R6508 75R
5% R0805
12
C6505 1000pF
3KV CAP_D14P7R5_V
1 2
1 2
GMACx_TXD0
GMACx_TXD1
GMACx_TXD2 GMACx_TXD3
GMACx_TXEN
GMACx_TXCLK
GMACx_RXD0
GMACx_RXD1
GMACx_RXD2 GMACx_RXD3
GMACx_RXDV
GMACx_RXCLK
GMACx_RXER
GMACx_MDC
GMACx_MDIO
GMACx_MCLKINOUT
ETHx_REFCLKO_25M
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
12
12
R6509
R6510
75R
75R
5%
5%
R0805
R0805
Gap > 5mm
Low-tension area
R6514
5%
4.7K
R0402
R6515
5%
510R
R0402
FEPHY0_LED1/PHYAD1
Reserve for EMI.
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
65.Ethernet-FEPHY_RMII0
65.Ethernet-FEPHY_RMII0
65.Ethernet-FEPHY_RMII0
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
Zhangdz
U6500
1
2
3
4 5
6
7
8 9
C6502
12
10nF
X5R 25V C0402
UTH16C04H
C6503
12
SOIC16_12R70X9R40X6R22
10nF
X5R 25V C0402
16
15
14
13 12
11
10
D6500 BS3500NCF
SMB_F
DNP
12
12
Default:LED
5%
5%
LED6500
LED_Yellow
LED0603
Net_ACT_LED
PHY_TXD0
PHY_TXD1
PHY_TXEN
FEPHY0_LED0/PHYAD0/PMEB
C6510
12
100pF
C0G 50V
C0402
DNP
Reserve for EMI.
R6520 510R
12
R0402
R6521
4.7K
12
R0402
PHY Address Config
Default Refclk:MAC output,PHY input Refclk:MAC input,PHY output
PHY Address PHYAD[1:0] 1 (default) 2'b01
GMACx_TXD0
GMACx_TXD1
GMACx_TXD2 GMACx_TXD3
GMACx_TXEN
GMACx_TXCLK
GMACx_RXD0
GMACx_RXD1
GMACx_RXD2 GMACx_RXD3
GMACx_RXDV
PHY_RXD0
PHY_RXD1
PHY_CRS_DV
GMACx_RXCLK
GMACx_RXER
GMACx_MDC
GMACx_MDIO
GMACx_MCLKINOUT
ETHx_REFCLKO_25M
2
PHY_RXER
PHY_MDC
PHY_MDIO
PHY_TXC
PHY OSC
1
1
2
3
4
5
6
7
8
FEPHY0_CHASSIS_GND
12
C6513 100pF
C0G 50V
C0402
DNP
12
NC2
NC1
11
FB6500 120R-100MHz
25% 2A L0603
J6500
1
A+
2
A-
3
B+
4
C+
5
C-
6
B-
7
D+
8
D-
RJ45_5812-10P8C-A_Tab-Down
RJ45_5812-10P8C-A
VCC3V3_FEPHY0
12
PHY_TXD0
PHY_TXD1
PHY_TXEN
PHY_RXD0
PHY_RXD1
PHY_CRS_DV
PHY_RXER
PHY_MDC
PHY_MDIO
PHY_TXC
PHY OSC
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
1
10
G2
Tab down
G1
9
12
C6504 1000pF
2KV C1206L
DNP
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
51 72
Sheet: of
51 72
Sheet: of
51 72
Page 52
5
Giga PHY0
And SDIO WIFI Option
GMAC0_TXD0 GMAC0_TXD1 GMAC0_TXD2 GMAC0_TXD3 GMAC0_TXEN
GMAC0_TXCLK
GMAC0_RXD0
D D
GMAC0_RXD1 GMAC0_RXD2 GMAC0_RXD3 GMAC0_RXDV_CRS
GMAC0_RXCLK
ETH0_REFCLKO_25M
GMAC0_MCLKINOUT
GMAC0_MDC
GMAC0_MDIO
GMAC0_RSTn_GPIO3_B7
GMAC0_INT/PMEB_GPIO3_C0
PHY0_XTALOUT
C6700
12
18pF
C0G 50V C0402
ETH0_REFCLKO_25M PHY0_XTALOUT
Y6700
1
X1
GND2X2
25MHz
CRY4_3R20X2R50X0R80
R6709 0R
R6714 100R
12
12
C6706 DNP
C0402
1 2
R6715 120R
5% R0402
4
GND
3
1 2
4
PHY0_XTALIN
12
R6703
C6701
12
R0402
R0402
18pF
C0G 50V C0402
5%DNP
0R
5% R0402
DNP
5%
PHY0_CLKOUT125GMAC0_MCLKINOUT
3.3Vpp
MAC <----- PHY
3
PHY0_MDI3-
R6700 0R
PHY0_MDI3+
PHY0_MDI2­PHY0_MDI2+
PHY0_MDI1­PHY0_MDI1+
PHY0_MDI0­PHY0_MDI0+
PHY0_MDI_3- PHY0_MDI_3+
PHY0_MDI_2- PHY0_MDI_2+
PHY0_MDI_1- PHY0_MDI_1+
PHY0_MDI_0- PHY0_MDI_0+
1 2
R6701 0R
1 2
R6702 0R
1 2
R6704 0R
1 2
R6705 0R
1 2
R6706 0R
1 2
R6707 0R
1 2
R6708 0R
1 2
ED6700 UDD32C03L01
1 2
ED6701 UDD32C03L01
1 2
ED6702 UDD32C03L01
1 2
ED6703 UDD32C03L01
1 2
R04025% R04025%
R04025% R04025%
R04025% R04025%
R04025% R04025%
12
SOD_323 DNP
SOD_323 DNP
SOD_323 DNP
SOD_323 DNP
C6702 10nF
X5R 25V C0402
PHY0_MDI_3­PHY0_MDI_3+
PHY0_MDI_2­PHY0_MDI_2+
PHY0_MDI_1­PHY0_MDI_1+
PHY0_MDI_0­PHY0_MDI_0+
12
C6703 10nF
X5R 25V C0402
MCT1 MX1+ MX1­MCT2 MX2+ MX2­MCT3 MX3+ MX3­MCT4 MX4+ MX4-
2
24 23 22 21 20 19 18 17 16 15 14 13
12
D6702 BS3500NCF
SMB_F
DNP
LAN0_MCT1 LAN0_D­LAN0_D+ LAN0_MCT2 LAN0_C­LAN0_C+ LAN0_MCT3 LAN0_B­LAN0_B+ LAN0_MCT4 LAN0_A­LAN0_A+
U6700
1
TCT1
2
TD1+
3
TD1-
4
TCT2
5
TD2+
6
TD2-
7
TCT3
8
TD3+
9
TD3-
10
TCT4
11
TD4+
12
TD4-
12
12
C6705
C6704
10nF
10nF
X5R 25V C0402
LAN0_MCT1 LAN0_MCT2 LAN0_MCT3 LAN0_MCT4
12
D6700 BS3500NCF
SMB_F
DNP
X5R 25V C0402
H5007
SOIC24_17R53X12R20X5R51
12
D6701 BS3500NCF
SMB_F
DNP
R6710 75R
5% R0805
12
12
D6703 BS3500NCF
SMB_F
DNP
1
9
8
6
4
2
7
5
3
1
11
G1
NC1
Tab down
G2
NC2
10
12
PHY0_CHASSIS_GND
12
FB6700 120R-100MHz
25% 2A L0603
12
C6708 1000pF
2KV C1206L
DNP
LAN0_D­LAN0_D+ LAN0_B­LAN0_C­LAN0_C+ LAN0_B+ LAN0_A­LAN0_A+
12
R6711 75R
5% R0805
R6712 75R
5% R0805
12
12
R6713 75R
5% R0805
12
C6707 1000pF
3KV CAP_D14P7R5_V
High-tension area
J6700
8
D-
7
D+
6
B-
5
C-
4
C+
3
B+
2
A-
1
A+
RJ45_5812-10P8C-A_Tab-Down
RJ45_5812-10P8C-A
Gap > 5mm
Low-tension area
5%
R6716 4.7K
VDD10_PHY0
R6721
C C
PHY0_MDI0+
VDD10_PHY0
VDD10_PHY0
B B
PHY0_MDI0-
PHY0_MDI1+ PHY0_MDI1­PHY0_MDI2+ PHY0_MDI2-
PHY0_MDI3+ PHY0_MDI3-
2.49K
R0402
VCC3V3_PHY0
U6701
1
MDI[0]+
2
MDI[0]-
3
AVDD10
4
MDI[1]+
5
MDI[1]-
6
MDI[2]+
7
MDI[2]-
8
AVDD10
9
MDI[3]+
10
MDI[3]-
12
1%
5%
R6723 0R
1 2
PHY0_LED0/CFG_EXT
PHY0_LED1/CFG_LDO0
PHY0_LED2/CFG_LDO1
RSET0
PHY0_CLKOUT125
PHY0_XTALIN
PHY0_XTALOUT
31
32
34
35
36
37
38
39
40
41
RSET
E_Pad
CLKOUT
AVDD10
AVDD33
XTAL_IN
INTB/PMEB
LED0/CFG_EXT
LED1/CFG_LDO033LED2/CFG_LDO1
XTAL_OUT/EXT_CLK
RXC/PHYAD1
RXCTL/PHYAD2
RXD0/RXDLY
RXD1/TXDLY RXD2/PLLOFF RXD3/PHYAD0
REG_OUT
DVDD33
DVDD_RG
DVDD10
30 29 28 27 26 25 24 23 22 21
GMAC0_INT/PMEB_GPIO3_C0
od
R0402
PHY0_REG_OUT
PHY0_RXCLK/PHYAD1 PHY0_RXDV/PHYAD2 PHY0_RXD0/RXDLY PHY0_RXD1/TXDLY PHY0_RXD2/PLLOFF PHY0_RXD3/PHYAD0
VCC3V3_PHY0 VCCIO_PHY0
VDD10_PHY0
R6718 4.7K
R6720 4.7K
R6724 4.7K
R6726 4.7K
R6729 4.7K
R6731 4.7K
R6734 4.7K
R6737 4.7K
AVDD3311PHYRSTB12MDC13MDIO14TXD315TXD216TXD117TXD018TXCTL19TXC
20
RTL8211F-CG
VCC3V3_PHY0
GMAC0_TXD1
GMAC0_TXD2
GMAC0_TXD3
PHY0_RSTn
GMAC0_MDC
GMAC0_MDIO
R6741 4.7K
VCC3V3_PHY0
GMAC0_RSTn_GPIO3_B7
PHYRSTB is 3.3V IO
PHY0_RXD0/RXDLY PHY0_RXD1/TXDLY
A A
PHY0_RXD2/PLLOFF PHY0_RXD3/PHYAD0
PHY0_RXCLK/PHYAD1
PHY0_RXDV/PHYAD2
1 2
R6743 0R
1 2
5%DNP
R0402
5%
R0402
R6744 22R
1 2
R6745 22R
1 2
R6746 22R
1 2
R6747 22R
1 2
R6748 22R
1 2
R6749 22R
1 2
12
C6720 100nF
X5R 10V C0402
R6742 1.8K
Close to PHY
QFN40_5R00X5R00X0R90_T
RTL8211F-CG(SW Mode) RTL8211FI-CG(SW Mode)Industrial
GMAC0_TXD0
GMAC0_TXEN
GMAC0_TXCLK
R04025%
GMAC0_RXD0
R04025%
GMAC0_RXD1
R04025%
GMAC0_RXD2
R04025%
GMAC0_RXD3
R04025%
GMAC0_RXCLK
R04025%
GMAC0_RXDV_CRS
PHY0_REG_OUT
5%
12
R0402
VCCIO_PHY0
12
C6726 DNP
C0402
Close to PIN30
RTL8211F-CG(SW Mode) RTL8211FI-CG(SW Mode)Industrial
12
12
12
VCC_PHY0_IO Voltage Config
12
12
12
PHY Address Config
12
Pull-up for additional 2ns delay to RXC for data latching
12
Pull-up for additional 2ns delay to TXC for data latching
12
Pull-up to disable PLL @ ALDPS mode(Low power mode)
L6700
2.2uH
IND_303015
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
12
PHY0_LED0/CFG_EXT
5%DNP
PHY0_LED2/CFG_LDO1
5%
PHY0_LED1/CFG_LDO0
5%DNP
PHY0_RXD3/PHYAD0
5%
PHY0_RXCLK/PHYAD1
5%
PHY0_RXDV/PHYAD2
5%
PHY0_RXD0/RXDLY
5%
PHY0_RXD1/TXDLY
5%DNP
PHY0_RXD2/PLLOFF
12
C6715
4.7uF
X5R 10V C0603
C6716 100nF
X5R 10V
C0402
R6717 4.7K
R6719 4.7K
R6725 4.7K
PHY Address PHYAD[2:0]
1 (default) 3'b001
R6732 4.7K
R6735 4.7K
R6738 4.7K
Close to PIN21
12
C6717 100nF
X5R 10V
C0402
12
C6723 100nF
X5R 10V
C0402
Close to PIN3,8,38
5%DNP
12
R0402
12
R0402
12
R0402
12
R0402
12
R0402
12
R0402
12
C6724 100nF
X5R 10V
C0402
5%
5%
5%DNP
5%DNP
5%
VCC3V3_PHY0
VCCIO_PHY0
VCCIO_PHY0
VCCIO_PHY0
VCCIO_PHY0
12
C6725 100nF
X5R 10V
C0402
RGMII Power Source
External 3.3V
External 1.8V
Internal 1.8V (default)
PHY0_LED2/CFG_LDO1
R6727
1 2
0R
R0402
C6709
12
100pF
C0G 50V
C0402
DNP
Reserve for EMI.
Note:
According to the actual choice of mounted Cannot be mounted at the same time
VCC_1V8
R6736 0R
1 2
VCC_3V3
R6739 0R
1 2
R6740 0R
1 2
Rockchip Confidential
5
4
3
2
CFG_EXT CFG_LDO[1:0]
1'b1
1'b1
1'b0 2'b10
R6722 0R
1 2
LED6700
5%
12
R6733 510R
R0402
5%
VCCIO_PHY0
R0402
R0402
VCC3V3_PHY0VDD10_PHY0 VCC_3V3
R0402
LED_Yellow
LED0603
Net_ACT_LED
5%DNP
5%DNP
5%
2'b00
2'b10
5%DNP
R0402
PHY0_Y_LED+
LED6701 LED_GREEN
LED0603
Net_Link_LED
C6711
12
4.7uF
10V X5R C0603
12
C6718
4.7uF
X5R 10V C0603
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
67.Ethernet-GEPHY_RGMII0
67.Ethernet-GEPHY_RGMII0
67.Ethernet-GEPHY_RGMII0
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Zhangdz
Designed by:
Zhangdz
Designed by:
Zhangdz
R6728
1 2
1 2
510R
R0402
R6730 510R
R0402
PHY0_LED1/CFG_LDO0PHY0_G_LED-
Reserve for EMI.
Close to PIN28
12
1uF
10V X5R C0402
100nF
X5R 10V
C0402
C6713
C6712
12
Close to PIN11,40
12
12
C6719
C6714
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
12
12
C6721
4.7uF
X5R 10V C0603
C6722 100nF
X5R 10V
C0402
Close to PIN29
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
1
VCC3V3_PHY0
5%
5%DNP
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Sheet: of
12
V1.1
V1.1
V1.1
52 72
52 72
52 72
C6710 100pF
C0G 50V
C0402
DNP
Page 53
5
Giga PHY1
GMAC1_TXD0_M1 GMAC1_TXD1_M1 GMAC1_TXD2_M1 GMAC1_TXD3_M1 GMAC1_TXEN_M1
GMAC1_TXCLK_M1
D D
GMAC1_RXD0_M1 GMAC1_RXD1_M1 GMAC1_RXD2_M1 GMAC1_RXD3_M1 GMAC1_RXDV_CRS_M1
GMAC1_RXCLK_M1
ETH1_REFCLKO_25M_M1
GMAC1_MCLKINOUT_M1
GMAC1_MDC_M1 GMAC1_MDIO_M1
GMAC1_RSTn_GPIO3_B0
GMAC1_INT/PMEB_GPIO3_A7
PHY1_XTALOUT
C6800
12
18pF
C0G 50V C0402
ETH1_REFCLKO_25M_M1 PHY1_XTALOUT
Y6800
1
X1
GND2X2
25MHz
CRY4_3R20X2R50X0R80
R6809 0R
1 2
R6814 100R
1 2
12
12
R6815
C6806
120R
DNP
5%
C0402
R0402
GND
4
4
3
C6801
12
18pF
C0G 50V C0402
5%DNP
R0402
5%
R0402
MAC <----- PHY
PHY1_XTALIN
12
R6802 0R
5% R0402
DNP
PHY1_CLKOUT125GMAC1_MCLKINOUT_M1
3.3Vpp
3
PHY1_MDI3-
R6800 0R
PHY1_MDI3+
PHY1_MDI2­PHY1_MDI2+
PHY1_MDI1­PHY1_MDI1+
PHY1_MDI0­PHY1_MDI0+
PHY1_MDI_3- PHY1_MDI_3+
PHY1_MDI_2- PHY1_MDI_2+
PHY1_MDI_1- PHY1_MDI_1+
PHY1_MDI_0- PHY1_MDI_0+
1 2
R6801 0R
1 2
R6803 0R
1 2
R6804 0R
1 2
R6805 0R
1 2
R6806 0R
1 2
R6807 0R
1 2
R6808 0R
1 2
ED6800 UDD32C03L01
1 2
ED6801 UDD32C03L01
1 2
ED6802 UDD32C03L01
1 2
ED6803 UDD32C03L01
1 2
R04025% R04025%
R04025% R04025%
R04025% R04025%
R04025% R04025%
SOD_323 DNP
SOD_323 DNP
SOD_323 DNP
SOD_323 DNP
PHY1_MDI_3­PHY1_MDI_3+
PHY1_MDI_2­PHY1_MDI_2+
PHY1_MDI_1­PHY1_MDI_1+
PHY1_MDI_0­PHY1_MDI_0+
12
12
C6803
C6802
10nF
10nF
X5R
X5R
25V
25V
C0402
C0402
MCT1 MX1+ MX1­MCT2 MX2+ MX2­MCT3 MX3+ MX3­MCT4 MX4+ MX4-
24 23 22 21 20 19 18 17 16 15 14 13
12
D6800 BS3500NCF
SMB_F
DNP
2
LAN1_MCT1 LAN1_D­LAN1_D+ LAN1_MCT2 LAN1_C­LAN1_C+ LAN1_MCT3 LAN1_B­LAN1_B+ LAN1_MCT4 LAN1_A­LAN1_A+
U6800
1
TCT1
2
TD1+
3
TD1-
4
TCT2
5
TD2+
6
TD2-
7
TCT3
8
TD3+
9
TD3-
10
TCT4
11
TD4+
12
12
12
D6801 BS3500NCF
SMB_F
DNP
C6805 10nF
X5R 25V C0402
TD4-
H5007
SOIC24_17R53X12R20X5R51
12
D6802 BS3500NCF
SMB_F
DNP
12
C6804 10nF
X5R 25V C0402
LAN1_MCT1 LAN1_MCT2 LAN1_MCT3 LAN1_MCT4
R6810 75R
5% R0805
12
12
12
D6803 BS3500NCF
SMB_F
DNP
High-tension area
LAN1_D­LAN1_D+ LAN1_B­LAN1_C­LAN1_C+ LAN1_B+ LAN1_A­LAN1_A+
12
12
R6812 75R
5% R0805
R6813 75R
5% R0805
12
C6807 1000pF
3KV CAP_D14P7R5_V
R6811 75R
5% R0805
J6800
8
8
D-
7
D+
6
6
B-
5
C-
4
4
C+
3
B+
2
2
A-
1
A+
RJ45_5812-10P8C-A_Tab-Down
RJ45_5812-10P8C-A
High-tension area
Gap > 5mm
Low-tension area
1
7
5
3
1
9
11
NC1
Tab down
NC2
10
12
PHY1_CHASSIS_GND
12
FB6800 120R-100MHz
25% 2A L0603
G1
G2
12
C6808 1000pF
2KV C1206L
DNP
5%
R6816 4.7K
VDD10_PHY1
R6821
C C
PHY1_MDI0+
VDD10_PHY1
VDD10_PHY1
B B
PHY1_MDI0-
PHY1_MDI1+ PHY1_MDI1­PHY1_MDI2+ PHY1_MDI2-
PHY1_MDI3+ PHY1_MDI3-
2.49K
R0402
VCC3V3_PHY1
U6801
1
MDI[0]+
2
MDI[0]-
3
AVDD10
4
MDI[1]+
5
MDI[1]-
6
MDI[2]+
7
MDI[2]-
8
AVDD10
9
MDI[3]+
10
MDI[3]-
12
1%
5%
R6828 0R
1 2
PHY1_LED0/CFG_EXT
PHY1_LED1/CFG_LDO0
PHY1_LED2/CFG_LDO1
RSET1
PHY1_XTALIN
PHY1_XTALOUT
PHY1_CLKOUT125
31
32
34
35
36
37
38
39
40
41
RSET
E_Pad
CLKOUT
AVDD10
AVDD33
XTAL_IN
INTB/PMEB
LED0/CFG_EXT
LED1/CFG_LDO033LED2/CFG_LDO1
XTAL_OUT/EXT_CLK
RXC/PHYAD1
RXCTL/PHYAD2
RXD0/RXDLY
RXD1/TXDLY RXD2/PLLOFF RXD3/PHYAD0
REG_OUT
DVDD33
DVDD_RG
DVDD10
30 29 28 27 26 25 24 23 22 21
GMAC1_INT/PMEB_GPIO3_A7
R0402
PHY1_REG_OUT
PHY1_RXCLK/PHYAD1 PHY1_RXDV/PHYAD2 PHY1_RXD0/RXDLY PHY1_RXD1/TXDLY PHY1_RXD2/PLLOFF PHY1_RXD3/PHYAD0
VCC3V3_PHY1 VCCIO_PHY1
VDD10_PHY1
R6818 4.7K
R6820 4.7K
R6824 4.7K
R6829 4.7K
R6831 4.7K
R6834 4.7K
R6837 4.7K
AVDD3311PHYRSTB12MDC13MDIO14TXD315TXD216TXD117TXD018TXCTL19TXC
20
RTL8211F-CG
VCC3V3_PHY1
GMAC1_TXD1_M1
GMAC1_TXD2_M1
GMAC1_TXD3_M1
PHY1_RSTn
GMAC1_MDC_M1
GMAC1_MDIO_M1
R6841 10K
VCC3V3_PHY1
GMAC1_RSTn_GPIO3_B0
PHYRSTB is 3.3V IO
PHY1_RXD0/RXDLY PHY1_RXD1/TXDLY
A A
PHY1_RXD2/PLLOFF PHY1_RXD3/PHYAD0
PHY1_RXCLK/PHYAD1
PHY1_RXDV/PHYAD2
1 2
R6843 0R
1 2
5%DNP
R0402
5%
R0402
12
C6820 100nF
X5R 10V C0402
R6844 22R
1 2
R6845 22R
1 2
R6846 22R
1 2
R6847 22R
1 2
R6848 22R
1 2
R6849 22R
1 2
R6842 1.8K
Close to PHY
QFN40_5R00X5R00X0R90_T
RTL8211F-CG(SW Mode) RTL8211FI-CG(SW Mode)Industrial
GMAC1_TXD0_M1
GMAC1_TXEN_M1
GMAC1_TXCLK_M1
R04025%
GMAC1_RXD0_M1
R04025%
GMAC1_RXD1_M1
R04025%
GMAC1_RXD2_M1
R04025%
GMAC1_RXD3_M1
R04025%
GMAC1_RXCLK_M1
R04025%
GMAC1_RXDV_CRS_M1
5%
12
R0402
VCCIO_PHY1
12
C6826 DNP
C0402
PHY1_REG_OUT
Close to PIN30
RTL8211F-CG(SW Mode) RTL8211FI-CG(SW Mode)Industrial
12
12
12
VCC_PHY0_IO Voltage Config
12
12
PHY Address Config
12
Pull-up for additional 2ns delay to RXC for data latching
12
Pull-up for additional 2ns delay to TXC for data latching
12
Pull-up to disable PLL @ ALDPS mode(Low power mode)
L6800
2.2uH
IND_303015
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
12
PHY1_LED0/CFG_EXT
5%DNP
PHY1_LED2/CFG_LDO1
5%
PHY1_LED1/CFG_LDO0
PHY1_RXD3/PHYAD0
5%
PHY1_RXCLK/PHYAD1
5%
PHY1_RXDV/PHYAD2
5%
PHY1_RXD0/RXDLY
5%
PHY1_RXD1/TXDLY
5%DNP
PHY1_RXD2/PLLOFF
12
C6814
4.7uF
X5R 10V C0603
C6815 100nF
X5R 10V
C0402
R6817 4.7K
R6819 4.7K
R6823 4.7K
R6825 4.7K
PHY Address PHYAD[2:0]
1 (default) 3'b001
R6832 4.7K
R6835 4.7K
R6838 4.7K
VDD10_PHY1
Close to PIN21
Close to PIN3,8,38
12
C6816 100nF
X5R 10V
C0402
12
C6821 100nF
X5R 10V
C0402
5%DNP
12
R0402
12
R0402
12
R0402
12
R0402
12
R0402
12
R0402
12
R0402
12
C6822 100nF
X5R 10V
C0402
5%
5%
5%DNP
5%DNP
5%DNP
5%
VCC3V3_PHY1
VCCIO_PHY1
VCCIO_PHY1
VCCIO_PHY1
VCCIO_PHY1
VCCIO_PHY1
12
C6823 100nF
X5R 10V
C0402
RGMII Power Source
External 3.3V
External 1.8V
Internal 1.8V(default)
PHY1_LED2/CFG_LDO1
R6826
1 2
0R
R0402
C6809
12
100pF
C0G 50V
C0402
DNP
Reserve for EMI.
Note:
According to the actual choice of mounted Cannot be mounted at the same time
VCC_1V8
R6836 0R
VCC_3V3
VCC_3V3
1 2
R6839 0R
1 2
R6840 0R
1 2
Rockchip Confidential
5
4
3
2
CFG_EXT CFG_LDO[1:0]
1'b1
1'b1
1'b0 2'b10
R6822 0R
1 2
LED6800
5%
12
R6833 510R
R0402
R0402
R0402
R0402
LED_Yellow
LED0603
Net_ACT_LED
5%
VCCIO_PHY1
5%DNP
5%DNP
VCC3V3_PHY1
5%
2'b00
2'b10
5%DNP
R0402
PHY1_Y_LED+
LED6801 LED_GREEN
LED0603
Net_Link_LED
Close to PIN28
C6811
12
1uF
6.3V X5R C0402
Close to PIN11,40
12
C6817
4.7uF
X5R
6.3V C0402
Close to PIN29
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
68.Ethernet-GEPHY_RGMII1_M1
68.Ethernet-GEPHY_RGMII1_M1
68.Ethernet-GEPHY_RGMII1_M1
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Zhangdz
Designed by:
Zhangdz
Designed by:
Zhangdz
R6827
1 2
1 2
C6812
12
1uF
6.3V X5R C0402
12
C6818 100nF
X5R 10V
C0402
12
C6824
4.7uF
X5R
6.3V C0402
Reviewed by:
Reviewed by:
Reviewed by:
510R
R0402
R6830 510R
R0402
PHY1_LED1/CFG_LDO0PHY1_G_LED-
Reserve for EMI.
C6813
12
100nF
X5R 10V
C0402
12
C6819 100nF
X5R 10V
C0402
12
C6825 100nF
X5R 10V
C0402
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Default
Default
Default
1
VCC3V3_PHY1
5%
5%DNP
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Sheet: of
12
V1.1
V1.1
V1.1
53 72
53 72
53 72
C6810 100pF
C0G 50V
C0402
DNP
Page 54
5
PCIE Ethernet
PCIE20_TXP PCIE20_TXN
PCIE20_RXP
D D
PCIE20_RXN
PCIE20_REFCLKP PCIE20_REFCLKN
PCIE20_CLKREQn_M1 PCIE20_WAKEn_M1 PCIE20_PERSTn_M1
PCIE_ETH_ISOLATE_L_GPIO3_B6
PHY2_XTALOUT
C6900
12
18pF
C0G 50V C0402
Y6900
1
X1
GND
GND2X2
25MHz
CRY4_3R20X2R50X0R80
4
PHY2_MDI3-
R6900 0R
4
PHY2_XTALIN
3
C6901
12
18pF
C0G 50V C0402
PHY2_MDI3+
PHY2_MDI2­PHY2_MDI2+
PHY2_MDI1­PHY2_MDI1+
PHY2_MDI0­PHY2_MDI0+
PHY2_MDI_3- PHY2_MDI_3+
PHY2_MDI_2- PHY2_MDI_2+
PHY2_MDI_1- PHY2_MDI_1+
PHY2_MDI_0- PHY2_MDI_0+
1 2
R6901 0R
1 2
R6902 0R
1 2
R6903 0R
1 2
R6904 0R
1 2
R6905 0R
1 2
R6906 0R
1 2
R6907 0R
1 2
ED6900 UDD32C03L01
1 2
ED6901 UDD32C03L01
1 2
ED6902 UDD32C03L01
1 2
ED6903 UDD32C03L01
1 2
3
R04025% R04025%
R04025% R04025%
R04025% R04025%
R04025% R04025%
12
SOD_323 DNP
SOD_323 DNP
SOD_323 DNP
SOD_323 DNP
C6902 10nF
X5R 25V C0402
PHY2_MDI_3­PHY2_MDI_3+
PHY2_MDI_2­PHY2_MDI_2+
PHY2_MDI_1­PHY2_MDI_1+
PHY2_MDI_0­PHY2_MDI_0+
12
C6903 10nF
X5R 25V C0402
MCT1 MX1+ MX1­MCT2 MX2+ MX2­MCT3 MX3+ MX3­MCT4 MX4+ MX4-
24 23 22 21 20 19 18 17 16 15 14 13
12
D6902 BS3500NCF
SMB_F
DNP
2
LAN2_MCT1 LAN2_D­LAN2_D+ LAN2_MCT2 LAN2_C­LAN2_C+ LAN2_MCT3 LAN2_B­LAN2_B+ LAN2_MCT4 LAN2_A­LAN2_A+
R6908 75R
5% R0805
12
12
12
D6903 BS3500NCF
SMB_F
DNP
R6909 75R
5% R0805
R6910 75R
5% R0805
12
12
R6911 75R
5% R0805
12
C6906 1000pF
3KV CAP_D14P7R5_V
LAN2_D­LAN2_D+ LAN2_B­LAN2_C­LAN2_C+ LAN2_B+ LAN2_A­LAN2_A+
8 7 6 5 4 3 2 1
RJ45_5812-10P8C-A_Tab-Down
RJ45_5812-10P8C-A
High-tension area
Gap > 5mm
Low-tension area
U6900
1
TCT1
2
TD1+
3
TD1-
4
TCT2
5
TD2+
6
TD2-
7
TCT3
8
TD3+
9
TD3-
10
TCT4
11
TD4+
12
TD4-
12
12
C6905
C6904 10nF
X5R 25V C0402
12
D6900 BS3500NCF
SMB_F
DNP
10nF
X5R 25V C0402
H5007
SOIC24_17R53X12R20X5R51
12
D6901 BS3500NCF
SMB_F
DNP
J6900
D­D+ B­C­C+ B+ A­A+
1
9
11
G1
NC1
8
7
6
5
4
2
Tab down
3
1
NC2
12
PHY2_CHASSIS_GNDLAN2_MCT1 LAN2_MCT2 LAN2_MCT3 LAN2_MCT4
12
FB6900 120R-100MHz
25% 2A L0603
G2
10
12
C6907 1000pF
2KV C1206L
DNP
5%
R6912 0R
1 2
C C
VCC3V3_PHY2
PHY2_MDI0+ PHY2_REG_OUT
VDD10_PHY2
VDD10_PHY2
B B
A A
PHY2_MDI0-
PHY2_MDI1+ PHY2_MDI1­PHY2_MDI2+ PHY2_MDI2-
PHY2_MDI3+ PHY2_MDI3-
RTL_CLKREQB
PCIE20_PERSTn_M1 RTL_PERSTB
R6914 0R
R6917
2.49K
R0402
1 2 3 4 5 6 7 8
VCC3V3_PHY2
R6923 0R
R6925 0R
1 2
U6901
1 2
12
1%
MDIP0 MDIN0 AVDD10_3 MDIP1 MDIN1 MDIP2 MDIN2 AVDD10_8
1 2
R0402
R0402
VDD10_PHY2
32
R0402
RTL_CLKREQBPCIE20_CLKREQn_M1
5%
RTL_ISOLATEBPCIE_ETH_ISOLATE_L_GPIO3_B6
R6916 0R
26
27
29
30
31
LED0
RSET
CKXTAL128CKXTAL2
LED1/GPO
AVDD10_30
AVDD33_32
MDIP39MDIN310AVDD33_1111CLKREQB12HSIP13HSIN14REFCLK_P15REFCLK_N
5%
VCC3V3_PHY2
12
5%
R0402
1 2
PHY2_LED0 PHY2_LED1 PHY2_LED2
25
LED2
REGOUT VDDREG
DVDD10 LANWAKEB ISOLATEB
PERSTB
HSON HSOP
EPAD
16
33
RTL_LANWAKEBPCIE20_WAKEn_M1
OD,Active Low
R6924 10K
5% R0402
DNP
In D3cold: PERSTB High -> Low, 3.3V Main Power(ISOLATEB) High -> Low Out D3cold: 3.3V Main Power(ISOLATEB) Low -> High, PERSTB Low -> High
R0402
TP6900 TP_0.7
24 23 22 21 20 19 18 17
RTL8111HS
QFN32_4R00X4R00X0R90_T
OD,Active Low
Active Low
5%
PHY2_XTALOUT PHY2_XTALIN
RTL_LANWAKEB RTL_ISOLATEB RTL_PERSTB
C6915 100nF
RTL_HSON
C6916 100nF
RTL_HSOP
C6917 100nF
RTL_REFCLK_N RTL_REFCLK_P
RTL_HSIN RTL_HSIP
R6921 0R R6922 0R
C6921 100nF C6922 100nF
R6927 1K
1 2
The isolate pin will follow the system state S0 to high , and S3 / S4 to Low
VCC_3V3
12
R6918 1K
C0402
C0201
C0201
C0201
C0201
5%DNP
5% R0402
X5R 10V
X5R 10V X5R 10V
X5R 10V X5R 10V
VCC3V3_PHY2
R6919
R02015% R02015%
1 2
15K
R0402
PCIE20_RXN PCIE20_RXP
PCIE20_REFCLKN PCIE20_REFCLKP
PCIE20_TXN PCIE20_TXP
VCC3V3_PHY2 VDD10_PHY2
1 2
1 2 1 2
1 2 1 2
1 2 1 2
R0402
5%
PHY2_REG_OUT
PHY2_LED0
PHY2_LED1
LED6900 LED_Yellow
LED0603 Net_ACT_LED
LED6901 LED_GREEN
LED0603 Net_Link_LED
L6900
2.2uH
IND_303015
Close to PIN24
RTL8111HS-CG(SW Mode)
R6926 0R
12
C6925 1uF
X5R 10V
C0402
DNP
Close to PIN24
RTL8111H-CG(LDO Mode)
VCC_3V3 VCC3V3_PHY2
R6920 0R
1 2
1 2
DNP
1 2
12
R0402
Rockchip Confidential
V1.1
5
4
3
2
C6908
4.7uF
X5R 10V C0603
R0603
R6913
5%
510R
R0402
R6915 510R
12
R0402
5%
VDD10_PHY2
VCC3V3_PHY2
VCC3V3_PHY2
Close to PIN22
12
C6909 100nF
X5R 10V
C0402
5%
12
12
C6910 1uF
X5R 10V
C0402
12
C6912 100nF
X5R 10V
C0402
C6911 100nF
X5R 10V
C0402
12
12
C6913 100nF
X5R 10V
C0402
C6914 100nF
X5R 10V
C0402
Close to PIN3,8,30
5%
12
C6918
4.7uF
X5R 10V C0603
Close to PIN11,32
12
12
C6919
C6920
100nF
100nF
X5R
X5R
10V
10V
C0402
C0402
12
12
C6923
4.7uF
X5R 10V C0603
C6924 100nF
X5R 10V
C0402
Close to PIN23
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
69.Ethernet-PCIE Ethernet
69.Ethernet-PCIE Ethernet
69.Ethernet-PCIE Ethernet
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
1
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
54 72
Sheet: of
54 72
Sheet: of
54 72
Page 55
5
HPL_OUT HP_SNS HPR_OUT
HP_DET_L_GPIO3_C2
MIC1_INN
D D
C C
SARADC_VIN2_HP_HOOK
VCC_3V3
12
R7002 100K
5% R0402
12
C7000
Note:
100nF
X5R
RK3568 is in sleep state.
10V
To support the insertion of
C0402
HP interrupt wake-up, GPIO needs to be assigned to
HPR_OUT
HP_SNS
HPL_OUT
HP_DET_L_GPIO3_C2
R7000 0R
1 2
R7003 0R
1 2
R7004 1K
1 2
PMUIO0 or PMUIO1 or PMUIO2 domain
4
3
2
1
Note:
JP7000 PJ6_B2323B
PJ6_B2323B
1
G
2
R
3
L
4
IN
5
DETA
6
DETB
L R G
DET
GND
HPR_OUT
HP_SNS
HPL_OUT
GND
Layout note:
Place 0ohm resister close to GND pin of Headphone Jack , at layout,HP_SNS walks in the middle of HPL/HPR and acts as an accompanying line to avoid interference.
R0402
R0402
R0402
5%
5%
5%
12
For Headphone design, HP_SNS connect to GND near the Jack.
ED7000 ESD5451N
ESD0402
R7001 0R
1 2
12
ED7001 ESD5451N
ESD0402
12
ED7002 ESD5451N
ESD0402
R0402
5%
Default
Headphone Jack(3-pole with DET)
Headphone Jack(4-pole with DET & MIC)
6 5 4 3
2 1
R0402
LR
VCCIO_ACODEC
5%
DET
G28G1
G M
2
Layout note:
Place 0ohm resister close to GND pin of Headphone Jack , at layout,HP_SNS walks in the middle of HPL/HPR and acts as an accompanying line to avoid interference.
7
M G
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
70.Audio-Headphone Port
70.Audio-Headphone Port
70.Audio-Headphone Port
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Default
Default
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
Default
1
GND
HPR_OUT
HP_SNS
HPL_OUT
GND
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
55 72
Sheet: of
55 72
Sheet: of
55 72
Option
B B
HP_DET_L_GPIO3_C2
Note:
RK3568 is in sleep state.
A A
To support the insertion of HP interrupt wake-up, GPIO needs to be assigned to PMUIO0 or PMUIO1 or PMUIO2 domain
VCC_3V3
12
12
R7009 100K
5% R0402
C7003 100nF
X5R 10V
C0402
HPL_OUT
HPR_OUT HP_SNS
R7010 1K R04025%
R7011 0R R04025%
R7012 0R R04025%
MIC1_INN
SARADC_VIN2_HP_HOOK
1 2
1 2
1 2
12
ED7003 ESD5451N
ESD0402
12
C7002 100nF
X5R 10V
C0402
12
ED7004 ESD5451N
ESD0402
12
R7008 100K
5% R0402
R7007 100K
5% R0402
12
ED7005 ESD5451N
ESD0402
1 2
R7005
2.2K
5%
R0402
12
R7013 0R
1 2
12
ED7006 ESD5451N
ESD0402
Note:
For Headphone design, HP_SNS connect to GND near the Jack.
R7006 100R
1 2
12
C7001 1uF
X5R 10V C0402
CTIA(L,R,G,M)
J7000
6 5 4 3
2
5%
R0402
1
PJ8_B2339J
PJ8_b2339j
Rockchip Confidential
5
4
3
Page 56
5
SPKN_OUT SPKP_OUT
MIC1_INP
D D
MIC1_INN
4
3
2
1
OptionDefault
MIC for 3-pole Headphone Jack
R7100 100R
VCCIO_ACODEC VCCIO_ACODEC
C C
B B
1 2
R0402
MIC1_INP
MIC1_INN
5%
12
C7100 1uF
C0402 10V X5R
V1.1
12
12
12
R7102
1.1K
5% R0402
C7102 100pF
C0G 50V C0402
R7104
1.1K
5% R0402
V1.1
12
ED7101 ESD5451N
ESD0402
12
ED7102 ESD5451N
ESD0402
1
2
MIC7100 MIC-4020
MIC2_4020
MIC for 4-pole Headphone Jack
R7101 100R
1 2
R0402
MIC1_INP
5%
12
12
C7101 1uF
C0402 10V X5R
C7103 220pF
C0402 C0G 50V
12
R7103
2.2K
5% R0402
12
ED7100 ESD5451N
ESD0402
1
2
MIC7101 MIC-4020
MIC2_4020
SPK
Note:8ohm/1.3W Speaker Output
SPKP_OUT SPKN_OUT
12
ED7103 ESD5451N
ESD0402
12
ED7104 ESD5451N
ESD0402
1
1
2
2
J7100 CN2M_2R00_V_P_DIP
CN2M_2R00_V_P_DIP
A A
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Rockchip Confidential
5
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
4
3
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
71.Audio-SingleMic+RK809_SPK
71.Audio-SingleMic+RK809_SPK
71.Audio-SingleMic+RK809_SPK
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Default
Default
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
56 72
Sheet: of
56 72
Sheet: of
56 72
Page 57
5
I2C3_SDA_M0 I2C3_SCL_M0
PDM_CLK1_M0_ADC
PDM_SDI3_M0_ADC PDM_SDI2_M0_ADC PDM_SDI1_M0_ADC
SPKN_OUT SPKP_OUT
MIC1_INP
D D
C C
MIC1_INN
AD[2:0] 0 0 0 = 0x30 7bit AD[2:0] 0 0 1 = 0x31 7bit AD[2:0] 0 1 0 = 0x32 7bit
MicArray
I2C3_SDA_M0
I2C3_SCL_M0
VCCIO_ACODEC
1 2
12
VCCIO_ACODEC
1 2
12
VCCIO_ACODEC
1 2
R7202 0R R0402 5%1 2
R7203 0R R0402 5%1 2
R7204 10K
R0402 5%
C7206 100nF
X5R 10V C0402
R7209 10K
R0402 5%
C7216 100nF
X5R 10V C0402
R7210 10K
R0402 5%
AD0_ADC2_S
RST_ADC1_S PDM_SDI1_M0_ADC PDM_CLK1_M0_ADC AD0_ADC1_S
R7205 10K
R0402 5%
QFN16_3R00X3R00X0R80_T
1 2
RST_ADC2_S PDM_SDI2_M0_ADC PDM_CLK1_M0_ADC AD0_ADC2_S
QFN16_3R00X3R00X0R80_T
I2C_SDA_ADC_S
I2C_SCL_ADC_S
1 2 3 4
AD1_ADC1_S
R7206 10K
R0402 5%
1 2
I2C_SDA_ADC_S I2C_SCL_ADC_S
1 2 3 4
AD1_ADC2_S
R7211 10K
R0402 5%
1 2
U7200
RESETb DATA CLOCK AD0
ES7202
U7201
RESETb DATA CLOCK AD0
ES7202
16
16
CCLK
AD15AD26AINRP7AINRN
CCLK
AD15AD26AINRP7AINRN
13
17
CDATA15AINLP14AINLN
8
13
17
CDATA15AINLP14AINLN
8
C7200 1uF C0402 X5R 6.3V1 2
C7203 1uF C0402 X5R 6.3V1 2
EPAD
12
REFQ
11
VDD
10
GND
9
REFP
C7210 1uF C0402 X5R 6.3V1 2
C7211 1uF C0402 X5R 6.3V1 2
C7212 1uF C0402 X5R 6.3V1 2
C7213 1uF C0402 X5R 6.3V1 2
EPAD
12
REFQ
11
VDD
10
GND
9
REFP
C7222 1uF C0402 X5R 6.3V1 2
C7223 1uF C0402 X5R 6.3V1 2
4
VCCIO_ACODEC VCCIO_ACODEC
MIC1_INP_PDM_S
MIC1_INN_PDM_S
VCCIO_ACODEC
12
C7207
12
C7209 1uF
6.3V X5R C0402
12
C7219 1uF
6.3V X5R C0402
VCCIO_ACODEC
12
1uF
6.3V X5R C0402
MIC2_INN_PDM_S
MIC2_INP_PDM_S
MIC3_INP_PDM_S
MIC3_INN_PDM_S
C7217 1uF
6.3V X5R C0402
MIC4_INN_PDM_S
MIC4_INP_PDM_S
12
C7208 1uF
6.3V X5R C0402
12
C7218 1uF
6.3V X5R C0402
R7200 22R
MIC1_INP_PDM_S
MIC1_INN_PDM_S
Equal spacing arrangement; according to mic algorithm
MIC MIC1 MIC MIC2 MIC MIC4MIC MIC3
SDI1_Lch SDI1_Rch
VCCIO_ACODEC VCCIO_ACODEC
R7207 22R
MIC3_INP_PDM_S
MIC3_INN_PDM_S
3
3.3V as default
5%1 2
C7201
R0402
12
100nF
X5R
6.3V C0402
C7204
12
10pF
C0G
DNP
50V C0402
12
5%1 2
C7214
R0402
12
100nF
X5R
6.3V C0402
C7220
12
10pF
C0G
DNP
50V C0402
12
MIC1 MIC2
MIC7200 MSM381A3729H9CP
1
VDD
4
OUT
2
GND1
3
GND2
MIC4P_3R76X2R95X1R10
ED7200 ESD5451N
ESD0402
R7201 22R
MIC2_INP_PDM_S
MIC2_INN_PDM_S
5%1 2
R0402
C7202
12
100nF
X5R
6.3V C0402
C7205
12
10pF
C0G
DNP
50V C0402
12
ED7201 ESD5451N
ESD0402
For 4MIC Array Applications
SDI2_Lch
MIC3 MIC4
MIC7202 MSM381A3729H9CP
1
VDD
4
OUT
2
GND1
3
GND2
MIC4P_3R76X2R95X1R10
ED7202 ESD5451N
ESD0402
SDI2_Rch
MIC4_INP_PDM_S
MIC4_INN_PDM_S
R7208 22R
5%1 2
R0402
C7215
12
100nF
X5R
6.3V C0402
C7221
12
10pF
C0G
DNP
50V C0402
12
ED7203 ESD5451N
ESD0402
2
MIC7201 MSM381A3729H9CP
1
VDD
4
OUT
2
GND1
3
GND2
MIC4P_3R76X2R95X1R10
MIC7203 MSM381A3729H9CP
1
VDD
4
OUT
2
GND1
3
GND2
MIC4P_3R76X2R95X1R10
1
Equal spacing arrangement; according to mic algorithm
For 2MIC Array
MIC MIC1 MIC MIC2
SDI1_Lch SDI1_Rch
Applications
Option1
Loopback for Mono Speaker
(External ADC, better performance)
16
CCLK
CDATA15AINLP14AINLN
AD15AD26AINRP7AINRN
13
8
17
EPAD
REFQ
VDD GND
REFP
C7224 1uF C0402 X5R 6.3V1 2
C7227 1uF C0402 X5R 6.3V1 2
12 11 10 9
12
C7232 1uF
6.3V X5R C0402
12
C7233 1uF
6.3V X5R C0402
VCCIO_ACODEC
12
C7231 1uF
6.3V X5R C0402
I2C_SDA_ADC_S
R7219 10K
R0402 5%
RST_ADC3_S PDM_SDI3_M0_ADC PDM_CLK1_M0_ADC AD0_ADC3_S
I2C_SCL_ADC_S
U7202
1
RESETb
2
DATA
3
CLOCK
4
AD0
ES7202
QFN16_3R00X3R00X0R80_T
VCCIO_ACODEC
R7220 10K
R0402 5%
1 2
AD1_ADC3_S
VCCIO_ACODEC
R7216
B B
10K
R0402 5%
1 2
C7230
12
100nF
X5R 10V C0402
1 2
R7212 3.3K R0402 1%1 2
12
C7225
2.2nF
X5R 50V C0402
12
C7228
2.2nF
X5R 50V C0402
R7217 3.3K R0402 1%1 2
External PA Output loopback from Speaker Jack
R7213 2.2K R0402 1%1 2
12
C7226
12
10nF
R7214
X7R
390R
16V C0402
1% R0402
12
12
C7229
R7215
10nF
390R
X7R 16V
1%
C0402
R0402
R7218 2.2K R0402 1%1 2
SPKP_OUT
SPKN_OUT
RK809-5 SPK
Note:8ohm/1.3W Speaker Output
SPKP_OUT SPKN_OUT
12
ED7204 ESD5451N
ESD0402
12
ED7205 ESD5451N
ESD0402
1
1
2
2
J7200 CN2M_2R00_V_P_DIP
CN2M_2R00_V_P_DIP
Option2
MIC1_INP
MIC1_INN
R7221 3.3K R0402 1%1 2
12
C7234
2.2nF
X5R 50V C0402
12
C7236
2.2nF
X5R 50V C0402
R7225 3.3K R0402 1%1 2
Loopback for Mono Speaker
A A
(Available while No MIC is connected to RK809-5)
(cost-effective)
Rockchip Confidential
5
4
R7222 2.2K R0402 1%1 2
12
C7235
12
10nF
R7223
X7R
390R
16V C0402
1% R0402
12
12
C7237
R7224
10nF
390R
X7R 16V
1%
C0402
R0402
R7226 2.2K R0402 1%1 2
3
SPKP_OUT
RK809-5 Output loopback from Speaker Jack
SPKN_OUT
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
2
Designed by:
Rockchip Electronics Co., Ltd
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
72.Audio-MicArray+RK809_SPK
72.Audio-MicArray+RK809_SPK
72.Audio-MicArray+RK809_SPK
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Zhangdz
Zhangdz
Zhangdz
1
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
Sheet: of
Sheet: of
57 72
57 72
57 72
Page 58
5
I2C3_SDA_M0 I2C3_SCL_M0
PDM_CLK1_M0_ADC
PDM_SDI3_M0_ADC PDM_SDI2_M0_ADC PDM_SDI1_M0_ADC
HPL_OUT HP_SNS HPR_OUT
D D
SPK_CTL_H_GPIO3_C3
MicArray
I2C3_SDA_M0
I2C3_SCL_M0
VCCIO_ACODEC
1 2
12
R7400 0R R0402 5%1 2
R7403 0R R0402 5%1 2
R7404 10K
R0402 5%
C7406 100nF
X5R 10V C0402
RST_ADC1 PDM_SDI1_M0_ADC PDM_CLK1_M0_ADC AD0_ADC1
R7405 10K
R0402 5%
QFN16_3R00X3R00X0R80_T
1 2
I2C_SDA_ADC
I2C_SCL_ADC
1 2 3 4
AD1_ADC1
R7406 10K
R0402 5%
1 2
U7400
RESETb DATA CLOCK AD0
ES7202
16
CCLK
AD15AD26AINRP7AINRN
CDATA15AINLP14AINLN
13
17
8
4
C7400 1uF C0402 X5R 6.3V1 2
C7401 1uF C0402 X5R 6.3V1 2
EPAD
12
REFQ
11
VDD
10
GND
9
REFP
C7410 1uF C0402 X5R 6.3V1 2
C7411 1uF C0402 X5R 6.3V1 2
3
VCCIO_ACODEC VCCIO_ACODEC
MIC1_INP_PDM
MIC1_INN_PDM
VCCIO_ACODEC
12
C7407
12
C7408 1uF
6.3V X5R C0402
1uF
12
C7409
6.3V
1uF
X5R
6.3V
C0402 X5R C0402
MIC2_INN_PDM
MIC2_INP_PDM
3.3V as default
R7401 22R
MIC1_INP_PDM
MIC1_INN_PDM
5%1 2
C7402
R0402
12
MIC1 MIC2
100nF
X5R
6.3V
MIC7400
C0402
MSM381A3729H9CP
12
ED7400 ESD5451N
ESD0402
1
VDD
4
OUT
2
GND1
3
GND2
MIC4P_3R76X2R95X1R10
C7404
12
10pF
C0G
DNP
50V C0402
R7402 22R
MIC2_INP_PDM
MIC2_INN_PDM
Equal spacing arrangement; according to mic algorithm
5%1 2
C7403
R0402
12
100nF
X5R
6.3V C0402
C7405
12
10pF
C0G
DNP
50V C0402
12
ED7401 ESD5451N
ESD0402
MIC7401 MSM381A3729H9CP
1
VDD
4
OUT
2
GND1
3
GND2
MIC4P_3R76X2R95X1R10
2
1
For 4MIC Array
MIC MIC1 MIC MIC2 MIC MIC4MIC MIC3
SDI1_Lch SDI1_Rch
VCCIO_ACODEC VCCIO_ACODEC
R7408 22R
MIC3_INP_PDM
MIC3_INN_PDM
R0402
C7420
12
10pF
C0G
DNP
50V C0402
SDI2_Lch
5%1 2
C7414
12
100nF
MIC3 MIC4
X5R
6.3V C0402
MIC7402 MSM381A3729H9CP
1
VDD
4
OUT
2
GND1
3
GND2
12
MIC4P_3R76X2R95X1R10
ED7402 ESD5451N
ESD0402
12
C7418 1uF
6.3V X5R C0402
VCCIO_ACODEC
12
MIC3_INP_PDM
MIC3_INN_PDM
C7417
1uF
6.3V
X5R
C0402
MIC4_INN_PDM
MIC4_INP_PDM
16
CCLK
AD15AD26AINRP7AINRN
13
CDATA15AINLP14AINLN
8
C7412 1uF C0402 X5R 6.3V1 2
C7413 1uF C0402 X5R 6.3V1 2
17
EPAD
12
REFQ
11
VDD
10
GND
9
REFP
C7422 1uF C0402 X5R 6.3V1 2
C7423 1uF C0402 X5R 6.3V1 2
12
C7419 1uF
6.3V X5R C0402
I2C_SDA_ADC I2C_SCL_ADC
VCCIO_ACODEC
R7407 10K
R0402
C C
AD[2:0] 0 0 0 = 0x30 7bit AD[2:0] 0 0 1 = 0x31 7bit AD[2:0] 0 1 0 = 0x32 7bit
1 2
12
VCCIO_ACODEC
1 2
5%
C7416 100nF
X5R 10V C0402
R7410 10K
R0402 5%
AD0_ADC2
RST_ADC2 PDM_SDI2_M0_ADC PDM_CLK1_M0_ADC AD0_ADC2
U7401
1
RESETb
2
DATA
3
CLOCK
4
AD0
ES7202
QFN16_3R00X3R00X0R80_T
AD1_ADC2
R7411 10K
R0402 5%
1 2
Applications
SDI2_Rch
R7409 22R
MIC4_INP_PDM
MIC4_INN_PDM
5%1 2
C7415
R0402
12
100nF
X5R
6.3V C0402
MIC7403 MSM381A3729H9CP
12
ED7403 ESD5451N
ESD0402
1
VDD
4
OUT
2
GND1
3
GND2
MIC4P_3R76X2R95X1R10
C7421
12
10pF
C0G
DNP
50V C0402
Loopback for
B B
A A
Dual Speakers
I2C_SDA_ADC
R7424 10K
R0402 5%
RST_ADC3 PDM_SDI3_M0_ADC PDM_CLK1_M0_ADC AD0_ADC3
5
I2C_SCL_ADC
U7404
1
RESETb
2
DATA
3
CLOCK
4
AD0
ES7202
QFN16_3R00X3R00X0R80_T
VCCIO_ACODEC
R7428 10K
R0402 5%
1 2
AD1_ADC3
16
VCCIO_ACODEC
R7419 10K
R0402 5%
1 2
C7439
12
100nF
X5R 10V C0402
1 2
Rockchip Confidential
CCLK
CDATA15AINLP14AINLN
AD15AD26AINRP7AINRN
13
8
17
EPAD
REFQ
VDD GND
REFP
C7430 1uF C0402 X5R 6.3V1 2
C7433 1uF C0402 X5R 6.3V1 2
12 11 10 9
12
C7444 1uF
6.3V X5R C0402
C7446 1uF C0402 X5R 6.3V1 2
C7451 1uF C0402 X5R 6.3V1 2
12
C7445 1uF
6.3V X5R C0402
VCCIO_ACODEC
12
C7440 1uF
6.3V X5R C0402
R7414 3.3K R0402 1%1 2
12
C7431
2.2nF
X5R 50V C0402
12
C7434
2.2nF
X5R 50V C0402
R7421 3.3K R0402 1%1 2
External PA Output loopback from Speaker Jack
R7425 3.3K R0402 1%1 2
12
C7447
2.2nF
X5R 50V C0402
12
C7452
2.2nF
X5R 50V C0402
R7430 3.3K R0402 1%1 2
4
R7415 2.2K R0402 1%1 2
12
C7427
12
R7417
10nF
390R
X7R 16V
1%
C0402
R0402
12
12
R7418
C7435
390R
10nF
X7R
1%
16V
R0402
C0402
R7422 2.2K R0402 1%1 2
R7426 2.2K R0402 1%1 2
12
C7448
12
R7427
10nF
390R
X7R 16V
1%
C0402
R0402
12
12
C7453
R7429
10nF
390R
X7R 16V
1%
C0402
R0402
R7431 2.2K R0402 1%1 2
SPK2_P
SPK2_N
SPK1_N
SPK1_P
3
Speaker Output
Note:4ohm/3W
HPR_OUT
HPL_OUT
R7412 10K
R7413 30K
R7416 30K
R7420 30K
R7423 30K
L7400 180R-100M
C7449
12
L0603
100nF
X5R 10V C0402
1 2
R0402
R0402
R0402
R0402
R0402
5%1 2
5%1 2
5%1 2
5%1 2
5%1 2
VCC5V0_SPKPAVCC_5V0
Layout note:
SPK_CTL_H_GPIO3_C3
1 2
C7424
1 2
C7425
1 2
C7426
1 2
C7436
1 2
C7437
1 2
C7438
C7450
12
100nF
X5R 10V C0402
GND
HPR_OUT
HP_SNS
HPL_OUT
GND
VHmin:1.8V
U7402
1
1uF
X5R
2
C0402
10V
3
100nF
X5R
C0402
10V
100nF
X5R
C0402
10V
TT8642
MSOP8
VHmin:1.8V
U7403
1
1uF
X5R
2
C0402
10V
3
100nF
X5R
C0402
10V
100nF
X5R
C0402
10V
TT8642
MSOP8
For NO Headphone design, HP_SNS connect to GND near the PMIC.
2
EN
BYPASS
IN+
IN-4VO1
EN
BYPASS
IN+
IN-4VO1
HP_SNS
8
VO2
7
GND
6
VDD
5
8
VO2
7
GND
6
VDD
5
R7432 0R
C7428
12
10uF
X5R 10V C0603
C7441
12
10uF
X5R 10V C0603
1 2
VCC5V0_SPKPA
1 2
1 2
VCC5V0_SPKPA
1 2
R0402
5%DNP1 2
FB7400 180R-100M
L06031.5A
FB7401 180R-100M
L06031.5A
12
C7432 680pF
C0G 50V C0402
FB7402 180R-100M
L06031.5A
FB7403 180R-100M
L06031.5A
12
C7442 680pF
C0G 50V C0402
SPK1_N
SPK1_P
12
12
C7429
ED7404
680pF
ST0561D4
C0G
ESD0402
50V
DNP
C0402
SPK2_NSPK_CTL_H_GPIO3_C3
SPK2_P
12
12
ED7406
C7443
ST0561D4
680pF
ESD0402
C0G
DNP
50V C0402
1
1
2
2
J7400 CN2M_2R00_V_P_DIP
CN2M_2R00_V_P_DIP
12
ED7405 ST0561D4
ESD0402
DNP
1
1
2
2
J7401 CN2M_2R00_V_P_DIP
CN2M_2R00_V_P_DIP
12
ED7407 ST0561D4
ESD0402
DNP
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
74.Audio-MicArray+EXT Dual_SPK
74.Audio-MicArray+EXT Dual_SPK
74.Audio-MicArray+EXT Dual_SPK
Date:
Wednesday, J une 16, 2021
Date:
Wednesday, J une 16, 2021
Date:
Wednesday, J une 16, 2021
Designed by:
Zhangdz
Designed by:
Zhangdz
Designed by:
Zhangdz
1
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Default
Default
Default
Reviewed by:
Reviewed by:
Reviewed by:
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
Sheet: of
Sheet: of
58 72
58 72
58 72
Page 59
5
SATA0_TXP SATA0_TXN
SATA0_RXP SATA0_RXN
SATA1_TXP SATA1_TXN
D D
SATA1_RXP SATA1_RXN
SATA2_TXP SATA2_TXN
SATA2_RXP SATA2_RXN
SATA0_ACT_LED SATA1_ACT_LED SATA2_ACT_LED
4
SATA3.0 Port0
Option
3
And USB3 OTG0 option, Can support SATA0+USB2 OTG0
SATA0_TXP SATA0_TXN
SATA0_RXN SATA0_RXP
NOTES: 1:The SATA differential trace impedance is 100 OHM. The SATA trace length is less than 5 inch. 2:10nF close to connector
Diff 100 Ohm ±10%
C8200 10nF
1 2
C8201 10nF
1 2
Diff 100 Ohm ±10%
C8202 10nF
1 2
C8203 10nF
1 2
Diff 100 Ohm ±10%
C0201X7R 10V C0201X7R 10V
Diff 100 Ohm ±10%
C0201X7R 10V C0201X7R 10V
SATA0TXP SATA0TXN
SATA0RXN SATA0RXP
2
8
J8200
GND4
1
GND1
2
TXP
3
TXN
4
GND2
5
RXN
6
RXP
7
GND3
GND5
SATA30_7P_V_DIP
9
SATA30_7P_V_DIP
SATA0_ACT_LED
12
R8200 510R
5% R0402
LED8200 LED_RED
LED0603
SATA0_ACT_LED
1
SATA3.0 Port1
And USB3 HOST1 option, Can support SATA1+USB2 HOST1
SATA1_TXP SATA1_TXN
C C
SATA1_RXN SATA1_RXP
NOTES: 1:The SATA differential trace impedance is 100 OHM. The SATA trace length is less than 5 inch. 2:10nF close to connector
Diff 100 Ohm ±10%
C8204 10nF
1 2
C8205 10nF
1 2
Diff 100 Ohm ±10%
C8206 10nF
1 2
C8207 10nF
1 2
SATA3.0 Port2
And PCIe2.0 option
SATA2_TXP SATA2_TXN
B B
SATA2_RXN SATA2_RXP
NOTES: 1:The SATA differential trace impedance is 100 OHM. The SATA trace length is less than 5 inch. 2:10nF close to connector
Diff 100 Ohm ±10%
C8208 10nF
1 2
C8209 10nF
1 2
Diff 100 Ohm ±10%
C8210 10nF
1 2
C8211 10nF
1 2
SATA Power
Option
Diff 100 Ohm ±10%
C0201X7R 10V C0201X7R 10V
Diff 100 Ohm ±10%
C0201X7R 10V C0201X7R 10V
Diff 100 Ohm ±10%
C0201X7R 10V C0201X7R 10V
Diff 100 Ohm ±10%
C0201X7R 10V C0201X7R 10V
The current is estimated according to the actual number of SATA High power switching separate power supply is recommended for more than 2
SATA1TXP SATA1TXN
SATA1RXN SATA1RXP
SATA2TXP SATA2TXN
SATA2RXN SATA2RXP
8
J8201
GND4
1
GND1
2
TXP
3
TXN
4
GND2
5
RXN
6
RXP
7
GND3
GND5
SATA30_7P_V_DIP
9
SATA30_7P_V_DIP
8
J8202
GND4
1
GND1
2
TXP
3
TXN
4
GND2
5
RXN
6
RXP
7
GND3
GND5
SATA30_7P_V_DIP
9
SATA30_7P_V_DIP
SATA1_ACT_LED
SATA2_ACT_LED
12
R8201 510R
5% R0402
LED8201 LED_RED
LED0603
SATA1_ACT_LED
12
R8202 510R
5% R0402
LED8202 LED_RED
LED0603
SATA2_ACT_LED
R8203 0R
VCC5V0_USB
A A
VCC12V_DCIN
1 2
R8205 0R
1 2
R1206
R1206
5%
C8213 120uF
SVPF 20V E_C6
C8216 100uF
SVPF 25V E_E7
C8214
12
100nF
X5R 10V
C0402
C8217
12
100nF
X5R 25V
C0402
12
+
5%
12
+
J8203
1
+5V
2
GND1
3
GND2
4
+12V
SATA_IDE_DIP_4Pin
SATA-IDE4M_5R08_DIP
VCC5V0_USB
VCC12V_DCIN
R8204 0R
1 2
R8206 0R
1 2
Rockchip Confidential
5
4
3
R1206
R1206
5%
C8212 120uF
SVPF 20V E_C6
C8218 100uF
SVPF 25V E_E7
C8215
12
100nF
X5R 10V
C0402
C8219
12
100nF
X5R 25V
C0402
2
12
+
5%
12
+
J8204
1
+5V
2
GND1
3
GND2
4
+12V
SATA_IDE_DIP_4Pin
SATA-IDE4M_5R08_DIP
Option
Project:
Project:
Project:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
File:
File:
File:
82.SATA-SATA3.0 Slot_7P
82.SATA-SATA3.0 Slot_7P
82.SATA-SATA3.0 Slot_7P
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Date:
Wednesday, June 16, 2021
Designed by:
Zhangdz
Designed by:
Zhangdz
Designed by:
Zhangdz
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
1
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
59 72
Sheet: of
59 72
Sheet: of
59 72
Page 60
5
PCIE20_TXP PCIE20_TXN
PCIE20_RXP PCIE20_RXN
PCIE20_REFCLKP PCIE20_REFCLKN
D D
C C
PCIE20_CLKREQn_M1 PCIE20_WAKEn_M1 PCIE20_PERSTn_M1
PCIE20_PRSNT_L_GPIO3_B6
PCIE_PWREN_H_GPIO0_D4
PCIE20_CLKREQn_M1
PCIE20_WAKEn_M1
R8300 22R
1 2
R8301 22R
1 2
R8302 22R
1 2
R8303 22R
1 2
R0402
R0402
R0402
R0402
5%
5%
5%
5%
4
PCIE20_CLKREQn_3V3_L
PCIE20_WAKEn_3V3_L
PCIE20_PERSTn_3V3_LPCIE20_PERSTn_M1
PCIE20_PRSNT_3V3_LPCIE20_PRSNT_L_GPIO3_B6
3
VCC12V_PCIE20
VCC3V3_PCIE20
PCIE20_WAKEn_3V3_L
PCIE20_CLKREQn_3V3_L
PCIE20_TXP PCIE20_TXN PCIE20_TX_N
C8301 100nF
1 2
C8302 100nF
1 2
C0201 X5R 10V C0201 X5R 10V
Hot-plug
VCC3V3AUX_PCIE20
PCIE20_TX_P
2
PCIe2.0 x1 Slot
x1
1
G1
A1
PRSNT1#
A2
+12V_4
A3
+12V_5
A4
GND_A4
A5
JTAG_TCK
A6
JTAG_TDI
A7
JTAG_TDO
A8
JTAG_TMS
A9
+3.3V_2
A10
+3.3V_3
A11
PERST#
A12
GND_A12
A13
REFCLK+
A14
REFCLK-
A15
GND_A15
A16
PERp0
A17
PERn0
A18
GND_A18
G2
2
J8300
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11
B12 B13 B14 B15 B16 B17 B18
PCIe-SMT-36PIN
PCIE36_X1_SMT
+12V_1 +12V_2 +12V_3 GND_B4 SMCLK SMDAT GND_B7 +3.3V_1 JTAG_TRST
3.3VAUX WAKE#
RSVD_B12 GND_B13 PETp0 PETn0 GND_B16 PRSNT2#_1 GND_B18
10W Slot: 12V 0.5Amax
3.3V 3Amax
3.3Vaux 0.375Amax
VCC12V_PCIE20
VCC3V3_PCIE20
PCIE20_PERSTn_3V3_L
PCIE20_REFCLKP PCIE20_REFCLKN
PCIE20_RXP PCIE20_RXNPCIE20_PRSNT_3V3_L
1
12
C8300 100nF
X5R 10V C0402
DNP
VCC12V_PCIE20 VCC3V3_PCIE20 VCC3V3_PCIE20
C8309
C8307
12
100nF
X5R 10V
C0402
C8321
12
100nF
X5R 10V
C0402
C8308
12
12
10uF
X5R 25V C1206
100nF
X5R 25V
C0402
2
C8310
12
22uF
X5R
6.3V C0603
C8311
12
100nF
X5R 10V
C0402
12
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
C8313
C8312
12
100nF
22uF
X5R
X5R
10V
6.3V
C0402
C0603
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
83.PCIE-PCIE2.0_1x1Lane_RC_36P
83.PCIE-PCIE2.0_1x1Lane_RC_36P
83.PCIE-PCIE2.0_1x1Lane_RC_36P
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
Reviewed by:
Zhangdz
1
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
60 72
Sheet: of
60 72
Sheet: of
60 72
VCC3V3_PCIE20VCC12V_DCIN
VCC3V3AUX_PCIE20
5%DNP
R0402
5%
R0402
C8319
12
120uF
+
SVPF 20V E_C6
C8306
12
10uF
X5R
6.3V C0603
C8320
12
10uF
X5R
6.3V C0603
VCC12V_DCIN
2 3
C8303
12
10uF
X5R 25V C1206
12
C8304
12
100nF
X5R 25V
C0402
R8305 100K
R0402 5%
1
12
PCIE_PWREN_H_GPIO0_D4
B B
A A
R8308
1 2
5%
10K
R0402
C8315
12
C8316
12
10uF
100nF
X5R
X5R
25V
25V
C1206
C0402
PCIE_PWREN_H_GPIO0_D4
1
12
R8309 51K
R0402 5%
R8310 10K
R0402
2 3
4.5V<VIN<18V
1 2
5%
Q8300 WPM3407-3/TR
SOT_23
R8307 10K
R0402 5%
Q8301 S8050
SOT_23
12
VCC12V_PCIE20
C8305
12
10uF
X5R 25V C1206
C8318 100nF
X5R 10V
C0402
U8300
5
VIN
2
GND
4
EN
FB/OUT
SY8113B/SM8103ADC
SOT_23_6
6
LX
1
BS
3
C8314 100nF
1 2
X5R 25V
C0402
FB=0.6V
L8300
4.7uH
IND_606045
VCC_3V3
R8304 0R
1 2
VCC3V3_PCIE20
R8306 0R
1 2
Note:
According to the actual choice of mounted Cannot be mounted at the same time
12
R8311
C8317
12
22pF
C0G 50V C0402
232K
1% R0402
12
R8312
49.9K
1% R0402
Rockchip Confidential
5
4
3
Page 61
5
PCIE30_TX0P PCIE30_TX0N
PCIE30_TX1P PCIE30_TX1N
PCIE30_RX0P PCIE30_RX0N
PCIE30_RX1P PCIE30_RX1N
PCIE30_REFCLKP_IN PCIE30_REFCLKN_IN
PCIE30X2_CLKREQn_M1
D D
C C
B B
PCIE30X2_WAKEn_M1
PCIE30X2_PERSTn_M1
PCIE30X2_PRSNT_L_GPIO2_D7
PCIE_PWREN_H_GPIO0_D4
Y8400
1
X1
GND2X2
25MHz
C8418
CRY4_3R20X2R50X0R80
12
18pF
C0G 50V
C0402
GND
PCIE30X2_CLKREQn_M1
PCIE30X2_WAKEn_M1
PI6C_03_S0 PI6C_03_S1
PI6C_03_SS0 PI6C_03_SS1
R8415 22R
4
3
PI6C_03_OE
C8419
12
18pF
C0G 50V
C0402
If board target trace impedance is 50ohm then R = 475ohm providing an IREF of 2.32 mA . The output current ( IOH ) is 6 * IREF . 6x2.32X50=696mV
12
R0402
R8419 470R
1% R0402
R8400 22R
R8401 22R
R8402 22R
R8403 22R
5%1 2
U8400
1
S0
2
S1
3
SS0
8
SS1
4
X1/CLK
5
X2
7
GNDX
6
OE
9
IREF
PI6C557-03BLE
TSSOP16_4R50X5R10X1R20
R0402
R0402
R0402
R0402
VDDX
VDDA
CLK0P CLK0N
CLK1P CLK1N
GNDA
PCIE30X2_CLKREQn_3V3_L
5%1 2
PCIE30X2_WAKEn_3V3_L
5%1 2
PCIE30X2_PERSTn_3V3_LPCIE30X2_PERSTn_M1
5%1 2
PCIE30X2_PRSNT_3V3_LPCIE30X2_PRSNT_L_GPIO2_D7
5%1 2
16
12
15 14
11 10
13
VCC3V3_PI6C_03
PI6C_03_CLK0P PI6C_03_CLK0N
PI6C_03_CLK1P PI6C_03_CLK1N
4
C8413
12
1uF
C0402 X5R 10V
C8415
12
1uF
C0402 X5R 10V
C8414
12
100nF
C0402 X5R 10V
R8408 2.2R
C8416
12
100nF
C0402 X5R 10V
R8413 33R R02015%1 2 R8414 33R R02015%1 2
R8420 33R R02015%1 2 R8421 33R R02015%1 2
3
2
1
PCIe3.0 x 2Lanes (X 4Slot)
10W Slot:
A1
PRSNT1#
A2
+12V_4
A3
+12V_5
A4
GND_A4
A5 A6 A7 A8 A9
+3.3V_2
A10
+3.3V_3
A11
PERST#
A12
GND_A12
A13
REFCLK+
A14
REFCLK-
A15
GND_A15
A16
PERp0
A17
PERn0
A18
GND_A18
A19 A20
GND_A20
A21
PERp1
A22
PERn1
A23
GND_A23
A24
GND_A24
A25
PERp2
A26
PERn2
A27
GND_A27
A28
GND_A28
A29
PERp3
A30
PERn3
A31
GND_A31
A32
C8408
12
100nF
X5R 25V
C0402
R8407 10K R04025%1 2
R8410 10K R04025%1 2
R8412 10K R04025%1 2
5
4
12
C8422 DNP
C0402
12V 0.5Amax
3.3V 3Amax
3.3Vaux 0.375Amax
PCIE30X2_PERSTn_3V3_LPCIE30X2_WAKEn_3V3_L
PCIE30_REFCLKP_CON PCIE30_REFCLKN_CON
PCIE30_RX0P PCIE30_RX0N
PCIE30_RX1P PCIE30_RX1N
C8409
12
22uF
X5R
6.3V C0603
VCC3V3_PI6C_03
C8421
12
4.7uF
C0402 X5R
6.3V
VCC12V_PCIE30
VCC3V3_PCIE30
C8410
C8411
12
12
100nF
22uF
X5R
X5R
10V
6.3V
C0402
C0603
PI6C_S1 PI6C_S0
PI6C_SS1 PI6C_SS0
0 0
1 1
12
C8400 100nF
X5R 10V C0402
DNP
C8412
12
100nF
X5R 10V
C0402
Out Freq
100MHz10
Spread %
No Spread
-0.5
10
-1.0
01
No Spread
J8400
1 2
5%
R0402
R0402
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11
B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
5%DNP1 2
5%1 2
12
PCIe-SMT-64PIN
PCIE64_X4_SMT
12
C8430 100nF
X5R 10V
C0402
VCC12V_PCIE30
VCC3V3_PCIE30
VCC3V3AUX_PCIE30
C8401 220nF C0201 X5R 10V1 2 C8402 220nF C0201 X5R 10V1 2
C8403 220nF C0201 X5R 10V1 2 C8404 220nF C0201 X5R 10V1 2
PCIE30X2_CLKREQn_3V3_L
PCIE30X2_PRSNT_3V3_L
Hot-plug
V1.1
VCC3V3_PI6C_03
VCC3V3_PI6C_03
VCC3V3_PI6C_03
VCC3V3_PI6C_03
PCIE_PWREN_H_GPIO0_D4
PCIE30_TX0_P
PCIE30_TX1_P
R8404 0R
VCC3V3_PCIE30
R8405 0R
Note:
According to the actual choice of mounted Cannot be mounted at the same time
R8406 10K R04025%1 2
R8409 10K R04025%DNP1 2
R8411 10K R04025%DNP1 2
R8416 10K R04025%1 2
VCC5V0_SYS
C8420
12
1uF
R8422
C0402
100K
X5R
R0402
10V
PCIE30_TX0P PCIE30_TX0N PCIE30_TX0_N
PCIE30_TX1P PCIE30_TX1N PCIE30_TX1_N
VCC3V3_PI6C_03
5%1 2
R0402
C8417
12
4.7uF
C0402 X5R
6.3V
PCIE30_REFCLKP_CON PCIE30_REFCLKN_CON
12
R8417
49.9R
1% R0201
12
R8423
49.9R
1% R0201
To CON
12
HCSL
R8418
49.9R
1% R0201
PCIE30_REFCLKP_IN PCIE30_REFCLKN_IN
To SOC
12
HCSL
R8424
49.9R
1% R0201
1
G1
+12V_1 +12V_2 +12V_3 GND_B4 SMCLK SMDAT GND_B7 +3.3V_1 JTAG_TRST
3.3VAUX WAKE#
RSVD_B12 GND_B13 PETp0 PETn0 GND_B16 PRSNT2#_1 GND_B18 PETp1 PETn1 GND_B21 GND_B22 PETp2 PETn2 GND_B25 GND_B26 PETp3 PETn3 GND_B29 RSVD_B30 PRSNT2#_2 GND_B32
C8405 10uF
X5R
6.3V C0603
1
2
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS
x1
RSVD_A19
x4
RSVD_A32
G2
2
VCC12V_PCIE30VCC3V3AUX_PCIE30VCC_3V3 VCC3V3_PCIE30 VCC3V3_PCIE30
C8407
C8406
12
12
10uF
100nF
X5R
X5R
25V
10V
C1206
C0402
PI6C_03_S0
PI6C_03_S1
PI6C_03_SS0
PI6C_03_SS1
PI6C_03_OE
U8401
IN
OUT
GND
EN3BP
PT5108E23E-33
SOT_23_5
VCC12V_DCIN VCC12V_PCIE30 VCC3V3_PCIE30VCC12V_DCIN
C8424
12
12
10uF
X5R
A A
PCIE_PWREN_H_GPIO0_D4
25V C1206
R8431 10K
R0402
1 2
5%
Rockchip Confidential
5
C8425 100nF
X5R 25V
C0402
2 3
12
Q8400
R8426
1
WPM3407-3/TR
100K
SOT_23
R0402 5%
12
R8429 10K
R0402 5%
Q8401
1
S8050
12
SOT_23
2 3
R8432 51K
R0402 5%
C8426
12
10uF
X5R 25V C1206
4
C8427
C8428
12
12
10uF
100nF
X5R
X5R
25V
25V
C1206
C0402
PCIE_PWREN_H_GPIO0_D4
R8427 10K
R0402
4.5V<VIN<18V
1 2
5%
U8402
LX
VIN
GND
BS
EN
FB/OUT
SY8113B/SM8103ADC
SOT_23_6
6
C8423 100nF
1 2
1
3
3
FB=0.6V
X5R 25V
C0402
L8400
4.7uH
IND_606045
12
C8429
R8428
12
22pF
232K
C0G 50V C0402
1% R0402
C8431
12
120uF
+
SVPF
R8430
49.9K
1% R0402
20V E_C6
12
C8433
C8432
12
12
100nF
10uF
X5R
X5R
10V
6.3V
C0402
C0603
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
2
Designed by:
Rockchip Electronics Co., Ltd
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
84.PCIE-PCIE3.0_1x2Lanes_RC_64P
84.PCIE-PCIE3.0_1x2Lanes_RC_64P
84.PCIE-PCIE3.0_1x2Lanes_RC_64P
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Zhangdz
Zhangdz
Zhangdz
1
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
Sheet: of
Sheet: of
61 72
61 72
61 72
5
2
4
12
R8425 DNP
R0402
Page 62
5
PCIE30_TX0P PCIE30_TX0N
PCIE30_TX1P PCIE30_TX1N
PCIE30_RX0P PCIE30_RX0N
PCIE30_RX1P PCIE30_RX1N
PCIE30_REFCLKP_IN PCIE30_REFCLKN_IN
D D
C C
PCIE30X2_CLKREQn_M1 PCIE30X2_WAKEn_M1
PCIE30X2_PERSTn_M1
PCIE30X2_PRSNT_L_GPIO2_D7
PCIE30X1_CLKREQn_M1 PCIE30X1_WAKEn_M1
PCIE30X1_PERSTn_M1
PCIE30X1_PRSNT_L_GPIO3_A0
PCIE_PWREN_H_GPIO0_D4
PCIE30X2_CLKREQn_M1
PCIE30X2_WAKEn_M1
R8501 22R
R8503 22R
R8506 22R
R8508 22R
PCIE30X2_LANE0_WAKEn_3V3_L PCIE30X2_LANE0_PERSTn_3V3_L
PCIE30_TX0P PCIE30_TX0N PCIE30X2_TX0_N
5%1 2
R0402
5%1 2
R0402
5%1 2
R0402
5%1 2
R0402
PCIE30X2_LANE0_CLKREQn_3V3_L
C8502 220nF C0201 X5R 10V1 2 C8504 220nF C0201 X5R 10V1 2
Hot-plug Hot-plug
PCIE30X2_LANE0_CLKREQn_3V3_L
PCIE30X2_LANE0_WAKEn_3V3_L
PCIE30X2_LANE0_PERSTn_3V3_LPCIE30X2_PERSTn_M1
PCIE30X2_LANE0_PRSNT_3V3_LPCIE30X2_PRSNT_L_GPIO2_D7
VCC12V_PCIE30
VCC3V3_PCIE30X2
VCC3V3AUX_PCIE30X2 VCC3V3AUX_PCIE30X1
PCIE30X2_TX0_P
4
PCIe3.0 x1 Slot
+12V_1 +12V_2 +12V_3 GND_B4 SMCLK SMDAT GND_B7 +3.3V_1 JTAG_TRST
3.3VAUX WAKE#
RSVD_B12 GND_B13 PETp0 PETn0 GND_B16 PRSNT2#_1 GND_B18
R0402
R0402
1
G1
PRSNT1#
+12V_4 +12V_5
GND_A4 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS
+3.3V_2 +3.3V_3
PERST#
GND_A12 REFCLK+ REFCLK-
x1
GND_A15
PERp0 PERn0
GND_A18
G2
2
5%DNP1 2
C8506
12
12
10uF
5%1 2
X5R
6.3V C0603
J8500
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11
B12 B13 B14 B15 B16 B17 B18
PCIe-SMT-36PIN
PCIE36_X1_SMT
VCC_3V3
R8500 0R
VCC3V3_PCIE30X2
R8505 0R
Note:
According to the actual choice of mounted Cannot be mounted at the same time
10W Slot: 12V 0.5Amax
3.3V 3Amax
3.3Vaux 0.375Amax
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
A12 A13 A14 A15 A16 A17 A18
VCC12V_PCIE30 VCC3V3_PCIE30X2 VCC3V3_PCIE30X2VCC3V3AUX_PCIE30X2
C8507 100nF
X5R 10V
C0402
C8520
12
10uF
X5R 25V C1206
VCC12V_PCIE30
VCC3V3_PCIE30X2
PCIE30X2_REFCLKP_CON PCIE30X2_REFCLKN_CON
PCIE30_RX0P PCIE30_RX0NPCIE30X2_LANE0_PRSNT_3V3_L
C8508
12
100nF
X5R 25V
C0402
3
12
C8500 100nF
X5R 10V C0402
DNP
PCIE30X1_CLKREQn_M1
PCIE30X1_WAKEn_M1
C8510
C8511
C8509
12
12
100nF
22uF
X5R
X5R
10V
6.3V
C0402
C0603
C8521
12
12
22uF
100nF
X5R
X5R
6.3V
10V
C0603
C0402
V1.1
PCIE30_TX1P PCIE30_TX1N
PCIE30X1_WAKEn_3V3_L PCIE30X1_PERSTn_3V3_L
PCIE30X1_CLKREQn_3V3_L
C8503 220nF C0201 X5R 10V1 2 C8505 220nF C0201 X5R 10V1 2
PCIE30X1_PRSNT_3V3_L
R8502 22R
R8504 22R
R8507 22R
R8509 22R
VCC_3V3
R8545 0R
VCC3V3_PCIE30X1
R8546 0R
Note:
According to the actual choice of mounted Cannot be mounted at the same time
R0402
R0402
R0402
R0402
2
PCIE30X1_CLKREQn_3V3_L
5%1 2
PCIE30X1_WAKEn_3V3_L
5%1 2
PCIE30X1_PERSTn_3V3_LPCIE30X1_PERSTn_M1
5%1 2
PCIE30X1_PRSNT_3V3_LPCIE30X1_PRSNT_L_GPIO3_A0
5%1 2
5%DNP1 2
R0402
5%1 2
R0402
VCC12V_PCIE30
VCC3V3_PCIE30X1
PCIE30X1_TX1_P PCIE30X1_TX1_N
PCIe3.0 x1 Slot
J8501
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11
B12 B13 B14 B15 B16 B17 B18
PCIe-SMT-36PIN
PCIE36_X1_SMT
C8512
12
10uF
X5R
6.3V C0603
+12V_1 +12V_2 +12V_3 GND_B4 SMCLK SMDAT GND_B7 +3.3V_1 JTAG_TRST
3.3VAUX WAKE#
RSVD_B12 GND_B13 PETp0 PETn0 GND_B16 PRSNT2#_1 GND_B18
1
G1
PRSNT1#
+12V_4 +12V_5
GND_A4 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS
+3.3V_2 +3.3V_3
PERST#
GND_A12 REFCLK+ REFCLK-
x1
GND_A15
PERp0 PERn0
GND_A18
G2
2
VCC12V_PCIE30 VCC3V3_PCIE30X1 VCC3V3_PCIE30X1VCC3V3AUX_PCIE30X1
C8515
C8514
C8513
12
100nF
X5R 10V
C0402
12
12
100nF
10uF
X5R
X5R
25V
25V
C0402
C1206
10W Slot: 12V 0.5Amax
3.3V 3Amax
3.3Vaux 0.375Amax
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
A12 A13 A14 A15 A16 A17 A18
C8516
12
22uF
X5R
6.3V C0603
1
VCC12V_PCIE30
VCC3V3_PCIE30X1
PCIE30X1_REFCLKP_CON PCIE30X1_REFCLKN_CON
PCIE30_RX1P PCIE30_RX1N
C8517
12
12
100nF
X5R 10V
C0402
C8518 22uF
X5R
6.3V C0603
12
C8501 100nF
X5R 10V C0402
DNP
C8519
12
100nF
X5R 10V
C0402
VCC3V3_PI6C_05
C8523
C8522
12
12
100nF
1uF
C0402
C0402
X5R
X5R
10V
10V
PI6C_05_S0
PI6C_05_S1 PI6C_05_S2
Y8500
1
X1
GND2X2
25MHz
CRY4_3R20X2R50X0R80
C8524
12
18pF
C0G 50V
C0402
B B
If board target trace impedance is 50ohm then R = 475ohm providing an IREF of 2.32 mA . The output current ( IOH ) is 6 * IREF . 6x2.32X50=696mV
A A
PCIE_PWREN_H_GPIO0_D4
GND
4
3
VCC12V_DCIN
R8522 22R
PI6C_05_PDn PI6C_05_OE
C8525
12
18pF
12
C0G 50V
C0402
C8536
12
12
10uF
X5R 25V C1206
R8540
1 2
10K
5%
R0402
R0402
R8528 470R
1% R0402
C8537 100nF
X5R 25V
C0402
5%1 2
VCC3V3_PI6C_05
12
12
R8537 100K
R0402 5%
1
12
R8541 51K
R0402 5%
U8500
1
VDDXD
2
S0
3
S1
4
S2
5
X1
6
X2
7
PDn
8
OE
9
GNDXD IREF10CLK3N
PI6C557-05BLE
TSSOP20_6R50x4R40x1R20
R8532 2.2R
C8528
4.7uF
C0402 X5R
6.3V
VCC12V_PCIE30
2 3
Q8500
1
WPM3407-3/TR
SOT_23
12
R8539 10K
R0402 5%
Q8501 S8050
SOT_23
2 3
CLK0P CLK0N
CLK1P CLK1N
GNDODA VDDODA
CLK2P CLK2N
CLK3P
R0402
C8538
12
10uF
X5R 25V C1206
PI6C_05_CLK0P
R8510 33R R02015%1 2
PI6C_05_CLK0N
R8511 33R R02015%1 2
20 19
18 17
16 15
14 13
12 11
5%1 2
C8530
C8529
12
12
100nF
1uF
C0402
C0402
X5R
X5R
10V
10V
PI6C_05_CLK1N
PI6C_05_CLK3P PI6C_05_CLK3N
R8516 33R R02015%1 2 R8517 33R R02015%1 2
R8527 33R R02015%1 2 R8529 33R R02015%1 2
12
12
12
VCC12V_DCIN
C8533
12
10uF
X5R 25V C1206
PCIE_PWREN_H_GPIO0_D4
VCC12V_DCIN VCC3V3_PCIE30X1
C8544
12
10uF
X5R 25V C1206
PCIE_PWREN_H_GPIO0_D4
R8512
49.9R
1% R0201
R8523
49.9R
1% R0201
R8530
49.9R
1% R0201
12
R8513
49.9R
1% R0201
12
R8524
49.9R
1% R0201
12
R8531
49.9R
1% R0201
C8534
12
100nF
X5R 25V
C0402
C8545
12
100nF
X5R 25V
C0402
PCIE30X2_REFCLKP_CON PCIE30X2_REFCLKN_CON
To CON HCSL
PCIE30X1_REFCLKP_CONPI6C_05_CLK1P PCIE30X1_REFCLKN_CON
To CON HCSL
PCIE30_REFCLKP_IN PCIE30_REFCLKN_IN
To SOC HCSL
4.5V<VIN<18V
R8535
1 2
10K
5%
R0402
4.5V<VIN<18V
R8542
1 2
10K
5%
R0402
U8502
5
VIN
2
GND
4
EN
C8539
12
100nF
X5R 10V
C0402
DNP
C8547
12
100nF
X5R 10V
C0402
DNP
FB/OUT
SY8113B/SM8103ADC
SOT_23_6
U8503
5
VIN
2
GND
4
EN
FB/OUT
SY8113B/SM8103ADC
SOT_23_6
PI6C_S2 PI6C_S1 PI6C_S0
0 0 0
0 0 1
0 1 0
0 1 1
VCC3V3_PI6C_05
VCC3V3_PI6C_05
VCC3V3_PI6C_05
VCC3V3_PI6C_05
VCC3V3_PI6C_05
PCIE_PWREN_H_GPIO0_D4
6
LX
1
BS
3
6
LX
1
BS
3
R8514 10K R04025%DNP1 2
R8518 10K R04025%1 2
R8520 10K R04025%1 2
R8525 10K R04025%1 2
R8526 4.7K R04025%1 2
VCC5V0_SYS VCC3V3_PI6C_05
C8526
12
1uF
R8533
1 2
C0402
100K
5%
X5R
R0402
10V
L8500
X5R 25V
C0402
X5R 25V
C0402
4.7uH
IND_606045
L8501
4.7uH
IND_606045
C8532 100nF
1 2
FB=0.6V
C8543 100nF
1 2
FB=0.6V
Rockchip Confidential
5
4
3
Spread %
-0.5
-1.0
-1.5
No Spread
PI6C_05_S2
PI6C_05_S0
PI6C_05_S1
PI6C_05_OE
PI6C_05_PDn
U8501
1
IN
2
GND
EN3BP
PT5108E23E-33
C8551
12
SOT_23_5
100nF
X5R 10V
C0402
C8535
12
22pF
C0G 50V C0402
C8546
12
22pF
C0G 50V C0402
R8519 10K R04025%DNP1 2
R8521 10K R04025%DNP1 2
OUT
12
R8536 232K
1% R0402
12
R8538
49.9K
1% R0402
12
R8543 232K
1% R0402
12
R8544
49.9K
1% R0402
Out Freq
100MHz
100MHz
100MHz
100MHz
R8515 10K R04025%1 2
5
4
12
C8531 DNP
C0402
VCC3V3_PCIE30X2
C8540
12
120uF
+
SVPF 20V E_C6
C8548
12
120uF
+
SVPF 20V E_C6
C8527
12
4.7uF
C0402 X5R
6.3V
C8542
C8541
12
12
100nF
10uF
X5R
X5R
10V
6.3V
C0402
C0603
C8550
C8549
12
12
100nF
10uF
X5R
X5R
10V
6.3V
C0603
C0402
Project:
Project:
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File:
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Date:
Date:
Date:
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Designed by:
2
Designed by:
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
85.PCIE-PCIE3.0_2x1Lane_RC_32P
85.PCIE-PCIE3.0_2x1Lane_RC_32P
85.PCIE-PCIE3.0_2x1Lane_RC_32P
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Wednesday, J une 16, 2021
Zhangdz
Zhangdz
Zhangdz
1
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
Sheet: of
Sheet: of
62 72
62 72
62 72
Page 63
5
PCIE30_TX0P PCIE30_TX0N
PCIE30_TX1P PCIE30_TX1N
PCIE30_RX0P
D D
C C
Selected according
PCIE30_RX0N
PCIE30_RX1P PCIE30_RX1N
PCIE30_REFCLKP_IN PCIE30_REFCLKN_IN
PCIE30X2_CLKREQn_M1 PCIE30X2_WAKEn_M1
PCIE30X2_PERSTn_M1
RESETn
PCIe3.0 x2 EP Mode-EDGE
PCIE30X2_PERSTn_M1 PCIE30X2_EP_PERSTn_3V3_L
RESETn
to actual demands
VCC3V3_PCIE30_EDGEVCC3V3_SYS
R8601 0R
1 2
Note:
R1206
5%DNP
12
C8605 22uF
X5R
6.3V C0603
DNP
12
C8606 22uF
X5R
6.3V C0603
DNP
12
The supply power needs to meet the current demand
VCC12V_DCIN VCC12V_PCIE_EDGE
B B
R8602 0R
1 2
R1206
Selected according to actual demands
5%DNP
12
+
C8608 100uF
SVPF 25V E_E7
DNP
12
C8609 10uF
X5R 25V C1206
DNP
12
4
R8600 22R
1 2
R8607 22R
1 2
V1.1
VCC3V3_PCIE30_EDGE
VCC12V_PCIE_EDGE
PCIE_ADDIN_PRSNT
J8600 PCIe-64PIN-EDGE
C8607 100nF
X5R 10V
C0402
DNP
PCIe-64PIN-EDGE
C8610 100nF
X5R 25V
C0402
DNP
VCC3V3_PCIE30_EDGE
EP<--RC
5%DNP
R0402
5%
R0402
C8602 100nF
12
X5R 10V C0402
A1
A4
A8
+12V_4A2+12V_5A3GND_A4
PRSNT1#
JTAG_TCKA5JTAG_TDIA6JTAG_TDOA7JTAG_TMS
+12V_1B1+12V_2B2+12V_3B3GND_B4B4SMCLKB5SMDATB6GND_B7B7+3.3V_1B8JTAG_TRSTB93.3VAUX
DNP
+3.3V_2A9+3.3V_3
3
2
1
RC-->EP
PCIE30_REFCLKP_IN PCIE30_REFCLKN_IN
PCIE30_RC_RX0P PCIE30_RC_RX0N
PCIE30_RC_RX1P PCIE30_RC_RX1N
A10
A11
PERST#
WAKE#
B10
B11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
PERp0
PERn0
PERp1
PERn1
PERp2
GND_A12
REFCLK+
REFCLK-
GND_A15
GND_A18
GND_A20
RSVD_A19
RSVD_B12
GND_B13
PETp0
PETn0
GND_B16
PRSNT2#_1
GND_B18
PETp1
PETn1
GND_B21
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
PERn2
GND_A23
GND_A24
GND_B22
PETp2
PETn2
GND_B25
GND_B26
B23
B24
B25
B26
B27
C8600 220nF C0201 X5R 10V
1 2
C8601 220nF C0201 X5R 10V
1 2
C8603 220nF C0201 X5R 10V
1 2
C8604 220nF C0201 X5R 10V
1 2
A28
A29
A30
A31
A32
PERp3
PERn3
GND_A27
GND_A28
GND_A31
RSVD_A32
PETp3
PETn3
GND_B29
RSVD_B30
PRSNT2#_2
GND_B32
B28
B29
B30
B31
B32
R8603 22R
1 2
R8604 22R
1 2
R0402
R0402
5%
5%DNP
PCIE30_TX0P PCIE30_TX0N
PCIE30_TX1P PCIE30_TX1N
PCIE_ADDIN_PRSNT
RC<--EP
RC<--EP
V1.1
EP-->RC
PCIE30X2_WAKEn_M1
PCIE30X2_CLKREQn_M1 PCIE30X2_RC_CLKREQn_3V3_L
R8605 22R
1 2
R8606 22R
1 2
R0402
R0402
5%
5%
EP-->RC
A A
EP<--RC
EP<--RC
Rockchip Confidential
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4
PCIE30X2_RC_WAKEn_3V3_L
PCIE30_RX0P PCIE30_RX0N
PCIE30_RX1P PCIE30_RX1N
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
3
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
86.PCIE-PCIE3.0_1x2Lanes_EP_64P
86.PCIE-PCIE3.0_1x2Lanes_EP_64P
86.PCIE-PCIE3.0_1x2Lanes_EP_64P
1
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Sheet: of
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
Zhangdz
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
V1.1
V1.1
V1.1
63 72
63 72
63 72
Page 64
5
4
3
2
1
MiniPCIe2.0 Slot_Support 4G module
PCIE20_TXP PCIE20_TXN
PCIE20_RXP PCIE20_RXN
D D
C C
PCIE20_REFCLKP PCIE20_REFCLKN
PCIE20_CLKREQn_M1 PCIE20_WAKEn_M1 PCIE20_PERSTn_M1
USB2_HOST3_DP USB2_HOST3_DM
4G_DISABLE_GPIO4_C2
4G_PWREN_H_GPIO0_C6
PCIE20_CLKREQn_M1
PCIE20_WAKEn_M1
R8700 22R
1 2
R8701 22R
1 2
R8702 22R
1 2
R0402
R0402
R0402
5%
MINIPCIE20_CLKREQn_3V3_L
5%
MINIPCIE20_WAKEn_3V3_L
5%
MINIPCIE20_PERSTn_3V3_LPCIE20_PERSTn_M1
PCIE20_TXN PCIE20_TXP MINIPCIE20_TX_P
C8700 100nF
1 2
C8701 100nF
1 2
C0201 X5R 10V C0201 X5R 10V
MINIPCIE20_WAKEn_3V3_L
MINIPCIE20_CLKREQn_3V3_L
PCIE20_REFCLKN PCIE20_REFCLKP
PCIE20_RXN PCIE20_RXP
MINIPCIE20_TX_N
VCC3V3_MINIPCIE
TP8702TP_0.7 TP8703TP_0.7
1 3 5 7
9 11 13 15
17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
54
GND_54
WAKE# COEX1 COEX2 CLKREQ# GND_9 REFCLK­REFCLK+ GND_15
Reserved_17 Reserved_19 GND_21 PERn0 PERp0 GND_27 GND_29 PETn0 PETp0 GND_35 GND_37 +3.3Vaux_39 +3.3Vaux_41 GND_43 Reserved_45 Reserved_47 Reserved_49 Reserved_51
GND_53
53
6.7mm
58
+3.3Vaux_2
GND_4 +1.5V_6 UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
GND_18
W_DISABLE#
PERST#
+3.3Vaux_24
GND_26
+1.5V_28
SMB_CLK
SMB_DATA
GND_34 USB_D­USB_D+
GND_40 LED_WWAN# LED_WLAN# LED_WPAN#
+1.5V_48
GND_50
+3.3Vaux_52
GND_57
57
J8700 Mini_PCIe_Slot_2xSMTS02046CTJ
GND_5656GND_58
Mini_PCIe_Slot
2 4 6 8
R8703 22R
10
R8704 22R
12
R8705 22R
14 16
18
R8706 0R
20 22 24 26 28 30 32 34
MINIPCIE_USB_DM
36
MINIPCIE_USB_DP
38 40 42 44 46 48 50 52
GND_55
55
VCC3V3_MINIPCIE
UIM_PWR
1 2 1 2 1 2
1 2
VCC3V3_MINIPCIE
LED8700 LED_BLUE
LED0603
LED_WWAN
VCC3V3_MINIPCIE
Gnd
R04025%
UIM_DATA
R04025%
UIM_CLK
R04025%
UIM_RESET
R04025%
4G_DISABLE_GPIO4_C2 MINIPCIE20_PERSTn_3V3_L
TP8700 TP_0.7 TP8701 TP_0.7
R8707 0R
1 2
R8708 0R
1 2
R8709 510R
1 2
Gnd
R0402
R0402
R0402
5%
USB2_HOST3_DM
5%
USB2_HOST3_DP
5%
VCC3V3_MINIPCIE
SMTS02046CTJ
Gnd
Gnd
SMTS02046CTJ
VCC3V3_MINIPCIE VCC3V3_MINIPCIE VCC3V3_MINIPCIE VCC3V3_MINIPCIE
C8702 22uF
X5R
6.3V C0603
FB/OUT
C8703
12
100nF
X5R 10V
C0402
6
LX
1
BS
3
12
C8715 100nF
1 2
FB=0.6V
12
B B
VCC12V_DCIN VCC3V3_MINIPCIE
4.5V<VIN<18V
C8717
C8716
12
12
A A
100nF
10uF
X5R
X5R
25V
25V
C0402
C1206
4G_PWREN_H_GPIO0_C6
R8711 10K
R0402
1 2
5%
C8719
12
100nF
X5R 10V
C0402
U8700
5
VIN
2
GND
4
EN
SY8113B/SM8103ADC
SOT_23_6
C8704 10uF
X5R
6.3V C0603
12
X5R 25V
C0402
C8707 100nF
X5R 10V
C0402
L8700
4.7uH
IND_606045
C8705 22uF
X5R
6.3V C0603
C8708
12
100nF
X5R 10V
C0402
12
C8718 22pF
C0G 50V C0402
12
12
R8712 232K
1% R0402
12
R8713
49.9K
1% R0402
12
C8709 10uF
X5R
6.3V C0603
C8706
12
100nF
X5R 10V
C0402
12
+
C8720 120uF
SVPF 20V E_C6
UIM_CLK UIM_DATA UIM_RESET
UIM_PWR
C8721
12
10uF
X5R
6.3V C0603
Rockchip Confidential
5
4
3
UIM_PWR
C8710 1uF
X5R 10V C0402
C8711
12
33pF
C0G 50V
C0402
12
C8722
12
100nF
X5R 10V
C0402
12
R8710 15K
5% R0402
12
C8712
12
33pF
C0G 50V
C0402
C8714
C8713
12
12
33pF
33pF
C0G
C0G
50V
50V
C0402
C0402
D8700 ESD5341N
ESD0402
2
12
D8701 ESD5341N
ESD0402
12
D8702 ESD5341N
ESD0402
C9
CD
C3
CLK
C7
I/O
C2
RST
C6
VPP
C1
VCC
C5
GND
MSIM7_07HF-135B
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
2
GND2
GND1
1
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
87.MiniPCIe2.0 Slot_With 4G Fun
87.MiniPCIe2.0 Slot_With 4G Fun
87.MiniPCIe2.0 Slot_With 4G Fun
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
Zhangdz
4
GND4
C7 C3
C2
C1
C6
C5
GND3
3
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
1
J8701 SIM_CARD
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
64 72
Sheet: of
64 72
Sheet: of
64 72
Page 65
SGMII_TXP_M1 SGMII_TXN_M1
SGMII_RXP_M1 SGMII_RXN_M1
Default
Default
D D
C C
B B
GAMC1_MDIO_M0 FS_PHYRSTnGMAC1_RSTn_GPIO3_B0 GMAC1_MDC_M0
GMAC0_MDIO GMAC0_MDC
Default
A A
GAMC1-->MULTI_PHY2-->SGMII GAMC1_MDC/GAMC1_MDIO
Option
GMAC0-->MULTI_PHY2-->SGMII GAMC0_MDC/GAMC0_MDIO
Other route selection,Please refer to Rockchip_RK3568_Hardware_Design_Guide 2.3.6 description
VCC3V3_FS
VDD10_FS
VDD10_FS
VCC3V3_FS
GMAC1_MDC_M0 GAMC1_MDIO_M0
GMAC0_MDC
GMAC0_MDIO
GMAC1_INT/PMEB_GPIO3_A7 GMAC1_RSTn_GPIO3_B0
GMAC0_INT/PMEB_GPIO3_C0 GMAC0_RSTn_GPIO3_B7
FS_XTAL_IN FS_XTAL_OUT
FS_MDI_0P FS_MDI_0N
FS_MDI_1P FS_MDI_1N FS_MDI_2P FS_MDI_2N
FS_MDI_3P FS_MDI_3N
R8834 0R R8836 0R
R8838 0R R8839 0R
5
3.3V
Option
1.8V or 3.3V
Option
R8812 0R
1 2
VDD10_FS
R8813
2.49K
R0402
1 2 3 4 5 6 7 8
9 10 11 12
PHYRSTB is 3.3V IO
FS_PHYRSTn
1 2 1 2
1 2 1 2
(RGMII1 is not available at this time)
(RGMII0 is not available at this time)
U8801
AVDD33_1 MDI_0P MDI_0N AVDD10_4 MDI_1P MDI_1N MDI_2P MDI_2N AVDD10_9 MDI_3P MDI_3N AVDD33_12
12
1%
12
C8821 100nF
X5R 10V C0402
VCCIO_FS VCC3V3_FS
R04025% R04025%
R04025%DNP R04025%DNP
5%
R0402
41
43
44
45
46
47
48
RSET
CLKOUT
XTAL_IN
HSOP_CLK42HSON_CLK
AVDD10_47
XTAL_OUT/EXT_CLK
PHYTSTB13MDC14MDIO15TXD316TXD217TXD118TXD019TXCTL20TXC21DVDD10_2222RXD3/CFG_MODE223RXD2/CFG_MODE1
12
R8830
1.8K
5% R0402
FS_MDIO FS_MDC
FS_XTAL_OUT
C8800
12
18pF
C0G 50V C0402
FS_HSON
C8806 100nF
FS_HSOP
C8807 100nF
FS_HSIN
C8808 100nF
FS_HSIP
C8810 100nF
FS_LED2/CFG_LDO1
37
HSIP38HSIN39HSOP40HSON
LED2/CFG_LDO1
LED1/CFG_LDO0
LED0/PHYAD0 INTB/PMEB/GPIO1 PTP_CLKIN/GPIO0
REG_OUT VDD_REG
DVDD33_30
DVDD_RG
RXC/PHYAD1
RXCTL/PHYAD2
RXD0/RXDLY
RXD1/CFG_MODE0
EPAD
24
49
FS_RXD2/CFG_MODE1 FS_RXD3/CFG_MODE2
FS_MDIO FS_MDC
GMAC0_RSTn_GPIO3_B7
GMAC1_INT/PMEB_GPIO3_A7
GMAC0_INT/PMEB_GPIO3_C0
Rockchip Confidential
5
4
Y8800
1
X1
GND2X2
25MHz
CRY4_3R20X2R50X0R80
1 2 1 2
1 2 1 2
RTL8211FS-CG
QFN48_6R00X6R00X1R00_T
C0201 X5R 10V C0201 X5R 10V
C0201 X5R 10V C0201 X5R 10V
Note:
SGMII can choose: SGMII_TXP_M0/SGMII_TXN_M0 SGMII_RXP_M0/SGMII_RXN_M0 or SGMII_TXP_M1/SGMII_TXN_M1 SGMII_RXP_M1/SGMII_RXN_M1
See "07.UART Map/GMAC0/1 Path Map" GMAC0/1 Path Map
FS_LED1/CFG_LDO0
36
FS_LED0/PHYAD0
35
FS_INTB/PMEB
34 33
FS_REGOUT
32 31 30 29
FS_RXC/PHYAD1
28
FS_RXCTL/PHYAD2
27
FS_RXD0/RXDLY
26
FS_RXD1/CFG_MODE0
25
VDD10_FS
R8835 0R
1 2
R8837 0R
1 2
R8840 0R
1 2
R8841 0R
1 2
4
4
GND
FS_XTAL_IN
3
C8801
12
18pF
C0G 50V C0402
Diff 100 Ohm ±10%
SGMII_RXN_M1 SGMII_RXP_M1
SGMII_TXN_M1 SGMII_TXP_M1
Diff 100 Ohm ±10%
VCC3V3_FS VCCIO_FS
RTL8211FSI-CG Industrial
12
R8831 10K
5% R0402
DNP
5%
R0402
5%DNP
R0402
5%
FS_INTB/PMEB
R0402
5%DNP
R0402
3
R04025%
FS_MDI_3N
R8800 0R
FS_MDI_3P
FS_MDI_2N FS_MDI_2P
FS_MDI_1N FS_MDI_1P
FS_MDI_0N FS_MDI_0P
FSMDI_3N FSMDI_3P
FSMDI_2N FSMDI_2P
FSMDI_1N FSMDI_1P
FSMDI_0N FSMDI_0P
12
Voltage Config
1 2
R8801 0R
1 2
R8802 0R
1 2
R8803 0R
1 2
R8804 0R
1 2
R8805 0R
1 2
R8806 0R
1 2
R8807 0R
1 2
ED8800 UDD32C03L01
1 2
ED8801 UDD32C03L01
1 2
ED8802 UDD32C03L01
1 2
ED8803 UDD32C03L01
1 2
R8814
5%
LED8800
510R
12
R0402
LED_GREEN
LED0603
Net_Link_LED
FS_LED2/CFG_LDO1
C8815 100pF
C0G 50V
C0402
DNP
Reserve for EMI.
R8821 4.7K
R8822 4.7K
R8825 4.7K
R8827 4.7K
R8817
DNP
1 2
0R
R0402
12
R0402
12
R0402
12
R0402
12
R0402
5%
5%
5%
5%
5%
12
SOD_323 DNP
SOD_323 DNP
SOD_323 DNP
SOD_323 DNP
R8816 0R
1 2
LED8801
FS_LED1/CFG_LDO0
FS_LED2/CFG_LDO1
FS_LED0/PHYAD0
FS_RXC/PHYAD1
FS_RXCTL/PHYAD2
PHY Address Config
5%
R0402
FS_RXD0/RXDLY
R8828 4.7K
12
FSMDI_3N
R04025%
FSMDI_3P
R04025%
FSMDI_2N
R04025%
FSMDI_2P
R04025%
FSMDI_1N
R04025%
FSMDI_1P
R04025%
FSMDI_0N
R04025%
FSMDI_0P
12
C8803
C8802
10nF
10nF
X5R
X5R
25V
25V
C0402
C0402
FS_LED1/CFG_LDO0
5%
R0402
LED_Yellow
LED0603
Net_ACT_LED
Power Source External 3.3V (default) Internal 1.8V 2'b10
R8823 4.7K
DNP
R8824 4.7K
R8826 4.7K
DNP
PHY Address PHYAD[2:0]
1 (default) 3'b001
12
1 2
1 2
12
12
12
Pull-up for additional 2ns delay to RXC for data latching
PHY Operating Mode Config
R8833 4.7K
12
FS_RXD1/CFG_MODE0
FS_RXD2/CFG_MODE1
5%
FS_RXD3/CFG_MODE2
R0402
Operating Mode CFG_MODE[2:0]
UTP <=> RGMII
FIBER <=> RGMII
UTP/FIBER <=> RGMII
UTP <=> SGMII(default)
SGMII (PHY) <=> RGMII
SGMII (MAC) <=> RGMII
UTP <=> FIBER (AUTO)
UTP <=> FIBER (FORCE)
3
R8829 4.7K
R8832 4.7K
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
12
12
2
U8800
1
MCT1
TCT1
2
MX1+
TD1+
3
MX1-
TD1-
4
MCT2
TCT2
5
MX2+
TD2+
6
MX2-
TD2-
7
MCT3
TCT3
8
MX3+
TD3+
9
MX3-
TD3-
10 11 12
12
C8805
C8804
10nF
10nF
X5R
X5R
25V
25V
C0402
C0402
FSLAN_MCT1 FSLAN_MCT2 FSLAN_MCT3 FSLAN_MCT4
12
Reserve for EMI.
C8812
12
100pF
C0G 50V
C0402
DNP
5%
R0402
5%
R0402
5%
R0402
5%
R0402
5%
R0402
MCT4
TCT4
MX4+
TD4+
MX4-
TD4-
H5007
SOIC24_17R53X12R20X5R51
12
D8803
D8802
BS3500NCF
BS3500NCF
SMB_F
SMB_F
DNP
DNP
VCC3V3_FS
R8818
5%DNP
510R
R0402
R8819
5%
510R
R0402
CFG_LDO[1:0] 2'b00
VCC3V3_FS
VCC3V3_FS
VCCIO_FS
VCCIO_FS
VCCIO_FS
FSLAN_MCT1
24
FSLAN_D-
23
FSLAN_D+
22
FSLAN_MCT2
21
FSLAN_C-
20
FSLAN_C+
19
FSLAN_MCT3
18
FSLAN_B-
17
FSLAN_B+
16
FSLAN_MCT4
15
FSLAN_A-
14
FSLAN_A+
13
R8808 75R
5% R0805
12
D8800 BS3500NCF
SMB_F
DNP
VCC_3V3
R8815 0R
If use Internal 1.8V is DNP
R8820 0R
FS_REGOUT
Close to PIN30
RTL8211F-CG(SW Mode) RTL8211FI-CG(SW Mode)Industrial
2
12
12
R8809 75R
5% R0805
12
D8801 BS3500NCF
SMB_F
DNP
Default: 3.3V
1 2
1 2
L8800
2.2uH
IND_303015
R8810 75R
5% R0805
R0402
R0402
12
12
VCCIO_FS
5%
VCC3V3_FSVCC_3V3
5%
C8822
4.7uF
X5R 10V C0603
12
R8811 75R
5% R0805
12
C8809 1000pF
3KV CAP_D14P7R5_V
12
C8816
4.7uF
X5R 10V C0603
12
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
FSLAN_D­FSLAN_D+ FSLAN_B­FSLAN_C­FSLAN_C+ FSLAN_B+ FSLAN_A­FSLAN_A+
RJ45_5812-10P8C-A_Tab-Down
RJ45_5812-10P8C-A
High-tension area
Gap > 5mm
Low-tension area
VDD10_FS
C8823 100nF
X5R 10V
C0402
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
88.Ethernet-GEPHY_SGMII
88.Ethernet-GEPHY_SGMII
88.Ethernet-GEPHY_SGMII
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
Zhangdz
1
J8800
8
8
D-
7
7
D+
6
6
B-
5
5
C-
4
4
C+
3
3
B+
2
2
A-
1
1
A+
Close to PIN29
C8813
12
4.7uF
10V X5R C0603
Close to PIN1,12
12
C8817 100nF
X5R 10V
C0402
12
C8819
4.7uF
X5R 10V C0603
Close to PIN30,31
Close to PIN22
12
C8824 100nF
X5R 10V
C0402
12
C8825 100nF
X5R 10V
C0402
Close to PIN4,9,47
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
1
11
NC1
Tab down
NC2
12
FSLAN_CHASSIS_GND
12
FB8800 120R-100MHz
25% 2A L0603
C8814
12
100nF
X5R 10V
C0402
12
C8818 100nF
X5R 10V
C0402
12
C8820 100nF
X5R 10V
C0402
12
C8826 100nF
X5R 10V
C0402
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Sheet: of
9
G1
G2
10
12
C8811 1000pF
2KV C1206L
DNP
12
C8827 100nF
X5R 10V
C0402
V1.1
V1.1
V1.1
65 72
65 72
65 72
Page 66
5
QSGMII_TXP_M1
QSGMII_TXP_M1 QSGMII_TXN_M1
QSGMII_RXP_M1 QSGMII_RXN_M1
Default
GMAC1_MDC_M0 GAMC1_MDIO_M0
GMAC1_INT/PMEB_GPIO3_A7 GMAC1_RSTn_GPIO3_B0
GMAC0_MDC
D D
GMAC0_MDIO
GMAC0_INT/PMEB_GPIO3_C0 GMAC0_RSTn_GPIO3_B7
QSGMII_PWREN_H_GPIO0_C5
3.3V
Option
3.3V
C8900 100nF C0201 X5R 10V1 2
QSGMII_TXN_M1
C8901 100nF C0201 X5R 10V1 2
QSGMII_RXP_M1
C8902 100nF C0201 X5R 10V1 2
QSGMII_RXN_M1
C8904 100nF C0201 X5R 10V1 2
Default
GAMC0+GMAC1-->MULTI_PHY2-->QSGMII GAMC1_MDC/GAMC1_MDIO or GAMC0_MDC/GAMC0_MDIO (RGMII0/RGMII1 is not available at this time)
Option
GAMC0+GMAC1-->MULTI_PHY2-->QSGMII GAMC1_MDC/GAMC1_MDIO or GAMC0_MDC/GAMC0_MDIO (RGMII0/RGMII1 is not available at this time)
Other route selection,Please refer to Rockchip_RK3568_Hardware_Design_Guide 2.3.6 description
GAMC1_MDIO_M0 QSGMII_MDIO_M0 GMAC1_MDC_M0
GMAC0_MDIO GMAC0_MDC
GMAC0_RSTn_GPIO3_B7
GMAC1_INT/PMEB_GPIO3_A7 QSGMII_INT
GMAC0_INT/PMEB_GPIO3_C0
R8914 0R R04025%1 2 R8913 0R R04025%1 2
R8915 0R R04025%DNP1 2 R8916 0R R04025%DNP1 2
R8917 0R
R8919 0R
R8920 0R
R8921 0R
R0402
R0402
R0402
R0402
HSIP HSIN
HSOP HSON
QSGMII_MDC_M0
QSGMII_RSTnGMAC1_RSTn_GPIO3_B0
5%1 2
5%DNP1 2
5%1 2
od
5%DNP1 2
4
Note:
QSGMII can choose: QSGMII_TXP_M0/QSGMII_TXN_M0 QSGMII_RXP_M0/QSGMII_RXN_M0 or QSGMII_TXP_M1/QSGMII_TXN_M1 QSGMII_RXP_M1/QSGMII_RXN_M1
See "07.UART Map/GMAC0/1 Path Map" GMAC0/1 Path Map
RK3568 has only two Macs, so it only supports two RJ45
PHYADDR0/PHY0LED0
C8903
12
100pF
C0G 50V
C0402
DNP
PHY0LED1
C8909
12
100pF
C0G 50V
C0402
DNP
3
12
R8904 510R
5% R0402
12
R8918 510R
5% R0402
LED8900 LED_GREEN
LED0603
Net_Link_LED
LED8901 LED_Yellow
LED0603
Net_ACT_LED
PHY0_MDIDN
R8900 0R R04025%1 2
PHY0_MDIDP
R8901 0R R04025%1 2
PHY0_MDICN
R8902 0R R04025%1 2
PHY0_MDICP
R8903 0R R04025%1 2
PHY0_MDIBN
R8905 0R R04025%1 2
PHY0_MDIBP
R8906 0R R04025%1 2
PHY0_MDIAN
R8907 0R R04025%1 2
PHY0_MDIAP
R8908 0R R04025%1 2
PHY0_MDI_DN PHY0_MDI_DP
ED8900 UDD32C03L01
1 2
PHY0_MDI_CN PHY0_MDI_CP
ED8901 UDD32C03L01
PHY0_MDI_BN PHY0_MDI_BP
ED8902 UDD32C03L01
PHY0_MDI_AN PHY0_MDI_AP
ED8903 UDD32C03L01
1 2
1 2
1 2
SOD_323 DNP
SOD_323 DNP
SOD_323 DNP
SOD_323 DNP
PHY0_MDI_DN PHY0_MDI_DP
PHY0_MDI_CN PHY0_MDI_CP
PHY0_MDI_BN PHY0_MDI_BP
PHY0_MDI_AN PHY0_MDI_AP
12
12
C8905
C8906
10nF
10nF
X5R
X5R
25V
25V
C0402
C0402
2
U8900
1
TCT1
2
TD1+
3
TD1-
4
TCT2
5
TD2+
6
TD2-
7
TCT3
8
TD3+
9
TD3-
10
TCT4
11
TD4+
12
TD4-
12
12
C8908
C8907
H5007
10nF
10nF
SOIC24_17R53X12R20X5R51
X5R
X5R
25V
25V
C0402
C0402
QSLAN0_MCT1 QSLAN0_MCT2 QSLAN0_MCT3 QSLAN0_MCT4
12
D8900 BS3500NCF
SMB_F
DNP
MCT1 MX1+ MX1­MCT2 MX2+ MX2­MCT3 MX3+ MX3­MCT4 MX4+ MX4-
12
24 23 22 21 20 19 18 17 16 15 14 13
D8901 BS3500NCF
SMB_F
DNP
QSLAN0_MCT1 QSLAN0_D­QSLAN0_D+ QSLAN0_MCT2 QSLAN0_C­QSLAN0_C+ QSLAN0_MCT3 QSLAN0_B­QSLAN0_B+ QSLAN0_MCT4 QSLAN0_A­QSLAN0_A+
12
R8909 75R
5% R0805
D8903 BS3500NCF
SMB_F
DNP
12
12
12
R8910 75R
5% R0805
D8902 BS3500NCF
SMB_F
DNP
R8911 75R
5% R0805
12
12
R8912 75R
5% R0805
12
C8910 1000pF
3KV CAP_D14P7R5_V
1
J8900
QSLAN0_D-
8
QSLAN0_D+
7
QSLAN0_B-
6
QSLAN0_C-
5
QSLAN0_C+
4
QSLAN0_B+
3
QSLAN0_A-
2
QSLAN0_A+
1
RJ45_5812-10P8C-A_Tab-Down
RJ45_5812-10P8C-A
High-tension area
Gap > 5mm
Low-tension area
9
11
G1
NC1
8
D-
7
D+
6
B-
5
C-
Tab down
4
C+
3
B+
2
A-
1
A+
G2
NC2
10
12
QSLAN0_CHASSIS_GND
12
FB8900 120R-100MHz
25% 2A L0603
12
C8911 1000pF
2KV C1206L
DNP
10 11 12
12
C8915
C8916
10nF
10nF
X5R
X5R
25V
25V
C0402
C0402
12
D8905 BS3500NCF
SMB_F
DNP
R8948 0R
R8952 0R
R8955 0R
R8956 0R
C8935
12
1uF
X5R
6.3V C0402
R8959 0R
U8901
1
MCT1
TCT1
2
MX1+
TD1+
3
MX1-
TD1-
4
MCT2
TCT2
5
MX2+
TD2+
6
MX2-
TD2-
7
MCT3
TCT3
8
MX3+
TD3+
9
MX3-
TD3-
MCT4
TCT4
MX4+
TD4+
MX4-
TD4-
H5007
SOIC24_17R53X12R20X5R51
12
D8906 BS3500NCF
SMB_F
DNP
VCC1V05_QS_DVDDL
5%1 2
R0603
VCC1V05_QS_PLLVDDL
5%1 2
R0603
VCC1V05_QS_DVDDL1
5%1 2
R0603
VCC1V05_QS_SVDDL
5%1 2
R0603
VCC1V05_QS_AVDDL
5%1 2
R0603
24 23 22 21 20 19 18 17 16 15 14 13
12
12
12
12
12
12
C8923 10uF
X5R
6.3V C0603
C8931 1uF
X5R
6.3V C0402
C8933 1uF
X5R
6.3V C0402
C8936 1uF
X5R
6.3V C0402
C8938 10uF
X5R
6.3V C0603
QSLAN1_MCT1 QSLAN1_D­QSLAN1_D+ QSLAN1_MCT2 QSLAN1_C­QSLAN1_C+ QSLAN1_MCT3 QSLAN1_B­QSLAN1_B+ QSLAN1_MCT4 QSLAN1_A­QSLAN1_A+
R8939 75R
5% R0805
D8904 BS3500NCF
SMB_F
DNP
J8901
QSLAN1_D-
8
8
QSLAN1_D+ QSLAN1_B­QSLAN1_C­QSLAN1_C+ QSLAN1_B+ QSLAN1_A­QSLAN1_A+
12
12
12
12
C8924
12
1uF
X5R
6.3V C0402
C8932
12
1nF
X5R 50V
C0402
C8934
12
10nF
X5R 25V
C0402
C8937
12
1nF
X5R 50V
C0402
C8939
12
1uF
X5R
6.3V C0402
R8940 75R
5% R0805
D8907 BS3500NCF
SMB_F
DNP
C8925
12
10nF
X5R 25V
C0402
C8940
12
10nF
X5R 25V
C0402
R8941 75R
5% R0805
12
12
12
R8942 75R
5% R0805
12
C8918 1000pF
3KV CAP_D14P7R5_V
C8920 10nF
X5R 25V
C0402
C8941 10nF
X5R 25V
C0402
C8942
12
10nF
X5R 25V
C0402
D-
7
7
D+
6
6
B-
5
5
C-
4
4
C+
3
3
B+
2
2
A-
1
1
A+
RJ45_5812-10P8C-A_Tab-Down
RJ45_5812-10P8C-A
High-tension area
Gap > 5mm
Low-tension area
C8944
C8943
12
12
10nF
10nF
X5R
X5R
25V
25V
C0402
C0402
G1
NC1
Tab down
G2
NC2
10
12
QSLAN1_CHASSIS_GND
12
FB8901 120R-100MHz
25% 2A L0603
12
C8919 1000pF
2KV C1206L
DNP
9
11
PHYADDR[4:0] : 1b00000
R8922 4.7K R04025%1 2 R8925 4.7K R04025%DNP1 2
R8927 4.7K R04025%1 2
R8931 4.7K R04025%1 2 R8934 4.7K R04025%DNP1 2
R8936 4.7K R04025%1 2
R8938 4.7K R04025%1 2
QSGMII_XTALO QSGMII_XTALI
VCC1V05_QS_DVDDL
VCC3V3_QS_DVDDIO
R8943 4.7K R04025%1 2
R8944 4.7K R04025%1 2
R8945 4.7K R04025%DNP1 2
R8949 22R
U8903
1
DVDDL_1
2
MDIO
3
MDC
4
PHY3LED1
5
EN_PWRLIGHT/PHY3LED2
6
PHYADDR4/PHY3LED0
7
PHYADDR3/PHY2LED2
8
PHYADDR2/PHY2LED0
9
PHY2LED1
10
RESERVED/PHY1LED2
11
PHYADDR1/PHY1LED0
12
PHY1LED1
13
EN_PHY/PHY0LED2
14
PHY0LED1
15
PHYADDR0/PHY0LED0
16
nRESET
17
AVDDH_17
18
PHY0MDIAP
19
PHY0MDIAN
C C
Y8900
1
4
X1
GND
3
GND2X2
25MHz
C8928
12
CRY4_3R20X2R50X0R80
18pF
C0G 50V C0402
VCC3V3_QS_DVDDIO
B B
12
R8954
1.8K
5% R0402
VCC1V05_QS_DVDDL
VCC3V3_QS_DVDDIO
12
R8958 10K
5% R0402
DNP
QSGMII_RSTn
VCC3V3_QS_AVDDH
C8945
12
100nF
X5R 10V
C0402
C8929
12
18pF
C0G 50V C0402
QSGMII_MDIO_M0 QSGMII_MDC_M0
EN_PWRLIGHT/PHY3LED2 PHYADDR4/PHY3LED0 PHYADDR3/PHY2LED2 PHYADDR2/PHY2LED0
RESERVED/PHY1LED2 PHYADDR1/PHY1LED0 PHY1LED1 EN_PHY/PHY0LED2 PHY0LED1 PHYADDR0/PHY0LED0
PHY0_MDIAP PHY0_MDIAN
VCC3V3_QS_AVDDH
5%1 2
R0402
74
75
76
DVDDL_75
DVDDIO_76
PHYADDR0/PHY0LED0 PHY0LED1
EN_PHY/PHY0LED2
PHYADDR1/PHY1LED0 PHY1LED1
RESERVED/PHY1LED2
PHYADDR2/PHY2LED0
PHYADDR3/PHY2LED2
PHYADDR4/PHY3LED0
EN_PWRLIGHT/PHY3LED2
VCC1V05_QS_SVDDL
HSOP
HSIN
HSIP
67
68
70
72
HSIP69HSIN
SVDDL
XTALO73XTALI
AVDDH_7171RESERVED
EN_PHY
1: Enable PHY 0: Disable PHY
R8928 4.7K R04025%DNP1 2
RESERVED/PHY1LED2 Must Pull Low
R8946 4.7K R04025%1 2
EN_PWRLIGHT
1: Enable Power on LED light 0: Disable Power on LED light
VCC3V3_QS_AVDDH
VCC1V05_QS_AVDDL
HSON
59
60
64
65
HSON66HSOP
AVDDL_60
AVDDH_65
PHY4MDIBP58PHY4MDIBN
PHY4MDICP61PHY4MDICN62PHY4MDIDP63PHY4MDIDN
PHY4MDIAN PHY4MDIAP
AVDDH_55 DVDDL_54
INTERRUPT
AVDDH_52 AVDDL_51
AVDDH_48 PHY3MDIDN PHY3MDIDP PHY3MDICN PHY3MDICP
AVDDL_43 PHY3MDIBN PHY3MDIBP PHY3MDIAN PHY3MDIAP
Default:Disable Software configuration enable
VCC3V3_QS_DVDDIO
VCC3V3_QS_DVDDIO
57 56 55 54
QSGMII_INT
53 52 51
1 2
50
MDIREF
MDIREF
R8957 2.49K R04021%
49
AGND
48 47 46 45 44 43 42 41 40 39
VCC3V3_QS_AVDDH VCC1V05_QS_DVDDL1
VCC3V3_QS_AVDDH VCC1V05_QS_AVDDL
VCC3V3_QS_AVDDH
VCC1V05_QS_AVDDL
PHYADDR1/PHY1LED0
12
PHY1LED1
12
VCC5V0_SYS
12
C8921 10uF
X5R 10V C0603
VCC3V3_QS_VDDH
C8912 100pF
C0G 50V
C0402
DNP
C8917 100pF
C0G 50V
C0402
DNP
R8950 10K
R0402
12
R8932 510R
5% R0402
12
R8947 510R
5% R0402
1 2
5%
LED8902 LED_GREEN
LED0603
Net_Link_LED
LED8903 LED_Yellow
LED0603
Net_ACT_LED
12
PHY1_MDIDN
R8923 0R R04025%1 2
PHY1_MDIDP
R8924 0R R04025%1 2
PHY1_MDICN
R8926 0R R04025%1 2
PHY1_MDICP
R8929 0R R04025%1 2
PHY1_MDIBN
R8930 0R R04025%1 2
PHY1_MDIBP
R8933 0R R04025%1 2
PHY1_MDIAN
R8935 0R R04025%1 2
PHY1_MDIAP
R8937 0R R04025%1 2
PHY1_MDI_DN PHY1_MDI_DP
ED8904 UDD32C03L01
PHY1_MDI_CN PHY1_MDI_CP
PHY1_MDI_BN PHY1_MDI_BP
PHY1_MDI_AN PHY1_MDI_AP
ETA3409A/TCS4201:1.0uH/2A SY8089AAAC:2.2uH/2A
U8902
4
LX
VIN
2
GND
1
EN
FB/OUT
C8930
SY8089AAC
100nF
/ETA3409A/TCS4201
X5R
SOT_23_5 10V C0402
DNP
1 2
ED8905 UDD32C03L01
1 2
ED8906 UDD32C03L01
1 2
ED8907 UDD32C03L01
1 2
L8900
3
2.2uH
IND_404026
5
FB=0.6V
12
C8922 100pF
C0G 50V C0402
SOD_323 DNP
SOD_323 DNP
SOD_323 DNP
SOD_323 DNP
VCC1V05_QS_VDDL
12
R8951 27K
1% R0402
12
R8953 36K
1% R0402
PHY1_MDI_DN PHY1_MDI_DP
PHY1_MDI_CN PHY1_MDI_CP
PHY1_MDI_BN PHY1_MDI_BP
PHY1_MDI_AN PHY1_MDI_AP
12
12
12
C8914
C8913
10nF
10nF
X5R
X5R
25V
25V
C0402
C0402
QSLAN1_MCT1 QSLAN1_MCT2 QSLAN1_MCT3 QSLAN1_MCT4
C8927
C8926
12
12
100nF
22uF
X5R
X5R
10V
6.3V
C0402
C0603
PHY0MDIBP20PHY0MDIBN21AVDDL_2222PHY0MDICP23PHY0MDICN24PHY0MDIDP25PHY0MDIDN26AVDDH_2727PHY1MDIAP28PHY1MDIAN29PHY1MDIBP30PHY1MDIBN31AVDDL_3232PHY1MDICP33PHY1MDICN34PHY1MDIDP35PHY1MDIDN36PLLVDDL37AVDDH_38
A A
PHY0_MDIBP
PHY0_MDIBN
PHY0_MDICP
PHY0_MDICN
PHY0_MDIDP
PHY0_MDIDN
PHY1_MDIAP
PHY1_MDIAN
PHY1_MDIBP
PHY1_MDIBN
PHY1_MDICP
PHY1_MDICN
PHY1_MDIDP
VCC1V05_QS_AVDDL
VCC1V05_QS_AVDDL
VCC3V3_QS_AVDDH
VCC3V3_QS_AVDDH
Rockchip Confidential
5
EPAD
RTL8214C
38
77
QFN76_9R00X9R00X0R90_T
PHY1_MDIDN
VCC1V05_QS_PLLVDDL
4
VCC5V0_SYS
12
C8946 10uF
X5R 10V C0603
QSGMII_PWREN_H_GPIO0_C5
1 2
R8961 10K
5%
R0402
3
12
C8960 100nF
X5R 10V C0402
DNP
U8904
4
2
1
SY8089AAC
/ETA3409A/TCS4201
SOT_23_5
ETA3409A/TCS4201:1.0uH/2A SY8089AAAC:2.2uH/2A
3
LX
VIN
GND
5
EN
FB/OUT
L8901
2.2uH
IND_404026
FB=0.6V
12
C8947 100pF
C0G 50V C0402
VCC3V3_QS_VDDH
12
R8962
12
150K
1% R0402
12
R8963 33K
1% R0402
C8958 22uF
X5R
6.3V C0603
C8959
12
100nF
X5R 10V
C0402
2
R8960 0R
R8964 0R
VCC3V3_QS_AVDDH
5%1 2
C8948
R0603
12
10uF
X5R
6.3V C0603
VCC3V3_QS_DVDDIO
5%1 2
C8961
R0603
12
1uF
X5R
6.3V C0402
C8950
C8949
12
12
10nF
10uF
X5R
X5R
25V
6.3V
C0402
C0603
C8962
12
10nF
X5R 25V
C0402
C8952
C8951
12
12
10nF
10nF
X5R
X5R
25V
25V
C0402
C0402
Project:
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File:
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Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
C8954
C8953
12
12
10nF
10nF
X5R
X5R
25V
25V
C0402
C0402
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
89.Ethernet-GEPHY_QSGMII
89.Ethernet-GEPHY_QSGMII
89.Ethernet-GEPHY_QSGMII
Wednesday, J une 16, 2021
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Wednesday, J une 16, 2021
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C8956
C8955
12
10nF
X5R 25V
C0402
Rockchip Electronics Co., Ltd
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Rockchip Electronics Co., Ltd
Default
Default
Default
12
10nF
X5R 25V
C0402
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Sheet: of
C8957
12
10nF
X5R 25V
C0402
V1.1
V1.1
V1.1
66 72
66 72
66 72
Page 67
5
4
3
2
1
PWM3_IR
D D
IR Receiver
VCC3V3_PMU
12
R9000 10K
5%
PWM3_IR
C C
R9001 22R
1 2
C9000
12
1nF
X5R 50V C0402
R0402
R0402
5%
12
D9000 ESD5451N
ESD0402
DNP
OUT1G2VCC
IR9000 IRM_3638
IJ3_IRM_3638
3
VCC_IR VCC_3V3
R9002 22R
12
C9001 100nF
10V X5R C0402
12
C9002 10uF
X5R 10V C0603
R9003 22R
V1.1
12
12
5%DNP
R0402
VCC3V3_PMU
5%
R0402
B B
A A
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4
3
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
90.IR Receiver
90.IR Receiver
90.IR Receiver
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
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Rev:
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Rev:
V1.1
Rev:
V1.1
Sheet: of
67 72
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67 72
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67 72
Page 68
5
UART2_RX_M0_DEBUG UART2_TX_M0_DEBUG
4
3
2
1
D D
Debug UART2
VCC3V3_PMU
J9100
1
3.3V
UART2_RX_M0_DEBUG
UART2_TX_M0_DEBUG
C C
1 2
1 2
R9100 100R R04025%
R9101 100R R04025%
12
D9100 ESD5451N
ESD0402
12
D9101 ESD5451N
ESD0402
2
3
4
RX
TX
GND
CON4M_1X4_2R54_V
CN4M_2R54_V_DIP
B B
A A
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File:
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Date:
Date:
Designed by:
Designed by:
4
3
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
91.Debug UART
91.Debug UART
91.Debug UART
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
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Rev:
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Rev:
V1.1
Rev:
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68 72
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68 72
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Page 69
5
4
3
2
1
SARADC_VIN0_KEY/RECOVERY
SARADC_VIN4
D D
C C
SARADC_VIN5 SARADC_VIN6 SARADC_VIN7
RESETn
RK809_PWRON
Key Array
SARADC_VIN0_KEY/RECOVERY
12
Note:
If there is no Key requirement, It is suggested to reserve a SW9200 Key to facilitate the development debug
RECOVERY_Key function: If SARADC_VIN0=0V at after power on and reset, then system will enter into loader mode.
D9200 ESD5451N
ESD0402
ADC=9
R9200 100R
1 2
12
R9201 3K
1%
12
12
R0402
R9202
5.1K
1% R0402
R9203 12K
1% R0402
ADC=235
ADC=457
ADC=683
R0402
5%
2
112
3
4
3
G
2
112
3
4
3
G
2
112
3
4
3
G
2
112
3
4
3
G
SW9200 TS-1125S
4
SW5_6R20X6R20X2R50
5
V+/RECOVERY_Key
SW9201 TS-1125S
4
SW5_6R20X6R20X2R50
5
V-_Key
SW9202 TS-1125S
4
SW5_6R20X6R20X2R50
5
MENU_Key
SW9203 TS-1125S
4
SW5_6R20X6R20X2R50
5
ESC_Key
PowerOn/OFF_Key Reset_Key
RK809_PWRON
B B
R9204 100R
1 2
R0402
5%
2 3
1 2
112 4
3
G
D9201 ESD5451N
ESD0402
SW9204 TS-1125S
4
SW5_6R20X6R20X2R50
5
PowerOn/OFF_Key
RESETn
R9205 100R
1 2
R0402
5%
2 3
3
1 2
D9202 ESD5451N
ESD0402
112 4 G
SW9205 TS-1125S
4
SW5_6R20X6R20X2R50
5
Reset_Key
SARADC
J9200
1
SARADC_VIN4
Voltage range:0v-1.8V
A A
SARADC_VIN5 SARADC_VIN6 SARADC_VIN7
Rockchip Confidential
5
R9207 100R R04025%
1 2
R9208 100R R04025%
1 2
R9209 100R R04025%
1 2
R9210 100R R04025%
1 2
4
12
D9203 ESD5451N
ESD0402
12
D9204 ESD5451N
ESD0402
12
D9205 ESD5451N
ESD0402
3
12
D9206 ESD5451N
ESD0402
1
2
2
3
3
4
4
5
5
6
6
CON6M_1X6_2R54_V
CN6M_2R54_V_DIP
Rockchip Electronics Co., Ltd
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2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
92.KEY Array/SARADC
92.KEY Array/SARADC
92.KEY Array/SARADC
Wednesday, June 16, 2021
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Wednesday, June 16, 2021
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V1.1
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Page 70
5
4
3
2
1
Working_LEDEN_H_GPIO0_B7
SARADC_VIN1_HW_ID
SARADC_VIN3_BOM_ID
D D
Working_LEDEN_H_GPIO0_B7
C C
HW_ID
SARADC_VIN1 Up
VCCA_1V8 VCCA_1V8
HW_ID0
12
R9303 10K
1%
B B
SARADC_VIN1_HW_ID SARADC_VIN3_BOM_ID
R0402
12
R9305 10K
1% R0402
DNP
HW_ID1
HW_ID2
HW_ID3
HW_ID4
HW_ID5
HW_ID6
HW_ID7
HW_ID8
Resistance
10K DNP
20K 100K
HW_ID9
HW_ID10
100K 20K
HW_ID11
HW_ID12
Down Resistance
110K10K
100K33K
36K18K
51K36K
51K51K
36K51K
18K36K
33K100K
10K110K
10KDNP
Working LED
BOM_ID
12
R9304 10K
1% R0402
12
R9306 10K
1% R0402
DNP
R9301
1 2
10K
5%
R0402
SARADC_VIN3 Up
BOM_ID0
BOM_ID1
BOM_ID2
BOM_ID3
BOM_ID4
BOM_ID5
BOM_ID6
BOM_ID7
BOM_ID8
BOM_ID9
BOM_ID10
BOM_ID11
BOM_ID12
Resistance
10K DNP
20K 100K
100K 20K
12
R9302 51K
R0402 5%
VCC3V3_SYS
12
1
2 3
Down Resistance
110K10K
100K33K
36K18K
51K36K
51K51K
36K51K
18K36K
33K100K
10K110K
10KDNP
R9300 1K
5% R0402
LED9300 LED_BLUE
LED0603
Working_LED
Q9300 S8050
SOT_23
A A
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3
2
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RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
93.LED/HW_ID/BOM_ID
93.LED/HW_ID/BOM_ID
93.LED/HW_ID/BOM_ID
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V1.1
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70 72
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Page 71
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UART9_TX_M1 UART9_RX_M1
UART4_RX_M1 UART4_TX_M1
UART3_TX_M1 UART3_RX_M1
UART7_TX_M1 UART7_RX_M1
D D
RS485_DIR_GPIO3_B5
UART6_TX_M1
UART6_RX_M1
CAN0_TX_M1 CAN0_RX_M1
4
3
2
1
UART3_M1
VCC_3V3 VCC_3V3
J9500
1
2
3
4
CN4M_2R54_V
CN4M_2R54_V_P_DIP
VCC_3V3 VCC_3V3
J9501
1
2
3
4
CN4M_2R54_V
CN4M_2R54_V_P_DIP
12
12
C9500 100nF
X5R 10V
C0402
C9502 100nF
X5R 10V
C0402
UART4_M1
UART4_RX_M1
UART4_TX_M1
R9503 100R
1 2
R9504 100R
1 2
ED9502 ESD5451N
ESD0402
R0402
R0402
Default, and GMAC0 RST/INT Option
UART3_RX_M1
UART3_TX_M1
VCC_3V3
J9502
5%
5%
12
12
ED9503 ESD5451N
ESD0402
1
2
3
4
VCC_3V3
CN4M_2R54_V
CN4M_2R54_V_P_DIP
C9501
12
100nF
X5R 10V
C0402
UART9_M1
Default, and SATA LED0/1 Option
UART9_RX_M1
UART9_TX_M1
R9500 100R
1 2
R9501 100R
1 2
R9502 100R
1 2
R9505 100R
1 2
R0402
R0402
R0402
R0402
5%
5%
5%
5%
ED9500 ESD5451N
ESD0402
ED9504 ESD5451N
ESD0402
12
12
ED9501 ESD5451N
ESD0402
12
12
ED9505 ESD5451N
ESD0402
12
R9530
4.7K
5% R0402
VCC_3V3VCC3V3_485
R04025%
SOD_323
R0805
R0805
R9507 60.4R
1 2
R9510 60.4R
1 2
5%
5%
U9501
5
1
4
8
TCAN1044V-Q1
SOP8_5R00X4R00X1R75
SOIC (8)
TXD:transmit data input RXD:receiver data output
VCC
VIO
TXD
CANH
RXD
CANL
GND
S
12
3
7
6
2
ED9508 ESD5451N
ESD0402
R1206
R1206
12
12
C9509 100nF
X5R 10V C0402
1%
1 2
1%
ED9509 ESD5451N
ESD0402
12
C9504
4.7nF
X5R 50V C0402
RS485_B_D-
RS485_A_D+
12
FB9500
C9506
12
C9510
4.7uF
X5R 10V C0603
R9527 0R
R9529 0R
120R-100MHz
100nF
25%
X5R
2A
50V
L0603
C0603
R9521 0R
1 2
R9523 0R
1 2
1 2
1 2
3
J9504
1
2
3
4
CN4M_2R54_V
CN4M_2R54_V_P_DIP
VCC_3V3
5%DNP
R0402
VCC_5V0
5%
R0402
5%
R0805
5%
R0805
UART6_M1-Option
If no MicroSD Card function:
UART6_RX_M1
UART6_TX_M1
TCAN332G:PIN3=3.3V,PIN5,8=NC
TCAN1044V-Q1:PIN3=5V,PIN5=VIO,PIN8=S
1%
R1206
1%
R1206
12
ED9511 ESD5341N
ESD0402
2
CANH
CANL
CAN_VSS
R9524 60.4R
1 2
R9525 60.4R
1 2
12
C9516
C9515
12
12
47pF
C0402 C0G 50V
DNP
47pF
C0402 C0G 50V
DNP
ED9510 ESD5341N
ESD0402
R9512 100R
1 2
R9514 100R
1 2
C9511
4.7nF
1 2
X5R 50V C0402
R0402
R0402
ED9507 ESD5451N
ESD0402
12
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
Designed by:
5%
5%
12
12
ED9506 ESD5451N
ESD0402
12
FB9501
C9512
120R-100MHz
100nF
25%
X5R
2A
50V
L0603
C0603
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
95.UART/RS485/CAN Port
95.UART/RS485/CAN Port
95.UART/RS485/CAN Port
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
Zhangdz
VCC_3V3 VCC_3V3
J9503
1
2
3
4
CN4M_2R54_V
CN4M_2R54_V_P_DIP
J9505
1
CANH
CANL
CANH
CANL
CAN_VSS
Reviewed by:
Reviewed by:
Reviewed by:
1
2
2
3
3
CN3M_2R54_V
CN3M_2R54_V_DIP
J9506
1
1
2
2
3
3
CN3M_2R54_V
CN3M_2R54_V_DIP
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Default
Default
Default
1
C9505
12
100nF
X5R 10V
C0402
Rev:
V1.1
Rev:
V1.1
Rev:
V1.1
Sheet: of
71 72
Sheet: of
71 72
Sheet: of
71 72
UART7_M1 To RS485
C C
VCC_3V3
12
R9508 10K
R0402 5%
U9500
DNP
UART7_RX_M1
RS485_DIR_GPIO3_B5
UART7_TX_M1
B B
R9513 22R
1 2
R9515 0R
1 2
R9517 22R
1 2
DNP
R9518
1 2
5%
10K
R0402
R0402
R0402
R0402
12
1
R9520 51K
R0402 5%
DNP
5%
1
2 3
Q9500 S8050
SOT_23
DNP
RO
2
RE#
3
DE
4
DI
SIT3485E
SOP8_4R00X5R00x1R75
5%
5%
C9503
12
100nF
X5R 10V
C0402
8
VCC
7
B
6
A
5
GND
R9506 0R
1 2
D9500 B5819WS
12
R9509
3.3K
R0402
JK250-180T
5%
R9511 0R
1 2
R9516 0R
1 2
JK250-180T
12
R9519
3.3K
R0402 5%
CAN0_M1-Option
If no MicroSD Card function:
VCC_3V3 VCC3V3_CAN VCC_CAN
R9522 0R
1 2
CAN0_TX_M1
CAN0_RX_M1
A A
R9526 22R
1 2
R9528 22R
1 2
R04025%
R04025%
Rockchip Confidential
5
5%
R0402
C9507
12
12
4.7uF
C9508
X5R
100nF
10V
X5R
C0603
10V C0402
C9514
C9513
12
12
12pF
C0402 C0G 50V
DNP
12pF
C0402 C0G 50V
DNP
12
4
Page 72
5
4
3
2
1
H9900 HOLE_3R20
HOLE_C3R20_C6R00
1
D D
H9904 HOLE_3R20
HOLE_C3R20_C6R00
1
C C
H9901 HOLE_3R20
HOLE_C3R20_C6R00
1
H9905 HOLE_3R20
HOLE_C3R20_C6R00
1
H9902 HOLE_3R20
HOLE_C3R20_C6R00
1
H9906 HOLE_3R20
HOLE_C3R20_C6R00
1
H9903 HOLE_3R20
HOLE_C3R20_C6R00
1
H9907 HOLE_3R20
HOLE_C3R20_C6R00
1
J9900
2
Radiator_38x38
Radiator_38RX38RX10R
1
B B
TOP Mark BOTTOM Mark
M9900
A A
MARK
MARK
M9901 MARK
MARK
M9902 MARK
MARK
M9903 MARK
MARK
M9904 MARK
MARK
Rockchip Confidential
5
M9905 MARK
MARK
Project:
Project:
Project:
File:
File:
File:
Date:
Date:
Date:
Designed by:
Designed by:
4
3
2
Designed by:
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
RK3568_AIoT_REF_SCH
99.Mark/Hole/Heatsink
99.Mark/Hole/Heatsink
99.Mark/Hole/Heatsink
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Wednesday, June 16, 2021
Zhangdz
Zhangdz
Zhangdz
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rockchip Electronics Co., Ltd
Rev:
Rev:
Rev:
Sheet: of
Sheet: of
Reviewed by:
Reviewed by:
Reviewed by:
Default
Default
Default
Sheet: of
1
V1.1
V1.1
V1.1
72 72
72 72
72 72
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