Roadstar tlp 1071xl schematic

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- TLP-1071XL

- TLP-1071XL

TLP-1071XL

Service Manual

Service Manual

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ALlGNMENTPROCEDURES I

REGULATORADJUSTMENT

MAY RESULT IN DAMAGE TO THE HORIZONTAL OUTPUTTRANSISTOR OR PULSE LlMITER

DI ODE.

THE FOLLOWING PROCEDURES ARE RECOMMENDED TO INSURE SAFE OPERATION.

1. CONNECT THE TV TO AC 11 0-240V THEN ADJUST THE AC SWITCHING MODE POWER REGULA-

2. CONNECT A DC DIGITAL VOL TMTER OR OTHER PRECISION ACCURACY VOL METER TO THE

HORIZONTAL OSCILLATOR
ADJUSTMENT

1. POWER ADJUSTMENT
ADJUST THE REGULATOR VPO1 TO DC 10.8V.

2. VERTICAL HIGHTNESS ALlGNMENT
ADJUST THE VERTICAL HIGHTNESS VRV1 & VRV2, ENABLE THE CIRCLE OF PICTURE APPRO-

ADJUST HORIZONTAL POSITION VRH1, LET THE SQUARE SIGNAL IN THE CENTER OF THE

SCREEN.

4. RF AGC ALiGMENT
ADJUST VIF PROCESS AGC CONTROL VRI1 AT INPUT SIGNAL INTENSITY 50dB, THE SCREEN

COULD LOOKING CLEAR AND 80dB,THE SCREEN DON'T INFLECT.

5. WHITE BALANCE ALlGNMENT

ADJUST THE VRY4, VRY5, AT CENTER POSITION. ADJUST SCREEN VR, LET THE SCREEN
WILL BE LITTLE BRIGHTNESS. ADJUST VRY4 LET THE SCREEN TO BE YELLOW, AND THEN
ADJUST VRY5 LET THE SCREEN APPROACH TO WHITE.

6. FOCUS ADJUSTMENT
ADJUST FOCUS VR, LET THE STRIP IN THE SCREEN TO BE CLEAR.

7. SCREEN ADJUSTMENT

ADJUST SCREEN VR LET THE BRIGHTNESS SUIT AS DESIRED.

A MA TCHING PAD.

OSCILLOSCOPE : CONNECT TO THE ICA1 PIN 2.

ALlGNMENTPROCEDURE

Don't Adjust System BIG I H 33.4 MHz, Connect to the

(Please check) System M,N 41.25 MHz, ICA1 PIN 2

System I 33.5 MHz,

System D,K,

32.4 MHz, 1 Khz FM
Mod deviation

25 kHz 80 dB output.

3. VERTICAL DEFLECTION ALlGNMENT
(1) TUNE THE RECEIVER IN A TEST PATTERN.

WHEN THE INSIDE OF THE LARGEST CIRCLE OF TEST PATTERN REACHES
NEAR ROUND PATTERN. (SEE THE FIGURE)

(3) IF THE PATTERN NOT AT CENTER POSITION, ADJUST V-POSITION CONTROL

VRV2 (5K OHM).

IPICTURE SCREEN I

THE LARGEST PATTERN

IC BLOCK DIAGRAM I

2. IF demodulator tuned circuit 6.1 V 28. B. Y input signal 3.9 V

3. IF demodulator tuned circuit 6.1 V 29. R-Y input signal 3.9 V

4. Video identification output 4.2 V 30. R- Y output signal 1.5 V

5. Sound IF input and volume contrai 3.4 V 31. B- Y output signal 1.5 V

6. External audio input 3.8 V 32. O V

7. IF video output 3.1 V 33. Loop filter burst phase detector 4.6 V

8. Decoupling digital supply 1.8 V 34. 3.58 MHz XTAL connection 2.1 V

9. Ground 1 O V 35. 4.43 MHz XTAL connection 3.4 V

10. Positive supply voltage 8.2 V 36. Start horizontal oscillator 8.4 V

11. Ground 2 O V 37. Horizontal output 1.4 V

12. Decoupling filter tuning 3.3 V 38. Flyback inputlsandcastle output 1.2 V

13. Internai CVBS input 4.2 V 39. Phase 2 loop filter 3.3 V

14. Peaking contrai input 3.1 V 40. Phase 1 loop filter 3.6 V

15. External CVBS input 3.4 V 41. Vertical feedback input 2.2 V

16. Chrominance and AN switch input O V 42. Vertical ramp generator 2.9 V

17. Brightness contrai input 5.1 V 43. Verticaloutput 2.3 V

18. B output 1.8 V 44. AFC output 5.7 V

19. G output 1.8 V 45. IF input 1 4.1 V

20. R output 1.8 V 46. IF input 2 4.1 V

21. RGB insertion and blanking input 0.2 V 47. TunerAGC output 3.6 V

22. R input 3.3 V 48. AGC decoupling capacitor 4.1 V

23. G input 3.3 V 49. Tuner take-over adjustment 1.7 V

24. B input 3.3 V 50. Audio output 3.5 V

25. Contrast contrai input 1.2- 3.6 V 51. Decoupling sound demodulator 5.5 V

26. Saturation contrai input 0.5- 4.2 V 52. Decoupling bandgap supply 6.6 V

CLOCHE PlL

b 100.nF no nF:h

7 8 J 6 2

L~~=:J TOA8395

cves 16 OE-

FILTER EJAPH"SIS

EST..=. P-

INTE OUTPUT

IFICATION STAGE IO

1 1

lref/ICENT SANO

PINNING

f,.uIDENT 1 referencs trequency input/identification incut

TEST 2 lesI oUtput

ICEHT es V p 3 positive supply voltage

TEST ANO n.c. 4. not connected

vp .c- n.c. 5 not connected

".c- .c- GND 6 I ground

".~ ~ CLOCHE,., 7 C1oc!1e relerence lilter

GNO .c- PLL,., a PLL reference

,.. .,CHe" -(A-Y) 9 -(A-Y) output

...'-" -_I -{e-V')

~L'-..ef -{R-V')

_'7 n.c. 12 not connected

-(8- Y) 10 -(B- Y) output

n.c. 11 not connected

9 -{R-Y)

-{e-Y)

_'6

n.c. 13 not connected
n.c. 14 not connected

Fig.2 Pin conliguration SANO 15 sandcastle pulse input

CV8S 16 I video (c!1rominance) input

t(R-Y) -f C~G

~--[~~J---+G Il UNE SAMPLE- t(B-Y}

MEMOAY ~~D LP

cckxJC -{ijn -enca

Inpu .;...nal- pc&-amplliets

I --addIlion QUIPUt coIOUl- dilletenca

) 1 SIGNAL

ay

SAMPlE- t{B-Y}

ANO.

V P1 an&kJo supply Z n.c.

sandcasda OETECTOR

puise InpUt

9

5

SA NOCA STl 15 .n.c.

O diQilal suppiy I ~. 8

NOI

HOLO

3 MHz shihino clod< TDA4661 6 n.c.

6MHz 7 -I.c.

VCO

bul/8fs QutpUI Slçnals

13 n.c.

SYMBOL PTN CESCRIFnON.

V Pio 1 +5 V SUPp/y voltage for digilaJ part
n.c: 2 not connected

GNO2. 3 ground far digitaJ part lO V)

i.c. 4 intemaJly conn9cted v
SANO 5 sandcastle pulsa inpui

n.c. 6 noi conneded G
i.c. ì inlemally conneded I.c. n.c.
i.c. B inlemally connecled SANO v'(8-y)

V P1 9 +5 V' supply vollage for analog part n.c. V. (R-Y)
GNO1 10 ground for anaJog part (O V) i.c. GNO1
Va R.Y) 11 :f:(R-Y) OUlput signaJ i.c. vf'1

Va (e:;Y) 12 :f:(B-Y} OUtpJl signaJ
n.-c. 13 noI connected
VI (B-V) 14 :t(B-Y) inptrt signaJ
n.c. 15 noi connected

n.c. n.c.

N02 V

"EHla

V.~ 1(~Y)

1(8-Y)

VI (R:'V) 16 :t(R-Y) input signaJ Fig.2 Pin configuralion.

Vcc Ze ZA Y1A YOA SA Se Sc

HEF40538 Y1A to Y1C independent inputs/outputs

PINNING

Y OA to YOC independent inpu'tS/oUtputs

7U9S0S

HEF40538P{N): 16-lead DIL; plastic

(SOT38-1)

(SOn 4)

HEF40538T(D): 16-lead SO; plastic

(SOT109-1) Yn

( ): Package Designator North America

E enable input (active LOW)

n

7Z82376.1

Fig. 3 Schematic diagram (one switch).

88"d~-~

8end CmtrQ C~ Driver

V1N, V!N,

11'1

11:2

'?

2 5W2

O 5Wrra-f OPERA ~

.O. s: t8 8tk:s ~

VI (-) 1 ~ L L- Y"-I
I. Ir. ~ (~) ~ ~ -La. L. V1(~) 3 ~ H L V,,-z

1..1r. -(&;c) ~ ~ ~. L. L.
V7 (-) ~ 1 L H V"-1

1,.1.1. (&;c) ~ ~ 44l-.

VI (~) ~ 3 H H V,.-1
119~1r (&;c) ~ ~ 4 ~ L
V-nf 1 1 L H-L V.(D'f L8J (114)

V1t. 1 1 L L-H V.(D3L8J(1I4)

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