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Rx5C348A
Technical data
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RICOH Rx5C348A, Rx5C348B Technical data

’11.04.13
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4-wire Serial Interface
Rx5C348A/B
OUTLINE
Package 32-kHz Clock Output
RS5C348A Controllable by command RS5C348B RV5C348A Controllable by command RV5C348B RT5C348B TSSOP10G (Pin Pitch 0.5mm, Height0.85mm,
(Limited)
SSOP10 (Pin Pitch 0.5mm, Height1.25mm,
6.4mm×3.5mm) SSOP10G (Pin Pitch 0.5mm, Height1.2mm,
4.0mm×2.9mm)
4.0mm×2.9mm)
Keeping output enabled Keeping output enabled
Keeping output enabled
FEATURES
Timekeeping supply voltage ranging from 1.45 to 5.5V
Low power consumption Rx5C348A: 0.35µA TYP (0.8µA MAX)
Rx5C348B: 0.55µA TYP (1.0µA MAX)
Only four signal lines (CE, SCLK, SI, and SO) required for connection to the CPU.
Maximum clock frequency of 2 MHz (with VDD = 5V)
Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days, and weeks) (in BCD format)
Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to the CPU and provided with an interrupt flag and an interrupt halt
2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and minute alarm settings)
32-kHz clock output circuit (Nch. open drain output)
The Rx5C348A is designed to disable 32-kHz clock output in response to a command from the host computer and the Rx5C348B is designed to keep 32-kHz output enabled.
Oscillation halt sensing circuit which can be used to judge the validity of internal data
Supply voltage monitoring circuit with two supply voltage monitoring threshold settings
Automatic identification of leap years up to the year 2099
Selectable 12-hour and 24-hour mode settings
Built-in oscillation stabilization capacitors (CG and CD)
High precision oscillation adjustment circuit
Ultra-compact SSOP10 (RS5C348A/B), SSOP10G (RV5C348A/B), TSSOP10G (RT5C348B) (Limited)
CMOS process
The products scheduled to be discontinued (be sold to limited customer) : "Limited" These products will be discontinued in the future. You can not select these products newly. We will provide these products to the customer who has been using or has ordered them before. But we recommend changing to other products as soon as possible.
at VDD=3V
at VDD=3V
Rev.2.01 - 1 -
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Rx5C348A/B
PIN CONFIGURATION
32KOUT
SCLK
SO
Rx5C348A/B
1 2
3 4
SI
56
10
9 8 7
VDD OSCIN OSCOUT CE
/INTRVSS
BLOCK DIAGRAM
32KOUT
OSCIN
OSCOUT
/INTR
32kHz
OUTPUT
CONTROL
OSC
OSC
DETECT
DIVIDER
CORREC
-TION
INTERRUPT CONTROL
DIV
TOP VIEW
COMPARATOR_W
COMPARATOR_D
(SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)
ADDRESS DECODER
TIME COUNTER
ADDRESS
REGISTER
SHIFT REGISTER
ALARM_W REGISTER
(MIN,HOUR, WEEK)
ALARM_D REGISTER
(MIN,HOUR)
CONTROL
I/O
VDD
VOLTAGE
DETECT
VSS
SCLK SI
SO
CE
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Rev.2.01 - 2 -
Rx5C348A/B
PIN DESCRIPTION
Symbol Item Description CE Chip enable
Input
SCLK Serial Clock
Input
SI Serial Input The SI pin is used to input data intended for writing in synchronization with
SO Serial Output The SO pin is used to output data intended for reading in synchronization
/INTR Interrupt
Output
32KOUT 32kHz Clock
Output
OSCIN OSCOUT
VDD VSS
Oscillation Circuit Input / Output Positive/Negative Power Supply Input
The CE pin is used for interfacing with the CPU. Should be held high to allow access to the CPU. Incorporates a pull-down resistor. Should be held low or open when the CPU is powered off. Allows a maximum input voltage of 5.5v regardless of supply voltage. The SCLK pin is used to input clock pulses synchronizing the input and output of data to and from the SI and SO pins. Allows a maximum input voltage of 5.5v regardless of supply voltage.
the SCLK pin. CMOS input. Allows a maximum input voltage of 5.5v regardless of supply voltage.
with the SCLK pin. CMOS output.
The /INTR pin is used to output alarm interrupt (Alarm_W) and alarm interrupt (Alarm_D) and output periodic interrupt signals to the CPU signals. Disabled at power-on from 0V. N-channel open drain output. Allows a maximum pull-up voltage of 5.5v regardless of supply voltage. The 32KOUT pin is used to output 32.768-kHz clock pulses. Enabled at power-on from 0 volts. Nch. open drain output. The Rx5C348A is designed to disable 32-kHz clock output in response to a command from the host computer and the Rx5C348B is designed to keep 32-kHz output enabled. The OSCIN and OSCOUT pins are used to connect the 32.768-kHz crystal oscillator (with all other oscillation circuit components built into the Rx5C348A/B).
The VDD pin is connected to the power supply. The VSS pin is grounded.
Rev.2.01 - 3 -
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Rx5C348A/B
ABSOLUTE MAXIMUM RATINGS
(VSS=0V)
Symbol Item Pin Name Description Unit
VDD Supply Voltage 2 VDD -0.3 to +6.5 V VI Input Voltage CE, SCLK, SI -0.3 to +6.5 V
Output Voltage 1 SO -0.3 to VDD + 0.3 V VO
Output Voltage 2 /INTR, 32KOUT -0.3 to +6.5 V PD Power Dissipation Topt Operating Temperature -40 to +85 Tstg Storage Temperature -55 to +125
Topt = 25°C
300 mW
°C °C
RECOMMENDED OPERATING CONDITIONS
(VSS=0V, Topt=-40 to +85°C)
Symbol Item Pin Name Min. Typ. Max. Unit Vaccess Supply Voltage Power supply voltage
for interfacing with CPU
VCLK Time keeping Voltage fXT Oscillation Frequency 32.768 kHz
VPUP Pull-up Voltage /INTR, 32KOUT 5.5 V
1.45 5.50 V
2.0 5.5 V
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Rev.2.01 - 4 -
Rx5C348A/B
DC ELECTRICAL CHARACTERISTICS
(Unless otherwise specified: VSS=0V, VDD=3.0V, Topt=-40 to +85°C, Crystal oscillator 32768Hz,CL=7pF,R1=30kΩ)
Symbol Item Pin Name Conditions Min. Typ. Max. Unit
VIH “H” Input Voltage 0.8x VIL “L” Input Voltage IOH “H” Output
Current
IOL1 /INTR,
IOL2
IIL Input Leakage RDNCE Pull-down Resistance CE 40 120 400
IOZ1 SO VO=5.5V or VSS IOZ2 IDD
(Rx5C34 8A)
IDD (Rx5C34 8B)
VDETH Supply Voltage VDETL Supply Voltage CG Internal Oscillation
“L” Output Current
Current
Output Off-state Current
Time Keeping Current
Monitoring Voltage “H” Monitoring Voltage “L” Capacitance 1
CE, SCLK, SI VDD=2.0 to 5.5V
VDD
-0.3 0.2x
SO VOH=VDD-0.5V -0.5 mA
VOL=0.4V 32KOUT(Rx5C348A ) SO, 32KOUT(Rx5C348B ) SI, SCLK VI=5.5V or VSS
VDD=5.5V
VDD=5.5V /INTR, 32KOUT VO=5.5V
VDD=5.5V VDD VDD=3V,
CE= OPEN
Output = OPEN
32KOUT=OFF
*1) VDD VDD=3V,
CE= OPEN
Output = OPEN
32KOUT=ON VDD
VDD OSCIN 12
Topt=-30 to +70°C
Topt=-30 to +70°C
2.0
0.5
-1.0 1.0
-1 1
-1 1
0.55 1.00
1.90 2.10 2.30
1.45 1.60 1.80
5.5
VDD
0.35 0.80
V
mA
µA kΩ
µA
µA
V
pF
CD Internal Oscillation
Capacitance 2
*1) For time keeping current when outputting 32.768kHz from the 32KOUT pin, see “P.40. Typical Characteristics”.
Rev.2.01 - 5 -
OSCOUT 12
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Rx5C348A/B
AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified: VSS=0V,Topt=-40 to +85°C Input and Output Conditions: VIH=0.8×VDD,VIL=0.2×VDD,VOH=0.8×VDD,VOL=0.2×VDD,CL=50pF
Symbol Item Condi-
tions
t
CE Set-up Time 400 200 ns
CES
t
CE Hold Time 400 200 ns
CEH
tCR CE Recovery Time 62 62 f
SCLK Clock
SCLK
1.0 2.0 M
Frequency
t
SCLK Clock High
CKH
400 200 ns
Time
t
SCLK Clock Low
CKL
400 200 ns
Time
t
SCLK Set-up Time 200 100 ns
CKS
tRD Data Output Delay
300 150 ns
Time
tRZ Data Output Floating
300 150 ns
Time
t
Data Output Delay
CEZ
300 150 ns Time After Falling of CE
tDS Input Data
200 100 ns Set-up Time
tDH Input Data
200 100 ns Hold Time
t
CKH
VDD≥2.0V VDD≥4.5V Min. Typ. Max. Min. Typ. Max.
t
CKL
Unit
µs Hz
CE
t
t
CES
CKS
SCLK
t
DS
t
DH
SI
SO
tRD
t
RD
t
RZ
*) For reading/writing timing, see “P.28. Adjustment of Oscillation frequency”.
t
CEH
tCR
t
CEZ
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Rev.2.01 - 6 -
05
2.8
±
0.2
4.0
±
0.3
005 +0 1
0.55
±
0.2
PACKAGE DIMENSIONS
RS5C348A/B (SSOP10)
3.5±0.2
10 6
0.2
±
4.4
6.4±0.2
0° to 10°
0.2
±
0.5
Rx5C348A/B
1
0.9MAX
0.2±0.1
5
0.1
0.5
0.1
M
0.1
±
1.15
0.1
±
0.1
1.35MAX
0.15
+0.1
-0.
unit: mm
RV5C348A/B (SSOP10G)
+0.3
2.9
-0.1
10
1
6
5
0.5
0° to 10°
0.127
0.1
±
1.1
+0.1
-0.05
0.2±0.1
0.1
0.15
-
M
0.1
unit: mm
Rev.2.01 - 7 -
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Rx5C348A/B
005 +0 1
RT5C348B (TSSOP10G)
2.9±0.2
10
(Limited)
0° to 10°
6
2.80±0.2
4.0±0.2
0.55±0.2
1
0.2±0.1
0.5
5
0.1
0.15
(0.75)
-
M
0.1
+0.1
0.13
-0.05
0.85±0.15
unit: mm
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Rev.2.01 - 8 -
Rx5C348A/B
GENERAL DESCRIPTION
Interface with CPU The Rx5C348A/B is connected to the CPU by four signal lines CE (Chip Enable), SCLK (Serial Clock), SI (Serial Input), and SO (Serial Output), through which it reads and writes data from and to the CPU. The CPU can be accessed when the CE pin is held high. Access clock pulses have a maximum frequency of 1 MHz allowing high-speed data transfer to the CPU.
Clock and Calendar Function The Rx5C348A/B reads and writes time data from and to the CPU in units ranging from seconds to the last two digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two digits are a multiple of 4. Consequently, leap years up to the year 2099 can automatically be identified as such.
*) The year 2000 is a leap year while the year 2100 is not a leap year.
Alarm Function The Rx5C348A/B incorporates the alarm interrupt circuit configured to generate interrupt signals to the CPU at preset times. The alarm interrupt circuit allows two types of alarm settings specified by the Alarm_W registers and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings including combinations of multiple day-of-week settings such as "Monday, Wednesday, and Friday" and "Saturday and Sunday". The Alarm_D registers allow hour and minute alarm settings. The Alarm_W outputs from /INTR pin, and the Alarm_D outputs also from /INTR pin. Each alarm function can be checked from the CPU by using a polling function.
High-precision Oscillation Adjustment Function The Rx5C348A/B has built-in oscillation stabilization capacitors (CG and CD), which can be connected to an external crystal oscillator to configure an oscillation circuit. To correct deviations in the oscillator frequency of the crystal, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to ±1.5ppm at 25°C) from the CPU. The maximum range is approximately ±189ppm in increments of approximately 3ppm. Such oscillation frequency adjustment in each system has the following advantages:
* Allows timekeeping with much higher precision than conventional RTCs while using a crystal oscillator
with a wide range of precision variations. * Corrects seasonal frequency deviations through seasonal oscillation adjustment. * Allows timekeeping with higher precision particularly with a temperature sensing function out of RTC,
through oscillation adjustment in tune with temperature fluctuations.
Power-on Reset, Oscillation Halt Sensing Function and Supply Voltage Monitoring Function The Rx5C348A/B incorporates an oscillation halt sensing circuit equipped with internal registers configured to record any past oscillation halt. Power on reset function reset the control resisters when the system is powered on from 0V. At the same time, the fact is memorized to the resister as a flag, thereby identifying whether they are powered on from 0V or battery backed-up. The Rx5C348A/B also incorporates a supply voltage monitoring circuit equipped with internal registers configured to record any drop in supply voltage below a certain threshold value. Supply voltage-monitoring threshold settings can be selected between 2.1V and 1.6V through internal register settings. The sampling rate is normally 1s. The oscillation halt sensing circuit and the power-on reset flag are configured to confirm the established invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the supply voltage monitoring circuit can be applied to battery supply voltage monitoring.
Periodic Interrupt Function The Rx5C348A/B incorporates the periodic interrupt circuit configured to generate periodic interrupt signals aside from interrupt signals generated by the alarm interrupt circuit for output from the /INTR pin. Periodic interrupt signals have five selectable frequency settings of 2 Hz (once per 0.5 seconds), 1 Hz (once per 1 second), 1/60 Hz (once per 1 minute), 1/3600 Hz (once per 1 hour), and monthly (the first day of every month). Further, periodic interrupt signals also have two selectable waveforms, a normal pulse form (with a frequency of 2 Hz or 1 Hz) and special form adapted to interruption from the CPU in the level mode (with second, minute, hour, and month interrupts). The condition of periodic interrupt signals can be monitored with using a polling function.
32kHz Clock Output The Rx5C348A/B incorporates a 32-kHz clock circuit configured to generate clock pulses with the oscillation
Rev.2.01 - 9 -
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Rx5C348A/B
frequency of a 32.768kHz crystal oscillator for output from the 32KOUT pin. The 32-kHz clock output can be disabled by certain register settings but cannot be disabled without manipulation of any two registers with different addresses to prevent disabling in such events as the runaway of the CPU. The pin is N-channel open drain output.
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Rev.2.01 - 10 -
Rx5C348A/B
Address Mapping
Address Register Name D a t a A3A2A1A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 Second Counter -
*2) 1 0 0 0 1 Minute Counter - M40 M20 M10 M8 M4 M2 M1 2 0 0 1 0 Hour Counter - - H20
3 0 0 1 1 Day-of-week Counter - - - - - W4 W2 W1 4 0 1 0 0 Day-of-month
Counter
5 0 1 0 1 Month Counter and
Century Bit 6 0 1 1 0 Year Counter Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 7 0 1 1 1 Oscillation
Adjustment
Register *3) 8 1 0 0 0 Alarm_W
(Minute Register) 9 1 0 0 1 Alarm_W
(Hour Register) A 1 0 1 0 Alarm_W
(Day-of-week
Register) B 1 0 1 1 Alarm_D
(Minute Register) C 1 1 0 0 Alarm_D
(Hour Register) D 1 1 0 1 - - - - - - - ­E 1 1 1 0 Control Register 1
*3) F 1 1 1 1 Control Register 2
*3)
Notes: * 1) All the data listed above accept both reading and writing. * 2) The data marked with "-" is invalid for writing and reset to 0 for reading. * 3) When the XSTP bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment Register, Control Register 1 and Control Register 2 excluding the XSTP bit. * 4) Writing to the Oscillation Adjustment Register requires filling the (0) bit. * 5) These bit names apply to the Rx5C348A. For the Rx5C348B the bit names are SCRATCH2 and
SCRATCH3.
- - D20 D10 D8 D4 D2 D1 /19⋅20
(0) *4)
- WM40 WM20 WM10 WM8 WM4 WM2 WM1
- - WH20
- WW6 WW5 WW4 WW3 WW2 WW1 WW0
- DM40 DM20 DM10 DM8 DM4 DM2 DM1
- - DH20
WALE DALE
VDSL VDET SCRA
S40 S20 S10 S8 S4 S2 S1
H10 H8 H4 H2 H1
P⋅/A
- - MO10 MO8 MO4 MO2 MO1
F6 F5 F4 F3 F2 F1 F0
WH10 WH8 WH4 WH2 WH1
WP⋅/ A
DH10 DH8 DH4 DH2 DH1
DP⋅/A
/12⋅24
TCH1
/CLEN2 *5)
XSTP /CLEN1
TEST CT2 CT1 CT0
CTFG WAFG DAFG
*5)
Rev.2.01 - 11 -
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Rx5C348A/B
Register Settings
Control Register 1 (ADDRESS Eh)
D7 D6 D5 D4 D3 D2 D1 D0 WALE DALE
WALE DALE 0 0 0 0 0 0 0 0 Default Settings
*1) Default settings: Default value means read / wr itten values when the XSTP bit is set to “1” due to
VDD power-on from 0v or oscillation stopping *2) This bit name applies to the Rx5C348A only. For the Rx5C348B the bit name is SCRATCH3..
(1) WALE, DALE Alarm_W Enable Bit, Alarm_D Enable Bit
WALE,DALE Description
0 Disabling the alarm interrupt circuit (under the control of the settings 1 Enabling the alarm interrupt circuit (under the control of the settings
(2) /12⋅24 /12-24-hour Mode Selection Bit
/12⋅24
0 Selecting the 12-hour mode with a.m. and p.m. indications. (Default) 1 Selecting the 24-hour mode
Setting the /12⋅24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively .
24-hour mode 12-hour mode 24-hour mode 12-hour mode 00 12 (AM12) 12 32 (PM12) 01 01 (AM 1) 13 21 (PM 1) 02 02 (AM 2) 14 22 (PM 2) 03 03 (AM 3) 15 23 (PM 3) 04 04 (AM 4) 16 24 (PM 4) 05 05 (AM 5) 17 25 (PM 5) 06 06 (AM 6) 18 26 (PM 6) 07 07 (AM 7) 19 27 (PM 7) 08 08 (AM 8) 20 28 (PM 8) 09 09 (AM 9) 21 29 (PM 9) 10 10 (AM10) 22 30 (PM10) 11 11 (AM11) 23 31 (PM11)
Setting the /12⋅24 bit should precede writing time data
(3) /CLEN2 (Rx5C348A) 32kHz Clock Output Bit 2
/CLEN2 Description
/12⋅24 /12⋅24
of the Alarm_W registers and the Alarm_D registers). of the Alarm_W registers and the Alarm_D registers)
Description
/CLEN2 *2) /CLEN2 *2)
TEST CT2 CT1 CT0 (For Writing) TEST CT2 CT1 CT0 (For Reading)
*1)
(Default)
0 Enabling the 32-kHz clock circuit (Default)
1 Disabling the 32-kHz clock circuit Setting the /CLEN2 bit or the /CLEN1 bit (D3 in the control register 2) to 0, specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin. Conversely, setting both the /CLEN1 and /CLEN2 bit to 1 disabling (”H”) such output.
SCRATCH3 (Rx5C348B) Scratch Bit 3
SCRATCH3 Description
0 (Default)
1 For the Rx5C348B, this bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH3 bit will be set to 0 when the XSTP bit is set to 1 in Control Register 2.
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Rev.2.01 - 12 -
A
(4) TEST T est Bit
TEST Description
0 Normal operation mode. (Default)
1 Test mode. The TEST bit is used only for testing in the factory and should normally be set to 0.
(5) CT2, CT1, and CT0 Periodic Interrupt Selection Bits
CT2 CT1 CT0
0 0 0 - OFF(H) (Default) 0 0 1 - Fixed at “L” 0 1 0 Pulse Mode
0 1 1 Pulse Mode 1 0 0 Level Mode 1 0 1 Level Mode 1 1 0 Level Mode 1 1 1 Level Mode
* 1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the
second counter as illustrated in the timing chart below.
Description Wave form mode
*1) *1) *2) *2) *2) *2)
Rx5C348A/B
Interrupt Cycle and Falling Timing
2Hz (Duty50%) 1Hz (Duty50%) Once per 1 second (Synchronized with
second counter increment) Once per 1 minute (at 00 seconds of every minute) Once per hour (at 00 minutes and 00 seconds of every hour) Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month)
In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the
* 2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1
CTFG Bit
/INTR Pin
falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will reset the other time counters of less than 1 second, driving the /INTR pin low.
minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below.
pprox. 92µs
(Increment of second counter)
Rewriting of the second counter
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Rev.2.01 - 13 -
Rx5C348A/B
CTFG Bit
/INTR Pin
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or
60sec. as follows: Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784 ms. For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%. Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784 ms.
Control Register 2 (Address Fh) D7 D6 D5 D4 D3 D2 D1 D0 VDSL VDET SCRA
VDSL VDET SCRA 0 0 0 1 0 0 0 0 Default Settings *)
*) Default settings: Default value means read / written values when the XSTP bit is set to “1” due to VDD power-on from 0v or oscillation stopping
(1) VDSL VDD Supply Voltage Monitoring Threshold Selection Bit
VDSL Description 0 Selecting the VDD supply voltage monitoring threshold setting of
1 Selecting the VDD supply voltage monitoring threshold setting of
The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.
(2) VDET Supply Voltage Monitoring Result Indication Bit
VDET Description 0 Indicating supply voltage above the supply voltage monitoring
1 Indicating supply voltage below the supply voltage monitoring
Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring circuit. Conversely, setting the VDET bit to 1 causes no event.
(3) SCRATCH1 Scratch Bit 1
SCRATCH1 Description
0 (Default)
1 This bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH1 bit will be set to 0 when the XSTP bit is set to 1 in Control Register 2.
(4) XSTP Oscillation Halt Sensing Bit
XSTP Description
0 Sensing a normal condition of oscillation
1 Sensing a halt of oscillation (Default) The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator. Oscillation Halt sensing circuit operates only when CE pin is Low.
* The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events as power-on from 0 volts and a drop in supply voltage. The XSTP bit will hold the setting of 1 even after the
Setting CTFG bit to 0
(Increment of second counter)
TCH1 TCH1
2.1v.
1.6v.
threshold settings. threshold settings.
Setting CTFG bit to 0
(Increment of second counter)
XSTP /CLEN1 CTFG WAFG DAFG (For Writing) XSTP /CLEN1 CTFG WAFG DAFG (For Reading)
(Increment of second counter)
(Default)
(Default)
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Rev.2.01 - 14 -
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