RICOH RV5C387A Technical data

1

I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC

WITH VOLTAGE MONITORING FUNCTION

RV5C387A

OUTLINE

The RV5C387A is a CMOS real-time clock IC connected to the CPU by two signal, SCL and SDA, and configured to

perform serial transmission of time and calendar data to the CPU. The periodic interrupt circuit is configured to

generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2 alarm circuits

generate interrupt signals at preset times. The oscillation circuit is driven under constant voltage so that fluctuations

in oscillation frequency due to voltage are small and supply current is also small (TYP. 0.35µA for the RV5C387A at

3 volts). The oscillation halt sensing circuit can be used to judge the validity of internal data in such events as

power-on. The supply voltage monitoring circuit is configured to record a drop in supply voltage below two

selectable supply voltage monitoring threshold settings. The 32-kHz clock output function (Nch. open drain) is

intended to output sub-clock pulses for the external microcomputer. The oscillation adjustment circuit is intended

to adjust time counts with high precision by correcting deviations in the oscillation frequency of the crystal

oscillator. The 32-kHz clock circuit can be disabled by certain register settings. This model comes in an ultra-

compact 10-pin SSOP-G (with a height of 1.20mm and a pin pitch of 0.5mm).

FEATURES

• Timekeeping supply voltage ranging from 1.45 to 5.5 volts

• Low supply current: TYP. 0.35µA (MAX. 0.8µA) at 3 volts

• Only two signal lines (SCL, SDA) required for connection to the CPU.

(I

2

C bus compatible, 400kHz at VDD≥2.5V, address 7bits)

• Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days,

and weeks) (in BCD format)

• 1900/2000 identification bit for Year 2000 compliance

• Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month)

to the CPU and provided with an interrupt flag and an interrupt halt circuit

•2 alarm circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and minute

alarm settings)

• 32-kHz clock circuit (Nch. open drain output)

• Oscillation halt sensing circuit which can be used to judge the validity of internal data

• Supply voltage monitoring circuit with two supply voltage monitoring threshold settings

• Automatic identification of leap years up to the year 2099

• Selectable 12-hour and 24-hour mode settings • Built-in oscillation stabilization capacitors (C

G and CD)

• High precision oscillation adjustment circuit • CMOS process

• Ultra-compact 10-pin SSOP-G(with a height of 1.20mm and size 4.0mm

×2.9mm)

NO.EA-080-0208

NO.EA-080-100928

RV5C387A

2

BLOCK DIAGRAM

COMPARATOR_W

ALARM_W REGISTER

(MIN,HOUR,WEEK)

ALARM_D REGISTER

(MIN,HOUR)

COMPARATOR_D

TIME COUNTER

(SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)

ADDRESS

REGISTER

ADDRESS
DECODER

SHIFT REGISTER

INTERRUPT CONTROL

32kHz

OUTPUT

CONTROL

DIVIDER

CORREC

-TION

DIV

OSC

OSCIN

32KOUT

OSCOUT

OSC

DETECT

I/O

CONTROL

VSS

SCL

SDA

VDD

INTRB

INTRC

INTRA

VOLTAGE

DETECT

32KOUT

1

SCL

2

SDA

3

VSS

INTRC

VDD

OSCIN

OSCOUT

INTRB

INTRA

4

5

8

9

10

7

6

• 10-pin SSOP-G

APPLICATIONS

• Communication devices (multi function phone, portable phone, PHS or pager)

• OA devices (fax, portable fax)

• Computer (desk-top and mobile PC, portable word-processor, PDA, electric note or video game)

• AV components (portable audio unit, video camera,camera, digital camera or remote controller)

• Home appliances (rice cooker, electric oven)

• Other (car navigation system, multi-function watch)

Note

· I2C bus is a trademark of PHILIPS ELECTRONICS N.V.

· Purchase of I

2

C components of Ricoh Company, Ltd. conveys a license under the Philips I2C Patent Rights to

use these components in an I

2

C system, provided that the system comforms to the I2C Standard

Specification as defined by Philips.

PIN CONFIGURATION

3

RV5C387A

PIN DESCRIPTIONS

Pin No.

Symbol Item Description

2 SCL Serial Clock Line

This pin is used to input shift clock pulses to synchronize data input/output to and

from the SDA pin with this clock. Allows a maximum input voltage of 5.5 volts

regardless of supply voltage.

3 SDA Serial Data Line

This pin inputs and outputs written or read data in synchronization with shift clock

pulses from the SCL pin. Allows a maximum input voltage of 5.5 volts regardless

of supply voltage.

6INTRA Interrupt Output A

This pin outputs periodic interrupt pulses to the CPU. This pin is off when power

is activated from 0V. This pin functions as an Nch open drain output.

7 INTRB Interrupt Output B

This pin outputs alarm interrupt (ALARM_W) to the CPU. This pin is off when

power is activated from 0V. This pin functions as an Nch open drain output.

4 INTRC Interrupt Output C

This pin outputs alarm interrupt (ALARM_D) to the CPU. This pin is off when

power is activated from 0V. This pin functions as an Nch open drain output.

1 32KOUT

32-kHz Clock Output

The 32KOUT pin is used to output 32.768-kHz clock pulses. Enabled at power-on

from 0 volts. Nch. open drain output. The RV5C387A is designed to be disable 32-

kHz clock output in response to a command from the host computer.

The OSCIN and OSCOUT pins are used to connect the 32.768-kHz crystal

oscillator (with all other oscillation circuit components built into the RV5C387A).

The VDD pin is connected to the power supply. The VSS pin is grounded.

9 OSCIN Oscillatory Circuit

8

OSCOUT

Input/Output

10 VDD

Positive Power Supply Input

5 VSS

Negative Power Supply Input

RV5C387A

4

ABSOLUTE MAXIMUM RATINGS

Symbol Item Conditions Ratings Unit

VDD

Supply Voltage –0.3 to +6.5 V

VI Input Voltage 2 SCL, SDA –0.3 to +6.5 V

V

O Output Voltage

SDA, INTRA, INTRB

–0.3 to +6.5 V

INTRC, 32KOUT

PD

Power Dissipation Topt=25˚C 300 mW

Topt Operating Temperature –40 to +85 ˚C

Tstg Storage Temperature –55 to +125 ˚C

(Vss=0V)

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under

any conditions. Moreover, such values for any two items must not be reached simultaneously. Operation

above these absolute maximum ratings may cause degradation or permanent damage to the device. These

are stress ratings only and do not necessarily imply functional operation below these limits.

RECOMMENDED OPERATING CONDITIONS

(Vss=0V,Topt=–40 to +85˚C)

Symbol Item Conditions MIN. TYP. MAX. Unit

V

DD Supply Voltage 2.0 5.5 V

VCLK Timekeeping Voltage 1.45 5.5 V

fXT Oscillation Frequency 32.768 kHz

V

PUP Pull-up Voltage SCL, SDA, INTRA, INTRB, INTRC, 32KOUT 5.5 V

5

RV5C387A

DC ELECTRICAL CHARACTERISTICS

Symbol Item Pin name Conditions MIN. TYP. MAX. Unit

VIH “H” Input Voltage

SCL,SDA VDD

=2.5 to 5.5V

0.8V

DD 5.5

V

VIL “L” Input Voltage –0.3 0.2V

DD

IOL1 32KOUT 0.5

I

OL2 “L” Output Current INTRA, INTRB, INTRC VOL=0.4V 1.0 mA

IOL3 SDA 4.0

I

IL Input Leakage Current SCL

V

I=5.5V or Vss

–1 1 µA

VDD=5.5V

I

OZ

SDA, INTRA, INTRB Vo=5.5V or Vss

–1 1 µA

INTRC VDD=5.5V

V

DD

=3V,

IDD VDD

SCL=SDA=3V,

0.35 0.8 µA

Output=OPEN

32KOUT=OFF mode*

1

V

DETH

Supply Voltage Monitoring

VDD

Topt=–30 to +70˚C 1.90 2.10 2.30 V

Voltage (

“H”

)

V

DETL

Supply Voltage Monitoring

VDD

Topt=–30 to +70˚C 1.45 1.60 1.80 V

Voltage (

“L”

)

CG

Internal Oscillation Capacitance 1

OSCIN 12

pF

C

D

Internal Oscillation Capacitance 2

OSCOUT 12

Unless otherwise specified : Vss=0V,VDD=3V,Topt=–40 to +85˚C

*

1) For standby current for outputting 32.768-kHz clock pulses from the 32KOUT pin, see “USAGES, 7. Typical Characteristics”.

RV5C387A

6

Symbol Item Conditions

V

DD≥2.0V VDD≥2.5V

Unit

MIN. TYP. MAX. MIN. TYP. MAX.

fSLC SCL clock frequency 100 400 kHz

t

LOW SCL clock “L” time 4.7 1.3 µs

tHIGH SCL clock “H” time 4.0 0.6 µs

tHD ; STA

Start condition hold time 4.0 0.6 µs

tSU ; STO Stop condition setup time 4.0 0.6 µs

tSU ; STA Start condition setup time 4.7 0.6 µs

tSU ; DAT Data setup time 250 200 ns

tHD ; DAT Data hold time 0 0 ns

tPL ; DAT

SDA “L” stable time after falling of SCL

2.0 0.9 µs

tPZ ; DAT

SDA off stable time after falling of SCL

2.0 0.9 µs

tR

Rising time of SCL and SDA (input)

1000 300 ns

tF

Falling time of SCL and SDA (input)

300 300 ns

t

SP

Spike width that can be removed

50 50 ns

with input filter

AC ELECTRICAL CHARACTERISTICS

Unless otherwise specified : VSS=0V, Topt=–40 to +85˚C

I/O conditions: V

IH=0.8×VDD, VIL=0.2×VDD, VOL=0.2×VDD, CL=50pF

SSrP

SCL

SDA(IN)

SDA(OUT)

t

LOW

tHD;STA tHD;DAT

tPZ;DAT

tPL;DAT

tSU;STA

tSU;STO

tHIGH

tHD;STA tSP

tSU;DAT

Sr

S

Start condition

Stop condition

Repeated start condition

P

*

) For read/write timing, see “USAGES, 1.5 Considerations in Reading and Writing Time Data”.

7

RV5C387A

GENERAL DESCRIPTION

1. Interface with CPU

The RV5C387A is connected to the CPU by two signal lines SCL and SDA, through which it reads and writes data

from and to the CPU. Since the output of the I/O pin of SDA is open drain, data interfacing with a CPU different

supply voltage is possible by applying pull-up resistors on the circuit board. The maximum clock frequency of

400kHz (at V

DD≥2.5V) of SCL enables data transfer in I

2

C bus fast mode.

2. Clock and Calendar Function

The RV5C387A reads and writes time data from and to the CPU in units ranging from seconds to the last two digits

of the calendar year. The calendar year will automatically be identified as a leap year when its last two digits are a

multiple of 4. Also available is the 1900/2000 identification bit for Year 2000 compliance. Consequently, leap years

up to the year 2099 can automatically be identified as such.

*

) The year 2000 is a leap year while the year 2100 is not a leap year.

3. Alarm Function

The RV5C387A incorporates an alarm circuit configured to generate interrupt signals to the CPU for output from

the INTRB or INTRC pin at preset times. The alarm circuit allows two types of alarm settings specified by the

Alarm_W registers and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm

settings including combinations of multiple day-of-week settings such as “Monday, Wednesday, and Friday” and

“Saturday and Sunday”. The Alarm_D registers allow hour and minute alarm settings. The Alarm_W signal outputs

from INTRB pin, and the Alarm_D signal outputs from INTRC pin. The current INTRB or INTRC pin conditions

specified by these two registers can be checked from the CPU by using a polling function.

4. High-precision Oscillation Adjustment Function

The RV5C387A has built-in oscillation stabilization capacitors (CG and CD), which can be connected to an external

crystal oscillator to configure an oscillation circuit. To correct deviations in the oscillation frequency of the crystal

oscillator, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to

±1.5ppm at 25˚C) from the CPU within a maximum range of approximately ±189ppm in increments of approximately

3ppm. Such oscillation frequency adjustment in each system has the following advantages:

· Allows timekeeping with much higher precision than conventional real-time clocks while using a crysta

l oscillator with a wide range of precision variations.

· Corrects seasonal frequency deviations through seasonal oscillation adjustment.

· Allows timekeeping with higher precision particularly in systems with a temperature sensing function

through oscillation adjustment in tune with temperature fluctuations.

RV5C387A

8

5. Oscillation Halt Sensing Function and Supply Voltage Monitoring Function

The RV5C387A incorporates an oscillation halt sensing circuit equipped with internal registers configured to record

any past oscillation halt, thereby identifying whether they are powered on from 0 volts or battery backed-up. As

such, the oscillation halt sensing circuit is useful for judging the validity of time data.

The RV5C387A also incorporates a supply voltage monitoring circuit equipped with internal registers configured to

record any drop in supply voltage below a certain threshold value. Supply voltage monitoring threshold settings can

be selected between 2.1 and 1.6 volts through internal register settings.

The oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to

the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the supply

voltage monitoring circuit can be applied to battery supply voltage monitoring.

6. Periodic Interrupt Function

The RV5C387A incorporates a periodic interrupt circuit configured to generate periodic interrupt signals aside from

interrupt signals generated by the alarm circuit for output from the INTRA pin. Periodic interrupt signals have five

selectable frequency settings of 2Hz (once per 0.5 seconds), 1Hz (once per 1 second), 1/60Hz (once per 1 minute),

1/3600Hz (once per 1 hour), and monthly (the first day of every month). Further, periodic interrupt signals also

have two selectable waveforms of a normal pulse form (with a frequency of 2Hz or 1Hz) and special form adapted to

interruption from the CPU in the level mode (with second, minute, hour, and month interrupts). The register

records of periodic interrupt signals can be monitored by using a polling function.

7. 32-kHz Clock Output Function

The RV5C387A incorporates a 32-kHz clock circuit configured to generate clock pulses with the oscillation frequen-

cy of a 32.768-kHz crystal oscillator for output from the 32KOUT pin. The 32KOUT pin is Nch. open drain output.

The 32-kHz clock output can be disabled by certain register settings. But it cannot be disabled without manipulation

of any two registers with different addresses, to prevent disabling in such events as the runaway of the CPU. The

32-kHz clock circuit is enabled at power-on.

9

RV5C387A

00 000Second Counter –

*

2

S40 S20 S

10 S8

S4 S2 S1

10 001Minute Counter – M

40 M

20 M10 M8

M4 M2 M1

20 0 1 0

Hour Counter

––

H

20

H10 H

8 H4 H2 H1

P/A

30 011Day-of-week Counter – – – – – W4 W2 W1

40 100Day-of-month Counter – – D20 D10 D8 D4 D2 D1

50 1 0 1

Month Counter and Century Bit

19/20 – – MO10 MO8 MO4 MO2 MO1

60 110Year Counter Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1

70 1 1 1

Oscillation Adjustment Register

*

3

–F6 F5 F4 F3 F2 F1 F0

81 0 0 0

Alarm_W (minute register)

–WM40 WM20 WM10 WM8 WM4 WM2 WM1

91 001Alarm_W (hour register) – –

WH

20

WH

10 WH8

WH4 WH

2 WH1

WP/A

A1 0 1 0

Alarm_W (Day-of-week register)–WW6 WW5 WW4 WW3 WW2 WW1 WW0

B1 0 1 1

Alarm_D (minute register)

–DM

40 DM20 DM10 DM8 DM4 DM2 DM1

C1 100Alarm_D (hour register) – –

DH

20

DH

10 DH8

DH4 DH2 DH1

DP/A

D1 101––––––––

E1 110Control Register 1*

3

WALE DALE 12/24 CLEN2 TEST CT2 CT1 CT0

F1 111Control Register 2*

3

VDSL VDET

SCRATCH

XSTP CLEN1 CTFG WAFG DAFG

D3 D2

D1

D0

Address

A3

A2 A1 A0

Register

D4D5D6D7

FUNCTIONAL DESCRIPTIONS

1. Address Mapping

*

1) All the data listed above accept both reading and writing.

*

2) The data marked with “–” is invalid for writing and reset to 0 for reading.

*

3) When the XSTP bit is set to 1 in control register 2, all the bits are reset to 0 in oscillation adjustment register 1, control register 1 and control register 2

excluding the XSTP bit.

RV5C387A

10

WALE, DALE Description

0

Disabling the alarm interrupt circuit (under the control of the settings of the
Alarm_W registers and the Alarm_D registers).

1

Enabling the alarm interrupt circuit (under the control of the settings of the

Alarm_W registers and the Alarm_D registers)

D7 D6 D5 D4 D3 D2 D1 D0

WALE DALE 12/24 CLEN2 TEST CT

2 CT1 CT

0

WALE DALE 12/24 CLEN2 TEST CT

2 CT

1 CT0

00000000

(For writing)

(For reading)

Default settings

*

1

(Default setting)

2. Register Settings

2.1 Control Register 1 (at Address Eh)

*

) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.

2.1-1 WALE and DALE

Alarm_W Enable Bit and Alarm_D Enable Bit

2.1-2 12/24

12-/24-hour Mode Selection Bit

12/24 Description

0 Selecting the 12-hour mode with a.m. and p.m. indications.

1 Selecting the 24-hour mode

Setting the 12/24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.

Table of Time Digit Indications

24-hour mode 12-hour mode 24-hour mode 12-hour mode

00 12 (AM12) 12 32 (PM12)
01 01 (AM 1) 13 21 (PM 1)
02 02 (AM 2) 14 22 (PM 2)
03 03 (AM 3) 15 23 (PM 3)
04 04 (AM 4) 16 24 (PM 4)
05 05 (AM 5) 17 25 (PM 5)
06 06 (AM 6) 18 26 (PM 6)
07 07 (AM 7) 19 27 (PM 7)
08 08 (AM 8) 20 28 (PM 8)
09 09 (AM 9) 21 29 (PM 9)
10 10 (AM10) 22 30 (PM10)
11 11 (AM11) 23 31 (PM11)

*

) Setting the 12/24 bit should precede writing time data.

(Default setting)

11

RV5C387A

TEST Description

0 Normal operation mode

1 Test mode

2.1-4 TEST

Test Bit

(Default setting)

The TEST bit is used only for testing in the factory and should normally be set to 0.

2.1-3 CLEN2

32-kHz Clock Output Bit 2

CLEN2 Description

0 Enabling the 32-kHz clock circuit

1 Disabling the 32-kHz clock circuit

(Default setting)

For the RV5C387A, setting the CLEN2 bit or the CLEN1 bit (D3 in the control register 2) to 0, specifies generating

clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.

Conversely, setting both the CLEN1 and the CLEN2 bit to 1 specifies disabling (“H”) such output.

RV5C387A

12

2.1-5 CT2, CT1, and CT0

Periodic Interrupt Selection Bits

CT2 CT1 CT0

Description

Waveform Mode

Interrupt Cycle and Fall Timing

000—Off (“H”)

001—Fixed at low (“L”)

010Pulse Mode 2Hz (Duty cycle of 50%)

011Pulse Mode 1Hz (Duty cycle of 50%)

100Level Mode Once per 1 second (Synchronized with second counter increment)

101Level Mode Once per minute (at 00 seconds of every minute)

110Level Mode Once per hour (at 00 minutes and 00 seconds of every hour)

111Level Mode

Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month)

(Default setting)

1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter

as illustrated in the timing chart on the next page.

2) Level Mode: periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute,

1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of

periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting

of 1 second are output in synchronization with the increment of the second counter as illustrated

in the timing chart on the next page.

3) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20 seconds as follows:

Pulse Mode: the “L” period of output pulses will increment or decrement by a maximum of ±3.784ms.

For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.

Level Mode: a periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784ms.

13

RV5C387A

Relation Between the Mode Waveform and the CTFG Bit

• Pulse mode

Approx. 92µs

CTFG bit

INTRA pin

(Increment of second counter)

Rewriting of the second counter

• Level mode

Setting CTFG bit to 0

(Increment of

second counter)

(Increment of

second counter)

(Increment of

second counter)

CTFG bit

INTRA pin

Setting CTFG bit to 0

*

) In the pulse mode, the increment of the second counter is delayed by approximately 92µs from the falling edge of clock pulses. Consequently, time

readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.

Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTRA pin low.

RV5C387A

14

VDSL Description

0Selecting the supply voltage monitoring threshold setting of 2.1 volts.

1Selecting the supply voltage monitoring threshold setting of 1.6 volts.

2.2-1 VDSL

Supply Voltage Monitoring Threshold Selection Bit

The VDSL bit is intended to select the supply voltage monitoring threshold settings.

VDET Description

0

Indicating supply voltage above the supply voltage monitoring threshold settings.

1

Indicating supply voltage below the supply voltage monitoring threshold settings.

2.2-2 VDET

Supply Voltage Monitoring Result Indication Bit

(Default setting)

Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will hold the

setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring circuit.

Conversely, setting the VDET bit to 1 causes no event.

D7 D6 D5 D4 D3 D2 D1 D0

VDSL VDET

SCRATCH

XSTP CLEN1 CTFG WAFG DAFG

VDSL VDET

SCRATCH

XSTP CLEN1 CTFG WAFG DAFG

00010000

2.2 Control Register 2 (at Address Fh)

(For write operation)

(For read operation)

Default setting*

1

SCRATCH Description

0

1

2.2-3 SCRATCH

Scratch Bit

(default settings)

The SCRATCH bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH bit will

be set to 0 when the XSTP bit is set to 1 in the control register 2.

(Default setting)

*

) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.

15

RV5C387A

2.2-4 XSTP

Oscillation Halt Sensing Bit

The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator. The oscillation halt sensing circuit

operates only when the CE pin is

“L”.

· The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events as

power-on from 0 volts and a drop in supply voltage. The XSTP bit will hold the setting of 1 even after the restart of

oscillation. As such, the XSTP bit can be applied to judge the validity of clock and calendar data after power-on or

a drop in supply voltage.

· When the XSTP bit is set to 1, all bits will be reset to 0 in the oscillation adjustment register, control register 1,

and control register 2, stopping the output from the INTRA, INTRB, INTRC pin and starting the output of 32.768-

kHz clock pulses from the 32KOUT pin.

· The XSTP bit accepts only the writing of 0, which restarts the oscillation halt sensing circuit. Conversely, setting

the XSTP bit to 1 causes no event.

XSTP Description

0 Sensing a normal condition of oscillation

1 Sensing a halt of oscillation

(Default setting)

CLEN1 Description

0 Enabling the 32-kHz clock output

1 Disabling the 32-kHz clock output

2.2-5 CLEN1

32-kHz Clock Output Bit 1

(Default setting)

Setting the CLEN1 bit or the CLEN2 bit (D4 in control register 1) to 0, specifies generating clock pulses with the

oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin. Conversely, setting both

the CLEN1 bit and the CLEN2 bit to 1 specifies disabling (“L”) such output.