RICOH RV5C386A Datasheet

Preliminary

9.Jun.99

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I2C-Bus Real-Time Clock ICs
with Voltage Monitoring Function

RV5C386A

1. OUTLINE
The RV5C386A is a CMOS real-time clock IC connected to the CPU by two signal lines, SCL and SDA, and
configured to perform serial transmission of time and calendar data to the CPU. The periodic interrupt circuit
is configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month.
The 2 alarm interrupt circuits generate interrupt signals at preset times. As the oscillation circuit is driven
under constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time
keeping current is small (TYP. 0. 35 µA at 3 volts). The oscillation halt sensing circuit can be used to judge
the validity of internal data in such events as power-on; The supply voltage monitoring circuit is configured to
record a drop in supply voltage below two selectable supply voltage monitoring threshold settings. The 32­kHz clock output function (CMOS output) is intended to output sub-clock pulses for the external
microcomputer. The 32-kHz clock output can be disabled by certain input pin. The oscillation adjustment
circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency
of the crystal oscillator. This model comes in an ultra-compact SSOP10G (Pin Pitch 0.5mm, Height1.2mm,

4.0mm×2.9mm).

2. FEATURES

• Timekeeping supply voltage ranging from 1.45 to 5.5V

• Low power consumption 0.35µA TYP (0.8µA MAX) at VDD=3V

• Only two signal lines (SCL and SDA) required for connection to the CPU.
( I2C-Bus Interface, 400kHz at VDD≥2.5V, address 7bits)

• Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days,

and weeks) (in BCD format)

• 1900/2000 identification bit for Year 2000 compliance

• Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month)

to the CPU and provided with an interrupt flag and an interrupt halt

• 2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and

minute alarm settings)

• 32-kHz clock circuit (CMOS output, equipped with a control pin)

• Oscillation halt sensing circuit which can be used to judge the validity of internal data

• Supply voltage monitoring circuit with two supply voltage monitoring threshold settings

• Automatic identification of leap years up to the year 2099

• Selectable 12-hour and 24-hour mode settings • Built-in oscillation stabilization capacitors (CG and CD)

• High precision oscillation adjustment circuit

• CMOS process • Ultra-compact SSOP10G

*) I2C-Bus is a trademark of PHILIPS N.V.
Purchase of I2C-Bus components of Ricoh Company, LTD. conveys a license under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system comforms to the I2C standard
Specification as definded by Philips.

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RV5C386A PRELIMINARY

SDA

3. PIN CONFIGURATION

RV5C386A (SSOP10G)

VDD

32KOUT

SCL

SDA

/INTRB

1
2

3
4
5 6

10

9
8
7

OSCIN
OSCOUT
CLKC

/INTRAVSS

4. BLOCK DIAGRAM

32KOUT

CLKC

OSCIN

OSCOUT

/INTRA

/INTRB

32kHz

OUTPUT

CONTROL

OSC

OSC

DETECT

DIVIDER

CORREC

-TION

INTERRUPT CONTROL

DIV

TOP VIEW

COMPARATOR_W

COMPARATOR_D

TIME COUNTER

(SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)

ADDRESS

DECODER

SHIFT REGISTER

ALARM_W REGISTER

(MIN,HOUR, WEEK)

ALARM_D REGISTER

(MIN,HOUR)

ADDRESS

REGISTER

VDD

VOLTAGE

DETECT

VSS

SCL

I/O

CONTROL

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PRELIMINARY RV5C386A

5. PIN DESCRIPTION

Symbol Item Description

SCL Serial

Clock Line

SDA Serial

Data Line

/INTRA Interrupt

Output A

/INTRB Interrupt

Output B

32KOUT 32kHz Clock

Output

CLKC Clock control

input

OSCIN
OSCOUT

VDD
VSS

Oscillation
Circuit
Input / Output
Positive Power
Supply Input
Negative Power
Supply Input

The SCL pin is used to input clock pulses synchronizing the input and output
of data to and from the SDA pin. Allows a maximum input voltage of 5.5
volts regardless of supply voltage.
The SDA pin is used to input or output data intended for writing or reading in
synchronization with the SCL pin. Up to 5.5v beyond VDD may be input.
This pin functions as an Nch open drain output.
The /INTRA pin is used to output periodic interrupt signals to the CPU and
alarm interrupt (Alarm_D) signals. Disabled at power-on from 0 volts. Nch.
open drain output.
The /INTRB pin is used to output alarm interrupt (Alarrm_W) signals to the
CPU. Disabled at power-on from 0 volts. Nch. open drain output.
The 32KOUT pin is used to output 32.768-kHz clock pulses. Enabled at
power-on from 0 volts. CMOS output. The output is disabled if the CLKC pin
is set to Low or open.
The CLKC pin is used to control output of the 32KOUT pin. The clock output
is disabled and held low when the pin is set to low or open. Incorporates a
pull-down resistor.
The OSCIN and OSCOUT pins are used to connect the 32.768-kHz crystal
oscillator (with all other oscillation circuit components built into the
RV5C386A).
The VDD pin is connected to the power supply.

The VSS pin is grounded.

6. ABSOLUTE MAXIMUM RATINGS
Symbol Item Pin Name Description Unit

VDD Supply Voltage -0.3 to +6.5 V
VI Input Voltage SCL, SDA, CLKC -0.3 to +6.5 V

Output Voltage 1 SDA, /INTRA, /INTRB -0.3 to +6.5 V VO

Output Voltage 1 32KOUT -0.3 to VDD+0.3 V
PD Power Dissipation
Topt Operating Temperature -40 to +85
Tstg Storage Temperature -55 to +125

7. RECOMMENDED OPERATING CONDITIONS

Symbol Item Pin Name Min, Typ. Max. Unit
VDD Supply Voltage 2.0 5.5 V
VCLK Timekeeping Voltage 1.45 5.5 V
fXT Oscillation Frequency 32.768 kHz
VPUP Pull-up Voltage SCL, SDA, /INTRA,

Topt = 25°C

/INTRB

(VSS=0V)

300 mW

°C
°C

(VSS=0V, Topt=-40 to +85°C)

5.5 V

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RV5C386A PRELIMINARY

8. DC ELECTRICAL CHARACTERISTICS
(Unless otherwise specified : VSS=0V,VDD=3V,Topt=-40 to +85°C)

Symbol Item Pin Name Conditions Min. Typ. Max. Unit
VIH “H” Input Voltage 0.8VDD 5.5

VIL “L” Input Voltage
IOH “H” Output

Current
IOL1 32KOUT 0.5
IOL2 /INTRA,

IOL3
IIL Input Leakage

ICLKC Pull Down

IOZ Output Off-state

IDD Time Keeping

VDETH

VDETL

CG Internal

CD Internal

*1) For Standby Current for outputting 32.768kHz clock pulses from the 32KOUT pin, see, “14.7 Typical

Characteristics”.

“L” Output

Current

Current

Resistance Input

Current

Current

Current

Supply Voltage

Monitoring

Voltage “H”

Supply Voltage

Monitoring

Voltage “L”

Oscillation

Capacitance 1

Oscillation

Capacitance 2

SCL,SDA,

CLKC
32KOUT VOH=VDD-0.5V -0.5mA mA

/INTRB
SDA

SCL VI=5.5V or VSS
CLKC VI=5.5V 0.35 1.0

SDA,
/INTRA,
/INTRB

VDD

VDD

VDD

OSCIN 12

OSCOUT 12

VDD=2.0 to 5.5V

-0.3 0.2VDD

VOL=0.4V

VDD=5.5V

VO=5.5V or VSS
VDD=5.5V -1 1

VDD=3V,
SCL=SDA=3V,
CLKC=VSS
Output = OPEN
*1)

Topt=-30 to +70°C

Topt=-30 to +70°C

1.0

4.0

-1 1

0.35 0.8

1.90 2.10 2.30 V

1.45 1.60 1.80 V

µA

V

mA

µA
µA

µA

pF

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PRELIMINARY RV5C386A

t

PZ;DAT

HIGH

SU;DAT

HD;STA

SP

SU;STO

LOW

SU;STA

HD;STA

t

PL;DAT

HD;DAT

9. AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified : VSS=0V,Topt=-40 to +85°C
Input and Output Conditions : VIH=0.8×VDD,VIL=0.2×VDD,VOH=0.8×VDD,VOL=0.2×VDD,CL=50pF

Symbol Item Condi-

tions

f

SCL

t

LOW

t

HIGH

t

HD;STA

t

SU;STO

t

SU;STA

t

SU;DAT

t

HD;DAT

t

PL;DAT

SCL Clock Frequency 100 400 KHz
SCL Clock Low Time 4.7 1.3
SCL Clock High Time 4.0 0.6
Start Condition Hold Time 4.0 0.6
Stop Condition Set Up Time 4.0 0.6
Start Condition Set Up Time 4.7 0.6
Data Set Up Time 250 200 ns
Data Hold Time 0 0 ns
SDA “L” Stable Time

After Falling of SCL

t

PZ;DAT

SDA off Stable Time
After Falling of SCL

t

R

Rising Time of SCL and
SDA (input)

t

F

Falling Time of SCL and
SDA (input)

t

SP

Spike Width that can be
removed with Input Filter

VDD≥2.0V VDD≥2.5V

Min. Typ. Max. Min. Typ. Max.

2.0 0.9

2.0 0.9

1000 300 ns

300 300 ns

50 50 ns

Unit

µs
µs
µs
µs
µs

µs
µs

SCL

SDA(IN)

SDA(OUT)

S

Sr

S

t

t

Start Condition

Repeated Start Condition

t

Stop Condition

P

Sr P

t

t

t

t

t

t

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RV5C386A PRELIMINARY

M

-0.1

+0.3

0.15

-0.05

0.1

+0.1

φ

φ

10. PACKAGE DIMENSIONS (Unit : mm)
RV5C386A (SSOP10G)

0 to 10

2.9

°

10

1

0.2±0.1

0.5

6

0.2

0.3

±

±

2.8

4.0

0.2

±

0.55

5

0.127

0.1

±

1.1

+0.1

-0.05

0.1

11. TAPING SPECIFICATION

The RV5C386A has one designated taping direction. The product designation for the taping components is
"RV5C386A-E2".

T

W

1

T

2

A B D

4.4

±0.1

3.2

±0.1

0

1.5

+0.1

-0

1.5

+0.1

-0

E

P

5.5

0

±0.1

P

4.0

2

0

B

P

1

8.0

±0.1

F

W

D

1

P

2

2.0

±0.05

Unit:mm

T T

0.3

±0.05

2

2.0

(MAX)

W W

12.0
±0.3

1

9.5

D

0

A

P

1

Pull-Out Directions

D

1

E F P

1.75

±0.1

±0.05

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PRELIMINARY RV5C386A

12. GENERAL DESCRIPTION

(1) Interface with CPU

The RV5C386A is connected to the CPU by two signal lines SCL and SDA, through which it reads and writes
data from and to the CPU. Since the output of the I/O pin of SDA is open drain, data interfacing with a CPU
different supply voltage is possible by applying pull-up resistors on the circuit board. The maximum clock
frequency of 400kHz (at VDD≥2.5V) of SCL enables data transfer in I2C-Bus fast mode.

(2) Clock and Calendar Function

The RV5C386A reads and writes time data from and to the CPU in units ranging from seconds to the last two
digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two
digits are a multiple of 4. Also available is the 1900 / 2000 identification bit for Year 2000 compliance.
Consequently, leap years up to the year 2099 can automatically be identified as such.

*) The year 2000 is a leap year while the year 2100 is not a leap year.

(3) Alarm Function

The RV5C386A incorporates the alarm interrupt circuit configured to generate interrupt signals to the CPU at
preset times. The alarm interrupt circuit allows two types of alarm settings specified by the Alarm_W
registers and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings
including combinations of multiple day-of-week settings such as "Monday, Wednesday, and Friday" and
"Saturday and Sunday". The Alarm_D registers allow hour and minute alarm settings. The Alarm_W
outputs from /INTRB pin, and the Alarm_D outputs from /INTRA pin. The current /INTRA or /INTRB
conditions specified by the flag bits for each alarm function can be checked from the CPU by using a polling
function.

(4) High-precision Oscillation Adjustment Function

The RV5C386A has built-in oscillation stabilization capacitors (CG and CD), which can be connected to an
external crystal oscillator to configure an oscillation circuit. To correct deviations in the oscillation frequency
of the crystal oscillator, the oscillation adjustment circuit is configured to allow correction of a time count gain
or loss (up to ±1.5 ppm at 25°C) from the CPU within a maximum range of approximately + 189 ppm in
increments of approximately 3 ppm. Such oscillation frequency adjustment in each system has the following
advantages:
* Allows timekeeping with much higher precision than conventional RTCs while using a crystal oscillator with

a wide range of precision variations.
* Corrects seasonal frequency deviations through seasonal oscillation adjustment.
* Allows timekeeping with higher precision particularly with a temperature sensing function out of RTC,

through oscillation adjustment in tune with temperature fluctuations.

(5) Oscillation Halt Sensing Function and Supply Voltage Monitoring Function

The RV5C386A incorporates an oscillation halt sensing circuit equipped with internal registers configured to
record any past oscillation halt, thereby identifying whether they are powered on from 0 volts or battery
backed-up. As such, the oscillation halt sensing circuit is useful for judging the validity of time data.
The RV5C386A also incorporates a supply voltage monitoring circuit equipped with internal registers
configured to record any drop in supply voltage below a certain threshold value. Supply voltage monitoring
threshold settings can be selected between 2.1 and 1.6 volts through internal register settings. The
oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to
the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the
supply voltage monitoring circuit can be applied to battery supply voltage monitoring.

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RV5C386A PRELIMINARY

(6) Periodic Interrupt Function

The RV5C386A incorporates the periodic interrupt circuit configured to generate periodic interrupt signals
aside from interrupt signals generated by the alarm interrupt circuit for output from the /INTRA pin. Periodic
interrupt signals have five selectable frequency settings of 2 Hz (once per 0.5 seconds), 1 Hz (once per 1
second), 1/60 Hz (once per 1 minute), 1/3600 Hz (once per 1 hour), and monthly (the first day of every month).
Further, periodic interrupt signals also have two selectable waveforms, a normal pulse form (with a frequency
of 2 Hz or 1 Hz) and special form adapted to interruption from the CPU in the level mode (with second,
minute, hour, and month interrupts). The condition of periodic interrupt signals can be monitored by using a
polling function.

(7) 32kHz Clock Output

The RV5C386A incorporates a 32-kHz clock circuit configured to generate clock pulses with the oscillation
frequency of a 32.768kHz crystal oscillator for output from the 32KOUT pin (CMOS push-pull output). The
32-kHz clock output is enabled and disabled when the CLKC pin is held high, and low or open, respectively.

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PRELIMINARY RV5C386A

13. FUNCTION DESCRIPTIONS

13.1. Address Mapping
Address Register Name D a t a

A3A2A1A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 Second Counter -

*2)
1 0 0 0 1 Minute Counter - M40 M20 M10 M8 M4 M2 M1
2 0 0 1 0 Hour Counter - - H20

3 0 0 1 1 Day-of-week Counter - - - - - W4 W2 W1
4 0 1 0 0 Day-of-month Counter - - D20 D10 D8 D4 D2 D1
5 0 1 0 1 Month Counter and

Century Bit
6 0 1 1 0 Year Counter Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1
7 0 1 1 1 Oscillation Adjustment

Register *3)
8 1 0 0 0 Alarm_W

(Minute Register)
9 1 0 0 1 Alarm_W

(Hour Register)
A 1 0 1 0 Alarm_W

(Day-of-week Register)
B 1 0 1 1 Alarm_D

(Minute Register)
C 1 1 0 0 Alarm_D

(Hour Register)
D 1 1 0 1 - - - - - - - ­E 1 1 1 0 Control Register 1 *3) WALE DALE

F 1 1 1 1 Control Register 2 *3) VDSL VDET SCRA-

Notes:
* 1) All the data listed above accept both reading and writing.
* 2) The data marked with "-" is invalid for writing and reset to 0 for reading.
* 3) When the XSTP bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment
Register, Control Register 1 and Control Register 2 excluding the XSTP bit.

/19⋅20

S40 S20 S10 S8 S4 S2 S1

H10 H8 H4 H2 H1

P⋅/A

- - MO10 MO8 MO4 MO2 MO1

- F6 F5 F4 F3 F2 F1 F0

- WM40 WM20 WM10 WM8 WM4 WM2 WM1

- - WH20
WP⋅/A

- WW6 WW5 WW4 WW3 WW2 WW1 WW0

- DM40 DM20 DM10 DM8 DM4 DM2 DM1

- - DH20

DP⋅/A

/12⋅24

TCH1

WH10 WH8 WH4 W H2 WH1

DH10 DH8 DH4 DH2 DH1

SCRA-

TCH3
XSTP SCRA-

TEST CT2 CT1 CT0

CTFG WAFG DAFG

TCH2

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RV5C386A PRELIMINARY

13.2. Register Settings

13.2.1. Control Register 1 (ADDRESS Eh)
D7 D6 D5 D4 D3 D2 D1 D0

WALE DALE
WALE DALE

0 0 0 0 0 0 0 0 Default Settings *)

*) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on
from 0 volts or supply voltage drop.

(1) WALE, DALE Alarm_W Enable Bit, Alarm_D Enable Bit

WALE,DALE Description

0 Disabling the alarm interrupt circuit (under the control of the settings
1 Enabling the alarm interrupt circuit (under the control of the settings

(2) /12⋅24 12-/24-hour Mode Selection Bit

/12⋅24

0 Selecting the 12-hour mode with a.m. and p.m. indications. (Default)
1 Selecting the 24-hour mode

Setting the /12 ⋅ 24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.

/12⋅24
/12⋅24

of the Alarm_W registers and the Alarm_D registers).
of the Alarm_W registers and the Alarm_D registers)

SCRATCH3 TEST CT2 CT1 CT0 (For Writing)
SCRATCH3 TEST CT2 CT1 CT0 (For Reading)

(Default)

Description

24-hour mode 12-hour mode 24-hour mode 12-hour mode

00 12 (AM12) 12 32 (PM12)
01 01 (AM 1) 13 21 (PM 1)
02 02 (AM 2) 14 22 (PM 2)
03 03 (AM 3) 15 23 (PM 3)
04 04 (AM 4) 16 24 (PM 4)
05 05 (AM 5) 17 25 (PM 5)
06 06 (AM 6) 18 26 (PM 6)
07 07 (AM 7) 19 27 (PM 7)
08 08 (AM 8) 20 28 (PM 8)
09 09 (AM 9) 21 29 (PM 9)
10 10 (AM10) 22 30 (PM10)
11 11 (AM11) 23 31 (PM11)

Setting the /12⋅24 bit should precede writing time data

(3) SCRATCH3 Scratch Bit 3

SCRATCH3 Description

0 (Default)
1

The SCRATCH3 bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH3

bit will be set to 0 when the XSTP bit is set to 1 in the Control Register 2.

(4) TEST Test Bit

TEST Description

0 Normal operation mode. (Default)
1 Test mode.

The TEST bit is used only for testing in the factory and should normally be set to 0.

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PRELIMINARY RV5C386A

(5) CT2,CT1, and CT0 Periodic Interrupt Selection Bits

DescriptionCT2 CT1 CT0

Wave form mode Interrupt Cycle and Falling Timing
0 0 0 - OFF(H) (Default)
0 0 1 - Fixed at “L”
0 1 0 Pulse Mode *1) 2Hz(Duty50%)
0 1 1 Pulse Mode *1) 1Hz(Duty50%)
1 0 0 Level Mode *2) Once per 1 second (Synchronized with

second counter increment)

1 0 1 Level Mode *2) Once per 1 minute (at 00 seconds of every

minute)

1 1 0 Level Mode *2) Once per hour (at 00 minutes and 00

seconds of every hour)

1 1 1 Level Mode *2) Once per month (at 00 hours, 00 minutes,

and 00 seconds of first day of every month)

*1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second

counter as illustrated in the timing chart below.

CTFG Bit

/INTRA Pin

Approx. 92µs

(Increment of second counter)

Rewriting of the second counter

In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling edge of

clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag
behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will
reset the other time counters of less than 1 second, driving the /INTRA pin low.

*2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1

minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the
falling edge of periodic interrupt signals. For example, periodic interrupt signals with an
interrupt cycle setting of 1 second are output in synchronization with the increment of the second
counter as illustrated in the timing chart below.

CTFG Bit

/INTRA Pin

Setting CTFG bit to 0

(Increment of
second counter)

(Increment of
second counter)

Setting CTFG bit to 0

(Increment of
second counter)

*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as follows:

Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784 ms. For

example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.

Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784 ms.

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RV5C386A PRELIMINARY

SCRA-

TCH1

XSTP

SCRA-

TCH1

SCRA-

13.2.2. Control Register 2 (Address Fh)
D7 D6 D5 D4 D3 D2 D1 D0

VDSL

TCH2

VDSL

0 0 0 1 0 0 0 0 Default Settings *)

(1) VDSL Supply Voltage Monitoring Threshold Selection Bit

(2) VDET Supply Voltage Monitoring Result Indication Bit

(3) SCRATCH1 Scratch Bit 1

(4) XSTP Oscillation Halt Sensing Bit

VDET

*) Default settings: Default value means read / written values when the XSTP bit is reset due to power-on from
0 volts or supply voltage drop.

VDSL Description

0 Selecting the supply voltage monitoring threshold setting of 2.1v. (Default)
1 Selecting the supply voltage monitoring threshold setting of 1.6v.

The VDSL bit is intended to select the supply voltage monitoring threshold settings.

VDET Description

0 Indicating supply voltage above the supply voltage monitoring

threshold settings.

1 Indicating supply voltage below the supply voltage monitoring

threshold settings.

Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will hold the

setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring circuit.
Conversely, setting the VDET bit to 1 causes no event.

SCRATCH1 Description

0 (Default)
1

The SCRATCH1 bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH1

bit will be set to 0 when the XSTP bit is set to 1 in the Control Register 2.

XSTP Description

0 Sensing a normal condition of oscillation
1 Sensing a halt of oscillation (Default)

The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator.

* The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events as

power-on from 0 volts and a drop in supply voltage. The XSTP bit will hold the setting of 1 even after the
restart of oscillation. As such, the XSTP bit can be applied to judge the validity of clock and calendar data
after power-on or a drop in supply voltage.

* When the XSTP bit is set to 1, all bits will be reset to 0 in the Oscillation Adjustment Register, Control Register

1, and Control Register 2, stopping the output from /INTRA and /INTRB pins and starting the output of

32.768-kHz clock pulses from the 32KOUT pin.

* The XSTP bit accepts only the writing of 0, which restarts the oscillation halt sensing circuit. Conversely,

setting the XSTP bit to 1 causes no event.

* It is recommendable to frequently check the XSTP bit for setting errors or data garbles, which may seriously

affect the operation of the RV5C386A.

XSTP

TCH2

CTFG
CTFG

WAFG
WAFG

DAFG (For Writing)
DAFG (For Reading)

(Default)

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PRELIMINARY RV5C386A

(5) SCRATCH2 Scratch Bit 2

SCRATCH2 Description

0 (Default)
1

The SCRATCH2 bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH2

bit will be set to 0 when the XSTP bit is set to 1 in the Control Register 2.

(6) CTFG Periodic Interrupt Flag Bit

CTFG Description

0 Periodic interrupt output = “H” (Default)
1 Periodic interrupt output = “L”

The CTFG bit is set to 1 when the periodic interrupt signals are output from the /INTRA pin (“L”). The CTFG bit

accepts only the writing of 0 in the level mode, which disables (“H”) the /INTRA pin until it is enabled (“L”) again in
the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.

(7) WAFG,DAFG Alarm_W Flag Bit and Alarm_D Flag Bit

WAFG,DAFG Description

0 Indicating a mismatch between current time and preset alarm time (Default)
1 Indicating a match between current time and preset alarm time

The WAFG and DAFG bits are valid only when the WALE and DALE have the setting of 1, which is caused

approximately 61µs after any match between current time and preset alarm time specified by the Alarm_W
registers and the Alarm_D registers. The WAFG (DAFG) bit accepts only the writing of 0. /INTRB (/INTRA) pin
outputs off (“H”) when this bit is set to 0. And /INTRB (/INTRA) pin outputs “L” again at the next preset alarm
time. Conversely, setting the WAFG and DAFG bits to 1 causes no event. The WAFG and DAFG bits will have
the reading of 0 when the alarm interrupt circuit is disabled with the WALE and DALE bits set to 0. The settings
of the WAFG and DAFG bits are synchronized with the output of the /INTRB (/INTRA) pin as shown in the timing
chart below.

Approx. 61µs Approx. 61µs

WAFG(DAFG) Bit

/INTRB(/INTRA) Pin

(Match between
current time and
preset alarm time)

Writing of 0 to
WAFG(DAFG) bit

(Match between
current time and
preset alarm time)

Writing of 0 to

WAFG(DAFG) bit
(Match between
current time and
preset alarm time)

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