RICOH R2221T, R2221L, R2223T, R2223L Technical data

R2221T/L R2223T/L

2-wire Serial Interface Real Time Clock IC

NO.EA-227-110822

OUTLINE

The R2221T/L,R2223T/L is a CMOS real-time clock IC connected to the CPU by two signal lines, SCL, SDA, and configured to perform serial transmission of time and calendar data to the CPU. The periodic interrupt circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2 alarm interrupt circuits generate interrupt signals at preset times. As the oscillation circuit is driven under constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time keeping current is small (TYP. 0.18μA at 3V). The oscillation halt sensing circuit can be used to judge the validity of internal data in such events as power-on; the supply voltage monitoring circuit is configured to record a drop in supply voltage below supply voltage monitoring threshold settings. The 32.768kHz clock output function (CMOS output with control pin) is intended to output sub-clock pulses for the external microcomputer. The oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency of the crystal oscillator. Since the package for these ICs are TSSOP10G (4.0x2.9x1.0:R2221T,R2223T) or QFN018018-12 (1.8x1.8x0.43: R2221L, R2223L), high density mounting of ICs on boards is possible.

FEATURES

• Minimum Timekeeping supply voltage TYP:0.6 to 5.5v (Worst: 0.9V to 5.5v); VDD pin

• Ultra low power consumption 0.18μA TYP at VDD=3V (0.65μA MAX.)

•Two signal lines (SCL, SDA) required for connection to the CPU.

•Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days, and weeks) (in BCD format)

•Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to the CPU and provided with an interrupt flag and an interrupt halt

•2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and minute alarm settings)

•With Power-on flag to prove that the power supply starts from 0V

•32-kHz clock output pin (CMOS push-pull output with control pin)

•Supply voltage monitoring circuit with supply voltage monitoring threshold settings

•Automatic identification of leap years up to the year 2099

•Selectable 12-hour and 24-hour mode settings

•High precision oscillation adjustment circuit

•Built-in oscillation stabilization capacitors (CG and CD)

•Package TSSOP10G (4.0mm x 2.9mm x 1.0mm: R2221T, R2223T)

QFN018018-12 (under development) (1.8mm x 1.8mm x 0.43mm: R2221L, R2223L)

• CMOS process

1

R2221L/T, R2223L/T (Preliminary)

PIN CONFIGURATION

R2221T(TSSOP10G)

32KOUT				1	10		VDD
	SCL			2	9		OSCIN
	SDA			3	8		OSCOUT
				4	7		CLKC
	ECO
VSS				5	6
								INTR

TOP VIEW

R2223T(TSSOP10G)

32KOUT				1	10		VDD
	SCL			2	9		OSCIN
	SDA			3	8		OSCOUT
				4	7		CLKC
	INTRB
	VSS			5	6
							INTRA

TOP VIEW

R2221L(QFN018018-12:underdevelopment)

	32KOUT	NC	VDD
	9	8	7
SCL	10		6	OSCIN
SDA	11		5	OSCOUT
ECO	12	2	4	CLKC
	1		3
	VSS	NC	INTR

TOP VIEW

R2223L(QFN018018-12:

		32KOUT		under development)
			NC	VDD
		9	8	7
SCL		10		6		OSCIN
SDA		11		5		OSCOUT
		12		4		CLKC
INTRB			2
		1		3
		VSS	NC		INTRA

TOP VIEW

BLOCK DIAGRAM

32KOUT	32kHz		COMPARATOR_W		ALARM_W REGISTER			VDD
					(MIN,HOUR, WEEK)
	OUTPUT
CLKC
	CONTROL				ALARM_D REGISTER		VOLTAGE
			COMPARATOR_D				DETECT
					(MIN,HOUR)
*2)
ECO	DIVIDER			TIME COUNTER			POWER_ON
OSCIN		DIV					RESET
	OSC CORREC		(SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)					VSS
	-TION
OSCOUT
	OSC		ADDRESS		ADDRESS			SCL
							I/O
	DETECT		DECODER		REGISTER			SDA
						CONTROL
INTRA
INTR
*1)	INTERRUPT CONTROL
INTRB				SHIFT REGISTER

*1) As an interrupt pin, the R2221L/T has INTR, the R2223L/T has INTRA pin. The R2221T does not have INTRB pin.

*2) The R2221L/T has ECO pin. The R2223L/T can set ECO mode with the internal resister.

2

R2221L/T, R2223L/T (Preliminary)

SELECTION GUIDE

In the R2221L/T, R2223L/T, users can select the IC with designating the package, function version according to the application. The designation can be made by part number as below:

Part Number is designated as follows:

R2221T-E2 ←Part Number		R2223T-E2←Part Number
↑ ↑		↑ ↑
R2221a-bb		R2223a-bb
		Description
Code

Designation of the package.

aT: TSSOP10G

L:QFN018018-12 (under development)

bb	Designation of the taping type. Only E2 is available.

PIN DESCRIPTION

	Symbol			Item
SCL				Serial Clock
				Line
SDA				Serial Data Line
32KOUT				32kHz Clock
				Output
CLKC				Clock Control
				Interrupt
	INTRA
(R2223L/T)				Output A
				Interrupt
	INTRB
(R2223L/T)				Output B
INTR				Interrupt
(R2221L/T)				Output
ECO				Oscillator mode
(R2221L/T)				select pin
VDD				Positive/Negative
VSS				Power Supply Input
OSCIN				Oscillation
OSCOUT				Circuit
				Input / Output
	NC			No connection

Description

The SCL pin is used to input clock pulses synchronizing the input and output of data to and from the SDA pin. Allows a maximum input voltage of 5.5v regardless of supply voltage.

The SDA pin is used to input and output data intended for writing and reading in synchronization with the SCL pin. Allows a maximum input voltage of 5.5v regardless of supply voltage. Nch. open drain output. The 32KOUT pin is used to output 32.768-kHz clock pulses. The pin is CMOS push-pull output. The output is disabled and held “L” when CLKC pin is set to “L” or open, or certain register setting. This pin is enabled at power-on from 0v. Allows a maximum input voltage of 5.5v regardless of supply voltage.

The CLKC pin is used to control output of the 32KOUT pin. The clock output is disabled and held “L” when this pin is set to “L” or open. Incorporated pull down register.

The INTRA pin is used to output alarm interrupt (Alarm_D) and periodic interrupt signals to the CPU. Disabled at power-on from 0V. N-channel open drain output. Allows a maximum pull-up voltage of 5.5v regardless of supply voltage.

The INTRB pin is used to output alarm interrupt (Alarm_W) to the CPU. Disabled at power-on from 0V. N-channel open drain output. Allows a maximum pull-up voltage of 5.5v regardless of supply voltage.

The INTR pin is used to output alarm interrupt (Alarm_D Alarm_W) and periodic interrupt signals to the CPU. Disabled at power-on from 0V. N-channel open drain output. Allows a maximum pull-up voltage of 5.5v regardless of supply voltage.

Ultra low consumption oscillator mode (ECO mode) select pin

When the ECO pin is “L”, the oscillator becomes ultra low consumption oscillator mode. In the actual usage, set this pin at ”L” or ”H”. (R2223L/T realizes the ultra low consumption oscillator mode by resister. ) For further information to know the technical notes, refer to the item "ECO mode" at P.30.

The VDD pin is connected to the power supply. The VSS pin is grounded.

The OSCIN and OSCOUT pins are used to connect the 32.768-kHz crystal oscillator (with all other oscillation circuit components built into the R2221L/T, R2223L/T).

3

R2221L/T, R2223L/T (Preliminary)

ABSOLUTE MAXIMUM RATINGS

(VSS=0V)

Symbol

Item

Pin Name

Description

Unit

VDD

Supply Voltage

VDD

-0.3 to +6.5

V

VI

Input Voltage 1

SCL, SDA, CLKC,

-0.3 to +6.5

V

ECO

*1)

VO

Output Voltage 1

SDA,

,

-0.3 to +6.5

V

INTRA

INTRB

,

INTR

*1)

Output Voltage 2

32KOUT

-0.3 to VDD + 0.3

PD

Power Dissipation

Topt = 25°C

300

mW

Topt

Operating Temperature

-40 to +85

°C

Tstg

Storage Temperature

-55 to +125

°C

*1)R2221L/T:

,

R2223L/T:

,

.

ECO

INTR

INTRA

INTRB

RECOMMENDED OPERATING CONDITIONS

(VSS=0V, Topt=-40 to +85°C)

Symbol	Item		Pin Name				Min,	Typ.	Max.	Unit
Vaccess	Supply Voltage	Power supply voltage					1.5		5.5	V
		for interfacing
		with CPU
VCLK	Time keeping Voltage	CGout,CDout=0pF					0.9		5.50	V
		*1), *2)
VCLKL	Minimum Time keeping	CGout,CDout=0pF						0.6	0.9
	Voltage	*1), *2)
Vxstp	Oscillation halt sensing	power supply which						0.6	0.9	V
	Voltage	satisfies the condition
		XSTP=1 *3)
		CGout=CDout=0pF
		*1)*2)
fXT	Oscillation Frequency							32.768		kHz
VPUP	Pull-up Voltage			,		,			5.5	V
			INTRA		INTRB
		INTR *4)

*1) CGout is connected between OSCIN and VSS, CDout is connected between OSCOUT and VSS. R2221L//T, R2223L/T incorporates the capacitors between OSCIN and VSS, between OSCOUT and VSS. Then normally, CGout and CDout are not necessary.

For more detail, refer to the item named “•Cofiguration of Oscillation Circuit, ECO mode, and Correction of Time

Count Deviations” on P.29.

*2) Quartz crystal unit: CL (load capacity)=6 to 12.5pF, R1 (equivalent series resistance)=under 75 to 80KΩ(Max.) The adjustment method depends on the CL value, R1 value, use or unuse of ECO mode. For more detail, “•Cofiguration of Oscillation Circuit, ECO mode, and Correction of Time Count Deviations” on P.29.

*3) XSTP is the crystal oscillation halt sensing flag. When the crystal oscillation halts, XSTP=1. *4)R2221L/T: ECO , INTR. R2223L/T: INTRA , INTRB

4

R2221L/T, R2223L/T (Preliminary)

DC ELECTRICAL CHARACTERISTICS

(Unless otherwise specified: VSS=0V, VDD=3.0V, Topt=-40 to +85°C, Crystal oscillator 32768Hz)

Symbol

Item

Pin Name

Conditions

Min.

Typ.

Max.

Unit

VIH

“H” Input Voltage

SCL, SDA,

VDD=1.5 to 5.5V

0.8x

5.5

CLKC,

VDD

V

VIL

“L” Input Voltage

*1)

-0.3

0.2x

ECO

VDD

IOH

“H” Output

32KOUT

VOH=VDD-0.5V

-0.5

mA

Current

IOL1

“L” Output

32KOUT

VOL=0.4V

0.5

IOL2

Current

2.0

mA

INTRA

INTRB

INTR *1)

IOL3

SDA

3.0

IIL

Input Leakage

SCL,

VI=5.5V or VSS

-0.2

0.2

μA

Current

ECO

*1)

VDD=5.5V

ICLKC

Pull-down Resister

CLKC

VI=5.5V

0.2

1.00

μA

Input Leakage Current

IOZ

SDA,

VO=5.5V or VSS

-0.2

0.2

Output Off-state

,

VDD=5.5V

μA

INTRA

Current

INTRB

,

INTR

*1)

IDD1

Time Keeping Current

VDD

VDD=3V,

(ECO mode =ON)

Topt=-40 to +85°C

0.18

0.65

μA

*2) *3) *4)

VDD=3V,

0.18

0.5

μA

Topt=-30 to +70°C

*2) *3) *4)

IDD2

Time Keeping Current

VDD

VDD=3V,

0.35

0.9

μA

(ECO mode =OFF)

Topt=-40 to +85°C

*2) *3) *5)

VDD=3V,

0.35

0.75

μA

Topt=-30 to +70°C

*2) *3) *5)

VDET

Supply Voltage

VDD

Topt=-30 to +70°C

1.20

1.35

1.50

V

Monitoring Voltage

*1) R2221L/T:

,

R2223L/T:

,

ECO

INTR

INTRA

INTRB

*2) CGout,CDout=0pFFor time keeping current when outputting 32.768kHz from the 32KOUT pin, see “P.44

•TYPICAL CHARACTERISTICS”. For time keeping current when CGOUT, CDOUT is not equal to 0pF, see “P.31 •Adjustment of oscillation frequency”.

*3) VDD=3V,SCL=SDA=0V, CLKC=0V(32KOUT=OFF), OUTPUT=OPEN, CGout=CDout=0pf

*4) R1 of Crystal=30kΩ

*5) R1 of Crystal=55kΩ

5

R2221L/T, R2223L/T (Preliminary)

AC ELECTRICAL CHARACTERISTICS

Unless otherwise specified: VSS=0V,Topt=-40 to +85°C

Input and Output Conditions: VIH=0.8×VDD,VIL=0.2×VDD,VOH=0.8×VDD,VOL=0.2×VDD,CL=50pF

Sym	Item	Condi-		VDD≥1.5V *1)				Unit
-bol		Tions	Min.		Typ.		Max.
fSCL	SCL Clock Frequency						400	kHz
tLOW	SCL Clock Low Time		1.3					μs
tHIGH	SCL Clock High Time		0.6					μs
tHD;STA	Start Condition Hold Time		0.6					μs
tSU;STO	Stop Condition Set Up Time		0.6					μs
tSU;STA	Start Condition Set Up Time		0.6					μs
tSU;DAT	Data Set Up Time		100					ns
tHD;DAT	Data Hold Time		0					ns
tPL;DAT	SDA “L” Stable Time						0.9	μs
	After Falling of SCL
tPZ;DAT	SDA off Stable Time						0.9	μs
	After Falling of SCL
tR	Rising Time of SCL and SDA						300	ns
	(input)
tF	Falling Time of SCL and SDA						300	ns
	(input)
tSP	Spike Width that can be						50	ns
	removed with Input Filter
tRCV	Recovery Time from Stop		31					μs
	Condition to Start Condition *)

*) For , Recovery Time see “P.28 Interfacing with the CPU •Data Transmission under Special Conditions”.

S

Sr

P

S

SCL

tLOW

tHIGH

tHD;STA

tSP

SDA(IN)

tHD;STA	tSU;DAT	tHD;DAT	tSU;STA	tRCV
				tSU;STO

SDA(OUT)

	tPL;DAT		tPZ;DAT
S	Start Condition	P	Stop Condition
Sr	Repeated Start Condition

6

R2221L/T, R2223L/T (Preliminary)

PACKAGE DIMENSIONS

• R2221L, R2223L(under development)

1.8±0.05

1PIN INDEX

12

1

1

12

0.4

(BOTTOM VIEW)

1.8±0.05

0.43Max

unit: mm

7

R2221L/T, R2223L/T (Preliminary)

• R2221T, R2223T

2.9±0.2

10 6

2.8±0.2

1	5
	0.5

	0.2±0.1	0.1
		0.15 M

0 to 10°

4.0±0.2	0.55±0.2
	0.13 +0.1-0.05
(0.75)	±0.15
+0.1 -0.05	0.85
0.1

unit: mm

8

R2221L/T, R2223L/T (Preliminary)

GENERAL DESCRIPTION

• Interface with CPU

The R2221L/T,R2223L/T is connected to the CPU by two signal lines, SCL and SDA, through which it reads and writes data from and to the CPU. Since the I/O pin of SDA is open drain, data interfacing with a CPU different supply voltage is possible by applying pull-up resistors on the circuit board. The maximum clock frequency of 400kHz (at VDD≥1.5V) of SCL enables data transfer in I2C bus fast mode.

• Clock and Calendar Function

The R2221L/T, R2223L/T reads and writes time data from and to the CPU in units ranging from seconds to the last two digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two digits are a multiple of 4. Consequently, leap years up to the year 2099 can automatically be identified as such.

*) The year 2000 is a leap year while the year 2100 is not a leap year.

• Alarm Function

The R2221L/T, R2223L/T incorporates the alarm interrupt circuit configured to generate interrupt signals to the CPU at preset times. The alarm interrupt circuit allows two types of alarm settings specified by the Alarm_W registers and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings including combinations of multiple day-of-week settings such as "Monday, Wednesday, and Friday" and "Saturday and Sunday". The Alarm_D registers allow hour and minute alarm settings. In case of R2221L/T the Alarm outputs

from INTR In case of R2223L/T the Alarm_W outputs from INTRB pin, and the Alarm_D outputs from INTRA pin. Each alarm function can be checked from the CPU by using a polling function.

• High-precision Oscillation Adjustment Function

The R2221L/T, R2223L/T has built-in oscillation stabilization capacitors (CG and CD), which can be connected to an external crystal oscillator to configure an oscillation circuit. Two kinds of accuracy for this function are alternatives. To correct deviations in the oscillator frequency of the crystal, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to ±1.5ppm or ±0.5ppm at 25°C) from the CPU. The maximum range is approximately ±189ppm (or ±63ppm) in increments of approximately 3ppm (or 1ppm). Such oscillation frequency adjustment in each system has the following advantages:

*Allows timekeeping with much higher precision than conventional RTCs while using a crystal oscillator with a wide range of precision variations.

*Corrects seasonal frequency deviations through seasonal oscillation adjustment.

*Allows timekeeping with higher precision particularly with a temperature sensing function out of RTC, through oscillation adjustment in tune with temperature fluctuations.

• Power-on Reset, Oscillation Halt Sensing Function and Supply Voltage Monitoring Function

The R2221L/T, R2223L/T incorporates an oscillation halt sensing circuit equipped with internal registers configured to record any past oscillation halt.

Power on reset function reset the control resisters when the system is powered on from 0V. At the same time, the fact is memorized to the resister as a flag, thereby identifying whether they are powered on from 0V or battery backed-up.

The R2221L/T, R2223L/T also incorporates a supply voltage monitoring circuit equipped with internal registers configured to record any drop in supply voltage below a certain threshold value. Supply voltage monitoring threshold is VDET.

The oscillation halt sensing circuit and the power-on reset flag are configured to confirm the established invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the supply voltage monitoring circuit can be applied to battery supply voltage monitoring.

9

R2221L/T, R2223L/T (Preliminary)

• Periodic Interrupt Function

The R2221L/T, R2223L/T incorporates the periodic interrupt circuit configured to generate periodic interrupt signals aside from interrupt signals generated by the alarm interrupt circuit for output from the INTR (R2221L/T) or INTRA (R2223L/T) pin. Periodic interrupt signals have five selectable frequency settings of 2 Hz (once per 0.5 seconds), 1 Hz (once per 1 second), 1/60 Hz (once per 1 minute), 1/3600 Hz (once per 1 hour), and monthly (the first day of every month). Further, periodic interrupt signals also have two selectable waveforms, a normal pulse form (with a frequency of 2 Hz or 1 Hz) and special form adapted to interruption from the CPU in the level mode (with second, minute, hour, and month interrupts). The condition of periodic interrupt signals can be monitored with using a polling function.

• 32kHz Clock Output

The R2221L/T, R2223L/T incorporates a 32-kHz clock circuit configured to generate clock pulses with the oscillation frequency of a 32.768kHz crystal oscillator for output from the 32KOUT pin. The 32KOUT pin is CMOS push-pull output and the output is enabled and disabled when the CLKC pin is held high, and low or open, respectively. The 32-kHz clock output can be disabled by certain register settings but cannot be disabled without manipulation of any two registers with different addresses to prevent disabling in such events as the runaway of the CPU. The 32-kHz clock circuit is enabled at power-on, when the CLKC pin is held high.

• ECO mode

In the case that the equivalent series resistance of the crystal oscillator:R1 is small, approximately, R1 equal or less than 60kΩ to 65kΩ , by the pin or setting of the resister, ECO mode can be active, and time keeping consumption current can be reduced. ECO mode is realized by pin as for the R2221L/T, by the resister as for the R2223L/T. In terms of the R2223L/T, if the power supply starts up from 0V, ECO mode turns off. If ECO mode is inactive, if the equivalent series resistance of the crystal oscillator: R1 is large, (approximately equal or less than R1=75 kΩ to 80kΩ), it is possible to use with. When the ECO mode is inactive, time keeping current increases a little. And the oscillation frequency might change slightly whether the ECO mode being turned on or turned off.

10

R2221L/T, R2223L/T (Preliminary)

Address Mapping

Addres

Register Name

D a t a

Default

s

D4

*7)

[A3:A0]

D7

D6

D5

D3

D2

D1

D0

0

[0000]

Second Counter

-

S40

S20

S10

S8

S4

S2

S1

xxh

*2)

1

[0001]

Minute Counter

-

M40

M20

M10

M8

M4

M2

M1

xxh

2

[0010]

Hour Counter

-

-

H20

H10

H8

H4

H2

H1

xxh

P/ A

3

[0011]

Day-of-week

-

-

-

-

-

W4

W2

W1

xxh

Counter

4

[0100]

Day-of-month

-

-

D20

D10

D8

D4

D2

D1

xxh

Counter

5

[0101]

Month

Counter

-

-

-

MO10

MO8

MO4

MO2

MO1

xxh

and Century Bit

6

[0110]

Year Counter

Y80

Y40

Y20

Y10

Y8

Y4

Y2

Y1

xxh

7

[0111]

Oscillation

DEV

F6

F5

F4

F3

F2

F1

F0

00h

Adjustment

*4)

Register *3)

8

[1000]

Alarm_W

-

WM40

WM20

WM10

WM8

WM4

WM2

WM1

xxh

(Minute Register)

9

[1001]

Alarm_W

-

-

WH20

WH10

WH8

WH4

WH2

WH1

xxh

(Hour Register)

WP/ A

A

[1010]

Alarm_W

-

WW6

WW5

WW4

WW3

WW2

WW1

WW0

xxh

(Day-of-week

Register)

B

[1011]

Alarm_D

-

DM40

DM20

DM10

DM8

DM4

DM2

DM1

xxh

(Minute Register)

C

[1100]

Alarm_D

-

-

DH20

DH10

DH8

DH4

DH2

DH1

xxh

(Hour Register)

DP/ A

D

[1101]

User RAM

RAM7

RAM6

RAM5

RAM4

RAM3

RAM2

RAM1

RAM0

00h

E

[1110]

Control

Register

WALE

DALE

/24

TEST

CT2

CT1

CT0

00h

12

CLEN2

1 *3)

F

[1111]

Control

Register

ECO

VDET

XSTP

PON

CTFG

WAFG

DAFG

70h

CLEN1

2 *3)

*6)

*5)

Notes:

*1) All the data listed above accept both reading and writing.

*2) The data marked with "-" is invalid for writing and reset to 0 for reading.

*3) When the PON bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment Register, Control Register 1 and Control Register 2 excluding the XSTP bit and VDET bit.

*4) When DEV=0, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss up to ±1.5ppm. When DEV=1, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss up to or ±0.5ppm.

*5) PON is a power-on-reset flag.

*6) R2221L/T=SCRATCH, R2223L/T=ECO

*7) Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volt. “xxh” means indifinite.

11

R2221L/T, R2223L/T (Preliminary)

Register Settings

• Control Register 1 (ADDRESS Eh)

D7

D6

D5

D4

D3

D2

D1

D0

WALE

DALE

12

/24

CLEN2

TEST

CT2

CT1

CT0

(For Writing)

WALE

DALE

/24

TEST

CT2

CT1

CT0

(For Reading)

12

CLEN2

0

0

0

0

0

0

0

0

Default Settings *)

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volt.

(1) WALE, DALEAlarm_W Enable Bit, Alarm_D Enable Bit

		WALE,DALE								Description				(Default)
		0				Disabling the alarm interrupt circuit (under the control of the settings
						of the Alarm_W registers and the Alarm_D registers).
		1				Enabling the alarm interrupt circuit (under the control of the settings
						of the Alarm_W registers and the Alarm_D registers)
(2)	12 /24					12 /24-hour Mode Selection Bit
		12 /24				Description								(Default)
		0				Selecting the 12-hour mode with a.m. and p.m. indications.
		1				Selecting the 24-hour mode
Setting the			12 /24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.
		24-hour mode				12-hour mode				24-hour mode	12-hour mode
		00				12	(AM12)			12	32	(PM12)
		01				01	(AM 1)			13	21	(PM 1)
		02				02	(AM 2)			14	22	(PM 2)
		03				03	(AM 3)			15	23	(PM 3)
		04				04	(AM 4)			16	24	(PM 4)
		05				05	(AM 5)			17	25	(PM 5)
		06				06	(AM 6)			18	26	(PM 6)
		07				07	(AM 7)			19	27	(PM 7)
		08				08	(AM 8)			20	28	(PM 8)
		09				09	(AM 9)			21	29	(PM 9)
		10				10	(AM10)			22	30	(PM10)
		11				11	(AM11)			23	31	(PM11)
Setting the			12 /24 bit should precede writing time data
(3)	CLEN2					32kHz Clock Output Bit 2
			CLEN2							Description				(Default)
			0			Enabling the 32-kHz clock circuit
			1			Disabling the 32-kHz clock circuit
Setting the					bit or the				bit (D3 in the control register 2) to 0, and the CLKC pin to high
				CLEN2				CLEN1

specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output

from the 32KOUT pin. Conversely, setting both the CLEN1 and CLEN2 bit to 1 or CLKC pin to low specifies disabling (”L”) such output.

(4) TEST		Test Bit
	TEST		Description	(Default)
	0	Normal operation mode.
	1	Test mode.

The TEST bit is used only for testing in the factory and should normally be set to 0.

12

					R2221L/T, R2223L/T (Preliminary)
(5) CT2, CT1, and CT0			Periodic Interrupt Selection Bits
	CT2	CT1	CT0		Description
				Wave form	Interrupt Cycle and Falling Timing
				mode		(Default)
	0	0	0	-	OFF(H)
	0	0	1	-	Fixed at “L”
	0	1	0	Pulse Mode	2Hz (Duty50%)
				*1)
	0	1	1	Pulse Mode	1Hz (Duty50%)
				*1)
	1	0	0	Level Mode	Once per 1 second (Synchronized with
				*2)	second counter increment)
	1	0	1	Level Mode	Once per 1 minute (at 00 seconds of every
				*2)	minute)
	1	1	0	Level Mode	Once per hour (at 00 minutes and 00
				*2)	seconds of every hour)
	1	1	1	Level Mode	Once per month (at 00 hours, 00 minutes,
				*2)	and 00 seconds of first day of every month)

* 1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart below.

CTFG Bit
INTRA Pin
INTR for the R2221L/T	Approx. 46μs
	(Increment of second counter)	Rewriting of the second counter

In the pulse mode, the increment of the second counter is delayed by approximately 46 μs from the falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTRA ( INTR ) pin low.

* 2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below.

		CTFG Bit
				Pin
	INTRA
		(INTR)
				Setting CTFG bit to 0		Setting CTFG bit to 0
				(Increment of	(Increment of	(Increment of
				second counter)	second counter)	second counter)

At the level mode, the moment right after writing CT2-CT0, INTRA ( INTR) pin becomes "L" in very short moment. In such a case, ignore it or confirm it by CTFG bit.

*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or 60sec. as follows:

Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784 ms. For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.

Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784 ms.

13

R2221L/T, R2223L/T (Preliminary)

• Control Register 2 (Address Fh)

D7	D6	D5	D4		D3		D2	D1	D0	(For Writing)
ECO or	VDET	XSTP	PON				CTFG	WAFG	DAFG
					CLEN1
Scratch
ECO or	VDET	XSTP	PON				CTFG	WAFG	DAFG	(For Reading)
					CLEN1
Scratch
0	1	1	1	0			0	0	0	Default Settings *)

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volt.
(1) ECO(R2223L/T),SCRATCH(R2221L/T)			Oscillation Mode Selection Bit
	ECO		Description	(Default)
	0	Normal mode
	1	Low current mode.

When “1” is written on this bit, the IC mode becomes ultra low consumption current oscillation mode (ECO mode). In terms of the selection of ECO mode, refer to the item “ECO mode” on P.30. This bit is available only for the R2223L/T. As for the R2221L/T, “write” and “read” on this bit is possible just same as RAM, but the result has no influence on any function, or SCRATCH bit.

(2) VDET		Supply Voltage Monitoring Result Indication Bit
		VDET	Description
		0	Indicating supply voltage above the supply voltage monitoring
			threshold settings.
		1	Indicating supply voltage below the supply voltage monitoring	(Default)
			threshold settings.

Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring circuit. Conversely, setting the VDET bit to 1 causes no event.

(3) XSTP		Oscillation Halt Sensing Monitor Bit
	XSTP	Description
	0	Sensing a normal condition of oscillation
	1	Sensing a halt of oscillation	(Default)

The XSTP bit will be set to “1” when the oscillation halt is detected. Once this bit becomes “1”, unless otherwise “0” is written, this bit never return to “0”. If “1” is written, nothing will change.

(4) PON		Power-on-reset Flag Bit
		PON	Description
		0	Normal condition
		1	Detecting VDD power-on -reset	(Default)

The PON bit is for sensing power-on reset condition.

*The PON bit will be set to 1 when VDD power-on from 0 volt. The PON bit will hold the setting of 1 even after power-on.

*When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control Regist1, and Control Register 2, except PON,XSTP and VDET . As a result, INTRA and INTRB ( INTR for the R2221L/T) pin stops outputting.

*The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event.

14

								R2221L/T, R2223L/T (Preliminary)
(5) CLEN1					32kHz Clock Output Bit 1
	CLEN1						Description		(Default)
	0				Enabling the 32-kHz clock circuit
	1				Disabling the 32-kHz clock circuit
Setting the				bit or the			bit (D4 in the control register 1) to 0, and the CLKC pin to high
		CLEN1				CLEN2

specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output

from the 32KOUT pin. Conversely, setting both the CLEN1 and CLEN2 bit to 1 or CLKC pin to low specifies disabling (”L”) such output.

(6) CTFG		Periodic Interrupt Flag Bit
	CTFG	Description	(Default)
	0	Periodic interrupt output = “H”
	1	Periodic interrupt output = “L”

The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTRA ( INTR for the R2221L/T) pin (“L”). The CTFG bit accepts only the writing of 0 in the level mode, which disables (“H”) the INTRA ( INTR for the R2221L/T) pin until it is enabled (“L”) again in the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.

(7) WAFG,DAFG		Alarm_W Flag Bit and Alarm_D Flag Bit
	WAFG,DAFG	Description	(Default)
	0	Indicating a mismatch between current time and preset alarm time
	1	Indicating a match between current time and preset alarm time

The WAFG and DAFG bits are valid only when the WALE and DALE have the setting of 1, which is caused approximately 15μs after any match between current time and preset alarm time specified by the Alarm_W registers and the Alarm_D registers. The WAFG (DAFG) bit accepts only the writing of 0.

		INTRA		/		INTRB		( INTR for the R2221L/T) pin outputs off (“H”) when this bit is set	to 0. And
	INTRA		/		INTRB		( INTR for the R2221L/T) pin outputs “L” again at the next preset alarm time.		Conversely,

setting the WAFG and DAFG bits to 1 causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is disabled with the WALE and DALE bits set to 0. The settings of the WAFG and DAFG bits are synchronized with the output of the INTRA / INTRB ( INTR for the R2221L/T) pin as shown in the timing chart below.

						Approx. 15μs			Approx. 15μs
		WAFG(DAFG) Bit
				Pins
INTRB		/	INTRA
INTR	pin for the R2221L/T									Writing of 0 to
						Writing of 0 to
						WAFG(DAFG) bit				WAFG(DAFG) bit
				(Match between			(Match between			(Match between
				current time and			current time and			current time and
				preset alarm time)			preset alarm time)			preset alarm time)

15

R2221L/T, R2223L/T (Preliminary)

• Time Counter (Address 0-2h)

Second Counter (Address 0h)

D7

D6

D5

D4

D3

D2

D1

D0

(For Writing)

-

S40

S20

S10

S8

S4

S2

S1

0

S40

S20

S10

S8

S4

S2

S1

(For Reading)

0

Indefi

Indefi

Indefi

Indefi

Indefi

Indefi

Indefi

Default Settings *)

nite

nite

nite

nite

nite

nite

nite

Minute Counter (Address 1h)

D7

D6

D5

D4

D3

D2

D1

D0

(For Writing)

-

M40

M20

M10

M8

M4

M2

M1

0

M40

M20

M10

M8

M4

M2

M1

(For Reading)

0

Indefi

Indefi

Indefi

Indefi

Indefi

Indefi

Indefi

Default Settings *)

nite

nite

nite

nite

nite

nite

nite

Hour Counter (Address 2h)

D7

D6

D5

D4

D3

D2

D1

D0

(For Writing)

-

-

P/

A

H10

H8

H4

H2

H1

or

0

0

H20

H10

H8

H4

H2

H1

(For Reading)

P/

A

or

H20

0

0

Indefi

Indefi

Indefi

Indefi

Indefi

Indefi

Default Settings *)

nite

nite

nite

nite

nite

nite

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volt.

* Time digit display (BCD format) as follows:

The second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00. The minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00.

The hour digits range as shown in "P12 • Control Register 1 (ADDRESS Eh) (2) 12 /24: 12 /24-hour Mode Selection Bit" and are carried to the day-of-month and day-of-week digits in transition from PM11 to AM12 or from 23 to 00.

*Any writing to the second counter resets divider units of less than 1 second.

*Any carry from lower digits with the writing of non-existent time may cause the time counters to malfunction. Therefore, such incorrect writing should be replaced with the writing of existent time data.

•Day-of-week Counter (Address 3h)

	D7	D6		D5	D4	D3	D2	D1	D0	(For Writing)
	-	-		-	-	-	W4	W2	W1
	0	0		0	0	0	W4	W2	W1	(For Reading)
	0	0		0	0	0	Indefi	Indefi	Indefi	Default Settings *)
							nite	nite	nite
*) Default settings:			Default value means read / written values when the PON bit is set to “1” due to VDD

power-on from 0 volt.

*The day-of-week counter is incremented by 1 when the day-of-week digits are carried to the day-of-month digits.

*Day-of-week display (incremented in septimal notation):

(W4, W2, W1) = (0, 0, 0) → (0, 0, 1)→…→(1, 1, 0) → (0, 0, 0)

* Correspondence between days of the week and the day-of-week digits are user-definable (e.g. Sunday = 0,

16