RICOH R2051 Technical data

R2051 SERIES

2 wire interface Real-Time Clock ICs with Battery Backup switch-over Function

NO.EA-104-070626

OUTLINE

The R2051 is a CMOS real-time clock IC connected to the CPU by two signal lines, SCL and SDA, and configured to perform serial transmission of time and calendar data to the CPU. Further, battery backup switchover circuit and a voltage detector are incorporated. The periodic interrupt circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2 alarm interrupt circuits generate interrupt signals at preset times. As the oscillation circuit is driven under constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time keeping current is small (TYP. 0.4µA at 3V). The oscillation halt sensing circuit can be used to judge the validity of internal data in such events as power-on; The supply voltage monitoring circuit is configured to record a drop in supply voltage below two selectable supply voltage monitoring threshold settings. The 32.768kHz clock output function (CMOS output) is intended to output sub-clock pulses for the external microcomputer. The oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency of the quartz crystal unit. Battery backup switchover function is the automatic switchover circuit between a main power supply and a backup battery of primary or secondary battery. Switchover is executed by monitoring the voltage of a main power supply, therefore the voltage of a backup battery voltage is not relevant. Since the package for these ICs is SSOP16 (5.0x6.4x1.25: R2051Sxx), FFP12 (2.0x2.0x1.0: R2051Kxx), or TSSOP10G (4.0x2.9x1.0: R2051Txx), high density mounting of ICs on boards is possible.

FEATURES

• Minimum Timekeeping supply voltage Typ. 0.75V (Max. 1.00V); VDD pin

• Low power consumption 0.4µA TYP (1.0µA MAX.)

• Built-in Backup switchover circuit (can be used for a primary battery, a secondary battery, or an electric double

layer capacitor)

• Only two signal lines (SCL and SDA) required for connection to the CPU. ( I

• Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days,

and weeks) (in BCD format)

• Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to the CPU and provided with an interrupt flag and an interrupt halt (except R2051Txx)

• 2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and minute alarm settings) (except R2051Txx)

• Built-in voltage detector with delay

• With Power-on flag to prove that the power supply starts from 0V

• 32-kHz clock output pin (CMOS output. “H” level is always equal to VCC.)

• Supply voltage monitoring circuit with two supply voltage monitoring threshold settings

• Automatic identification of leap years up to the year 2099

• Selectable 12-hour and 24-hour mode settings

• High precision oscillation adjustment circuit

• Built-in oscillation stabilization capacitors (CG and CD)

• CMOS process

• Package SSOP16 (5.0mm x 6.4mm x 1.25mm : R2051Sxx), FFP12 (2.0mm x 2.0mm x 1.0mm : R2051Kxx)

TSSOP10G (4.0x2.9x1.0: R2051Txx)

at VDD=3V

C-Bus Interface, 400kHz)

R2051 Series

(NC)

PIN CONFIGURATION

R2051Sxx(SSOP16)

VSB

CLKOUT

SCL SDA

VDCC

VSS

2 3

4 5

6 7

16 15 14 13 12 11 10

TOP VIEW

BLOCK DIAGRAM

VSB

OSCIN

OSCOUT

BATTERY VOLTAGE MONITOR

CLOCK

VCC VDD NC OSCIN OSCOUT

NC INTR

CIN

SW2

REAL

TIME

R2051Kxx(FFP12)

CIN

VSS

VDCC

VDD

11 12

OSCOUT

SCL

OSCIN

INTR

CLKOUT

TOP VIEW

SW1

VOLTAGE

DETECTOR

DELAY

R2051Txx(TSSOP10G)

9 8 7

VCC VDD OSCIN OSCOUT

CIN VSS

VSB

CLKOUT

VDD

VCC

VSB

SCL

SDA

1 2

3 4 5 6

TOP VIEW

CPU POWER

SUPLLY

VCC

VDCC

SHIFTER

LEVEL

SCL

SDA

CLKOUT

CPU

CIN

VSS

( ) are for the R2051Txx only

VOLTAGE

REFERENCE

INTR

SELECTION GUIDE

In the R2051xxx Series, output voltage and options can be designated.

Part Number is designated as follows: R2051K01-E2 ←Part Number ↑ ↑ ↑ R2051abb-cc

Code Description

Designation of the package.

bb Serial number of Voltage detector setting etc. cc Designation of the taping type. Only E2 is available.

Part Number Package -V

R2051K01-E2 FFP12 2.40(Typ.) P.6 R2051K02-E2 FFP12 2.80(Typ.) P.7 R2051S01-E2 SSOP16 2.40(Typ.) P.6 R2051S02-E2 SSOP16 2.80(Typ,) P.7 R2051S03-E2 SSOP16 4.00(Typ.) P.8 R2051T01-E2 TSSOP10G 2.40(Typ.) P.6

K: FFP12 S: SSOP16 T: TSSOP10G

DET1 (switch-over threshold) DC Electrical

R2051 Series

Characteristics

R2051 Series

PIN DESCRIPTION

R2051Kxx

(FFP12)

R2051Sxx

(SSOP16)

R2051Txx

(TSSOP10G)

Symbol Item Description

2 4 3 SCL Serial

Clock Line

1 5 4 SDA Serial

Data Line

9 10 -

INTR

Interrupt Output

3 3 2 CLKOUT 32kHz Clock

Output

5 16 10 VCC Main Battery

input

4 2 1 VSB Power Supply

Input for Backup Battery

7 13 8 OSCIN

Oscillation Circuit

8 12 7 OSCOUT

Input / Output

6 15 9 VDD Positive Power

Supply Input

12 7 -

VDCC

VCC Power Supply Monitoring Result Output

10 9 6 CIN Noise Bypass

11 8 5 VSS Negative

Power Supply Input

- 1,6,

- NC No Connection

11,14

The SCL pin is used to input clock pulses synchronizing the input and output of data to and from the SDA pin. Allows a maximum input voltage of 5.5 volts regardless of supply voltage. The SDA pin is used to input or output data intended for writing or reading in synchronization with the SCL pin. Up to

5.5v beyond VDD may be input. This pin functions as an Nch open drain output.

INTR

The

pin is used to output alarm interrupt (Alarm_W) and alarm interrupt (Alarm_D) and output periodic interrupt signals to the CPU. Disabled at power-on from 0V. Nch. open drain output. The CLKOUT pin is used to output

32.768-kHz clock pulses. CMOS output. “H” level is always equal to VCC. Supply power to the IC.

Connect a primary battery for backup. Normally, power is supplied from VCC to the IC. If VCC level is equal or less than –V

DET1, power is supplied from this pin.

The OSCIN and OSCOUT pins are used to connect the 32.768-kHz quartz crystal unit (with all other oscillation circuit components built into the R2051).

The VDD pin is connected to the power supply. Connect a capacitor as much as

0.1µF between VDD and VSS. In the case of using a secondary battery, connecting the secondary battery to this pin is possible. While monitoring VCC Power supply, if the voltage is equal or lower than –V

DET1, this output level is “L”. When

VDCC

becomes “L”, SW1 turns off and SW2 turns on. As a result, power is supplied from VSB pin to the internal real time clock. When VCC is equal to +V

DET1

or more, SW1 turns on and SW2 turns off. After t DELAY passed,

VDCC

output becomes off, or “H”.ch Open-drain output. To stabilize the internal reference, connect a capacitor as much as 0.1µF between this pin and VSS. The VSS pin is grounded.

R2051 Series

ABSOLUTE MAXIMUM RATINGS

(VSS=0V)

Symbol Item Pin Name Description Unit

VCC Supply Voltage 1 VCC -0.3 to +6.5 V VDD Supply Voltage 2 VDD -0.3 to +6.5 V VSB Supply Voltage 3 VSB -0.3 to +6.5 V

Input Voltage 1 SCL, SDA -0.3 to +6.5 V VI Input Voltage 2 CIN -0.3 to V

IOUT Maximum Output Current VDD 10 mA PD Power Dissipation Topt Operating Temperature -40 to +85 Tstg Storage Temperature -55 to +125

*1) Except R2051Txx

Output Voltage 1 Output Voltage 2 CLKOUT -0.3 to V

INTR

Topt = +25°C

VDCC

*1)

-0.3 to +6.5 V

300 mW

DD+0.3 V

CC+0.3 V

°C °C

RECOMMENDED OPERATING CONDITIONS

(VSS=0V, Topt=-40 to +85°C)

Symbol Item Pin Name Min, Typ. Max. Unit

Vaccess Supply Voltage VCC power supply

voltage for interfacing with CPU

VCLK Minimum Timekeeping

Voltage CGout,CDout=0pF

*2), *3) fXT Oscillation Frequency 32.768 kHz VPUP Pull-up Voltage

*1) -VDET1 in Vaccess specification is guaranteed by design. *2) CGout is connected between OSCIN and VSS, CDout is connected between OSCOUT and VSS. R2051 series incorporates the capacitors between OSCIN and VSS, between OSCOUT and VSS. Then normally, CGout and CDout are not necessary. *3) Quartz crystal unit: CL=6-8pF, R1=30KΩ *4) Except R2051Txx

0.75 1.00 V

INTR

VDCC

*4)

-VDET1 *1)

5.5 V

R2051 Series

DC ELECTRICAL CHARACTERISTICS

• R2051K01, R2051S01, R2051T01

(Unless otherwise specified: VSS=0V,VCC=VSB=3.0V, 0.1uF between VDD and VSS, CIN and VSS, Topt=-40 to +85°C)

Symbol Item Pin Name Conditions Min. Typ. Max. Unit

VIH “H” Input Voltage 0.8x

SCL,SDA

VCC

VIL “L” Input Voltage IOH “H” Output

CLKOUT VOH=VCC-0.5V -0.5 mA

-0.3 0.2x

Current IOL1 CLKOUT 0.5 IOL2 *2)

“L” Output

Current

INTR

IOL4 SDA IOL3 *2)

VDCC

OL=0.4V

2.0

3.0

DD,VSB,VCC=2.0V

0.5

VOL=0.4V

IIL Input Leakage

SCL VI=5.5V or VSS -1.0 1.0

Current IOZ1 Output Off-state

SDA VO=5.5V or VSS -1.0 1.0

Current 1 IOZ2 *2) Output Off-state

Current 2 ISB Time Keeping Current

at Backup mode

INTR

VDCC

VSB VCC=0V, VSB=3.0V,

O=5.5V or VSS

VDD, Output=OPEN

-1.0 1.0

0.4 1.0

Time keeping

ISBL Leakage Current of

Backup pin at

VCC_on VDETH Supply Voltage

Monitoring Voltage

VSB VCC=3.0V,

VSB=5.5V or 0V, VDD, Output=OPEN

VDD

Topt=+25°C

-1.00 1.00

1.90 2.10 2.30 V

“H” VDETL Supply Voltage

Monitoring Voltage “L”

-VDET1 Detector Threshold

VDD VCC

Topt=+25°C Topt=+25°C

1.20 1.35 1.50 V

2.34 2.40 2.46 V Voltage (falling edge of VCC)

+VDET1 Detector Released

VCC

Topt=+25°C

2.44 2.52 2.60 V Voltage (rising edge of VCC)

∆VDET ∆Topt

Detector Threshold and Released Voltage

VCC, VSB

Topt=-40 to +85°C

*1) Temperature coefficient

VDDOUT1 VDD Output

Voltage 1

VDDOUT2 VDD Output

Voltage 2

CG Internal Oscillation

VDD VDD

Topt=+25°C, V

CC=3.0V,

Iout=1.0mA

Topt=+25°C, V

CC=2.0V,

VSB=3.0V, Iout=0.1mA

-0.12

-0.08

OSCIN 10

Capacitance 1

CD Internal Oscillation

OSCOUT 10

Capacitance 2

*1) Guaranteed by design. *2) Except R2051T01

5.5 V

VCC

µA µA µA

µA

±100

ppm

/°C

VCC

-0.04

VSB

-0.02 pF

R2051 Series

• R2051K02, R2051S02

(Unless otherwise specified: VSS=0V,VCC=3.3V, VSB=3.0V, 0.1uF between VDD and VSS, CIN and VSS, Topt=-40 to +85°C)

Symbol Item Pin Name Conditions Min. Typ. Max. Unit

VIH “H” Input Voltage 0.8x

SCL,SDA

VCC

VIL “L” Input Voltage IOH “H” Output

CLKOUT VOH=VCC-0.5V -0.5 mA

-0.3 0.2x

Current IOL1 CLKOUT 0.5 IOL2

“L” Output

Current

INTR

IOL4 SDA IOL3

VDCC

OL=0.4V

2.0

3.0

DD,VSB,VCC=2.0V

0.5

VOL=0.4V

IIL Input Leakage

SCL VI=5.5V or VSS -1.0 1.0

Current IOZ1 Output Off-state

SDA VO=5.5V or VSS -1.0 1.0

Current 1 IOZ2 Output Off-state

Current 2 ISB Time Keeping Current

at Backup mode

INTR

VDCC

VSB VCC=0V, VSB=3.0V,

O=5.5V or VSS

VDD, Output=OPEN

-1.0 1.0

0.4 1.0

Time keeping

ISBL Leakage Current of

Backup pin at

VCC_on VDETH Supply Voltage

Monitoring Voltage

VSB VCC=3.3V,

VSB=5.5V or 0V, VDD, Output=OPEN

VDD

Topt=+25°C

-1.00 1.00

1.90 2.10 2.30 V

“H” VDETL Supply Voltage

Monitoring Voltage “L”

-VDET1 Detector Threshold

VDD VCC

Topt=+25°C Topt=+25°C

1.20 1.35 1.50 V

2.73 2.80 2.87 V Voltage (falling edge of VCC)

+VDET1 Detector Released

VCC

Topt=+25°C

2.85 2.94 3.03 V Voltage (rising edge of VCC)

∆VDET ∆Topt

Detector Threshold and Released Voltage

VCC, VSB

Topt=-40 to +85°C

*1) Temperature coefficient

VDDOUT1 VDD Output

Voltage 1

VDDOUT2 VDD Output

Voltage 2

CG Internal Oscillation

VDD VDD

Topt=+25°C, V

CC=3.3V,

Iout=1.0mA

Topt=+25°C, V

CC=2.0V,

VSB=3.3V, Iout=0.1mA

-0.12

-0.08

OSCIN 10

Capacitance 1

CD Internal Oscillation

OSCOUT 10

Capacitance 2

*1) Guaranteed by design.

5.5 V

VCC

µA µA µA

µA

±100

ppm

/°C

VCC

-0.04

VSB

-0.02 pF

R2051 Series

• R2051S03

(Unless otherwise specified: VSS=0V, VCC=5.0V, VSB=3.0V, 0.1uF between VDD and VSS, CIN and VSS, Topt=-40 to +85°C)

Symbol Item Pin Name Conditions Min. Typ. Max. Unit

VIH “H” Input Voltage 0.8x

SCL,SDA

VCC

VIL “L” Input Voltage IOH “H” Output

CLKOUT VOH=VCC-0.5V -0.5 mA

-0.3 0.2x

Current IOL1 CLKOUT 0.5 IOL2

“L” Output

Current

INTR

IOL4 SDA IOL3

VDCC

OL=0.4V

2.0

3.0

DD,VSB,VCC=2.0V

0.5

VOL=0.4V

IIL Input Leakage

SCL VI=5.5V or VSS -1.0 1.0

Current IOZ1 Output Off-state

SDA VO=5.5V or VSS -1.0 1.0

Current 1 IOZ2 Output Off-state

Current 2 ISB Time Keeping Current

at Backup mode

INTR

VDCC

VSB VCC=0V, VSB=3.0V,

O=5.5V or VSS

VDD, Output=OPEN

-1.0 1.0

0.4 1.0

Time keeping

ISBL Leakage Current of

Backup pin at

VCC_on VDETH Supply Voltage

Monitoring Voltage

VSB VCC=5.0V,

VSB=5.5V or 0V, VDD, Output=OPEN

VDD

Topt=+25°C

-1.00 1.00

1.90 2.10 2.30 V

“H” VDETL Supply Voltage

Monitoring Voltage “L”

-VDET1 Detector Threshold

VDD VCC

Topt=+25°C Topt=+25°C

1.20 1.35 1.50 V

3.90 4.00 4.10 V Voltage (falling edge of VCC)

+VDET1 Detector Released

VCC

Topt=+25°C

4.07 4.20 4.33 V Voltage (rising edge of VCC)

∆VDET ∆Topt

Detector Threshold and Released Voltage

VCC, VSB

Topt=-40 to +85°C

*1) Temperature coefficient

VDDOUT1 VDD Output

Voltage 1

VDDOUT2 VDD Output

Voltage 2

CG Internal Oscillation

VDD VDD

Topt=+25°C, V

CC=5.0V,

Iout=1.0mA

Topt=+25°C, V

CC=2.0V,

VSB=3.0V, Iout=0.1mA

-0.12

-0.08

OSCIN 10

Capacitance 1

CD Internal Oscillation

OSCOUT 10

Capacitance 2

*1) Guaranteed by design.

5.5 V

VCC

µA µA µA

µA

±100

ppm

/°C

VCC

-0.04

VSB

-0.02 pF

R2051 Series

AC ELECTRICAL CHARACTERISTICS

Unless otherwise specified: VSS=0V,Topt=-40 to +85°C Input and Output Conditions: V

Sym

Item Condi-

-bol

SCL Clock Frequency 100 400 kHz

SCL

SCL Clock Low Time 4.7 1.3

LOW

SCL Clock High Time 4.0 0.6

HIGH

Start Condition Hold

HD;STA

Time

SU;ST

SU;STA

Stop Condition Set Up Time

Start Condition Set Up

Time

Data Set Up Time 250 200 ns

SU;DAT

HD;DA

PL;DAT

Data Hold Time 0 0 ns

SDA “L” Stable Time

After Falling of SCL

SDA off Stable Time

PZ;DAT

After Falling of SCL

tR Rising Time of SCL

and SDA (input)

tF Falling Time of SCL

and SDA (input)

tSP Spike Width that can

be removed with Input Filter

Recovery Time from

RCV

Stop Condition to Start Condition

DELAY

*2)

Output Delay Time of

Voltage Detector *1) VCC voltage interfacing with CPU is defined by Vaccess (P.5 RECOMMENDED OPERATING CONDITIONS) *2) Except R2051Txx *) For reading/writing timing, see “P.34 Interfacing with the CPU •Data Transmission under Special Condition”.

IH=0.8×VCC,VIL=0.2×VCC,VOH=0.8×VCC,VOL=0.2×VCC,CL=50pF

CC≥1.7V *1) VCC≥2.5V *1)

Tions

Min. Typ. Max. Min. Typ. Max.

4.0 0.6

4.7 0.6

2.0 0.9

2.0 0.9 1000 300 ns 300 300 ns 50 50 ns

62 62

Time Keeping

100 105 110 100 105 110 ms

Unit

µs µs µs

µs µs

µs

R2051 Series

SCL

Sr P

SDA(IN)

SDA(OUT)

VCC

VDCC

LOW

PL;DA

SU;DA

HD;ST

Start Condition

Repeated Start Condition

DET1

DELAY

Stop Condition

HIGH

HD;DA

PZ;DA

SU;ST

HD;ST

SU;STO

PACKAGE DIMENSIONS

• R2051Kxx

9 7

R2051 Series

0.103

0.5

1PIN INDEX

2PIN INDEX

0.15

0.3

0.2±0.15

(BOTTOM VIEW)

0.05

3 1

0.35

0.1

2.0

0.35

0.25

1.0Max

0.17±0.1

0.27±0.15

2.0±0.1

unit: mm

R2051 Series

• R2051Sxx

5.0±0.3

0 to 10°

0.225typ

0.65

4.4±0.2

6.4±0.3

0.5±0.3

+0.1

0.15

-0.05

1.15±0.1

0.22

+0.1

-0.05

0.10

0.15

0.1±0.1

unit: mm

• R2051Txx

R2051 Series

2.9±0.2

0.2±0.1

0.5

0.1

0.15

0 to 10

2.8±0.2

4.0±0.2

0.55±0.2

+0.1

0.13

-0.05

(0.75)

-0.05

+0.1

0.85±0.15

0.1

unit: mm

R2051 Series

GENERAL DESCRIPTION

• Battery Backup Switchover Function

The R2051 has two power supply input, or VCC and VSB. With monitoring input voltage of VCC pin by internal

Voltage Detector, it is selected which power supply of VCC or VSB is used for the internal power source.

Refer to the next table to see the state of the backup battery and internal power supply’s state of the IC by each

condition.

CC≥VDET1 VCC<VDET1

VCC→RTC, VDD

VDCC

=OFF(H) (except R2051Txx)

As a backup battery, not only a primary battery such as CR2025, LR44, or a secondary battery such as ML614,

TC616, but also an electric double layered capacitor or an aluminum capacitor can be used. Switchover point is judged with the voltage of the main power (VCC), therefore, if the backup voltage is higher than main supply voltage, switchover can be realized without extra load to the backup power supply.

The case of back-up by primary battery

The case of back-up by capacitor or secondary battery (Charging voltage is equal to CPU power supply v oltage)

VSB→RTC, VDD

VDCC

=L (except R2051Txx)

The case of back - up by capacitor or secondary battery (Charging voltage is not equal to CPU power supply v o ltage)

VCC

VSB

VDD

VSS

CPU Power Supply

0.1µF

CR2025 etc.

VCC

VSB

VDD

VSS

CPU power supply

0.1µF

ML614 etc.

VCC

VSB

VDD

VSS

CPU power supply (3V)

0.1µF

Double layer capacitor etc.

• Interface with CPU

The R2051 is connected to the CPU by two signal lines SCL and SDA, through which it reads and writes data from and to the CPU. Since the output of the I/O pin of SDA is open drain, data interfacing with a CPU different supply voltage is possible by applying pull-up resistors on the circuit board. The maximum clock frequency of 400kHz (at V

DD=3V) of SCL enables data transfer in I2C-Bus fast mode. VCC falls down under -VDET1, the R2051

stops accessing with CPU.

• Clock and Calendar Function

The R2051 reads and writes time data from and to the CPU in units ranging from seconds to the last two digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two digits are a multiple of 4. Consequently, leap years up to the year 2099 can automatically be identified as such.

*) The year 2000 is a leap year while the year 2100 is not a leap year.

R2051 Series

• Alarm Function

The R2051 incorporates the alarm interrupt circuit configured to generate interrupt signals to the CPU at preset times. The alarm interrupt circuit allows two types of alarm settings specified by the Alarm_W registers and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings including combinations of multiple day-of-week settings such as "Monday, Wednesday, and Friday" and "Saturday and Sunday". The Alarm_D registers allow hour and minute alarm settings. The Alarm_W outputs from

INTR

outputs also from R2051Txx has Alarm_D and Alarm_W registers, but does not have

pin. Each alarm function can be checked from the CPU by using a polling function.

INTR

output pin.

INTR

pin, and the Alarm_D

• High-precision Oscillation Adjustment Function

The R2051 has built-in oscillation stabilization capacitors (CG and CD), that can be connected to an quartz crystal unit to configure an oscillation circuit. Two kinds of accuracy for this function are alternatives. To correct deviations in the oscillator frequency of the crystal, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to ±1.5ppm or ±0.5ppm at 25°C) from the CPU. The maximum range is approximately ±189ppm (or ±63ppm) in increments of approximately 3ppm (or 1ppm). Such oscillation frequency adjustment in each system has the following advantages:

* Allows timekeeping with much higher precision than conventional RTCs while using a quartz crystal unit with a wide range of precision variations.

* Corrects seasonal frequency deviations through seasonal oscillation adjustment.

* Allows timekeeping with higher precision particularly with a temperature sensing function out of RTC, through oscillation adjustment in tune with temperature fluctuations.

• Power-on Reset, Oscillation Halt Sensing Function and Supply Voltage Monitoring Function

The R2051 has 3 power supply pins (VCC, VSB, VDD), among them, VCC pin and VDD pin have monitoring function of supply voltage. VCC power supply monitoring circuit makes pin becomes equal or lower than –V after the delay time, tDELAY from when the VCC power supply pin becomes equal or more than +V R2051Txx does not have

The R2051 incorporates an oscillation halt sensing circuit equipped with internal registers configured to record any past oscillation halt, the oscillation halt sensing circuit, VDD monitoring flag, and power-on reset flag are useful for judging the validity of time data.

Power on reset function reset the control resisters when the system is powered on from 0V. At the same time, the fact is memorized to the resister as a flag, thereby identifying whether they are powered on from 0V or battery backed-up.

The R2051 also incorporates a supply voltage monitoring circuit equipped with internal registers configured to record any drop in supply voltage below a certain threshold value. Supply voltage monitoring threshold settings can be selected between 2.1V and 1.35V through internal register settings. The sampling rate is normally 1s. The oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the supply voltage monitoring circuit can be applied to battery supply voltage monitoring.

VDCC

DET1. At the power-on of VCC, this circuit makes

output pin.

VDCC

pin “L” when VCC power supply

VDCC

pin turn off, or “H”

DET1.

• Periodic Interrupt Function

The R2051 incorporates the periodic interrupt circuit configured to generate periodic interrupt signals aside from interrupt signals generated by the periodic interrupt circuit for output from the have five selectable frequency settings of 2 Hz (once per 0.5 seconds), 1 Hz (once per 1 second), 1/60 Hz (once per 1 minute), 1/3600 Hz (once per 1 hour), and monthly (the first day of every month). Further, periodic interrupt signals also have two selectable waveforms, a normal pulse form (with a frequency of 2 Hz or 1 Hz) and special

INTR

pin. Periodic interrupt signals

R2051 Series

form adapted to interruption from the CPU in the level mode (with second, minute, hour, and month interrupts). The condition of periodic interrupt signals can be monitored with using a polling function. R2051Txx has the periodic

INTR

interrupt registers, but does not have

output pin.

• 32kHz Clock Output

The R2051 incorporates a 32-kHz clock circuit configured to generate clock pulses with the oscillation frequency of a 32.768kHz quartz crystal unit for output from the CLKOUT pin (CMOS push-pull output). The 32-kHz clock output is always enabled and the “H” level of the CLKOUT pin is same as VCC power supply.

R2051 Series

Address Mapping

Address Register Name D a t a A3A2A1A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 Second Counter -

*2) 1 0 0 0 1 Minute Counter - M40 M20 M10 M8 M4 M2 M1 2 0 0 1 0 Hour Counter - - H20

3 0 0 1 1 Day-of-week

Counter

4 0 1 0 0 Day-of-month

Counter

5 0 1 0 1 Month Counter and

Century Bit 6 0 1 1 0 Year Counter Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 7 0 1 1 1 Oscillation

Adjustment

(Minute Register) 9 1 0 0 1 Alarm_W

(Hour Register) A 1 0 1 0 Alarm_W

(Day-of-week

(Minute Register) C 1 1 0 0 Alarm_D

(Hour Register) D 1 1 0 1 - - - - - - - -

E 1 1 1 0 Control Register 1

*3) F 1 1 1 1 Control Register 2

*3)

Notes: * 1) All the data listed above accept both reading and writing. * 2) The data marked with "-" is invalid for writing and reset to 0 for reading. * 3) When the PON bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment Register, Control Register 1 and Control Register 2 excluding the * 4) When DEV=0, the oscillation adjustment circuit is configured to allow correction of a time count gain or

loss up to ±1.5ppm. When DEV=1, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss up to or ±0.5ppm.

* 5) PON is a power-on-reset flag.

- - - - - W4 W2 W1

- - D20 D10 D8 D4 D2 D1

DEV *4)

- WM40 WM20 WM10 WM8 WM4 WM2 WM1

- - WH20

- WW6 WW5 WW4 WW3 WW2 WW1 WW0

- DM40 DM20 DM10 DM8 DM4 DM2 DM1

- - DH20

WALE DALE VDSL VDET

S40 S20 S10 S8 S4 S2 S1

H10 H8 H4 H2 H1

- - MO10 MO8 MO4 MO2 MO1

/20

F6 F5 F4 F3 F2 F1 F0

WH10 WH8 WH4 WH2 WH1

WP/

DH10 DH8 DH4 DH2 DH1

DP/

XST

/24

SCRA

TCH2 PON *5)

XST

TEST CT2 CT1 CT0

SCRA TCH1

bit.

CTFG WAFG DAFG

R2051 Series

• Control Register 1 (Address Eh)

D7 D6 D5 D4 D3 D2 D1 D0

WALE DALE WALE DALE

0 0 0 0 0 0 0 0 Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

12 12

/24 /24

(1) WALE, DALE Alarm_W Enable Bit, Alarm_D Enable Bit

WALE,DALE Description

0 Disabling the alarm interrupt circuit (under the control of the settings

of the Alarm_W registers and the Alarm_D registers).

1 Enabling the alarm interrupt circuit (under the control of the settings

of the Alarm_W registers and the Alarm_D registers)

(2)

Setting the

/24

/24 Description

0 Selecting the 12-hour mode with a.m. and p.m. indications. (Default) 1 Selecting the 24-hour mode

/24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.

24-hour mode 12-hour mode 24-hour mode 12-hour mode

00 12 (AM12) 12 32 (PM12) 01 01 (AM 1) 13 21 (PM 1) 02 02 (AM 2) 14 22 (PM 2) 03 03 (AM 3) 15 23 (PM 3) 04 04 (AM 4) 16 24 (PM 4) 05 05 (AM 5) 17 25 (PM 5) 06 06 (AM 6) 18 26 (PM 6) 07 07 (AM 7) 19 27 (PM 7) 08 08 (AM 8) 20 28 (PM 8) 09 09 (AM 9) 21 29 (PM 9) 10 10 (AM10) 22 30 (PM10) 11 11 (AM11) 23 31 (PM11)

/24 bit should precede writing time data

/24-hour Mode Selection Bit

(3) SCRATCH2 Scratch Bit 2

SCRATCH2 Description

0 (Default)

1 The SCRATCH2 bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH2 bit will be set to 0 when the PON bit is set to 1 in the Control Register 1.

(4) TEST Test Bit

TEST Description

0 Normal operation mode. (Default)

1 Test mode. The TEST bit is used only for testing in the factory and should normally be set to 0.

SCRA

TCH2

SCRA

TCH2

TEST CT2 CT1 CT0 (For Writing) TEST CT2 CT1 CT0 (For Reading)

(Default)

R2051 Series

(5) CT2, CT1, and CT0 Periodic Interrupt Selection Bits

Description CT2 CT1 CT0

Wave form

mode

0 0 0 - OFF(H) (Default) 0 0 1 - Fixed at “L” 0 1 0 Pulse Mode

*1)

0 1 1 Pulse Mode

*1)

1 0 0 Level Mode

*2)

1 0 1 Level Mode

*2)

1 1 0 Level Mode

*2)

1 1 1 Level Mode

*2)

* 1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart below.

Interrupt Cycle and Falling Timing

2Hz (Duty50%) 1Hz (Duty50%) Once per 1 second (Synchronized with

second counter increment) Once per 1 minute (at 00 seconds of every minute) Once per hour (at 00 minutes and 00 seconds of every hour) Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month)

CTFG Bit

INTR Pin

pprox. 92µs

(Increment of second count er)

Rewriting of the second counter

In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will reset the other time counters of less than 1 second, driving the

INTR

pin low.

* 2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below.

CTFG Bit

INTR Pin

Setting CTFG bit to 0

(Increment of second counter)

Setting CTFG bit to 0

(Increment of second counter)

R2051 Series

*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or 60sec. as follows: Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784 ms. For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%. Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784 ms.

R2051Txx does not have

INTR

output pin

• Control Register 2 (Address Fh)

D7 D6 D5 D4 D3 D2 D1 D0

VDSL VDET VDSL VDET

0 0 *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

XST XST

Indefinite

PON SCRA PON SCRA

1 0 0 0 0 Default Settings *)

TCH1 TCH1

(1) VDSL VDD Supply Voltage Monitoring Threshold Selection Bit

VDSL Description

0 Selecting the VDD supply voltage monitoring threshold setting of

2.1v.

1 Selecting the VDD supply voltage monitoring threshold setting of

1.35v.

The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.

(2) VDET Supply Voltage Monitoring Result Indication Bit

VDET Description

0 Indicating supply voltage above the supply voltage monitoring

threshold settings.

1 Indicating supply voltage below the supply voltage monitoring

threshold settings. Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring circuit. Conversely, setting the VDET bit to 1 causes no event.

XST

(3)

The halt sensing. The

Oscillation Halt Sensing Monitor Bit

XST

0 Sensing a halt of oscillation 1 Sensing a normal condition of oscillation

XST

accepts the reading and writing of 0 and 1. The

XST

bit will hold 0 even after the restart of oscillation.

(4) PON Power-on-reset Flag Bit

PON Description

0 Normal condition 1 Detecting VDD power-on -reset (Default)

The PON bit is for sensing power-on reset condition.

* The PON bit will be set to 1 when VDD power-on from 0 volts. The PON bit will hold the setting of 1 even after power-on.

CTFG WAFG DAFG (For Writing) CTFG WAFG DAFG (For Reading)

(Default)

Description

XST

bit will be set to 0 when the oscillation

R2051 Series

* When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control Register 1, and Control Register 2, except

XST

and PON. As a result,

* The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event.

(5) SCRATCH1 Scratch Bit 1

SCRATCH1 Description

0 (Default)

1 The SCRATCH1 bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH1 bit will be set to 0 when the PON bit is set to 1 in the Control Register 2.

(6) CTFG Periodic Interrupt Flag Bit

CTFG Description

0 Periodic interrupt output = “H” (Default)

1 Periodic interrupt output = “L” The CTFG bit is set to 1 when the periodic interrupt signals are output from the bit accepts only the writing of 0 in the level mode, which disables (“H”) the again in the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event. R2051Txx has CTFG bit, but does not have

INTR

output pin

(7) WAFG,DAFG Alarm_W Flag Bit and Alarm_D Flag Bit

WAFG,DAFG Description

0 Indicating a mismatch between current time and preset alarm time (Default)

1 Indicating a match between current time and preset alarm time The WAFG and DAFG bits are valid only when the WALE and DALE have the setting of 1, which is caused approximately 61µs after any match between current time and preset alarm time specified by the Alarm_W registers and the Alarm_D registers. The WAFG (DAFG) bit accepts only the writing of 0. outputs off (“H”) when this bit is set to 0. And Conversely, setting the WAFG and DAFG bits to 1 causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is disabled with the WALE and DALE bits set to 0. The settings of the WAFG and DAFG bits are synchronized with the output of the timing chart below. R2051Txx has WAFG, DAFG bits. But does not have

INTR

pprox. 61µs

pin outputs “L” again at the next preset alarm time.

INTR

output pin.

pprox. 61µs

INTR

pin stops outputting.

INTR

pin (“L”). The CTFG

INTR

pin until it is enabled (“L”)

INTR

pin as shown in the

INTR

WAFG(DAFG) Bit

INTR Pin

Writing of 0 to

WAFG(DAFG) bit (Match between current time and preset alarm time)

(Match between current time and preset alarm time)

Writing of 0 to

(Match between current time and preset alarm time)

WAFG(DAFG) bit

R2051 Series

• Time Counter (Address 0-2h)

Second Counter (Address 0h)

D7 D6 D5 D4 D3 D2 D1 D0

- S40 S20 S10 S8 S4 S2 S1 (For Writing) 0 S40 S20 S10 S8 S4 S2 S1 (For Reading) 0 Indefi

nite

Minute Counter (Address 1h)

D7 D6 D5 D4 D3 D2 D1 D0

- M40 M20 M10 M8 M4 M2 M1 (For Writing) 0 M40 M20 M10 M8 M4 M2 M1 (For Reading) 0 Indefi

nite

Hour Counter (Address 2h)

D7 D6 D5 D4 D3 D2 D1 D0

- -

0 0

0 0 Indefi

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

* Time digit display (BCD format) as follows:

The second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00. The minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00. The hour digits range as shown in "P18 • Control Register 1 (ADDRESS Eh) (2) Mode Selection Bit" and are carried to the day-of-month and day-of-week digits in transition from PM11 to

AM12 or from 23 to 00. * Any writing to the second counter resets divider units of less than 1 second. * Any carry from lower digits with the writing of non-existent time may cause the time counters to malfunction. Therefore, such incorrect writing should be replaced with the writing of existent time data.

Indefi

nite

Indefi

nite

H20

nite

Indefi

nite

Indefi

nite

H10 H8 H4 H2 H1 (For Writing)

H10 H8 H4 H2 H1 (For Reading)

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Default Settings *)

/24: 12/24-hour

• Day-of-week Counter (Address 3h)

D7 D6 D5 D4 D3 D2 D1 D0

- - - - - W4 W2 W1 (For Writing) 0 0 0 0 0 W4 W2 W1 (For Reading) 0 0 0 0 0 Indefi

nite *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

* The day-of-week counter is incremented by 1 when the day-of-week digits are carried to the day-of-month digits. * Day-of-week display (incremented in septimal notation): (W4, W2, W1) = (0, 0, 0) → (0, 0, 1)→…→(1, 1, 0) → (0, 0, 0)

Indefi

nite

Indefi

nite

Default Settings *)

R2051 Series

* Correspondences between days of the week and the day-of-week digits are user-definable (e.g. Sunday = 0, 0, 0) * The writing of (1, 1, 1) to (W4, W2, W1) is prohibited except when days of the week are unused.

• Calendar Counter (Address 4-6h)

Day-of-month Counter (Address 4h)

D7 D6 D5 D4 D3 D2 D1 D0

- - D20 D10 D8 D4 D2 D1 (For Writing) 0 0 D20 D10 D8 D4 D2 D1 (For Reading) 0 0 Indefi

nite

Month Counter + Century Bit (Address 5h)

D7 D6 D5 D4 D3 D2 D1 D0

/20

Indefi

nite

Year Counter (Address 6h)

D7 D6 D5 D4 D3 D2 D1 D0

Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 (For Writing) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 (For Reading)

Indefi

nite *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

* The calendar counters are configured to display the calendar digits in BCD format by using the automatic calendar function as follows: The day-of-month digits (D20 to D1) range from 1 to 31 for January, March, May, July, August, October, and December; from 1 to 30 for April, June, September, and November; from 1 to 29 for February in leap years; from 1 to 28 for February in ordinary years. The day-of-month digits are carried to the month digits in reversion from the last day of the month to 1. The month digits (MO10 to MO1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1. The year digits (Y80 to Y1) range from 00 to 99 (00, 04, 08, …, 92, and 96 in leap years) and are carried to

the The * Any carry from lower digits with the writing of non-existent calendar data may cause the calendar counters to malfunction. Therefore, such incorrect writing should be replaced with the writing of existent calendar data.

/20 digits in reversion from 99 to 00.

/20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits.

- - MO10 MO8 MO4 MO2 MO1 (For Writing) 0 0 MO10 MO8 MO4 MO2 MO1 (For Reading) 0 0 Indefi

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

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Indefi

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Default Settings *)

R2051 Series

,F4,F3,F2,F1,

• Oscillation Adjustment Register (Address 7h)

D7 D6 D5 D4 D3 D2 D1 D0

DEV F6 F5 F4 F3 F2 F1 F0 (For Writing) DEV F6 F5 F4 F3 F2 F1 F0 (For Reading)

0 0 0 0 0 0 0 0 Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

DEV bit When DEV is set to 0, the Oscillation Adjustment Circuit operates 00, 20, 40 seconds. When DEV is set to 1, the Oscillation Adjustment Circuit operates 00 seconds.

F6 to F0 bits The Oscillation Adjustment Circuit is configured to change time counts of 1 second on the basis of the settings of the Oscillation Adjustment Register at the timing set by DEV.

* The Oscillation Adjustment Circuit will not operate with the same timing (00, 20, or 40 seconds) as the timing of writing to the Oscillation Adjustment Register. * The F6 bit setting of 0 causes an increment of time counts by ((F5, F4, F3, F2, F1, F0) - 1) x 2.

The F6 bit setting of 1 causes a decrement of time counts by (( The settings of "*, 0, 0, 0, 0, 0, *" ("*" representing either "0" or "1") in the F6, F5, F4, F3, F2, F1, and F0 bits cause neither an increment nor decrement of time counts.

Example: If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (0, 0, 0, 0, 0, 1, 1, 1), when the second digits read 00, 20, or 40, an

increment of the current time counts of 32768 + (7 - 1) x 2 to 32780 (a current time count loss).

If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (0, 0, 0, 0, 0, 0, 0, 1), when the second digits read 00, 20, 40, neither

an increment nor a decrement of the current time counts of 32768.

If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (1, 1, 1, 1, 1, 1, 1, 0), when the second digits read 00, a decrement

of the current time counts of 32768 + (- 2) x 2 to 32764 (a current time count gain).

An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3 ppm (2 / (32768 x 20) = 3.051 ppm). Conversely, a decrease of two clock pulses once per 20 seconds causes a time count gain of 3 ppm. Consequently, when DEV is set to “0 ”, deviations in time counts can be corrected with a precision of ±1.5 ppm. In the same way, when DEV is set to “1”, deviations in time counts can be corrected with a precision of ±0.5 ppm. Note that the oscillation adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency of the 32.768-kHz clock pulses. For further details, see "P38 Configuration of Oscillation Circuit and Correction of Time Count Deviations • Oscillation Adjustment Circuit".

) + 1) x 2.

R2051 Series

Alarm_W Registers (Address 8-Ah)

Alarm_W Minute Register (Address 8h)

D7 D6 D5 D4 D3 D2 D1 D0

- WM40 WM20 WM10 WM8 WM4 WM2 WM1 (For Writing) 0 WM40 WM20 WM10 WM8 WM4 WM2 WM1 (For Reading) 0 Indefi

nite

Alarm_W Hour Register (Address 9h)

D7 D6 D5 D4 D3 D2 D1 D0

- - WH20

0 0 WH20

0 0 Indefi

Alarm_W Day-of-week Register (Address Ah)

D7 D6 D5 D4 D3 D2 D1 D0

- WW6 WW5 WW4 WW3 WW2 WW1 WW0 (For Writing) 0 WW6 WW5 WW4 WW3 WW2 WW1 WW0 (For Reading) 0 Indefi

nite *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

* The D5 bit of the Alarm_W Hour Register represents WP/ and 1 for p.m.) and WH20 when the 24-hour mode is selected (tens in the hour digits). * The Alarm_W Registers should not have any non-existent alarm time settings. (Note that any mismatch between current time and preset alarm time specified by the Alarm_W registers may disable the alarm interrupt circuit.) * When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively. (See "P18 •Control Register 1 (ADDRESS Eh) (2) * WW0 to WW6 correspond to W4, W2, and W1 of the day-of-week counter with settings ranging from (0, 0,

0) to (1, 1, 0). * WW0 to WW6 with respective settings of 0 disable the outputs of the Alarm_W Registers.

Indefi

nite

WP/

nite

Indefi

nite

Indefi

nite

WH10 WH8 WH4 WH2 WH1 (For Writing)

WH10 WH8 WH4 WH2 WH1 (For Reading)

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

Indefi

nite

/24: 12/24-hour Mode Selection Bit")

Indefi

nite

Indefi

nite

Indefi

nite

when the 12-hour mode is selected (0 for a.m.

Indefi

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Indefi

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Indefi

nite

Indefi

Default Settings *)

nite

Default Settings *)

nite

Default Settings *)

nite

R2051 Series

Example of Alarm Time Setting

Alarm Day-of-week 12-hour mode 24-hour mode

Preset alarm

time

00:00 a.m. on all

days

01:30 a.m. on all

days

11:59 a.m. on all

days

00:00 p.m. on Mon.

to Fri.

01:30 p.m. on Sun. 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0

11:59 p.m.

on Mon. ,Wed.,

and Fri. Note that the correspondence between WW0 to WW6 and the days of the week shown in the above table is only an example and not mandatory.

Sun. Mon. Tue. Wed. Th. Fri. Sat. 1

WW0 WW1 WW2 WW3 WW4 WW5 WW

1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0

0 1 0 1 0 1 0 3 1 5 9 2 3 5 9

• Alarm_D Register (Address B-Ch)

Alarm_D Minute Register (Address Bh)

D7 D6 D5 D4 D3 D2 D1 D0

- DM40 DM20 DM10 DM8 DM4 DM2 DM1 (For Writing) 0 DM40 DM20 DM10 DM8 DM4 DM2 DM1 (For Reading) 0 Indefi

nite

Alarm_D Hour Register (Address Ch)

D7 D6 D5 D4 D3 D2 D1 D0

- - DH20

0 0 DH20

0 0 Indefi

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.

* The D5 bit represents DP/ the 24-hour mode is selected (tens in the hour digits). * The Alarm_D registers should not have any non-existent alarm time settings. (Note that any mismatch between current time and preset alarm time specified by the Alarm_D registers may disable the alarm interrupt circuit.) * When the 12-hour mode is selected, the hour digits read 12 and 32 for 0a.m. and 0p.m., respectively. (See "P18 •Control Register 1 (Address Eh) (2)

Indefi nite

DP/

nite

Indefi nite

DH10 DH8 DH4 DH2 DH1 (For Writing)

DH10 DH8 DH4 DH2 DH1 (For Reading)

Indefi

nite

when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and DH20 when

Indefi nite

Indefi

nite

Indefi nite

Indefi

nite

/24: 12/24-hour Mode Selection Bit")

Indefi nite

Indefi

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Indefi nite

Indefi

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Default Settings *)

R2051 Series

Interfacing with the CPU

The R2051 employs the I2C-Bus system to be connected to the CPU via 2-wires. Connection and system of

C-Bus are described in the following sections.

• Connection of I

2-wires, SCL and SDA pins that are connected to I2C-Bus are used for transmit clock pulses and data respectively. All ICs that are connected to these lines are designed that will not be clamped when a voltage beyond supply voltage is applied to input or output pins. Open drain pins are used for output. This construction allows communication of signals between ICs with different supply voltages by adding a pull-up resistor to each signal line as shown in the figure below. Each IC is designed not to affect SCL and SDA signal lines when power to each of these is turned off separately.

VDD1 VDD2 VDD3 VDD4

SCL

SDA

C-Bus

* For data interface, the following

conditions must be met:

VCC4≥VCC1 VCC4≥VCC2 VCC4≥VCC3

* When the master is one, the

micro-controller is ready for driving SCL to “H” and Rp of SCL may not be required.

Micro-

Controller

R2051

Other

Peripheral

Device

Cautions on determining Rp resistance,

(1) Dropping voltage at Rp due to sum of input current or output current at off conditions on each IC pin connected to the I

C-Bus shall be adequately small. (2) Rising time of each signal be kept short even when all capacity of the bus is driven. (3) Current consumed in I

C-Bus is small compared to the consumption current permitted for the entire system.

When all ICs connected to I

C-Bus are CMOS type, condition (1) may usually be ignored since input current and off-state output current is extremely small for the many CMOS type ICs. Thus the maximum resistance of Rp may be determined based on (2), while the minimum on (3) in most cases.

In actual cases a resistor may be place between the bus and input/output pins of each IC to improve noise

margins in which case the Rp minimum value may be determined by the resistance.

Consumption current in the bus to review (3) above may be expressed by the formula below:

Bus consumption current ≈

(Sum of input current and off state output current of all devices in standby mode ) × Bus standby duration Bus stand-by duration + the Bus operation duration

+ Supply voltage × Bus operation duration × 2 Rp resistance × 2 × (Bus stand-by duration + bus operation duration)

+ Supply voltage × Bus capacity × Charging/Discharging times per unit time

Operation of “× 2” in the second member denominator in the above formula is derived from assumption that “L”

R2051 Series

duration of SDA and SCL pins are the half of bus operation duration. “× 2” in the numerator of the same member is because there are two pins of SDA and SCL. The third member, (charging/discharging times per unit time) means number of transition from “H” to “L” of the signal line.

Calculation example is shown below: Pull-up resistor (Rp) = 10kΩ, Bus capacity = 50pF(both for SCL, SDA), V In a system with sum of input current and off-state output current of each pin = 0.1µA,

C-Bus is used for 10ms every second while the rest of 990ms in the stand-by mode,

In this mode, number of transitions of the SCL pin from “H” to “L” state is 100 while SDA 50, every second.

Bus consumption current ≈ 0.1µA×990msec 990msec + 10msec

+ 3V × 10msec × 2 10KΩ × 2 × (990msec + 10msec)

+ 3V × 50pF × (100 + 50)

≈ 0.099µA + 3.0µA + 0.0225µA ≈ 3.12µA

Generally, the second member of the above formula is larger enough than the first and the third members bus

consumption current may be determined by the second member is many cases.

CC=3v,

R2051 Series

• Transmission System of I

(1) Start Condition and Stop Condition

In I2C-Bus, SDA must be kept at a certain state while SCL is at the “H” state during data transmission as shown

below.

SCL

SDA

C-Bus

tSU;DAT

The SCL and SDA pins are at the “H” level when no data transmission is made. Changing the SDA from “H” to “L” when the SCL and the SDA are “H” activates the Start Condition and access is started. Changing the SDA from “L” to “H” when the SCL is “H” activates Stop Condition and accessing stopped. Generation of Start and Stop Conditions are always made by the master (see the figure below).

Start Condition Stop Condition

SCL

SDA

tHD;STA tSU;STO

tHD;DAT

• (2) Data transmission and its acknowledge

After Start condition is entered, data is transmitted by 1byte (8bits). Any bytes of data may be serially transmitted. The receiving side will send an acknowledge signal to the transmission side each time 8bit data is transmitted. The acknowledge signal is sent immediately after falling to “L” of SCL 8bit clock pulses of data is transmitted, by releasing the SDA by the transmission side that has asserted the bus at that time and by turning SDA to “L” by receiving side. When transmission of 1byte data next to preceding 1byte of data is received the receiving side releases the SDA pin at falling edge of the SCL 9bit of clock pulses or when the receiving side switches to the transmission side it starts data transmission. When the master is receiving side, it generates no acknowledge signal after last 1byte of data from the slave to tell the transmitter that data transmission has completed. The slave side (transmission side) continues to release the SDA pin so that the master will be able to generate Stop Condition, af ter falling edge of the SCL 9bit of clock pulses.

R2051 Series

SCL

from the master

SDA from

the transmission side

SDA from

the receiving side

Start

Condition

12 89

Acknowledge

signal

(3) Data Transmission Format in I2C-Bus

I2C-Bus has no chip enable signal line. In place of it, each device has a 7bit Slave Address allocated. The first 1byte is allocated to this 7bit address and to the command (R/W) for which data transmission direction is designated by the data transmission thereafter. 7bit addr ess is sequentially transmitted from the MSB and 2 and after bytes are read, when 8bit is “H” and when write “L”.

The Slave Address of the R2051 is specified at (0110010).

At the end of data transmission / receiving, Stop Condition is generated to complete transmission. However, if start condition is generated without generating Stop Condition, Repeated Start Condition is met and transmission / receiving data may be continue by setting the Slave Address again. Use this procedure when the transmission direction needs to be change during one transmission.

Data is written to the slave

from the master

Slave Address Data

S 0 A

A A P

Data

When data is read from the

slave immediately after 7bit

addressing from the master

When the transmission

direction is to be changed

during transmission.

Master to slave Slave to master

Start Condition

R/W=0(Write)(0110010)

Slave Address

S 1 A /A P

(0110010)

Slave Address

(0110010)

Data

R/W=1(Read)

R/W=0(Write)

Inform read has been com pleted by not generate an acknowledge signal to the slave side.

Stop Condition

Data

Inform read has b een c ompleted by not gener ate an acknowledge signal to the slave side.

Salve Address

Sr 10 AA

R/W=1(Read)(0110010)

/A P

A A /A

Repeated Start Condition

cknowledge Signal

R2051 Series

(4) Data Transmission Write Format in the R2051

Although the I2C-Bus standard defines a transmission format for the slave allocated for each IC, transmission method of address information in IC is not defined. The R2051 transmits data the internal address pointer (4bit) and the Transmission Format Register (4bit) at the 1byte next to one which transmitted a Slave Address and a write command. For write operation only one transmission format is available and (0000) is set to the Transmission Format Register. The 3byte transmits data to the address specified by the internal address pointer written to the 2byte. Internal address pointer setting are automatically incremented for 4byte and after. Note that when the internal address pointer is Fh, it will change to 0h on transmitting the next byte.

Example of data writing (When writing to internal address Eh to Fh)

R/W=0(Write)

1 AS 0 A

Slave Address

←(0110010)

A A /A

110 0 00 0 0 0 00 1 11

Address

Pointer

←Eh

Master to slave Slave to master

Start Condition

cknowledge signal

Transmission

Format

←

Data

Writing of data to the internal address Eh

Stop Condition

Data

Writing of data to the internal address Fh

A P

R2051 Series

(5) Data transmission read format of the R2051

The R2051 allows the following three read out method of data an internal register.

The first method to reading data from the internal register is to specify an internal address by setting the internal address pointer and the transmission format register described P31 (4), generate the Repeated Start Condition (See P30 (3)) to change the data transmission direction to perform reading. The internal address pointer is set to Fh when the Stop Condition is met. Therefore, this method of reading allows no insertion of Stop Condition before the Repeated Start Condition. Set 0h to the Transmission Format Register when this method used.

Example 1 of Data Read (when data is read from 2h to 4h)

Slave Address

(0110010)

←

Reading of data from the internal address 2h

Master to slave Slave to master

Start Condition

A A /A

R/W=0(Write)

10 0 00 1

Data

cknowledge signal

Repeated Start Condition

0 10 00 11 0 0 0 00 0 1

Address

Pointer

Transmission

←

Format

Reading of data from the internal address 3h

Data

Repeated Start Condition

1S 0A A

Sr1 0 A

Slave Address

(0110010)

←

R/W=1(Read)

Reading of data from the internal address 4h

Data

Stop Condition

/A P

R2051 Series

The second method to reading data from the internal register is to start reading immediately after writing to the Internal Address Pointer and the Transmission Format Register. Although this method is not based on I standard in a strict sense it still effective to shorten read time to ease load to the master. Set 4h to the transmission format register when this method used.

Example 2 of data read (when data is read from internal addresses Eh to 1h)

R/W=0(Write)

C-Bus

1 0 A

Slave Address

(0110010)

←

A A /A

10 0 00 1

Reading of data from the internal address Fh

Master to slave Slave to Master

Start Condition

1S A A

Address

Pointer

←

Data

cknowledge Signal

0 11 0 001

Transmission

Format

Reading of data from the internal address 0h

Reading of data from the internal address Eh

Data

Stop Condition

Data

Reading of data from the internal address 1h

Data

/A P

The third method to reading data from the internal register is to start reading immediately after writing to the Slave Address and R/W bit. Since the Internal Address Pointer is set to Fh by default as described in the first method, this method is only effective when reading is started from the Internal Address Fh.

R2051 Series

Example 3 of data read (when data is read from internal addresses Fh to 3h)

R/W=1(Read)

S A A

1 0 A

Slave Address ← (0110010)

A A /A

1 0 0 1 0 1

Reading of data from

Reading of data from the Internal Address 1h

Master to slave

Start Condition

the Internal Address Fh

Data

cknowledge Signal

Data

Reading of data from the Internal Address 0h

Reading of data from the Internal Address 2h

Data

Slave to master

Stop Condition

Data

Reading of data from the Internal Address 3h

Data

/A P

• Data Transmission under Special Condition

The R2051 holds the clock tentatively for duration from Start Condition to avoid invalid read or write clock on carrying clock. When clock carried during this period, which will be adjusted within approx. 61µs from Stop Condition. To prevent invalid read or write, clock and calendar data shall be made during one transmission operation (from Start Condition to Stop Condition). When 0.5 to 1.0 second elapses after Start Condition, any access to the R2051 is automatically released to release tentative hold of the clock, and access from the CPU is forced to be terminated (The same action as made Stop Condition is received: automatic resume function from

C-Bus interface). Therefore, one access must be complete within 0.5 seconds. The automatic resume function

prevents delay in clock even if SCL is stopped from sudden failure of the system during clock read operation.

Also a second Start Condition after the first Start Condition and before the Stop Condition is regarded “Repeated Start Condition”. Therefore, when 0.5 to 1.0 seconds passed after the first Start Condition, an access to the R2051 is automatically released.

If access is tried after automatic resume function is activated, no acknowledge signal will be output for writing while FFh will be output for reading.

The user shall always be able to access the real-time clock as long as three conditions are met.

No Stop Condition shall be generated until clock and calendar data read/write is started and completed.

One cycle read/write operation shall be complete within 0.5 seconds.

Do not make Start Condition within 61µs from Stop Condition. When clock is carried during the access,

which will be adjusted within approx. 61µs from Stop Condition.

Bad example of reading from seconds to hours (invalid read)

(Start Condition) → (Read of seconds) → (Read of minutes) → (Stop Condition) → (Start Condition) →

(Read of hour) → (Stop Condition)

Assuming read was started at 05:59:59 P.M. and while reading seconds and minutes the time advanced to 06:00:00 P.M. At this time second digit is hold so read the read as 05:59:59. Then the R2051 confirms (Stop Condition) and carries second digit being hold and the time change to 06:00:00 P.M. Then, when the hour digit is read, it changes to 6. The wrong results of 06:59:59 will be read.

R2051 Series

Configuration of Oscillation Circuit and Correction of Time Count Deviations

• Configuration of Oscillation Circuit

Typical externally-equipped element X’tal : 32.768kHz

OSCIN

Oscillator

Circuit

The oscillation circuit is driven at a constant voltage of approximately 1.2 volts relative to the level of the VSS pin input. As such, it is configured to generate an oscillating waveform with a peak-to-peak voltage on the order of

1.1 volts on the positive side of the VSS pin input.

< Considerations in Handling quartz crystal unit >

Generally, quartz crystal units have basic characteristics including an equivalent series resistance (R1) indicating the ease of their oscillation and a load capacitance (CL) indicating the degree of their center frequency. Particularly, quartz crystal units intended for use in the R2051 are recommended to have a typical R1 value of 30kΩ and a typical CL value of 6 to 8pF. To confirm these recommended values, contact the manufacturers of quartz crystal units intended for use in these particular models.

< Considerations in Installing Components around the Oscillation Circuit >

1) Install the quartz crystal unit in the closest possible vicinity to the real-time clock ICs.

2) Avoid laying any signal lines or power lines in the vicinity of the oscillation circuit (particularly in the area

marked "A" in the above figure).

3) Apply the highest possible insulation resist ance between the OSCIN and OSCOUT pins and the printed

circuit board.

4) Avoid using any long parallel lines to wire the OSCIN and OSCOUT pins.

5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt.

< Other Relevant Considerations >

1) We cannot recommend connecting the external input of 32.768-kHz clock pulses to the OSCIN pin.

2) To maintain stable characteristics of the quartz crystal unit, avoid driving any other IC through 32.768-kHz

clock pulses output from the OSCOUT pin.

OSCOUT

32kHz

(R1=30kΩ typ) (CL=6pF to 8pF) Standard values of internal elements CG,CD 10pF typ

R2051 Series

• Measurement of Oscillation Frequency

VCC

OSCIN

OSCOUT

CLKOUT

VDD

VSS

32768Hz

Frequency

Counter

* 1) The R2051 is configured to generate 32.768-kHz clock pulses for output from the CLKOUT pin. * 2) A frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended for use in the measurement of the oscillation frequency of the oscillation circuit.

• Adjustment of Oscillation frequency

The oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the usage of Model R2051 in the system into which they are to be built and on the allowable degree of time count errors. The flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment procedure for the relevant system.

Start

Use 32-kHz

YES

clock output?

Use 32-kHz clock output without regard

to its frequency precision

llowable time count precision on order of oscillation frequency variations of crystal oscillator (*1) plus frequency variations of RTC (*2)? (*3)

llowable time count precision on order of oscillation

frequency variations of crystal oscillator (*1) plus frequency variations of RTC (*2)? (*3)

YES

Course (A)

Course (B)

Course (C)

Course (D)

* 1) Generally, quartz crystal units for commercial use are classified in terms of their center frequency depending on their load capacitance (CL) and further divided into ranks on the order of ±10, ±20, and ±50ppm depending on the degree of their oscillation frequency variations. * 2) Basically, Model R2051 is configured to cause frequency variations on the order of ±5 to ±10ppm at 25°C. * 3) Time count precision as referred to in the above flow chart is applicable to normal temperature and actually affected by the temperature characteristics and other properties of quartz crystal units.

R2051 Series

Course (A)

When the time count precision of each RTC is not to be adjusted, the quartz crystal unit intended for use in that RTC may have any CL value requiring no presetting. The quartz crystal unit may be subject to frequency variations which are selectable within the allowable range of time count precision. Several quartz crystal units and RTCs should be used to find the center frequency of the quartz crystal units by the method described in "P36 • Measurement of Oscillation Frequency" and then calculate an appropriate oscillation adjustment value by the method described in "P38 • Oscillation Adjustment Circuit" for writing this value to the R2051.

Course (B)

When the time count precision of each RTC is to be adjusted within the oscillation frequency variations of the quartz crystal unit plus the frequency variations of the real-time clock ICs, it becomes necessary to correct deviations in the time count of each RTC by the method described in " P38 • Oscillation Adjustment Circuit". Such oscillation adjustment provides quartz crystal units with a wider range of allowable settings of their oscillation frequency variations and their CL values. The real-time clock IC and the quartz crystal unit intended for use in that real-time clock IC should be used to find the center frequency of the quartz crystal unit by the method described in " P36 • Measurement of Oscillation Frequency" and then confirm the center frequency thus found to fall within the range adjustable by the oscillation adjustment circuit before adjusting the oscillation frequency of the oscillation circuit. At normal temperature, the oscillation frequency of the oscillator circuit can be adjusted by up to approximately ±0.5ppm.

Course (C)

Course (C) together with Course (D) requires adjusting the time count precision of each RTC as well as the frequency of 32.768-kHz clock pulses output from the CLKOUT pin. Normally, the oscillation frequency of the quartz crystal unit intended for use in the RTCs should be adjusted by adjusting the oscillation stabilizing capacitors CG and CD connected to both ends of the quartz crystal unit. The R2051, which incorporate the CG and the CD, require adjusting the oscillation frequency of the quartz crystal unit through its CL value.

Generally, the relationship between the CL value and the CG and CD values can be represented by the following equation:

CL = (CG × CD)/(CG + CD) + CS where "CS" represents the floating capacity of the printed circuit board.

The quartz crystal unit intended for use in the R2051 is recommended to have the CL value on the order of 6 to 8pF. Its oscillation frequency should be measured by the method described in " P36 • Measurement of Oscillation Frequency". Any quartz crystal unit found to have an excessively high or low oscillation frequency (causing a time count gain or loss, respectively) should be replaced with another one having a smaller and greater CL value, respectively until another one having an optimum CL value is selected. In this case, the bit settings disabling the oscillation adjustment circuit (see " P38 • Oscillation Adjustment Circuit ") should be written to the oscillation adjustment register.

Incidentally, the high oscillation frequency of the quartz crystal unit can also be adjusted by adding an external oscillation stabilization capacitor CGout as illustrated in the diagram below.

Oscillator

Circuit

OSCIN

CG RD

OSCOUT

32kHz

CGout *1)

*1) The CGout should have a capacitance ranging

from 0 to 15 pF.

R2051 Series

Course (D)

It is necessary to select the quartz crystal unit in the same manner as in Course (C) as well as correct errors in the time count of each RTC in the same manner as in Course (B) by the method described in " P38 • Oscillation Adjustment Circuit ".

• Oscillation Adjustment Circuit

The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the number of 1-second clock pulses once per 20 seconds or 60 seconds. When DEV bit in the Oscillation Adjustment Register is set to 0, R2051 varies number of 1-second clock pulses once per 20 seconds. When DEV bit is set to 1, R2051 varies number of 1-second clock pulses once per 60 seconds. The oscillation adjustment circuit can be disabled by writing the settings of "*, 0, 0, 0, 0, 0, *" ("*" representing "0" or "1") to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment circuit. Conversely, when such oscillation adjustment is to be made, an appropriate oscillation adjustment value can be calculated by the equation below for writing to the oscillation adjustment circuit.

(1) When Oscillation Frequency (* 1) Is Higher Than Target Frequency (* 2) (Causing Time Count Gain)

When DEV=0:

Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.1)

Oscillation frequency × 3.051 × 10

≈ (Oscillation Frequency – Target Frequency) × 10 + 1

When DEV=1:

Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.0333)

Oscillation frequency × 1.017 × 10

≈ (Oscillation Frequency – Target Frequency) × 30 + 1

* 1) Oscillation frequency: Frequency of clock pulse output from the CLKOUT pin at normal temperature in the manner described in " P36 • Measurement of Oscillation Frequency". * 2) Target frequency: Desired frequency to be set. Generally, a 32.768-kHz quartz crystal unit has such temperature characteristics as to have the highest oscillation frequency at normal temperature. Consequently, the quartz crystal unit is recommended to have target frequency settings on the order of 32.768 to 32.76810 kHz (+3.05ppm relative to 32.768 kHz). Note that the target frequency differs depending on the environment or location where the equipment incorporating the RTC is expected to be operated. * 3) Oscillation adjustment value: Value that is to be finally written to the F0 to F6 bits in the Oscillation Adjustment Register and is represented in 7-bit coded decimal notation.

-6

(2) When Oscillation Frequency Is Equal To Target Frequency (Causing Time Count neither Gain nor Loss)

Oscillation adjustment value = 0, +1, -64, or –63

(3) When Oscillation Frequency Is Lower Than Target Frequency (Causing Time Count Loss)

When DEV=0:

Oscillation adjustment value = (Oscillation frequency - Target Frequency)

R2051 Series

Oscillation frequency × 3.051 × 10-6

≈ (Oscillation Frequency – Target Frequency) × 10

When DEV=1:

Oscillation adjustment value = (Oscillation frequency - Target Frequency)

Oscillation frequency × 1.017 × 10

≈ (Oscillation Frequency – Target Frequency) × 30

Oscillation adjustment value calculations are exemplified below

(A) For an oscillation frequency = 32768.85Hz and a target frequency = 32768.05Hz

When setting DEV bit to 0:

Oscillation adjustment value = (32768.85 - 32768.05 + 0.1) / (32768.85 × 3.051 × 10

≈ (32768.85 - 32768.05) × 10 + 1

= 9.001 ≈ 9

In this instance, write the settings (DEV,F6,F5,F4,F3,F2,F1,F0)=(0,0,0,0,1,0,0,1) in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count gain represents a distance from 01h.

When setting DEV bit to 1:

Oscillation adjustment value = (32768.85 - 32768.05 + 0.0333) / (32768.85 × 1.017 × 10

≈ (32768.85 - 32768.05) × 30 + 1

= 25.00 ≈ 25

In this instance, write the settings (DEV,F6,F5,F4,F3,F2,F1,F0)=(1,0,0,1,1,0,0,1) in the oscillation adjustment register.

(B) For an oscillation frequency = 32762.22Hz and a target frequency = 32768.05Hz

When setting DEV bit to 0:

Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 × 3.051 × 10

≈ (32762.22 - 32768.05) × 10

= -58.325 ≈ -58

To represent an oscillation adjustment value of - 58 in 7-bit coded decimal notation, subtract 58 (3Ah) from 128 (80h) to obtain 46h. In this instance, write the settings of (DEV,F6,F5,F4,F3,F2,F1,F0) = (0,1,0,0,0,1,1,0) in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count loss represents a distance from 80h.

When setting DEV bit to 1:

Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 × 1.017 × 10

≈ (32762.22 - 32768.05) × 30

= -174.97 ≈ -175

Oscillation adjustment value can be set from -62 to 63. Then, in this case, Oscillation adjustment value is out of range.

(4) Difference between DEV=0 and DEV=1

Difference between DEV=0 and DEV=1 is following,

DEV=0 DEV=1

Maximum value range -189.2ppm to +189.2ppm -62ppm to +63ppm Minimum resolution 3ppm 1ppm

-6

)

-6

)

-6

)

-6

)

R2051 Series

Notes:

1) Oscillation adjustment circuit does not affect the frequency of 32.768-kHz clock pulses output from the CLKOUT pin.

2) If following 3 conditions are completed, actual clock adjustment value could be different from target adjustment value that set by oscillator adjustment function.

1. Using oscillator adjustment function

2. Access to R2051 at random, or synchronized with external clock that has no relation to R2051, or synchronized with periodic interrupt in pulse mode.

3. Access to R2051 more than 2 times per each second on average. For more details, please contact to Ricoh.

• How to evaluate the clock gain or loss

The oscillator adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register once in 20 seconds or 60 seconds. The oscillation adjustment circuit does not effect the frequency of 32768Hz-clock pulse output from the CLKOUT pin. Therefore, after writing the oscillation adjustment register, we cannot measure the clock error with probing CLKOUT clock pulses. The way to measure the clock error as follows (except R2051Txx):

(1) Output a 1Hz clock pulse of Pulse Mode with interrupt pin

Set (0,0,x,x,0,0,1,1) to Control Register 1 at address Eh.

(2) After setting the oscillation adjustment register, 1Hz clock period changes every 20seconds ( or every 60 seconds) like next page figure.

1Hz clock pulse

T0 T0 T0 T1

1 time19 times

Measure the interval of T0 and T1 with frequency counter. A frequency counter with 7 or more digits is recommended for the measurement.

(3) Calculate the typical period from T0 and T1

T = (19×T0+1×T1)/20

Calculate the time error from T.

R2051 Series

Power-on Reset, Oscillation Halt Sensing, and Supply Voltage Monitoring

• PON,

The power-on reset circuit is configured to reset control register1, 2, and clock adjustment register when VDD power up from 0v. The oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-kHz clock pulses. The supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or 1.35v.

Each function has a monitor bit. I.e. the PON bit is for the power-on reset circuit, and oscillation halt sensing circuit, and VDET is for the supply voltage monitoring circuit. PON and VDET bits are activated to “H”. However,

XST

and

The functions of these three monitor bits are shown in the table below.

The relationship between the PON,

XST

, and VDET

XST

bit is for the

XST

bit is activated to “L”. The PON and VDET accept only the writing of 0, but

accepts the writing of 0 and 1. The PON bit is set to 1, when VDD power-up from 0V, but VDET is set to 0,

XST

is indefinite.

PON

Function Monitoring for the

power-on reset function

Address D4 in Address Fh D5 in Address Fh D6 in Address Fh Activated High Low High When VDD power up from 0v accept the writing 0 only Both 0 and 1 0 only

PON

0 0 0 Halt on oscillation, but no drop in

0 0 1 Halt on oscillation and drop in VDD

0 1 0 No drop in VDD supply voltage

0 1 1 Drop in VDD supply voltage below

1 * * Drop in supply voltage to 0v Power-up from 0v,

XST

1 Indefinite 0

XST

, and VDET is shown in the table below.

VDET Conditions of supply voltage and

oscillation

VDD supply voltage below threshold voltage

supply voltage below threshold voltage, but no drop to 0V

below threshold voltage and no halt in oscillation

threshold voltage and no halt on oscillation

Monitoring for the oscillation halt sensing function

Condition of oscillator, and

Halt on oscillation cause of condensation etc.

Halt on oscillation cause of drop in back-up battery voltage

Normal condition

No halt on oscillation, but drop in back-up battery voltage

a drop in supply voltage below a threshold voltage of 2.1 or 1.35v

back-up status

VDET

R2051 Series

)

32768Hz Oscillation

Power-on reset flag

Oscillation halt

sensin

VDD supply voltage monitor flag (VDET)

flag (XST

VDD

(PON)

Threshold voltage (2.1V or 1.35V)

Internal initialization

period (1 to 2 sec.)

VDET←0 XST←1 PON←0

VDET←0 XST←1 PON←1

Internal initialization

period (1 to 2 sec.)

VDET←0 XST←1 PON←0

When the PON bit is set to 1 in the control register 2, the DEV, F6 to F0, WALE, DALE,

/24, SCRATCH2, TEST, CT2, CT1, CT0, VDSL, VDET, SCRATCH1, CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation adjustment register, the control register 1, and the control register 2. The PON bit is also set to 1 at power-on from 0 volts.

< Considerations in Using Oscillation Halt Sensing Circuit > Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following:

1) Instantaneous power-down on the VDD

2) Condensation on the quartz crystal unit

3) On-board noise to the quartz crystal unit

4) Applying to individual pins volt age exceeding their respective maximum ratings

In particular, note that the

XST

bit may fail to be set to 0 in the presence of any applied supply voltage as illustrated below in such events as backup battery installation. Further, give special considerations to prevent excessive chattering in the oscillation halt sensing circuit.

VDD

R2051 Series

• Voltage Monitoring Circuit

R2051S/Kxx incorporates two kinds of voltage monitoring function. (R2051Txx incorporates one kind only.)

These are shown in the table below .

VCC Voltage Monitoring

Circuit (except R2051Txx)

Purpose CPU reset output Back-up battery checker Monitoring supply voltage VCC pin VDD pin (supply voltage for the

Output for result Function

VDCC

After falling VCC,

VDCC

outputs “L”. tDEALY after rising VCC,

VDCC

outputs “H” (OFF) Below the threshold voltage, SW1 turns off and SW2 turns on. Over the threshold voltage, SW1 turns on and SW2 turns off.

Detector Threshold (falling

-VDET1 Selecting from VDETH or VDETL by

edge of power supply voltage) Detector Released

+VDET1 Same as falling edge

Voltage (rising edge of power supply voltage) The way to monitor Always One time every second

The VDD supply voltage monitoring circuit is configured to conduct a sampling operation during an interval of

7.8ms per second to check for a drop in supply voltage below a threshold voltage of 2.1 or 1.35v for the VDSL bit setting of 0 (the default setting) or 1, respectively, in the Control Register 2, thus minimizing supply current requirements as illustrated in the timing chart below. This circuit suspends a sampling operation once the VDET bit is set to 1 in the Control Register 2. The VDD supply voltage monitor is useful for back-up battery checking.

VDD Voltage Monitoring

Circuit (VDET)

internal RTC circuit) Store in the Control Register 2 (D6 in Address Fh)

writing to the register (D7 in Address Fh)

( No hysteresis)

VDD

PON

Sampling timing for VDD

supply voltage monitor

VDET

(D6 in Address Fh)

Internal nitialization period (1 to 2sec.)

PON←0 VDET

←

2.1v or 1.35v

7.8ms

VDET←0

R2051 Series

(1) (2)

(3) (3)

(2)

The VCC supply voltage monitor circuit operates always. When VCC rising over +VDET1, SW1 turns on, and SW2

turns off. And tDELAY after rising VCC,

VDCC

OFF(H) tDELAY after oscillation starting. When VCC falling beyond -V

VDCC

outputs “L”. R2051Txx does not have

outputs OFF(H). But when oscillation is halt, VCC outputs

DET1, SW1 turns off, and SW2 turns on. And

VDCC

output pin.

VCC

VDD

32768Hz Oscillation

VDCC

SW1

SW2

Oscillation starting

tDELAY tDELAY tDELAY

ON ON ON

-V

DET1

ON ON

DET1

Same voltage level as VSB

Battery Switch Over Circuit

R2051 incorporates three power supply pins, VDD, VCC, and VSB. VDD pin is the power supply pin for internal real time clock circuit. When VCC voltage is lower than ±V than ±V

DET1, VCC supplies the power to VDD. The timing chart for VCC, VDD, and VSB is shown following.

DET1, VSB supplies the power to VDD, and when higher

VCC

VSB

VDD

DET1

-V

DET1

(1) When VSB is 0v and VCC is rising from 0v, VDD follows half of VCC voltage level. After VCC rising over

DET1, VDD follows VCC voltage level.

(2) When VCC is higher than +V

(3) Af ter VCC falling beyond -V

DET1, VDD level is equal to VCC.

DET1, VDD level is equal to VSB.

R2051 Series

Alarm and Periodic Interrupt

The R2051 incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to

INTR

generate alarm signals and periodic interrupt signals for output from the R2051Txx has these functions registers, but does not have the

(1) Alarm Interrupt Circuit

The alarm interrupt circuit is configured to generate alarm signals for output from the (enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week, hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers intended for the day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and minute digit settings).

(2) Periodic Interrupt Circuit

The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in the level mode for output from the register 1.

The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the Control Register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in the Control Register 1) as listed in the table below.

Flag bits Enable bits

Alarm_W WAFG

(D1 at Address Fh)

Alarm_D DAFG

(D0 at Address Fh)

Peridic interrupt CTFG

(D2 at Address Fh)

* At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the Control Register 1, the * When two types of interrupt signals are output simultaneously from the

INTR

pin is driven high (disabled).

INTR

pin becomes an OR waveform of their negative logic.

Example: Combined Output to /INTR Pin Under Control of ALARM_D and Periodic Interrupt

INTR

pin depending on the CT2, CT1, and CT0 bit settings in the control

WALE (D7 at Address Eh) DALE (D6 at Address Eh) CT2=CT1=CT0=0 (These bit setting of “0” disable the Periodic Interrupt) (D2 to D0 at Address Eh)

INTR

output pin.

INTR

pin as described below.

INTR

, which is driven low

pin, the output from the

Alarm_D

Periodic Interrupt

In this event, which type of interrupt signal is output from the DAFG, and CTFG bit settings in the Control Register 2.

INTR

pin can be confirmed by reading the

• Alarm Interrupt

The alarm interrupt circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the Control Register 1) and the flag bits (i.e. the WAFG and DAFG bits in the Control Register 2). The enable bits can be used to enable this circuit when set to 1 and to disable it when set to 0. When intended for reading, the flag bits can be used to monitor alarm interrupt signals. When intended for writing, the flag bits will cause no event when set to 1 and will

R2051 Series

←

drive high (disable) the alarm interrupt circuit when set to 0.

The enable bits will not be affected even when the flag bits are set to 0. In this event, therefore, the alarm interrupt circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match between current time and preset alarm time.

The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W Registers for the day-of-week digit settings and both the Alarm_W Registers and the Alarm_D Registers for the hour and minute digit settings) with the WALE and DALE bits once set to 0 and then to 1 in the Control Register 1. Note that the WALE and DALE bits should be once set to 0 in order to disable the alarm interrupt circuit upon the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm function.

INTR

Interval (1min.) during which a match between current time and preset alarm tim e occurs

INTR

WALE←1 (DALE)

current time = preset alarm time

WALE (DALE)

WALE←1

(DALE)

WAFG←0 (DAFG)

current time = preset alarm time

After setting WALE(DALE) to 0, Alarm registers is set to current time, and WALE(DALE) is set to 1, be not driven to “L” immediately,

INTR

will be driven to “L” at next alarm setting time.

INTR

will

• Periodic Interrupt

Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%. In the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output is return to High (OFF).

CT2 CT1 CT0

Wave form

mode

0 0 0 - OFF(H) (Default) 0 0 1 - Fixed at “L” 0 1 0 Pulse Mode *1) 2Hz(Duty50%) 0 1 1 Pulse Mode *1) 1Hz(Duty50%) 1 0 0 Level Mode *2) Once per 1 second (Synchronized with

1 0 1 Level Mode *2) Once per 1 minute (at 00 seconds of every 1 1 0 Level Mode *2) Once per hour (at 00 minutes and 00 1 1 1 Level Mode *2) Once per month (at 00 hours, 00 minutes,

Description

Interrupt Cycle and Falling Timing

Second counter increment) Minute) Seconds of every hour) and 00 seconds of first day of every month)

R2051 Series

*1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart below.

CTFG Bit

INTR Pin

pprox. 92µs

(Increment of second count er)

Rewriting of the second counter

INTR

pin low.

*2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below.

CTFG Bit

INTR Pin

Setting CTFG bit to 0

(Increment of second counter)

Setting CTFG bit to 0

(Increment of second counter)

*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as follows: Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784ms. For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%. Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784 ms.

R2051 Series

Typical Applications

• Typical Power Circuit Configurations

The case of back-up by primary battery

The case of bac k - up by capac itor or secondary battery (Charging voltage is equal to CPU power supply v oltage)

The case of back - up by capacitor or secondary bat t e ry (Charging voltage is not equal to CPU power supply v o ltage)

VCC

VSB

VDD

VSS

CPU Power Supply

0.1µF

CR2025 etc.

VCC

VSB

VDD

VSS

CPU power supply

0.1µF

ML614 etc.

VCC

VSB

VDD

VSS

CPU power supply (3V)

0.1µF

Double layer capacitor etc.

VDD pin cannot be connected to any additional heavy load components such as SRAM. And VDD pin must be connected C2, and C2 should be over 0.1µF.

C2 R1

Vbat

SW2

VSB

VDD

R2051 Series

SW1

VOLTAGE

DETECTOR

VCC

-V

DET1

CPU power supply

CPU

Rcpu

When secondary battery or double layer capacitor connects to VDD pin, after CPU power supply turning off, secondary battery discharges through the root above figure. If R1 is much smaller than CPU impedance (Rcpu), VCC voltage keeps higher than -V

DET1, and SW1 keeps on. Therefore R1 must be specified by following formula.

R1 > Rcpu x (Vbat - (-V

DET1)) / (-VDET1)

R1 is specified by back-up battery or double layer capacitor, too. Please check the data sheet for back-up devices.

• Connection of CIN pin

Please connect capacitor over 0.1µF between CIN and VSS pin.

• Connection of

INTR

and

DCC

Pin (except R2051Txx)

R2051 Series

INTR

The the power supply side. As such, it can be connected to a pull-up resistor of up to 5.5 volts regardless of supply voltage.

INTR or VDCC

OSCOUT

and

OSCIN

VSB

VSS

VDCC

pins follow the N-channel open drain output logic and contains no protective diode on

32768Hz

System power supply

*1)

Backup power supply

*1) Depending on whether the

VDCC

backup, it should be connected to a pull-up resistor at the following different positions:

(1) Position A in the left diagram when it is not to

be used during battery backup.

(2) Position B in the left diagram when it is to be

used during battery backup.

pins are to be used during battery

INTR

and

R2051 Series

Typical Characteristics

• Time keeping current (ISB) vs. Supply voltage (VSB)

(Topt=25°C) Test Circuit

0.5

VCC

OSCIN

0.4

0.3

0.2

0.1

Time keeping current (uA)

0123456

VSB(v)

INTR

VDCC

CLKOUT

SCL

SDA

• Stand-by current (ICC) vs. Supply voltage (VCC)

(Topt=25°C) Test circuit

Stand-by current (uA)

23456

R2051x01

R2051S03

VCC(v)

VCC

INTR

VDCC

CLKOUT

SCL

SDA

• Time keeping current (ISB) vs. Operating Temperature (Topt)

OSCOUT

VSB

VDD

CIN

VSS

OSCIN

OSCOUT

VSB

VDD

CIN

VSS

0.1µF

(VSB=3V) Test circuit

0.7

0.6

0.5

0.4

0.3

0.2

0.1

Time keeping current (uA)

-50 -25 0 25 50 75 100 Operating Temperature (Celsius)

VCC

INTR

VDCC

CLKOUT

SCL

SDA

OSCIN

OSCOUT

VSB

VDD

CIN

VSS

0.1µF

• Stand-by current (ICC) vs. Operating Temperature (Topt)

Test circuit

R2051 Series

6 5 4 3 2 1

Stand-by current(uA)

-50 -25 0 25 50 75 100 Operating temperature (Celsius)

CC=3v(R2051x01/02)

CC=5v

• CPU access current vs. SCL clock frequency (kHz)

(Topt=25°C)

CC=5v

VCC

INTR

VDCC

CLKOUT

SCL

SDA

OSCIN

OSCOUT

VSB

VDD

CIN

VSS

0.1µF

CC=3v

CPU access current (uA)

0 100 200 300 400 500

SCL clock frequency (KHz)

• Oscillation frequency deviation (∆f/f0) vs. Operating temperature (Topt)

(VCC=3V) Topt=25°C as standard Test circuit

-20

-40

-60

-80

df/f0(ppm)

-100

-120

-140

-160

Oscillation frequency deviation

-50 -25 0 25 50 75 100 Operating temperature Topt(°C)

Frequency

counter

VCC

INTR

VDCC

CLKOUT

SCL

SDA

OSCIN

OSCOUT

VSB

VDD

VSS

CIN

0.1µF

R2051 Series

• Frequency deviation (∆f/f0) vs. Supply voltage (VSB/VCC)

(Topt=25°C) VCC/VSB=3V as standard Test circuit

2 1 0

-1

-2

-3

-4

Frequency deviation df/f0(ppm)

0123456

VCC/VSB(v)

Frequency

counter

VCC

VDCC

CLKOUT

SCL

SDA

OSCIN

OSCOUTINTR

VSB

VDD

CIN

VSS

0.1µF

• Frequency deviation (∆f/f0) vs. CGout

(Topt=25°C, VCC=3V) CGout=0pF as standard Test circuit

-10

-20

-30

Frequency deviation df/f0(ppm)

-40 0 5 10 15 20

CGout(pF)

Frequency

counter

VCC

INTR

VDCC

CLKOUT

SCL

SDA

OSCIN

OSCOUT

VSB

VDD

CIN

VSS

0.1µF

• Detector threshold voltage (+VDET1/-VDET1) vs. Operating temperature (Topt) (VSB=3V)

(R2051x01) (R2051x02)

2.6

2.5

2.4

±VDET1(V)

Detector threshold voltage

2.3

-50 -25 0 25 50 75 100 Operating temperature Topt(°C)

-VDET1

DET1

2.9

2.8

±VDET1(V)

Detector threshold voltage

2.7

-50 -25 0 25 50 75 100 Operating temperature Topt(°C)

-V

+VDET1

DET1

(R2051S03) Test circuit

4.4

4.3

4.2

4.1 4

±VDET1(V)

-V

DET1

VCC

INTR

VDCC

R2051 Series

OSCIN

OSCOUT

VSB

3.9

Detector threshold voltage

3.8

-50 -25 0 25 50 75 100 Operating temperature Topt(°C)

CLKOUT

SCL

SDA

• VCC-VDD(VDDOUT1) vs. Output load current (IOUT1)

(Topt=25°C) Test circuit

CC=5V

-0.1

-0.2

-0.3

VCC-VDD(V)

-0.4

-0.5 0246810

Output load current I OUT1(mA)

CC=2.5V

CC=3V

VCC

INTR

VDCC

CLKOUT

SCL

SDA

• VSB-VDD(VDDOUT2) vs. Output load current (IOUT2)

OSCIN

OSCOUT

VSB

VDD

CIN

VSS

VDD

CIN

VSS

0.1µF

(Topt=25°C) Test circuit

-0.1

-0.2

-0.3

-0.4

-0.5

VSB-VDD(V)

-0.6

-0.7

-0.8

SB=1V

00.511.522.53

Output load current I OUT2(mA)

SB=3V

SB=2V

VCC

INTR

VDCC

CLKOUT

SCL

SDA

OSCIN

OSCOUT

VSB

VDD

CIN

VSS

0.1µF

R2051 Series

• VOL vs. IOL (

(Topt=25°C, VSB=VCC=2V) (Topt=25°C)

DCC

pin) (Except R2051Txx) • VOL vs. IOL (

INTR

pin) (Except R2051Txx)

0.8

0.6

0.4

VOL(v)

0.2

0246810

IOL(mA)

0.4

0.3

CC=3V

0.2

VOL(v)

0.1

0246810

IOL(mA)

CC=5V

Typical Software-based Operations

• Initialization at Power-on

R2051 Series

Set Oscillation Adjustment

*1) After power-on from 0 volt, the process of internal initialization require a time span on 1sec, so that access should be done after *2) The PON bit setting of 0 in the Control Register 1 indicates power-on from backup battery and not from 0v. For further details, see "P.41 ■Power-on Reset, Oscillation Halt Sensing, and Supply Voltage Monitoring

•PON, *3) This step is not required when the supply voltage monitoring circuit is not used. *4) This step involves ordinary initialization including the Oscillation Adjustment Register and interrupt cycle settings, etc.

Start

Power-on

PON=1?

Yes

XST

, and VDET ".

*1)

*2)

*4)

VDCC

*3)

VDET=0?

Yes

turning to OFF(H).

Warnin g B a ck -u p

Batter

Run-down

• Writing of Time and Calendar Data

Start Condition

Write to Time Counter and

Calendar Counter

Stop Condition

*1)

*2)

*3)

*1) When writing to clock and calendar counters, do not insert Stop Condition until all times from second to year have been written to prevent error in writing time. (Detailed in "P.34 Data Transmission under Special Condition". *2) Any writing to the second counter will reset divider units lower than the second digits.

*3) Take care so that process from Start Condition to Stop Condition will be complete within 0.5sec. (Detailed in "P.34 Data Transmission under Special Condition".

The R2051 may also be initialized not at power-on but in the process of writing time and calendar data.

R2051 Series

• Reading Time and Calendar Data

(1) Ordinary Process of Reading Time and Calendar Data

*1)

Start Condition

*1) When reading to clock and calendar counters, do not insert Stop Condition until all times from second to year have been written to prevent error in writing time. (Detailed in "P.34 Data Transmission under Special Condition".

Read from Time Counter

and Calendar Counter

*2) Take care so that process from Start Condition to Stop Condition will be complete within 0.5sec. (Detailed in "P.34 Data Transmission under Special Condition".

Stop Condition

*2)

(2) Basic Process of Reading Time and Calendar Data with Periodic Interrupt Function

Set Periodic Interrupt

Cycle Selection Bits

Generate Interrupt in CPU

CTFG=1?

Yes

Read from Time Counter

and Calendar Counte

*2)

*1)

Other Interrupt

Processes

*1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) This step must be completed within 0.5 second. *3) This step is intended to set the CTFG bit to 0 in the Control Register 2 to cancel an interrupt to the CPU.

*3)

Control Register 2

←(X1X1X011)

R2051 Series

(3) Applied Process of Reading Time and Calendar Data with Periodic Interrupt Function (Except R2051Txx)

Time data need not be read from all the time counters when used for such ordinary purposes as time count indication. This applied process can be used to read time and calendar data with substantial reductions in the load involved in such reading.

For Time Indication in "Day-of-Month, Day-of-week, Hour, Minute, and Second" Format:

Contr o l Register 1←

(XXXX0100)

Contr o l Register 2←

(X1X1X011)

Generate interrupt to CPU

CTFG=1?

Yes

Sec.=00?

*2)

*1)

Other interrupts

Processes

*1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) This step must be completed within 0.5 sec. *3) This step is intended to read time data from all the time counters only in the first session of reading time data after writing time data. *4) This step is intended to set the CTFG bit to 0 in the Control Register 2 to cancel an interrupt to the CPU.

Read Min.,Hr.,Day,

and Day-of- wee k

Control Register 2←

(X1X1X011)

Yes

*3)

Use previous Min.,Hr.,

Day , and Day- of-week data

*4)

R2051 Series

• Interrupt Process

(1) Periodic Interrupt (except R2051Txx)

Set Periodic Interrupt

Cycle Selection Bits

Generate Interrupt to CPU

CTFG=1?

Yes

Conduct

Periodic Interru

Control Register 2←

(X1X1X011)

*2)

*1)

Other Interrupt

Processes

*1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) This step is intended to set the CTFG bit to 0 in the Control Register 2 to cancel an interrupt to the CPU.

(2) Alarm Interrupt (except R2051Txx)

WALE or DALE←0

Set Alarm Min., Hr ., and

Day-of- week Re gister s

WALE or DALE←1

Generate Interrupt to CPU

WAFG or DAFG= 1?

Yes

Conduct Ala r m Interrupt

*1)

*2)

Other Interrupt

Processes

*1) This step is intended to once disable the alarm interrupt circuit by setting the WALE or DALE bits to 0 in anticipation of the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm interrupt function. *2) This step is intended to enable the alarm interrupt function after completion of all alarm interrupt settings. *3) This step is intended to once cancel the alarm interrupt function by writing the settings of "X,1,X, 1,X,1,0,1" and "X,1,X,1,X,1,1,0" to the Alarm_W Registers and the Alarm_D Registers, respectively.

*3)

Control Register 2 ←

(X1X1X101)

RICOH R2051 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual