Preliminary
RT9913A/B
Integrated Multi-Channel DC-DC Converter for
TFT LCD Panels
General Description
The RT9913A/B includes a high-performance boost
regulator, one linear-regulator controller for VGL, one low
dropout linear regulator, a gate pulse modulator (GPM), a
voltage detector and a V
active-matrix thin-film transistor (TFT) liquid-crystal displays
(LCDs).
The boost converter provides the regulated supply voltage
for the panel source driver ICs. With integrated 16V
N-Channel 0.2Ω MOSFET it allows the use of ultra-small
inductors and ceramic capacitors and provides fast transient
response to pulsed loads. The VGL linear-regulator
controller provides regulated TFT Gate-Off . The low-dropout
linear regulator (LDO) using an internal PMOS as the pass
device can supply up to 350mA current is suitable for the
supply voltage to the T-CON ASIC. And the GPM is
controlled by frame signals from timing controller to
modulate the Gate-On voltage. Voltage detector monitors
the supply voltage to issue a reset signal while the
detected voltage is too low. The V
high-performance operation amplifier) can drive the LCD
backplane (V
) and features high short-circuit current
COM
(140mA), fast slew rate (12V/μs), wide bandwidth (12MHz)
and rail-to-rail input and output.
Buffer (Unity- gain OPA) for
COM
Buffer (Unity-gain)
COM
Features
zz
2.5V to 5.5V Input Supply Voltage
z
zz
zz
z 640kHz/1.2MHz (A/B version) Current-Mode Step-Up
zz
Boost Regulator
Fast Transient Response to Pulsed Load
High Accuracy Output Voltage (
Built-In 16V, 2.0A, 0.2
ΩΩ
Ω N-Channel MOSFET
ΩΩ
High Efficiency Up to 90%
Programmable Soft-Start
Programmable Over-Current Protection
zz
z Linear-Regulator Controller for VGL
zz
zz
z Low Drop-Out Voltage Linear Regulator
zz
Adjustable Output Voltage (2.5V to 3.3V)
350mA Maximum Output Current
zz
z On-Chip GPM Controller with Adjustable Falling
zz
Time
Flicker Compensator
Power-On Sequence Control
zz
z Low Voltage Detector
zz
Programmable Detecting Voltage and Delay Time
zz
z Unity-Gain Operation Amplifier for V
zz
zz
z Over-Temperature Protection
zz
zz
z Thin 24-Lead VQFN Package
zz
zz
z RoHS Compliant and 100% Lead (Pb)-Free
zz
±±
±2%)
±±
COM
Buffer
Marking Information
Ordering Information
RT9913A/B
Package Type
QV : VQFN-24L 4x4 (V-Type)
Operating Temperature Range
P : Pb Free with Commercial Standard
Switching Frequency
A : 640kHz
B : 1.2MHz
Note :
RichTek Pb-free products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
DS9913A/B-00 February 2006 www.richtek.com
For marking information, contact our sales representative
directly or through a RichTek distributor located in your
area, otherwise visit our website for detail.
1
RT9913A/B
Pin Configurations
VFLK
VGH
VGHM
RE
VREF
FBN
Preliminary
(TOP VIEW)
OPAI
OPAO
AVDD
24 2223
1
2
3
4
5
6
7
21 20 19
GND
8 9 10 12
PGND
EN
FB
18
LX
17
VIN
16
COMP
15
SS
14
LDOI
13
LDOO
11
Typical Application Circuit
V
GL
-6V
C13
0.22uF
V
Q1
MMBT3904
R9
240k
R10
50k
C14
0.22uF
DIN
R6
65k
R7
110k
R8
6.8k
V
FLK
V
LDO
RESET
V
AVDD
Chip Enable
BAT54S
C12
0.1uF
D4
R14
100k
C4
27nF
C10
0.1uF
R
C1
10uF
SET
19
7
6
15
5
8
1
9
22
10
DRVN
VQFN-24L 4x4
C11
0.1uF
EN
DRVN
FBN
SS
VREF
CD
VFLK
RESET
AVDD
VDIV
AGND
CD
RESET
V
IN
3.3V
17
VIN
RT9913
11
VDIV
COMP
VGHM
OPAO
OPAI
LDOI
LDOO
PGND
21
AGND
4.7uH
LX
FB
VGH
RE
ADJ
L1
ADJ
C7
0.1uF
V
AVDD
8.5V
C2
4.7uF x 3
C6
0.1uF
D3
BAT54S
C8
0.1uF
R
30k
GH
18
20
16
C
COMP
NC
D2
BAT54S
SS12
D1
R3
56k
C3
1nF
C5
0.1uF
R1
330k
R2
56k
2
C15
1.5nF
C9
1uF
V
GHM
25V
V
COM_OUT
C16
1uF
V
LDO
2.5V
V
IN
3.3V
V
COM_IN
V
AVDD
R12
56k
R13
56k
3
4
23
24
14
13
12
R11
1.2k
R5
56k
R4
56k
DS9913A/B-00 February 2006www.richtek.com
2
Preliminary
RT9913A/B
Functional Pin Description
Pin Number Pin Name Pin Function
1 VFLK VFLK is produced by timing controller for charging or discharging VGHM.
2 VGH Switch input for charge VGHM
3 VGHM VGHM is the supply voltage for the gate driver ICs.
4 RE Switch input for discharge VGHM
5 VREF
6 FBN
7 DRVN
8 CD Pin for external capacitor setting the delay time for voltage detector reset delay time.
9 RESET Voltage Detector open-drain Output for Reset.
10 VDIV
11 AGND Analog Ground.
12 ADJ
13 LDOO Voltage Output of the LDO.
14 LDOI Voltage Input of the LDO.
15 SS
16 COMP Compensation Error Amplifier Pin. Connect a compensation network to ground.
17 VIN
18 LX Switching pin. Drain of the internal power NMOS for the main step-up regulator.
19 EN Active-High Enable Control Input and OCP level setting.
20 FB
21 PGND Power Ground. PGND is the source of the power NMOS.
22 AVDD VDD for Source Driver Power. It also supplies OP power and GPM level shift voltage.
23 OPAO Unit-Gain OPA Output Pin.
24 OPAI Unit-Gain OPA Input Pin.
Exposed Pad GND Exposed pad should be soldered to PCB board and connected to GND.
Internal Reference Bypass Terminal. Connect a 0.22uF ceramic capacitor from the VREF
to analog ground (AGND). The source capability is 100uA.
Negative Linear-Regulator Feedback Input. Connect FBN to the center of a resistive
voltage-divider between the negative output voltage VGL and the VREF to set the
negative linear-regulator output voltage. Place the resistive voltage-divider close to the
pin.
Negative Linear-Regulator Base Drive. Open drain of an internal PMOS. Connect DRVN
to the base of the external linear-regulator NPN pass transistor.
Voltage Detector Divider Input. Connect VDIV to the center of a resistive voltage-divider
between the detected voltage input (VDIN) and analog ground (AGND).
Low-Dropout Linear Regulator (LDO) Feedback Input. ADJ regulates to 1.24V nominal.
Connect ADJ to the center of a resistive voltage-divider between the LDO output voltage
LDOO and the analog ground (AGND) the LDO output voltage. Place the resistive
voltage-divider close to the pin.
Soft-Start Control Pin. Connect a soft-start capacitor (C
capacitor is charged with a constant current 4uA.
Supply Input. The supply voltage powers all the control circuits including the boost
converter, negative linear-regulator, gate pulse regulator and voltage detector.
Main Boost Regulator Feedback Input. FB regulates to 1.24V nominal. Connect FB to the
center of a resistive voltage-divider between the main output AVDD and the analog
ground (AGND) the boost regulator output voltage. Place the resistive voltage-divider
close to the pin.
) to this pin. The soft-start
SS
DS9913A/B-00 February 2006 www.richtek.com
3
RT9913A/B
Function Block Diagram
Preliminary
EN
SS
V
IN
VIN
VDIV
RESET
LDOI
LDOO
ADJ
VREF
FBN
AGND
Boost Regulator Block Diagram
CD
Voltage
Detector
LDO
1.24V
Voltage
Reference
+
-
DRVN
Boost
Regulator
GPM
LX
PGND
FB
COMP
V
IN
VGHM
RE
AVDD
VGH
VFLK
OPAO
+
-
OPAI
VIN
4uA
EN
COMP
FB
Oscillator
1.24V
Protection
+
Error
Amplifier
Slope
Compensation
Summing
Comparator
+
-
Clock
SoftStart
Control
and
Driver
Logic
Current
Sense
SS
LX
PGND
DS9913A/B-00 February 2006www.richtek.com
4
Preliminary
Absolute Maximum Ratings (Note 1)
RT9913A/B
z Supply Input Voltage, V
z VGH-AVDD, VGHM-AVDD ---------------------------------------------------------------------------------- 18V
z LX ---------------------------------------------------------------------------------------------------------------- −0.3V to 16V
z VGH, VGHM RE ---------------------------------------------------------------------------------------------- −0.3V to 30V
z AVDD ------------------------------------------------------------------------------------------------------------ −0.3V to 16V
z OPAI, OPAO --------------------------------------------------------------------------------------------------- −0.3V to (AVDD + 0.3V)
z DRVN ------------------------------------------------------------------------------------------------------------ (V
z VFLK, VREF, FBN, CD, RESET_, VDIV, SS, COMP, EN, FB ------------------------------------ −0.3V to (V
z LDOI ------------------------------------------------------------------------------------------------------------- −0.3V to 7V
z ADJ, LDOO ---------------------------------------------------------------------------------------------------- −0.3V to (LDOI + 0.3V)
z Power Dissipation, P
----------------------------------------------------------------------------------- −0.3V to 7V
IN
@ T
D
= 25°C
A
− 16V) to (VIN + 0.3V)
IN
+ 0.3V)
IN
VQFN-24L 4x4 ------------------------------------------------------------------------------------------------ 1.786W
z Package Thermal Resistance (Note 4)
VQFN-24L 4x4, θJA------------------------------------------------------------------------------------------- 56°C/W
z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------ 260°C
z Storage Temperature Range ------------------------------------------------------------------------------- −65°C to 150°C
z Junction Temperature ---------------------------------------------------------------------------------------- 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) --------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 3)
z Ambient Temperature Range ------------------------------------------------------------------------------- −40°C to 85°C
z Junction Temperature Range ------------------------------------------------------------------------------- −40°C to 125°C
Electrical Characteristics
(VIN = 3.3V, V
System Supply
Input Supply Voltage
VIN Under Voltage Lockout Threshold V
VIN Quiescent Current IQ
Shut Down Current
EN Threshold
Main Boost Regulator
Operation Frequency
= 8.5V, TA = 25°C, unless otherwise specification)
OUT
Parameter Symbol Test Condition Min Typ Max Units
2.5 -- 5.5 V
V
rising
IN
1.8 2.0 2.2
Hysteresis 0.05 0.1 0.15
V
= 1.3V, LX no switching
FB
= 1.1V, LX switching
V
FB
VIN = 3.3V
-- -- 1.5
0.8 -- --
0.15 0.4 1 mA
1 2 3.5 mA
-- 1 5
Logic-High Voltage
Logic-Low Voltage
V
I
IN
V
V
IN
UVLO
IH
IL
RT9913 A -- 640 -- kHz
F
OSC
RT9913 B 0.9 1.2 1.4 MHz
V
μA
V
Maximum Duty Cycle 86 90 94 %
To be continued
DS9913A/B-00 February 2006 www.richtek.com
5
RT9913A/B
Parameter Symbol Test Condition Min Typ Max Units
Preliminary
Feedback Voltage
V
FB
FB Input Bias Current
Transconductance of Error Amplifier Gm
Voltage Gain of Error Amplifier
A
V
Feedback Voltage Line Regulation
Output Voltage Load Regulation
LX ON-Resistance
R
LX(ON)
No load, TA = 25°C
V
= 1.5V
FB
I
= 5μA
COMP
-- 700 -- V/V
V
= 2.5V to 5.5V
IN
V
= 3.3V,
IN
I
= 20 to 200mA
LOAD
50 200 500
1.22 1.24 1.26 V
-40 -- +40 nA
-- 160 --
μA/V
-- 0.1 0.15 %/V
−1
-- 0 %
mΩ
Current Sense Transresistance -- 0.5 -- A/V
Soft-Start Charge Current
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Current Limit
I
SS
T
ΔT
I
LIM
SD
2 4 6
-- 170 --
-- 20 --
SD
-- 2 -- A
μA
°C
°C
Gate-Off Regulation Controller
V
source current capability I
REF
FBN Regulation Voltage
FBN Effective Load Regulation Error
FBN Line Regulation Error
DRVN Source Current
Power-On-Delay Time
REF
V
FBN
I
DRVN
T
Refer to V
VGL
-- 100 1000
V
= −10V,
DRVN
I
= 50uA to 1mA
DRVN
I
= 0.1mA, 2.5V<VIN<5.5V
DRVN
−20
−30 −5
-- 1 6 mV
0 20 mV
0 mV
1 4 6 mA
FB
> 1V
25 32 39 ms
μA
Low Drop-Out Linear Regulator (LDO)
Input Voltage
Dropout Voltage
Feedback Voltage
Current Limit
Quiescent Current
Line Regulation
Load Regulation
Gate Pulse Modulator
VFLK Input High Voltage
VFLK Input Low Voltage
Power-On-Delay Time (Note 5)
6
V
LDOI
V
DROP
V
ADJ
I
LIM
I
LDO
V
IH_FLK
V
IL FLK
T
VGHM
2.5 -- 5.5 V
V
= 3.3V, I
IN
1.22 1.24 1.26 V
OUT
= 350mA
200 300 500 mV
350 500 650 mA
-- 60 100
V
= 2.8V to 5.5V,
IN
I
= 100mA, V
OUT
I
= 1mA to 300mA
OUT
1.5 -- -- V
-- -- 0.6 V
Refer to V
FB
> 1V
LDO
= 2.5V
-- 0.1 0.3 %/V
0 0.2 0.5 %
50 64 78 ms
μA
To be continued
DS9913A/B-00 February 2006www.richtek.com
Parameter Symbol Test Condition Min Typ Max Units
Gate Pulse Modulator
Preliminary
RT9913A/B
VGH Switch On-Resistance RP1 10 30 50
RE Switch On-Resistance RN2 10 25 50
Ω
Ω
Voltage Detector
Minimum Operating Voltage 1.6 -- -- V
Detecting voltage adjustment
V
DIV
Detecting voltage accuracy
Adjustable delay time-constant k
V
Buffer
COM
Supply Voltage Range
Supply Current
Input Offset Voltage
Input Bias Current
Output Voltage Swing High
Output Voltage Swing Low
V
SUP
I
OP
V
V
OS
I
BIAS
V
OH
V
OL
-- 1.1 -- V
−2%
= k(Ω)*C10(F)
t
D
AVDD -- 15 V
80k 120k 160k
-- 2% %
Ω
-- 0.5 0.9 mA
= AVDD/2, TA = 25°C
COM
-- 1 50 nA
I
= 100μA
OUT
= 75mA
I
OUT
I
= −100μA
OUT
= −75mA
I
OUT
−15
AVDD-20 AVDD-5 -- mV
AVDD-1.5 AVDD-1.3 -- V
-- 2 20 mV
-- 1.5 1.8 V
0 15 mV
Source 100 140 180 mA
Short-Circuit Current To AVDD/2
Sink 100 140 180 mA
-3dB Bandwidth
F
3db
-- 12 -- MHz
Gain Bandwidth Product GBW -- 8 -- MHz
Slew Rate SR 8 12 16
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θ
Note 5. It is guaranteed by design.
is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JA
JEDEC 51-3 thermal measurement standard.
V/μs
DS9913A/B-00 February 2006 www.richtek.com
7
RT9913A/B
Typical Application Circuit
Preliminary
Boost Efficiency vs. Output Current
95
90
85
80
75
70
65
Efficiency (%)
60
55
50
0 20 40 60 80 100 120 140 160 180 200
V
= 8.5V, f = 1.2MHz
AVDD
Output Current (mA)
Boost Efficiency vs. Outpu t Curren t
95
90
85
80
75
70
65
Efficiency(%)
60
55
50
0 20 40 60 80 100 120 140 160 180 200
Output Current (mA)
V
= 12V, f = 1.2MHz
AVDD
V
= 3.3V
IN
V
= 3.0V
IN
V
= 2.7V
IN
VIN = 3.3V
VIN = 3.0V
Boost Output Voltage vs. Output Current
8.62
8.6
8.58
8.56
8.54
8.52
Output Voltage (V)
8.5
V
= 8.5V, f = 1.2MHz
8.48
0 20 40 60 80 100 120 140 160 180 200
AVDD
Output Current (mA)
Boost Output Voltage vs. Output Current
12.04
12
11.96
11.92
Output Voltage (V)
11.88
11.84
11.8
11.76
0 20 40 60 80 100 120 140 160 180 200
VIN = 3.0V
VIN = 3.3V
V
= 12V, f = 1.2MHz
AVDD
Output Current (mA)
V
V
V
= 2.7V
IN
= 3.0V
IN
= 3.3V
IN
Boost Efficiency vs. Output Current
90
88
V
AVDD
86
84
82
Efficiency (%)
80
78
76
0 20 40 60 80 100 120 140 160 180 200
V
C1 = 6.9μF, C2 = 30μF
Output Current (mA)
= 7.5V
= 8V
= 8.5V
= 3V, f = 1.2MHz
IN
= 7V
Boost Output Voltage v s. Output Current
8.6
8.4
V
= 8.5V
AVDD
8.2
8
V
= 8V
AVDD
7.8
7.6
7.4
V
= 7.5V
AVDD
7.2
Output Voltage (V)
7
V
= 7V
AVDD
6.8
6.6
0 20 40 60 80 100 120 140 160 180 200
V
= 3V, f = 1.2MHz, C1 = 6.9μF, C2 = 30μF
IN
Output Current (mA)
DS9913A/B-00 February 2006www.richtek.com
8
Boost Feedback (V)
Boost Feedback vs. Temperature
1.255
1.250
1.245
1.240
1.235
1.230
1.225
1.220
1.215
1.210
1.205
-40-30-20-100 102030405060708090
Temperature
(°C)
Preliminary
V
AVDD
ac coupled
(500mV/Div)
I
LOAD
(100mA/Div)
I
L
(500mA/Div)
RT9913A/B
Boost Regulator Load
Transient Response
I
= 10mA to 200mA
LOAD
Time (200μs/Div)
V
AVDD
(5V/Div)
V
IN
(5V/Div)
EN
(2V/Div)
I
IN
(500mA/Div)
V
LX
(5V/Div)
V
ripple
AVDD
ac coupled
(50mV/Div)
I
L
(200mA/Div)
Boost Regulator Soft-Start
I
= 200mA
LOAD
Time (2.5ms/Div)
Boost Regulator Stability
Time (400ns/Div)
f = 1.2MHz
I
LOAD
= 100mA
V
LX
(5V/Div)
V
ripple
AVDD
ac coupled
(50mV/Div)
I
L
(200mA/Div)
-5.75
-5.77
-5.79
-5.81
-5.83
VGL Voltage (V)
-5.85
-5.87
Boost Regulator Stability
I
= 10mA, f = 1.2MHz
LOAD
Time (400ns/Div)
VGL Regulator Load Regulation
0 102030405060708090100
Load Current (mA)
DS9913A/B-00 February 2006 www.richtek.com
9
RT9913A/B
Preliminary
-5.75
-5.77
-5.79
-5.81
-5.83
VGL Output Voltage (V)
-5.85
(5V/Div)
(5V/Div)
(10V/Div)
(10V/Div)
VGL Regulator Line Regulation
IGL = 50mA
-14 -13 -12 -11 -10 -9 -8 -7
Input Voltage(V)
Power Off Sequence
with GPM Function
V
AVDD
VGH
VGL
VGHM
FLK = 50kHz/50%
V
AVDD
(5V/Div)
VGH
(10V/Div)
VGHM
(10V/Div)
VGL
(5V/Div)
(5V/Div)
(5V/Div)
(10V/Div)
(10V/Div)
Power On Sequence
Time (25ms/Div)
Power Off Sequence
V
VGHM
FLK = V
AVDD
VGL
VGH
IN
VFLK
(1V/Div)
VGHM
(10V/Div)
10
Time (2.5ms/Div)
VGHM
R11 = 670Ω, C15 = 1.5nF
Time (10μs/Div)
Time (25ms/Div)
VGHM
VFLK
(1V/Div)
VGHM
(10V/Div)
R11 = 1.2kΩ, C15 = 680pF
Time (10μs/Div)
DS9913A/B-00 February 2006www.richtek.com
Preliminary
RT9913A/B
VFLK
(1V/Div)
VGHM
(10V/Div)
V
LDOO
ac coupled
(100mV/Div)
VGHM
R11 = 1.2kΩ, C15 = 2.2nF
Time (10μs/Div)
LDO Line Transient
V
LDOO
ac coupled
(50mV/Div)
I
LDOO
(200mA/Div)
2.59
2.585
LDO Load Transient
I
= 10mA to 350mA
LDOO
Time (100μs/Div)
LDO Load Regulation
V
LDOI
(1V/Div)
Dropout Voltage (mV)
4
3
V
LDOO
= 2.5V, V
= 3V to 4V, I
LDOI
LDOO
Time (100μs/Div)
LDO Dropout Voltage
500
450
400
350
300
250
200
150
100
50
0
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Load Current (A)
85°C
= 50mA
25°C
-40°C
2.58
2.575
LDO Output Voltage (V)
2.57
I
LDO
(200mA/Div)
V
LDO
(1V/Div)
V
= 2.5V, V
LDOO
0 50 100 150 200 250 300 350
LDOI
= 3.3V
LDO Loading Current (mA)
LDO OCP
I
= 100mA to 600mA
OUT
Time (100μs/Div)
DS9913A/B-00 February 2006 www.richtek.com
11
RT9913A/B
Preliminary
V
OPAI
(1V/Div)
V
OPAO
(1V/Div)
V
OPAI
(5V/Div)
OPA Large-Signal Step Response
Time (1μs/Div)
OPA Rail-to-Rail Input/Output
V
OPAI
(100mV/Div)
V
OPAO
(100mV/Div)
OPA Small-Signal Step Response
Time (500ns/Div)
OPA Slew Rate
V
OPAI
V
OPAO
V
OPAO
(5V/Div)
Time (400μs/Div)
(2V/Div)
Time (1μs/Div)
12
DS9913A/B-00 February 2006www.richtek.com
Application Information
Preliminary
RT9913A/B
The RT9913 contains a high performance boost regulator
to generate voltage for output voltage, gate-on driver and
negative voltage regulated by linear regulator controller
for gate-off driver. It also includes of a high-current rail-to-
rail operation amplifier, a gate pulse modulator (GPM), a
programmable timing control voltage detector, and a low
dropout linear regulator. The following content contains
the detailed description and the information of component
selection.
Boost Regulator
The boost regulator is a high efficiency current-mode PWM
architecture with 1.2MHz or 640kHz operation frequency.
It performs fast transient responses to generate gate driver
supplies for TFT LCD display. The high operation frequency
allows smaller components used to minimize the
thickness of LCD panel. To regulate the output voltage is
to set resistive voltage-divider sensing at FB pin. The error
amplifier varies the COMP voltage by sensing FB pin to
regulate the output voltage. For better stability, the slope
compensation signal summed with the current-sense
signal will be compared with the COMP voltage to
determine the current trip point and duty cycle.
Soft-Start
The RT9913 provides soft-start function to minimize the
inrush current. When EN pin is connected to high, an
internal constant current charges an external capacitor.
The rising voltage rate on COMP pin is limited during the
charging period and the inductor peak current also limited
at the same time. In the meanwhile, the frequency
increases slowly at the beginning. When the EN pin is
connected to GND, the external capacitor will be
discharged for next soft start time.
The soft-start function is implemented by the external
capacitor with a 4μA constant current charging to the soft-
start capacitor. Therefore, the capacitor should be large
enough for output voltage regulation. Typical value for soft-
start capacitor range is 27nF. The available soft start
capacitor range is from 10nF to 200nF.
Inductor Selection & Maximum output current
capability
The minimum inductance value, peak current rating and
series resistance are factors to consider when selecting
the inductor. These factors influence the converter's
efficiency, maximum output load capability, transient-
response time and output voltage ripple. Physical size
and cost are also important factors to be considered. The
maximum output current, input voltage, output voltage and
switching frequency determine the inductor value. Very
high inductance values minimize the current ripple and
therefore reduce the peak current, which decreases core
losses in the inductor and I2R losses in the entire power
path. However, large inductor values also require more
energy storage and more turns of wire, which increase
physical size and can increase I2R losses in the inductor.
Low inductance values decrease the physical size but
increase the current ripple and peak current.
Finding the best inductor involves choosing the best
compromise between circuit efficiency, inductor size and
cost.
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input current
at the minimum input voltage V
using the following
IN(MIN)
equation.
VI
×
I
=
MAX) IN(DC,
V
The expected efficiency at that operating point (η
AVDDAVDD(MAX)
η
×
(MIN)IN(MIN)
) can
MIN
be taken from an appropriate curve in the Typical Operating
Characteristics. Calculate the ripple current at that
operating point and the peak current required for the
inductor :
I
RIPPLE
I
RIPPLE
2
−×
fVL
××
OSCAVDD
=
I I
+=
MAX) IN(DC,PEAK
)V(VV
IN(MIN)AVDDIN(MIN)
The inductor's saturation current rating and the LX over-
current protection (I
inductor DC current rating should exceed I
) should exceed I
OCP
and the
PEAK
IN(DC,MAX)
. For
good efficiency, choosing an inductor with less than 0.1Ω
series resistance is suggested.
DS9913A/B-00 February 2006 www.richtek.com
13
RT9913A/B
Preliminary
Diode Selection
To achieve high efficiency, Schottky diode is the
recommended diode for lower forward drop voltage and
faster switching time. The output diode rating should be
large enough for maximum output voltage, average power
dissipation and the pulsating diode peak current.
Output Capacitor Selection
For lower output voltage ripple, low-ESR ceramic capacitor
is recommended. The output voltage ripple consists of
two components: one is the pulsating output ripple current
flowing through the ESR, and the other is the capacitive
ripple caused by charging and discharging.
+=
VVV
RIPPLE_CRIPPLE_ESRRIPPLE
−
AVDD
VV
⎞
INAVDD
⎟
×
fV
⎠
RI
ESRPEAK
C
OUT
⎜
⎝
I
⎛
PEAK
+×≅
Input Capacitor Selection
For better input bypassing, low-ESR ceramic capacitor is
recommended for better performance. A 10μF input
capacitor is sufficient and it is flexible to reduce the value
for a lower output power requirement.
Over Current Protection
The RT9913 main boost converter has over-current
protection to limit peak inductor current. It prevents large
current damaging the inductor and diode. During the
ON-time, once the inductor current exceeds the current
limit, the internal LX switch turns off immediately and
shortens the duty cycle. Therefore, the output voltage
drops if the over-current condition occurs. Actual current
limit is always larger than nominal value because of the
internal circuit delay. Current limit is also affected by the
input voltage, duty cycle, and inductor value. The following
figure shows the different over-current settings and the
corresponding R
and V
AVDD
2.2
2
1.8
1.6
1.4
1.2
OCP Current (A)
1
falls to 90%.
resistance while OCP function works
SET
OCP Current vs. R
SET
Output Voltage
The regulated output voltage is the following formula :
R1
OUT
⎛
⎜
⎝
⎞
+×=
11.24VV
⎟
R2
⎠
The recommended value for R2 should be up to 100kΩ
without some sacrificing. To place the resistor-divider as
close as possible to the chip can reduce noise sensitivity.
Loop Compensation
The voltage feedback loop can be compensated with an
external compensation network consisted of R3, C3 and
C
(As Figure 1). Choose R3 to set high frequency
COMP
integrator gain for fast transient response and C3 to set
the integrator zero to maintain loop stability.
Place C
between COMP and GND to add an additional
COMP
high-frequecncy pole. The value is between 10pF and
47pF. For typical application VIN = 3.3V , V
,C
= 4.7μF x 3 , L = 4.7μH, the recommened value
OUT
OUT
= 8.5V
for compensation is as below:
0.8
0.6
50 100 150 200 250 300
(kΩ)
R
SET
Figure 1. OCP settings versus R
SET
@ V
= 2.5V
EN
Over Temperature Protection
The RT9913 main boost converter has thermal protection
function to prevent the excessive power dissipation from
overheating. When the junction temperature exceeds
170°C, it will shut down the device. Once the device cools
down by approximately 20°C, it will start to operate
normally. For continuous operation, do not operate over
the maximum junction temperature rating around 150°C.
R3 = 56kΩ , C3 = 1nF , Ccomp=NC
14
DS9913A/B-00 February 2006www.richtek.com
Preliminary
RT9913A/B
Gate-Low Linear Regulator Controller
The gate-low linear regulator controller is to provide the
TFT-LCD gate off voltage. One stage charge pump can
provide a negative voltage. Using the gate-low regulator
after the produced negative voltage can regulate the
exceeded voltage. With a 6.8kΩ base to emitter resistor
it can drive an extra NPN pass transistor and at least 4mA
source current. VGL can be regulated by the voltage-divider
resistor and 0.22μF ceramic output capacitor. The output
load current (I
(β), drive current (I
drop (VBE) and base-to-emitter resistor (R8) as the following
equation :
β
=
DRVNLOAD
C14
C13
The VGL regulator controls the intermediate charge-pump
stage and regulates the final charge-pump's output voltage
as the following equation :
) can be decided by the current gain
LOAD
), base-to-emitter forward voltage
DRVN
V
BE
)
-(I I
R8
VGL Regulation Circuit
VREF
1.24V
R10
R9
VGL
FBN
RL
+
-
DRVN
Q1
PWM
R8
C12
Figure 2
LX
C11
VGL
ZD1
V
IN
VIN
LX
Boost
Regulator
FB
RT9913A/B
V
AVDD
Figure 3
GPM
The GPM function is controlled by frame signals from
timing controller to modulate the Gate-On voltage (VGHM).
According to the different loading capacitor (C16), the
falling slope of the Gate-On voltage is programmable by
an external resistor (R11) .The VGL lags 32ms (typ.) behind
AVDD and the VGHM lags 64ms (typ.) behind AVDD while
power on.
VGH
VFLK
PGOOD
Pos-edge
64ms delay
PGOOD
Delay
Gate Pulse Modulator
VGHM
P1
N2
RE
C15
R11
Gate
Driver IC
VGL = −V
Zener Diode for the Negative Regulator
Instead of the gate-low linear regulator controller,
bypassing a zener diode(ZD1) after the charge-pump satge
can also stable the negative voltage. However, for better
efficiency, using the gate-low linear regulator controller is
recommended.
VGL = −(V
(R9/R10)
REF
AVDD
− VD)
Figure 4
The GPM operation sequence is shown in Figure 5.
PGOOD is the logic signal detecting the feedback voltage
(VFB). If V
is below 1V, PGOOD becomes low ;
FB
otherwise, PGOOD is high while VFB is above 1V. When
PGOOD is high lasting more than 64ms, PGOOD Delay
signal is built and then VGHM is controled by V
FLK
signal.
VD : forward voltage drop of the charge pump diode
DS9913A/B-00 February 2006 www.richtek.com
15
RT9913A/B
Preliminary
VIN
AVDD
VGH
PGOOD
PGOOD Delay
VFLK
64ms
VGHM
adjustable falling slope
V
GH
Figure 5
GPM for Power Sequence
The GPM function also achieves the power-on sequence
control. The GPM internal delay time (64ms) can be used
for VGH built-up delay. The application circuit is shown in
Figure 6 connecting input voltage to V
a 1uF to VGHM .VGH will lag 64ms after V
and bypassing
FLK
built.
AVDD
Charge Pumps
The charge pump stages can be achieved by the flying
capacitors and the Schottky diodes. According to the
application circuit, the positive and negative charge-pump
output voltages can be determined by the following
equations :
VGH = 3V
V
: the forward voltage drop of the charge pump diodes
D
AVDD
− 2V
D
The flying capacitor requires the voltage rating larger than
16V and 0.1uF ceramic capacitors are enough for the low-
current applications (10mA) . Besides, Schottky diodes
with a current rating should equal to or greater than two
times the average charge-pump input current. Note that
the voltage difference between VGH (VGHM) and AVDD
should not exceed 18V.
Operational Amplifier
The operational amplifier to drive the LCD backplane V
The operational amplifier features +/- 140mA output short-
circuit current, 12V/μs slew rate, and 12MHz bandwidth.
COM
.
VGH
VIN
VIN
AVDD
VGH
VGL
VGHM
VGH
VFLK
RT9913A/B
32ms
GPM
64ms
Figure 6
VGHM
RE
1uF
V
GHM
An internal short-circuit protection circuit is implemented
to protect the device from output short circuit. The
operational amplifier limits the short circuit current while
the output is directly shorted.
LDO
The low-dropout linear regulator (LDO) can supply up to
350mA current while input voltage is 3.3V. It uses an
internal PMOS as the pass device. The output current
limitation is 500mA. It is suitable for the supply voltage
for the T-CON ASIC.
LDOI
+
Current
Limit
LDOO
R4
ADJ
R5
AGND
16
Figure 7
DS9913A/B-00 February 2006www.richtek.com
Preliminary
RT9913A/B
Voltage Detector
The voltage detector monitors the VDIN voltage to generate
a reset signal while VDIN is lower than the detecting level.
The detecting level is decided by an external resistor divider.
V
= V
DET
V
= 50mV (1+R6/R7)
HYS
The delay time is programmable by an external capacitor
(C10) as equation. For example, setting C10 = 100nF can
generate 12ms delay for reset signal.
tD = 120k x C10
VDIN
R6
R7
(1+R6/R7) = 1.1V x (1+R6/R7)
REF2
VDIV
V
REF2
= 1.1V
+
-
Delay
Circuit
CD
C10
VIN
RESET
VLDO
R14
Layout Guideline
For high frequency switching power supplies, the PCB
layout is important to get good regulation, high efficiency
and stability. The following descriptions are the guidelines
for better PCB layout.
z For good regulation place the power components as
close as possible. The traces should be wide and short
especially for the high-current output loop.
z The current limit setting resistor R
EN pin, The trace must be shorter and avoid the trace
near any switching nodes.
z The feedback voltage-divider resistors must be near the
feedback pin. The divider center trace must be shorter
and avoid the trace near any switching nodes.
z The compensation circuit should be kept away from
the power loops and be shielded with a ground trace to
prevent any noise coupling.
z Minimize the size of the Lx node and keep it wide and
shorter. Keep the Lx node away from the FB and analog
ground.
must be near the
SET
VDI
V
HYS
GND
t
D
Figure 8
V
DET+VHYS
V
DET
Min Operating Voltage
GND
RESET
Release Voltage
Detecting Voltage
z The power ground (PGND) consists input and output
capacitor grounds, the components' ground of charge
pump and GPM. The PGND should be wide and short
connected to a ground plane.
z The analog ground (AGND) consists the grounds of
compensation, soft-stat capacitor, FB divider, and OP
divider. The AGND should be separated from PGND and
connected to the ground of the input capacitor.
z The exposed pad of the chip should be connected to
ground plane for thermal consideration.
DS9913A/B-00 February 2006 www.richtek.com
17
RT9913A/B
Outline Dimension
Preliminary
D
E
A
A3
A1
D2
SEE DETAIL A
1
be
E2
L
1
2
1
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters Dimension s In Inches
Symbol
Min Max Min Max
A 0.800 1.000 0.031 0.039
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 3.950 4.050 0.156 0.159
D2 2.300 2.750 0.091 0.108
E 3.950 4.050 0.156 0.159
E2 2.300 2.750 0.091 0.108
e 0.500 0.020
L 0.350 0.450
RICHTEK TECHNOLOGY CORP .
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
0.014 0.018
V-Type 24L QFN 4x4 Package
RICHTEK TECHNOLOGY CORP .
Taipei Office (Marketing)
8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
18
DS9913A/B-00 February 2006www.richtek.com
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