Richtek RT9026GFP, RT9026GQW, RT9026GSP, RT9026PFP, RT9026PQW Schematic [ru]
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DDR Termination Regulator
RT9026
General Description
RT9026 is a 3A sink/source tracking termination regulator .
It is specifically designed for low-cost and low-external
component count systems. The RT9026 possesses a high
speed operating amplif ier that provides fa st load transient
response and only requires 20μF of ceramic output
capacitance. The RT9026 supports remote sensing
functions and all features required to power the DDRI/II/III
and low-power DDRIII/DDRIV VTT bus termination
according to the JEDEC specification. In addition, the
RT9026 includes integrated sleep-state controls pla cing
VTT in High-Z in S3 (suspend to RAM) and soft-off f or VTT
and VTTREF in S5 (shutdown). The RT9026 is available
in the thermal efficient package SOP-8 (Exposed Pad),
MSOP-10 (Exposed Pad) and WDFN-10L 3x3.
Applications
z DDRI/II/III and Low-Power DDRIII/DDRIV Memory
Termination
z SSTL-2, SSTL-18
z HSTL T ermination
Ordering Information
RT9026
Package Type
SP : SOP-8 (Exposed Pad-Option 1)
FP : MSOP-10 (Exposed Pad)
QW : WDFN-10L 3x3 (W-Type)
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Features
zz
Support DDRI, DDRII, DDRIII, Low-Power DDRIII and
z
zz
DDRIV Requirement
``
` Source/Sink 3A for DDRI and DDRII
``
``
` Source/Sink 2A for DDRIII
``
``
` Source/Sink 1.5A for Low-Power DDRIII
``
``
` Source/Sink 1.2A for Low-Power DDRIV
``
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z Input Voltage Range : 3.15V to 5.5V
zz
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z VLDOIN Voltage Range : 1.2V to 3.3V
zz
zz
z Requires Only 20
zz
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z Supports High-Z in S3 and Soft-Off in S5
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z Integrated Divider T racks 1/2 V DDQSNS for Both VTT
zz
μμ
μF Ceramic Output Capacitance
μμ
and VTTREF
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z Remote Sensing (VTTSNS)
zz
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z ±20mV Accuracy for VTT and VTTREF
zz
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z 10mA Buffered Reference (Sourcing/Sinking)
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(VTTREF)
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z Built-In Soft-Start
zz
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z Over Current Protection
zz
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z Thermal Shutdown Protection
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z SOP-8 (Exposed Pad), MSOP-10 (Exposed Pad) and
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10-Lead WDFN Package
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z RoHS Compliant and Halogen Free
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Pin Configurations
(TOP VIEW)
GND
GND
8
VTT
7
VLDOIN
6
5
10
9
8
7
6
VIN
VDDQSNS
VIN
S5
GND
S3
VTTREF
9
11
GND
2
S3
VTTSNS
VTTREF
3
4
SOP-8 (Exposed Pad)
VDDQSNS
VLDOIN
VTT
PGND
VTTSNS
2
3
4
5
MSOP-10 (Exposed Pad)
VDDQSNS
VLDOIN
VTT
PGND
VTTSNS
1
2
3
4
5
GND
10
VIN
9
S5
8
GND
7
S3
9
11
VTTREF
WDFN-10L 3x3
DS9026-06 August 2011 www.richtek.com
1
RT9026
Marking Information
RT9026PSP
RT9026PSP : Product Code
RT9026
PSPYMDNN
YMDNN : Date Code
RT9026PFP
A0-YM
DNN
A0- : Product Code
YMDNN : Date Code
RT9026GSP
RT9026GSP : Product Code
RT9026
YMDNN : Date Code
GSPYMDNN
RT9026PQW
E6- : Product Code
E6-YM
YMDNN : Date Code
DNN
RT9026GQW
E6= : Product Code
E6=YM
YMDNN : Date Code
DNN
Typical Application Circuit
RT9026
VLDOIN
3.3V or 5V
C1
10µF
C2
1µF
7
VLDOIN
5
6
VTTREF
VDDQSNS
VTTSNS
VIN
GND
1, 9 (Exposed Pad)
VTT
S3
4
3
8
2
S3
VTTREF
C3
0.1µF
VTT
C4
10µF x 2
RT9026GFP
A0=YM
DNN
VLDOIN
C1
10µF
VTT
C4
10µF x 2
A0= : Product Code
YMDNN : Date Code
RT9026
1
VDDQSNS
2
VLDOIN
3
VTT
5
VTTSNS
4
PGND
VIN
GND
VTTREF
S5
S3
10
8, 11 (Exposed Pad)
6
9
S5
7
S3
C3
0.1µF
3.3V or 5V
C2
1µF
VTTREF
Figure 1. For SOP-8 (Exposed Pad) Package Figure 2. For MSOP-10 (Exposed Pad) / WDFN-10L 3x3
Package
Functional Pin Description
Pin No.
RT9026□SP
1,
9 (Exposed Pad)
2 7 S3
3 5 VTTSNS
RT9026□FP
RT9026□QW
8,
11 (Exposed Pad)
Pin Name
GND
Ground. The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
Active Low Suspend to RAM Mode Control Pin, VTT is turned
off and left High-Z, VTTREF is active.
VTT Voltage Sense Input Pin. Connect to plus terminal of the
output capacitor.
2
Pin Function
To be Continued
DS9026-06 August 2011www.richtek.com
Pin No.
RT9026□SP
RT9026□FP
RT9026□QW
4 6 VTTREF
Pin Name
Buffered output that is a reference output, equal to
VDDQSNS/2.
5 1 VDDQSNS VLDOIN Sense Input Pin.
6 10 VIN Analog Input Pin (to control loop).
7 2 VLDOIN
8 3 VTT
Power supply of the VTT and VTTREF output stage (to power
MOS).
Output voltage for connection to termination resistors, equal to
VDDQSNS/2.
-- 4 PGND Power Ground of the VTT Output.
RT9026
Pin Function
-- 9 S5
Function Block Diagram
VDDQSNS
GND
VIN
+
VIN OK
-
S3
S5
2.32V/
2.2V
ENREF
Half DDQ
+
-
ENVTT
Active low shutdown control pin, both VTT and VTTREF are
turned off and discharged to ground.
VLDOIN
+
-
+
-
5V(10%)
+
+
-5V(10%)
ENREF
ENVTT
+
-
+
-
PGOOD
VTTREF
VTT
PGND
VTTSNS
Table 1. S3 and S5 Control Table
State S3 S5 VTT VREF
Normal High High
Standby Low High
Shutdown
Shutdown
DS9026-06 August 2011 www.richtek.com
Low Low 0V (Discharge) 0V (Discharge)
High Low 0V (Discharge) 0V (Discharge)
1.25V/0.9V/0.75V
/0.675V/0.6V
12mV/6mV
(High-Z)
1.25V/0.9V/0.75V
/0.675V/0.6V
1.25V/0.9V/0.75V
/0.675V/0.6V
3
RT9026
Supply
Absolute Maximum Ratings (Note 1)
l Supply Input Voltage, VIN----------------------------------------------------------------------------------------------6V
l Supply Input Voltage, VLDOIN, VDDQSNS------------------------------------------------------------------------3.6V
l Power Dissipation, P
SOP-8 (Exposed Pad)--------------------------------------------------------------------------------------------------1.333W
MSOP-10 (Exposed Pad)----------------------------------------------------------------------------------------------1.163W
WDFN-10L 3x3-----------------------------------------------------------------------------------------------------------1.429W
l Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA--------------------------------------------------------------------------------------------75°C/W
SOP-8 (Exposed Pad), θJC--------------------------------------------------------------------------------------------28°C/W
MSOP-10 (Exposed Pad), θJA----------------------------------------------------------------------------------------86°C/W
MSOP-10 (Exposed Pad), θJC----------------------------------------------------------------------------------------30°C/W
WDFN-10L 3x3, θJA------------------------------------------------------------------------------------------------------70°C/W
WDFN-10L 3x3, θJC-----------------------------------------------------------------------------------------------------8.2°C/W
l Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------------260°C
l Junction Temperature---------------------------------------------------------------------------------------------------150°C
l Storage Temperature Range------------------------------------------------------------------------------------------- −65°C to 150°C
l ESD Susceptibility (Note 3)
HBM (Human Body Mode)---------------------------------------------------------------------------------------------2kV
MM (Machine Mode)----------------------------------------------------------------------------------------------------200V
@ TA = 25°C
D
Recommended Operating Conditions (Note 4)
l Supply Input Voltage, VIN----------------------------------------------------------------------------------------------3.15V to 5.5V
l Supply Input Voltage, VLDOIN, VDDQSNS------------------------------------------------------------------------1.2V to 3.3V
l Junction Temperature Range------------------------------------------------------------------------------------------ −40°C to 125°C
l Ambient Temperature Range------------------------------------------------------------------------------------------ −40°C to 85°C
Electrical Characteristics
(VIN = 5V, VLDOIN = VDDQSNS = 2.5V, C1=10µF, C2=1µF, C3=0.1µF, C4=10µFx2, T
and RT9026PQW, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
VIN (to control loop)
Current
VIN Standby Current I
VIN Shutdown Current I
VLDOIN (to power MOS)
Supply Current
VLDOIN Standby Current I
VLDOIN Shutdown Current I
VDDQSNS Input Current I
VTTSNS Input Current I
I
VIN = 5V, No Load, S5 = S3 = 5V -- -- 2 mA
VIN
VIN = 5V, No Load, S5 = 5V, S3 = 0V -- -- 300 µA
VINSTB
VIN = 5V, No Load, S5 = S3 = 0V
VINSHDN
I
VLDOIN
VLDOINSTB
VLDOINSHDN
VDDQSNS
VTTSNS
(Only for RT9026PFP and RT9026PQW)
VIN = 5V, No Load, S5 = S3 = 5V -- -- 2 mA
VIN = 5V, No Load, S5 = 5V, S3 = 0V -- -- 10 µA
VIN = 5V, No Load, S5 = S3 = 0V -- -- 1 µA
VIN = 5V, S5 = S3 = 5V -- -- 50 µA
VIN = 5V, S5 = S3 = 5V -- -- 1 µA
VDDQSNS = VLDOIN = 2.5V -- 1.25
VTT Output Voltage VTT
VDDQSNS = VLDOIN = 1.8V -- 0.9 -VDDQSNS = VLDOIN = 1.5V -- 0.75
= 25°C, S5 function only for RT9026PFP
A
-- -- 1 µA
--
--
V
To be Continued
DS9026-06 August 2011www.richtek.com
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Parameter Symbol Test Conditions Min Typ Max Unit
= 2.5V/1.8V,
VTT Output Voltage VTT
VTTREF, VTT Output
Tolerance
VTT Source Current Limit I
V
VTTTOL
VTTOCLsr
RT9026
VDDQSNS = VLDOIN = 1.35V -- 0.675
VDDQSNS = VLDOIN = 1.2V -- 0.6 -VDDQSNS = VLDOIN =
2.5V/1.8V/1.5V/1.35V/1.2V,
∣I
∣= 0A
VTT
VDDQSNS = VLDOIN = 1.2V,
∣I
∣= 1.2A
VTT
−20
−30
-- 20
-- 30
VDDQSNS = VLDOIN =
2.5V/1.8V/1.5V/1.35V,
∣I
∣= 1.5A
VTT
VDDQSNS = VLDOIN
∣I
∣= 3A
VTT
−30
−40
-- 30
-- 40
VTT = 0V 3 4 -- A
-V
mV
VTT Sink Current Limit I
VTT Discharge Current I
VTTREF Output Voltage V
VDDQSNS/2, VTTREF
Output Voltage Tolerance
VTTREF Source Current Limit I
VTTOCLsk
DSCHRG
VTTREF
V
VTTREFTOL
VTTREFOCL
VTT = VDDQSNS 3 4 -- A
VDDQSNS = 0V, VTT = 1.25V,
S5 = S3 = 0V
V
VTTREF
V2
VDDQSNS
=
--
10 17 -- mA
1.25/0.9/
0.75/
-- V
0.675/0.6
VLDOIN = VDDQSNS =
2.5V/1.8V/1.5V/1.35V/1.2V,
I
VTTREF
V
VTTREF
< 10mA
= 0V 20 40 60 mA
−20 -- 20 mV
Rising -- -- 2.7
UVLO Threshold Voltage V
UVLO
V
Hysteresis -- 0.2 --
Logic-High VIH S5, S3 pin 1.6 -- --
Input Voltage
V
Logic-Low VIL S5, S3 pin -- -- 0.4
Logic Input Leakage Current I
S5, S3 pin -- -- 1 µA
ILK
Thermal Shutdown Protection TSD -- 160 -- °C
Thermal Shutdown Hysteresis ∆TSD -- 20 -- °C
Note 1. Stresses listed as the above “ Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four-layers thermal conductivity test board of
JEDEC 51-7 thermal measurement standard. The case point of θJC is on the exposed pad for SOP-8 (Exposed Pad)
, MSOP-10 (Exposed Pad) and WDFN-10L 3x3 package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
DS9026-06 August 2011 www.richtek.com
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