richtek RT8885A Datasheet
®
RT8885A
Dual Output 3-Phase + 2-Phase PWM Controller
and GPU Core Power Supply
General Description
The RT8885A is a dual output 3-phase + 2-phase PWM
controller with 3 integrated MOSFET gate drivers and a
single SVID interface for CPU and GPU core power supply.
This part complies with Intel VR12/IMVP7 Pulse Width
Modulation Specification. The RT8885A adopts G-NAVP
(Green-Native AVP), which is a Richtek proprietary topology
derived from finite DC gain compensator in constant on-
time control mode. G-NAVPTM makes this part an easy-
setting PWM controller to meet all Intel mobile CPU/GPU
AVP (Active Voltage Positioning) requirements. The
RT8885A uses SVID interface to control an internal 8-bit
DAC for output voltage programming. The built-in high
accuracy DAC converts the VID code to a reference voltage
ranging from 0V to 1.52V with 5mV step voltage. The
system accuracy of the controller reaches 0.8%. Each
output channel of the RT8885A can operate in multi-phase
continuous conduction mode or in single-phase diode
emulation mode to reach a maximum of 90% efficiency in
different load conditions. The droop function (load line) is
selectable and the load line is easily programmed by setting
the DC gain of the error amplifier. With proper
compensation, the load transient response can achieve
optimized AVP performance. The output voltage transition
slew rate is programmed via the SVID interface. The
RT8885A supports inductor DCR and sense-resistor
current sensing. This device provides power good
indication, current monitor, thermal monitor and thermal
throttling output signals for IMVP7 CPU and GPU core.
This part also provides complete fault protection functions
including over voltage, under voltage, negative voltage, over
current, thermal shutdown and under voltage lockout.
TM
Features
Dual Output : 3-Phase (CORE) + 2-Pha se (GFX)
Integrated MOSFET Drivers : 2 (CORE) + 1 (GFX)
VR12/IMVP7 PWM Specification Compliant
Serial VID Interface
G-NAV P
Fast Line/Load Transient Response
Quick Response for Load Transient
0.5% DAC Accuracy
0.8% System Accuracy
Accurate Current Balance
Selectable Droop Function
Selectable Forced DEM Operation
Built-in ADC for Platform Programming
Power Good Indicator
Current Monitor Output
Thermal Monitor
Thermal Throttling Indicator VRHOT
Phase Shedding in PS1
Phase Shedding and Diode Emulation in PS2
Differential Remote Output Voltage Sense
Lossless Inductor DCR Current Sense
Switching Frequency up to 1MHz per Phase
OVP, UVP, NVP, OCP, OTP, UVLO
56-Lead WQFN Package
RoHS Compliant and Halogen Free
TM
T opology
Applications
IMVP7 Intel CPU/CPU Core Power Supply
Laptop Computer
AVP Step-Down Converter
For CPU
Simplified Application Circuit
V
GFX
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
©
Buck A1
Buck A2
RT8885A
PWMA2 Driver Bus #2
SVID BusFrom CPU
DS8885A-01 January 2014 www.richtek.com
Driver Bus #1Driver Bus #A1
PWM3
Buck 1
Buck 2
Buck 3
V
CORE
1
RT8885A
Ordering Information
RT8885A
Package Type
QW : WQFN-56L 7x7 (W-Type)
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Pin Configurations
UGATEA
PHASEA
LGATEA
PWMA2
TONSETA
ISENA2P
ISENA2N
ISENA1P
ISENA1N
COMPA
FBA
RGNDA
IMONA
VSENA
VDIO
ALERT
VCLK
BOOTA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Marking Information
(TOP VIEW)
PVCC2
BOOT2
UGATE2
PHASE2
LGATE2
PGND
RT8885A
ZQW
YMDNN
PHASE1
PVCC1
LGATE1
454647484950515253545556
44 43
57
262524232221201918171615
27 28
BOOT1
UGATE1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RT8885AZQW : Product Number
YMDNN : Date Code
PWM3
TONSET
ISEN2P
ISEN2N
ISEN1N
ISEN1P
ISEN3P
ISEN3N
VSEN
COMP
FB
RGND
IMON
VREF/QRTH
EN
VCC
SET1
TSEN/ZLL
SET2
RSET/OFS
RSETA/OFSA
IBIAS
AGND
OCSET
VRHOT
VR_READY
VRA_READY
TSENA/ZLLA
WQFN-56L 7x7
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
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2
RT8885A
Functional Pin Description
Pin No. Pin Name Pin Function
1 PWMA2
2 TON SETA
3, 5 ISENA[2:1]P Positive Current Sense Input for Channel 2 and Channel 1 of GFX VR.
4, 6 ISENA[2:1]N
7 COMPA GFX VR Compensation Pin. This pin is the output of the error amplifier.
8 FBA
9 RGN DA
10 IMONA
11 VSENA
12 VDIO
13
14 VCLK
15 VRA_READ Y
16 VR_READY
17
18 IBIAS
19 TSENA/ZLLA
20 OCSET
21 AGND Analog Ground Pin.
22 TSEN/ZLL
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DS8885A-01 January 2014 www.richtek.com
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ALER T
VRHOT
GFX VR Channel 2 PWM Signal Output. Connect this pin to the PWM input
of external MOSFET driver for channel 2 of GFX VR.
GFX VR PWM On-Time Setting Pin. Connect this pin to input voltage VIN via
a resistor to set the ripple size of GFX VR output in CCM.
Negative Current Sense Input Pin for Channel 2 and Channel 1 of GFX VR.
ISENA2N can be pulled high to VCC to disable GFX VR channel 2. Connect
to this pin with a sense resistor of 680.
GFX VR Output Voltage Feedback Pin. Connect this pin to the CPU voltage
remote sense pin with a resistor. This pin is the inverting input node of the
error amplifier.
Return Ground for GFX VR. This pin is the inverting input node for differential
remote voltage sensing.
GFX VR Current Monitor Output. Connect a thermally compensated resistor
network from this pin to VREF/QRTH pin. IMONA pin output voltage V
is proportional to the total output current of GFX VR.
GFX VR Output Voltage Sensing Pin. Voltage on this pin is monitored for
voltage-related protections.
Data Transmission Line of SVID Interface. This pin has an open drain
structure. Pull high this pin to platform VCCIO rail with a resistor placed close
to controller.
Alert Line of the SVID Interface (Active Low). This pin has an open drain
structure. Pull high this pin to platform VCCIO rail with a resistor placed close
to controller.
Clock Signal Line of SVID Interface. This pin has an open drain structure. Pull
high VCLK to platform VCCIO rail with a resistor placed close to controller.
GFX VR Power Good Indicator Output. This pin has an open drain structure.
Pull high this pin to platform VCCIO rail with a resistor.
CORE VR Power Good Indicator Output. This pin has an open drain
structure. Pull high this pin to platform VCCIO rail with a resistor.
Thermal Throttling Output (Active Low). This pin has an open drain structure.
Pull high this pin to platform VCCIO rail with a resistor.
Internal Bias Current Setting Pin. Connect this pin to GND only with a 53.6k
resistor placed close to the controller.
This Pin Provides Two Functions for GFX VR : Thermal Monitor Input, and
Droop Enable/Disable Setting. Connect a thermally compensated resistive
voltage divider from VCC to GND and connect the joint of the voltage divider
to this pin.
CORE VR and GFX VR Over Current Protection Threshold Setting Pin.
Connect a resistive voltage divider from VCC to GND and connect the joint of
the voltage divider to this pin to set summed total over current protection
threshold and per phase over current protection threshold for CORE VR and
GFX VR individually.
This Pin Provides Two Functions for CORE VR : Thermal Monitor Input, and
Droop Enable/Disable Setting. Connect a thermally compensated resistive
voltage divider from VCC to GND and connect the joint of the voltage divider
to this pin.
IMONA
3
RT8885A
Pin No. Pin Name Pin Func ti on
This pin provides three settings for GFX VR : internal compensation ramp
23 RSETA/OFSA
24 RSET/OFS
25 SET2
26 SET1
27 VCC
28 EN Voltage Regulator Enable Signal Input.
29 VREF/QRTH
30 IMON
31 RGND
32 FB
33 COMP CORE VR Compensation Pin. This pin is the output of the error amplifier.
34 VSEN
35, 39, 38 ISEN[3:1]N
36, 40, 37 ISEN[3:1]P Positive current sense input for channel 3, 2 and 1 of CORE VR.
41 TONSET
42 PWM3
43 BOOT1
44 UGATE1
factor for control loop, output voltage offset and forced-DEM operation.
Connect a resistive voltage divider from VCC to GND and connect the joint
of the voltage divider to this pin.
This pin provides three settings for CORE VR : internal compensation
ramp factor for control loop, output voltage offset and forced-DEM
operation. Connect a resistive voltage divider from VCC to GND and
connect the joint of the voltage divider to this pin.
This pin provides three settings for GFX VR : initial startup voltage
V
INI_GFX
, maximum output current ICCMAXA and PWM on-time of quick
response for load transient response boost. Connect a resistive voltage
divider from VCC to GND, and connect the joint of the voltage divider to
this pin.
This pin provides three settings for CORE VR : Initial startup voltage
V
INI_CORE
, maximum output current ICCMAX and PWM on-time of quick
response for load transient response boost. Connect a resistive voltage
divider from VCC to GND and connect the joint of the voltage divider to
this pin.
Controller Power Supply Pin. Connect this pin to GND with a ceramic
capacitor larger than 1F.
This Pin Provides Two Functions : Fixed 0.6V Reference Voltage Output,
and Quick Response Trigger Threshold Setting. Connect a resistive
voltage divider from VCC to GND and connect the joint of the voltage
divider to this pin. Bypass this pin to GND with ceramic capacitor for noise
decoupling.
CORE VR Current Monitor Output. Connect a thermally compensated
resistor network from this pin to VREF/QRTH pin. IMON pin output voltage
V
is proportional to the total output current of CORE VR.
IMON
Return Ground for CORE VR. This pin is the inverting input node for
differential remote voltage sensing.
CORE VR Feedback Pin. This pin is the inverting input node of the error
amplifier.
CORE VR output voltage sensing pin. Voltage on this pin is monitored for
voltage related protections.
Negative Current Sense Input Pin for Channel 3, 2 and 1 of CORE VR.
ISENA2N and ISENA3N can be pulled high to VCC to disable CORE VR
channel 2 and channel 3, respectively. Connect to this pin with a sense
resistor of 680.
CORE VR PWM On-Time Setting Pin. Connect this pin to input voltage
VIN via a resistor to set the ripple size of CORE VR output in CCM.
CORE VR Channel 3 PWM Signal Output. Connect this pin to the PWM
input of external MOSFET driver for channel 3 of CORE VR.
CORE VR Channel 1 Bootstrap Flying Capacitor Connection Pin. This pin
powers channel 1 high side MOSFET drivers. Connect this pin to PHASE1
pin wi th a cer amic capacitor.
CORE VR Channel 1 High Side MOSFET Floating Gate Driver Output.
Connect this pin to the gate of high side MOSFET of channel 1.
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
4
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Pin No. Pin Name Pin Function
CORE VR Channel 1 Switching Node Connection Pin. Connect this pin to
45 PHASE1
46 LGATE1
47 PVCC1
48 LGATE2
49 PHASE2
50 UGATE2
51 BOOT2
52 PVCC2
53 LGATEA
54 PHASEA
55 UGATEA
56 BOOTA
57
(Exposed Pad)
PGND
the joint of high side MOSFET sources, the low side MOSFET drains and
the inductor of channel 1.
CORE VR Channel 1 Low Side MOSFET Gate Driver Output. Connect
this pin to the gate of low side MOSFET of channel 1.
CORE VR Embedded MOSFET Driver Power Supply Pin. This pin
powers channel 1 and channel 2 MOSFET gate drivers. Connect this pin
to GND with a ceramic capacitor larger than 1μF.
CORE VR Channel 2 Low Side MOSFET Gate Driver Output. Connect
this pin to the gate of low side MOSFET of channel 2.
CORE VR Channel 2 Switching Node Connection Pin. Connect this pin to
the joint of high side MOSFET sources, the low side MOSFET drains and
the inductor of channel 2.
CORE VR Channel 2 High Side MOSFET Floating Gate Driver Output.
Connect this pin to the gate of high side MOSFET of channel 2.
CORE VR Channel 2 Bootstrap Flying Capacitor Connection Pin. This pin
powers channel 2 high side MOSFET drivers. Connect this pin to
PHASE2 pin with a ceramic capacitor.
GFX VR Embedded MOSFET Driver Power Supply Pin. Connect this pin
to GND with a ceramic capacitor larger than 1F.
GFX VR Channel 1 Low Side MOSFET Gate Driver Output. Connect this
pin to the gate of low side MOSFET of channel 1.
GFX VR Channel 1 Switching Node Connection Pin. Connect this pin to
the joint of high side MOSFET sources, the low side MOSFET drains and
the inductor of channel 1.
GFX VR Channel 1 High Side MOSFET Floating Gate Driver Output.
Connect this pin to the gate of high side MOSFET of channel 1.
GFX VR Channel 1 Bootstrap Flying Capacitor Connection Pin. This pin
powers channel 1 high side MOSFET drivers. Connect this pin to
PHASEA pin with a ceramic capacitor.
Power Ground. The exposed pad is the return ground of all low side
MOSFET gate drivers. This exposed pad must be soldered to a large
PCB and connected to GND for maximum power dissipation.
RT8885A
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
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5
RT8885A
Function Block Diagram
AGND
VR_READY
PWMA2
BOOTA
UGATEA
PHASEA
PVCC2
LGATEA
TONSETA
ISENA1P
ISENA1N
ISENA2P
ISENA2N
TONSET
BOOT1
UGATE1
PHASE1
PVCC1
LGATE1
PGND
BOOT2
UGATE2
PHASE2
LGATE2
PWM3
VRA_READY
VCC
EN
ALERT
VDIO
VCLK
VRHOT
TSEN/ZLL
TSENA/ZLLA
RSETA/OFSA
RSET/OFS
OCSET
SET1
SET2
UVLO
Control & Protection Logic
SVID
ADC
XCVR
VQRTH VQRTHA
PWM
Offset
AMP
ERROR
+
CMP
+
Cancellation
-
Driver
TON
QR
-
+
Logic
Generator
Phase
Selector
CMP
+
-
VSENA
VQRTHA
+-+
SUM
To Protection Logic
Current
OCPOV/UV/NV
Logic
Driver
Balance
VSEN
IMON
Logic
Driver
TON
Generator
Phase
Selector
CMP
PWM
+
-
-
Current
Balance
QR
CMP
+
-
To Protection Logic
+
VQRTH
Offset
Cancellation
OCPOV/UV/NVIBIAS
AMP
ERROR
+
-
VSET
SUM
IMON
QRTH
VREF/
IMONA
Offset
Generator
Logic
From Control
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
©
DAC
RGNDA
VSETA
Rate Control
Soft-Start & Slew
FBA
COMPA
IMONA
VSENA
DAC
Rate Control
RGND
Soft-Start & Slew
+
-
+-+-+
FB
COMP
ISEN3P
ISEN2P
ISEN3N
ISEN1P
ISEN2N
-
0.6V
ISEN1N
From Control Logic
VREF/QRTH
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6
Operation
RT8885A
The RT8885A adopts G-NAVPTM (Green-Native AVP),
which is a Richtek proprietary topology derived from finite
DC gain compensator in constant on-time control mode.
G-NAVPTM is based on the finite gain peak current mode
with CCRCOT (Constant Current Ripple Constant On-Time)
topology. The control loop consists of PWM modulators
with power stages, current sense amplifiers and an error
amplifier as shown in functional block diagram. The
HS_FET on-time is determined by CCRCOT on-time
generator. Low offset current sense amplifiers are used
for current balance, loop control and over current detection.
By increasing the loading current, the current signal is
rose to increase the steady state COMP voltage, and then
the output voltage is decreased to achieving AVP.
A near-DC offset canceling is added to the output of EA to
eliminate the inherent output offset of finite gain peak
current mode controller. After EN go high, the internal ADC
sense pin setting for VINITAL, ICCMAX, over current
protection and internal compensation ramp setting. The
internal ADC also sense IMON and TSEN pin voltage for
INTEL reporting.
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DS8885A-01 January 2014 www.richtek.com
©
7
RT8885A
Table 1. VR12/IMVP7 Compliant VID Table
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H 1 H0 DAC Voltage (V)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0 0 0.000
1
0 1 0.250
0
0 2 0.255
1
0 3 0.260
0
0 4 0.265
1
0 5 0.270
0
0 6 0.275
1
0 7 0.280
0
0 8 0.285
1
0 9 0.290
0
0 A 0.295
1
0 B 0.300
0
0 C 0.305
1
0 D 0.310
0
0 E 0.315
1
0 F 0.320
0
1 0 0.325
1
1 1 0.330
0
1 2 0.335
1
1 3 0.340
0
1 4 0.345
1
1 5 0.350
0
1 6 0.355
1
1 7 0.360
0
1 8 0.365
1
1 9 0.370
0
1 A 0.375
1
1 B 0.380
0
1 C 0.385
1
1 D 0.390
0
1 E 0.395
1
1 F 0.400
0
2 0 0.405
1
2 1 0.410
0
2 2 0.415
1
2 3 0.420
0
2 4 0.425
1
2 5 0.430
0
2 6 0.435
1
2 7 0.440
0
2 8 0.445
1
2 9 0.450
0
2 A 0.455
1
2 B 0.460
0
2 C 0.465
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8
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RT8885A
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H 1 H0 DAC Voltage (V)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
2 D 0.470
0
2 E 0.475
1
2 F 0.480
0
3 0 0.485
1
3 1 0.490
0
3 2 0.495
1
3 3 0.500
0
3 4 0.505
1
3 5 0.510
0
3 6 0.515
1
3 7 0.520
0
3 8 0.525
1
3 9 0.530
0
3 A 0.535
1
3 B 0.540
0
3 C 0.545
1
3 D 0.550
0
3 E 0.555
1
3 F 0.560
0
4 0 0.565
1
4 1 0.570
0
4 2 0.575
1
4 3 0.580
0
4 4 0.585
1
4 5 0.590
0
4 6 0.595
1
4 7 0.600
0
4 8 0.605
1
4 9 0.610
0
4 A 0.615
1
4 B 0.620
0
4 C 0.625
1
4 D 0.630
0
4 E 0.635
1
4 F 0.640
0
5 0 0.645
1
5 1 0.650
0
5 2 0.655
1
5 3 0.660
0
5 4 0.665
1
5 5 0.670
0
5 6 0.675
1
5 7 0.680
0
5 8 0.685
1
5 9 0.690
0
5 A 0.695
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DS8885A-01 January 2014 www.richtek.com
©
9
RT8885A
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H 1 H0 DAC Voltage (V)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
5 B 0.700
0
5 C 0.705
1
5 D 0.710
0
5 E 0.715
1
5 F 0.720
0
6 0 0.725
1
6 1 0.730
0
6 2 0.735
1
6 3 0.740
0
6 4 0.745
1
6 5 0.750
0
6 6 0.755
1
6 7 0.760
0
6 8 0.765
1
6 9 0.770
0
6 A 0.775
1
6 B 0.780
0
6 C 0.785
1
6 D 0.790
0
6 E 0.795
1
6 F 0.800
0
7 0 0.805
1
7 1 0.810
0
7 2 0.815
1
7 3 0.820
0
7 4 0.825
1
7 5 0.830
0
7 6 0.835
1
7 7 0.840
0
7 8 0.845
1
7 9 0.850
0
7 A 0.855
1
7 B 0.860
0
7 C 0.865
1
7 D 0.870
0
7 E 0.875
1
7 F 0.880
0
8 0 0.885
1
8 1 0.890
0
8 2 0.895
1
8 3 0.900
0
8 4 0.905
1
8 5 0.910
0
8 6 0.915
1
8 7 0.920
0
8 8 0.925
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
10
©
DS8885A-01 January 2014www.richtek.com
RT8885A
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H 1 H0 DAC Voltage (V)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
8 9 0.930
0
8 A 0.935
1
8 B 0.940
0
8 C 0.945
1
8 D 0.950
0
8 E 0.955
1
8 F 0.960
0
9 0 0.965
1
9 1 0.970
0
9 2 0.975
1
9 3 0.980
0
9 4 0.985
1
9 5 0.990
0
9 6 0.995
1
9 7 1.000
0
9 8 1.005
1
9 9 1.010
0
9 A 1.015
1
9 B 1.020
0
9 C 1.025
1
9 D 1.030
0
9 E 1.035
1
9 F 1.040
0
A 0 1.045
1
A 1 1.050
0
A 2 1.055
1
A 3 1.060
0
A 4 1.065
1
A 5 1.070
0
A 6 1.075
1
A 7 1.080
0
A 8 1.085
1
A 9 1.090
0
A A 1.095
1
A B 1.100
0
A C 1.105
1
A D 1.110
0
A E 1.115
1
A F 1.120
0
B 0 1.125
1
B 1 1.130
0
B 2 1.135
1
B 3 1.140
0
B 4 1.145
1
B 5 1.150
0
B 6 1.155
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
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©
11
RT8885A
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage (V)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
0 B A 1.175
1
1 B B 1.180
0
0 B C 1.185
0
1 B D 1.190
1
0 B E 1.195
1
1 B F 1.200
0
0 C 0 1.205
0
1 C 1 1.210
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0 D 0 1.285
0
1 D 1 1.290
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
B 7 1.160
0
B 8 1.165
1
B 9 1.170
0
C 2 1.215
1
C 3 1.220
0
C 4 1.225
1
C 5 1.230
0
C 6 1.235
1
C 7 1.240
0
C 8 1.245
1
C 9 1.250
0
C A 1.255
1
C B 1.260
0
C C 1.265
1
C D 1.270
0
C E 1.275
1
C F 1.280
0
D 2 1.295
1
D 3 1.300
0
D 4 1.305
1
D 5 1.310
0
D 6 1.315
1
D 7 1.320
0
D 8 1.325
1
D 9 1.330
0
D A 1.335
1
D B 1.340
0
D C 1.345
1
D D 1.350
0
D E 1.355
1
D F 1.360
0
E 0 1.365
1
E 1 1.370
0
E 2 1.375
1
E 3 1.380
0
E 4 1.385
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
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RT8885A
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H 1 H0 DAC Voltage (V)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
E 5 1.390
0
E 6 1.395
1
E 7 1.400
0
E 8 1.405
1
E 9 1.410
0
E A 1.415
1
E B 1.420
0
E C 1.425
1
E D 1.430
0
E E 1.435
1
E F 1.440
0
F 0 1.445
1
F 1 1.450
0
F 2 1.455
1
F 3 1.460
0
F 4 1.465
1
F 5 1.470
0
F 6 1.475
1
F 7 1.480
0
F 8 1.485
1
F 9 1.490
0
F A 1.495
1
F B 1.500
0
F C 1.505
1
F D 1.510
0
F E 1.515
1
F F 1.520
Table 2. OCSET Pin Setting (Summed/Per Phase OCP) for CORE VR
CORE VR Per Phase Over
Current Protection (OCP)
Threshold I
PHOCP
(A)
CORE VR Total Summed
Current OCP (% of I
CCMAX
)
ADC Code
PHOC_CTRL [2:0]
OCSET Pin Voltage Before
Current Injection V
OCSET
120 52.5
128 87.5
136 122.5
10
144 157.5
000
152 192.5
160 227.5
Disable
262.5
120 332.5
128 367.5
136 402.5
15
144 437.5
001
152 472.5
160 507.5
Disable
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DS8885A-01 January 2014 www.richtek.com
©
542.5
13
RT8885A
CORE VR Per Phase Over
Current Protection (OCP)
Threshold I
PHOCP
(A)
22.5
33.8
50.6
75.9
113.9
170.9
CORE VR Total Summed
Current OCP (% of I
CCMAX
120 612.5
128 647.5
136 682.5
144 717.5
152 572.5
160 787.5
Disable
120 892.5
128 927.5
136 962.5
144 997.5
152 1032.5
160 1067.5
Disable
120 1172.5
128 1207.5
136 1242.5
144 1277.5
152 1312.5
160 1347.5
Disable
120 1452.5
128 1487.5
136 1522.5
144 1557.5
152 1592.5
160 1627.5
Disable
120 1732.5
128 1767.5
136 1802.5
144 1837.5
152 1872.5
160 1907.5
Disable
120 2012.5
128 2047.5
136 2082.5
144 2117.5
152 2152.5
160 2187.5
Disable
ADC Code
)
PHOC_CTRL [2:0]
010
011
100
101
110
111
OCSET Pin Voltage Before
Current Injection V
OCSET
822.5
1102.5
1382.5
1662.5
1942.5
2222.5
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
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Table 2. OCSET Pin Setting (Summed/Per Phase OCP) for GFX VR
GFX VR Per Phase Over
Current Protection (OCP)
Threshold I
PHOCPA
(A)
170.9
113.9
75.9
50.6
33.8
22.5
GFX VR Total Summed
Current OCP (% of I
120 52.5
128 87.5
136 122.5
144 157.5
152 192.5
160 227.5
Disable
120 332.5
128 367.5
136 402.5
144 437.5
152 472.5
160 507.5
Disable
120 612.5
128 647.5
136 682.5
144 717.5
152 572.5
160 787.5
Disable
120 892.5
128 927.5
136 962.5
144 997.5
152 1032.5
160 1067.5
Disable
120 1172.5
128 1207.5
136 1242.5
144 1277.5
152 1312.5
160 1347.5
Disable
120 1452.5
128 1487.5
136 1522.5
144 1557.5
152 1592.5
160 1627.5
Disable
CCMAXA
ADC Cod e
)
PHOC_CTRL [2:0]
111
110
101
100
011
010
RT8885A
OCSET Pin Voltage Difference
V
OCSET
Current Injection) (mV)
(Before and After
262.5
542.5
822.5
1102.5
1382.5
1662.5
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©
15
RT8885A
GFX VR Per Phase Over
Current Protection (OCP)
Threshold I
PHOCPA
(A)
15
10
CORE VR Initial
Maximum Output Current
Startup Voltage
V
INI_CORE
(V)
0
0.9
GFX VR Total Summed
Current OCP (% of I
120 1732.5
128 1767.5
136 1802.5
144 1837.5
152 1872.5
160 1907.5
Disable
120 2012.5
128 2047.5
136 2082.5
144 2117.5
152 2152.5
160 2187.5
Disable
Table 3. SET1 Pin Setting (V
CCMAX
for 3 Phase
I
Operation (A)
40 40 52.5
50 45 87.5
60 50 122.5
70 55 157.5
75 60 192.5
80 65 227.5
85 70 262.5
90 75 297.5
95 80 332.5
100 85 367.5
105 90 402.5
110 100 437.5
115 110 472.5
120 120 507.5
40 40 612.5
50 45 647.5
60 50 682.5
70 55 717.5
75 60 752.5
80 65 787.5
85 70 822.5
90 75 857.5
95 80 892.5
100 85 927.5
105 90 962.5
110 100 997.5
115 110 1032.5
120 120 1067.5
ADC Code
)
CCMAXA
PHOC_CTRL [2:0]
001
000
INI_CORE
and I
Maximum Output Current
I
CCMAX
for 2/1 Phase
Operation* (A)
OCSET Pin Voltage Difference
V
OCSET
(Before and After
Current Injection) (mV)
1942.5
2222.5
)
CCMAX
SET1 Pin Voltage Difference
V
(Before and Af ter
SET1
Current Injection) (mV)
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
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RT8885A
CORE VR Initial
Startup Voltage
V
INI_CORE
(V)
Maximum Output Current
CCMAX
for 3 Phase
I
Operation (A)
Maximum Output Current
I
for 2/1 Phase
CCMAX
Operation* (A)
40 40 1172.5
50 45 1207.5
60 50 1242.5
70 55 1277.5
75 60 1312.5
80 65 1347.5
1
85 70 1382.5
90 75 1417.5
95 80 1452.5
100 85 1487.5
105 90 1522.5
110 100 1557.5
115 110 1592.5
120 120 1627.5
40 40 1732.5
50 45 1767.5
60 50 1802.5
70 55 1837.5
75 60 1872.5
80 65 1907.5
1.1
85 70 1942.5
90 75 1977.5
95 80 2012.5
100 85 2047.5
105 90 2082.5
110 100 2117.5
115 110 2152.5
120 120 2187.5
* Pull high ISEN2N or ISEN3N to VCC to disable channel 2 or channel 3.
SET1 Pin Voltage Difference
V
(Before and After
SET1
Current Injection) (mV)
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©
17
RT8885A
GFX VR
Initial Startup
Voltage
V
INI_GFX
(V)
0
0.9
Maximum
Output
Current
I
CCMAXA
Table 4. SET2 Pin Setting (V
SET2 Pin Voltage
Difference V
(Before and Af ter
(A)
Current Injection) (mV)
SET2
Initial Startup
V
and I
INI_GFX
GFX VR
Voltage
INI_GFX
(V)
CCMAXA
Maximum
Output
Current
I
CCMAXA
)
SET2 Pin Voltage
Difference V
SET2
(Before and Af ter
(A)
Current Injection) (mV)
15 52.5 15 1172.5
20 87.5 20 1207.5
25 122.5 25 1242.5
30 157.5 30 1277.5
35 192.5 35 1312.5
40 227.5 40 1347.5
45 262.5 45 1382.5
50 297.5 50 1417.5
1
55 332.5 55 1452.5
60 367.5 60 1487.5
65 402.5 65 1522.5
70 437.5 70 1557.5
75 472.5 75 1592.5
80 507.5
80 1627.5
15 612.5 15 1732.5
20 647.5 20 1767.5
25 682.5 25 1802.5
30 717.5 30 1837.5
35 752.5 35 1872.5
40 787.5 40 1907.5
45 822.5 45 1942.5
50 857.5 50 1977.5
1.1
55 892.5 55 2012.5
60 927.5 60 2047.5
65 962.5 65 2082.5
70 997.5 70 2117.5
75 1032.5 75 2152.5
80 1067.5
80 2187.5
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