Richtek RT8884B User Manual

RT8884B

Multi-Phase PWM Controller for CPU Core Power Supply

General Description

The RT8884B is a 4/3/2/1 multi-phase synchronous Buck

controller designed to meet Intel VR12.5 compatible CPU

specification with a serial VID control interface. The

RT8884B adopts G-NAVP

Richtek's proprietary topology derived from finite DC gain

of EA amplifier with current mode control, making it easy

to set the droop to meet all Intel CPU requirements of

AVP (Adaptive Voltage Positioning). Based on the G-

NAVPTM topology, the RT8884B also features a quick

response mechanism for optimized AVP performance

during load transient. The RT8884B supports mode

transition function with various operating states. A Serial

VID (SVID) interface is built in the RT8884B to

communicate with Intel VR12.5 compliant CPU. The

RT8884B supports VID on-the-fly function with three

different slew rates : Fast, Slow and Decay. By utilizing

the G-NAVPTM topology, the operating frequency of the

RT8884B varies with VID, load current and input voltage

to further enhance the efficiency even in CCM. Besides

G-NAVPTM, the CCRCOT (Constant Current Ripple

Constant On Time) technology provides superior output

voltage ripple over the entire input/output range.

(Green Native AVP) which is

Features



Intel VR12.5 Serial VID Interface Compatible





 4/3/2/1 Phase PWM Controller



 G-NAV P



 0.5% DAC Accuracy



 Differential Remote Voltage Sensing



 Built-in ADC for Platform Programming



 Accurate Current Balance



 System Thermal Compensated AVP



 Diode Emulation Mode at Light Load Condition for



T opology

Single Phase Operation



 Fast T ran sient Respon se



 VR Ready Indicator



 Thermal Throttling



 Current Monitor Output



 OVP, UVP, OCP, NVP, UVLO



 External No-Load Offset Setting



 DVID Enhancement



 Small 32-Lead WQFN Package



 RoHS Compliant and Halogen Free



Applications

 VR12.5 Intel Core Power Supply

 Notebook/Desktop Computer/Servers Multi-phase CPU

Core Power Supply

 AVP Step-Down Converter

Simplified Application Circuit

RT8884B

To PCH

VR_RDY

VR_HOT

To CPU

VCLK

VDIO

ALERT

PWM1

PWM2

PWM3

PWM4

DS8884B-01 September 2013 www.richtek.com

RT9624A

CORE

RT8884B

Ordering Information

RT8884B

Package Type QW : WQFN-32L 4x4 (W-Type)

Lead Plating System G : Green (Halogen Free and Pb Free)

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Pin Configurations

(TOP VIEW)

ISEN2N

ISEN2PENPWM2

31 30 29 28

ISEN1P ISEN3P ISEN3N ISEN4N ISEN4P

COMP TSEN

IMON

VREF VR_HOT

10 11 12 13

GND

DVD

VR_RDY

TONSET

VCLK

ALERT

152616

VDIO

Marking Information

0F= : Product Code

0F=YM

DNN

YMDNN : Date Code

FB ISEN1N

VCC

SET2 PWM1

SET3 PWM3

SET1

VSEN

RGND

WQFN-32L 4x4

IBIAS PWM4

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Functional Pin Description

Pin No. Pin Name Pin Function

1, 30, 2, 5 ISEN [1:4] P Positive Current Sense Inputs of Channel 1, 2, 3 and 4.

32, 31, 3, 4 ISEN [1:4] N Negat ive Curre nt Sense Inputs of Chan nel 1, 2, 3 and 4 .

RT8884B

6 IMON

7 VREF

8 COMP CORE VR Compensation. This pin is an erro r amplifier output pin .

9 FB

10 VSEN

11 R G N D

12 VCC

13 SET1

14 SET2

15 SET3

CPU CORE Current Monitor Outpu t. This pin outputs a voltage proportion al to the output curre nt.

Fixed 0. 6V Output Ref erence Voltage. T his voltage is only used to offset th e output voltage of IMON pin. Connect a 0.47μF decoupling capacitor between this pi n a nd GND.

Negative Input of the Error Amplif ier. This pin is for output voltag e fee dba ck to controller.

VR Voltage Sense Input . This pin is connected to the terminal of VR output voltage .

Return Ground for VR. Th is pin is the negative node of the di fferential rem o te voltage se nsing.

Contro lle r Power Supply. Connect this pin to 5V and place a minimum 2.2μF decoup lin g capacitor. The decoupling capacito r should be pl aced to th is pin as close as possible.

Platform Setting. Platform can use this pin to set DVID time, RSET, DVID

width and OCS.

Platform Setting. Platform can use this p in t o set ICCMAX, QRTH and

QRSET.

Platform Setting. Platform can use this to set output offset voltage.

Internal B ias Current Setting. Connect a 100kΩ resistor from this pin to GND for

16 IBIAS

17 TSEN Thermal Sense Input fo r CORE VR.

19 VDIO VR and CPU Data Transmission In terface.

21 VCLK Synchronous Clock from the CPU.

22 TONSET

23 VR_RDY VR Ready Indicator.

24 DVD

27, 28, 26, 25 PWM [1:4] PWM Outputs for Channel 1, 2, 3 and 4.

29 EN VR Enable.

(Exposed Pad)

VR_HOT

ALERT

GND

setting the internal current. Don ’t conn ect a bypass capacit or from this pin to GND.

Thermal Monitor Output. ( Active low).

SVID Alert. (Active low)

On-time Setting. An on-time setting resistor is connected from this pin to input voltage .

Divided Input Voltage Detec tio n of CORE VR. Connect this pin to a vo ltag e divide r from input voltage of power stage to det ect in put voltag e.

Ground. The exposed p ad must be soldered to a la rge PCB and connec ted to GND for maximum power dissipation.

DS8884B-01 September 2013 www.richtek.com

RT8884B

Function Block Diagram

SET2

SET1

SET3

TSEN

DVD

VCLK

VDIO

ALERT

VR_HOT

IMONI

VCC

VSEN

VR_RDY

IBIAS

RGND

COMP

ISEN1P ISEN1N

ISEN2P

ISEN2N

ISEN3P

ISEN3N

ISEN4P

ISEN4N

From Control Logic

DAC

DVID_TH, DVID_WTH

Soft-Start & Slew

Rate Control

MUX

ADC

VSET

Current mirror

IB1

Current mirror

IB2

Current mirror

IB3

Current mirror

IB4

ERROR

AMP

SVID Interface

Configuration Registers

Control Logic

Offset

Cancellation

IMON Filter IMONI

OCS

UVLO

TON, QR_TH QRWIDTH

DVID_TH, DVID_WTH

RSETOCS

1/2

To Protection Logic

RSET

Loop Control

Protection Logic

PWM

CMP

QR_TH

QRWIDTH

Current Balance

To Protection Logic

TON GEN

IB4IB3IB1 IB2

OCP

GND

TONSET

PWM1

PWM2

PWM3

PWM4

VSEN

IMON VREF

OVP/UVP/NVP

DS8884B-01 September 2013www.richtek.com

Operation

The RT8884B adopts G-NAVPTM (Green Native AVP) which

is Richtek's proprietary topology derived from finite DC

gain of EA amplifier with current mode control, making it

easy to set the droop to meet all Intel CPU requirements

of AVP (Adaptive Voltage Positioning).

The RT8884B adopts the G-NAVPTM controller, which is

one type of current mode constant on-time control with

DC offset cancellation. The approach can not only improve

DC offset problem for increasing system accuracy but also

provide fast transient response. For the RT8884B, when

current feedback signal reaches COMP signal to generate

an on-time width to achieve PWM modulation.

TON GEN

Generate the PWM1 to PWM4 sequentially according to

the phase control signal from the Loop Control Protection

Logic.

SVID Interface/Configuration Registers/Control Logic

The interface that receives the SVID signal from CPU and

sends the relative signals to Loop Control Protection Logic

to execute the action by CPU.

RT8884B

Loop Control Protection Logic

It controls the power on sequence, the protection behavior,

and the operational phase number.

Current Balance

Each phase current sense signal is sent to the current

balance circuit which adjusts the on-time of each phase

to optimize current sharing.

Offset Cancellation

Cancel the current/voltage ripple issue to get the accurate

VSEN.

UVLO

Detect the DVD and VCC voltage and issue POR signal as

they are high enough.

DAC

Generate an analog signal according to the digital code

generated by Control Logic.

Soft-Start & Slew Rate Control

Control the Dynamic VID slew rate of VSET according to

the SetVID fast or SetVID slow.

The registers save the pin setting data from ADC output.

The Control Logic controls the ADC timing and generates

the digital code of the VID that is relative to VSEN.

DS8884B-01 September 2013 www.richtek.com

RT8884B

Table 1. VR12.5 VID Code Table

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)

0 0 0 0 0 0 0 0 00 0.000

0 0 0 0 0 0 0 1 01 0.500

0 0 0 0 0 0 1 0 02 0.510

0 0 0 0 0 0 1 1 03 0.520

0 0 0 0 0 1 0 0 04 0.530

0 0 0 0 0 1 0 1 05 0.540

0 0 0 0 0 1 1 0 06 0.550

0 0 0 0 0 1 1 1 07 0.560

0 0 0 0 1 0 0 0 08 0.570

0 0 0 0 1 0 0 1 09 0.580

0 0 0 0 1 0 1 0 0A 0.590

0 0 0 0 1 0 1 1 0B 0.600

0 0 0 0 1 1 0 0 0C 0.610

0 0 0 0 1 1 0 1 0D 0.620

0 0 0 0 1 1 1 0 0E 0.630

0 0 0 0 1 1 1 1 0F 0.640

0 0 0 1 0 0 0 0 10 0.650

0 0 0 1 0 0 0 1 11 0.660

0 0 0 1 0 0 1 0 12 0.670

0 0 0 1 0 0 1 1 13 0.680

0 0 0 1 0 1 0 0 14 0.690

0 0 0 1 0 1 0 1 15 0.700

0 0 0 1 0 1 1 0 16 0.710

0 0 0 1 0 1 1 1 17 0.720

0 0 0 1 1 0 0 0 18 0.730

0 0 0 1 1 0 0 1 19 0.740

0 0 0 1 1 0 1 0 1A 0.750

0 0 0 1 1 0 1 1 1B 0.760

0 0 0 1 1 1 0 0 1C 0.770

0 0 0 1 1 1 0 1 1D 0.780

0 0 0 1 1 1 1 0 1E 0.790

0 0 0 1 1 1 1 1 1F 0.800

0 0 1 0 0 0 0 0 20 0.810

0 0 1 0 0 0 0 1 21 0.820

0 0 1 0 0 0 1 0 22 0.830

0 0 1 0 0 0 1 1 23 0.840

0 0 1 0 0 1 0 0 24 0.850

0 0 1 0 0 1 0 1 25 0.860

0 0 1 0 0 1 1 0 26 0.870

0 0 1 0 0 1 1 1 27 0.880

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RT8884B

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)

0 0 1 0 1 0 0 0 28 0.890

0 0 1 0 1 0 0 1 29 0.900

0 0 1 0 1 0 1 0 2A 0.910

0 0 1 0 1 0 1 1 2B 0.920

0 0 1 0 1 1 0 0 2C 0.930

0 0 1 0 1 1 0 1 2D 0.940

0 0 1 0 1 1 1 0 2E 0.950

0 0 1 0 1 1 1 1 2F 0.960

0 0 1 1 0 0 0 0 30 0.970

0 0 1 1 0 0 0 1 31 0.980

0 0 1 1 0 0 1 0 32 0.990

0 0 1 1 0 0 1 1 33 1.000

0 0 1 1 0 1 0 0 34 1.010

0 0 1 1 0 1 0 1 35 1.020

0 0 1 1 0 1 1 0 36 1.030

0 0 1 1 0 1 1 1 37 1.040

0 0 1 1 1 0 0 0 38 1.050

0 0 1 1 1 0 0 1 39 1.060

0 0 1 1 1 0 1 0 3A 1.070

0 0 1 1 1 0 1 1 3B 1.080

0 0 1 1 1 1 0 0 3C 1.090

0 0 1 1 1 1 0 1 3D 1.100

0 0 1 1 1 1 1 0 3E 1.110

0 0 1 1 1 1 1 1 3F 1.120

0 1 0 0 0 0 0 0 40 1.130

0 1 0 0 0 0 0 1 41 1.140

0 1 0 0 0 0 1 0 42 1.150

0 1 0 0 0 0 1 1 43 1.160

0 1 0 0 0 1 0 0 44 1.170

0 1 0 0 0 1 0 1 45 1.180

0 1 0 0 0 1 1 0 46 1.190

0 1 0 0 0 1 1 1 47 1.200

0 1 0 0 1 0 0 0 48 1.210

0 1 0 0 1 0 0 1 49 1.220

0 1 0 0 1 0 1 0 4A 1.230

0 1 0 0 1 0 1 1 4B 1.240

0 1 0 0 1 1 0 0 4C 1.250

0 1 0 0 1 1 0 1 4D 1.260

0 1 0 0 1 1 1 0 4E 1.270

0 1 0 0 1 1 1 1 4F 1.280

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RT8884B

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)

0 1 0 1 0 0 0 0 50 1.290

0 1 0 1 0 0 0 1 51 1.300

0 1 0 1 0 0 1 0 52 1.310

0 1 0 1 0 0 1 1 53 1.320

0 1 0 1 0 1 0 0 54 1.330

0 1 0 1 0 1 0 1 55 1.340

0 1 0 1 0 1 1 0 56 1.350

0 1 0 1 0 1 1 1 57 1.360

0 1 0 1 1 0 0 0 58 1.370

0 1 0 1 1 0 0 1 59 1.380

0 1 0 1 1 0 1 0 5A 1.390

0 1 0 1 1 0 1 1 5B 1.400

0 1 0 1 1 1 0 0 5C 1.410

0 1 0 1 1 1 0 1 5D 1.420

0 1 0 1 1 1 1 0 5E 1.430

0 1 0 1 1 1 1 1 5F 1.440

0 1 1 0 0 0 0 0 60 1.450

0 1 1 0 0 0 0 1 61 1.460

0 1 1 0 0 0 1 0 62 1.470

0 1 1 0 0 0 1 1 63 1.480

0 1 1 0 0 1 0 0 64 1.490

0 1 1 0 0 1 0 1 65 1.500

0 1 1 0 0 1 1 0 66 1.510

0 1 1 0 0 1 1 1 67 1.520

0 1 1 0 1 0 0 0 68 1.530

0 1 1 0 1 0 0 1 69 1.540

0 1 1 0 1 0 1 0 6A 1.550

0 1 1 0 1 0 1 1 6B 1.560

0 1 1 0 1 1 0 0 6C 1.570

0 1 1 0 1 1 0 1 6D 1.580

0 1 1 0 1 1 1 0 6E 1.590

0 1 1 0 1 1 1 1 6F 1.600

0 1 1 1 0 0 0 0 70 1.610

0 1 1 1 0 0 0 1 71 1.620

0 1 1 1 0 0 1 0 72 1.630

0 1 1 1 0 0 1 1 73 1.640

0 1 1 1 0 1 0 0 74 1.650

0 1 1 1 0 1 0 1 75 1.660

0 1 1 1 0 1 1 0 76 1.670

0 1 1 1 0 1 1 1 77 1.680

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RT8884B

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)

0 1 1 1 1 0 0 0 78 1.690

0 1 1 1 1 0 0 1 79 1.700

0 1 1 1 1 0 1 0 7A 1.710

0 1 1 1 1 0 1 1 7B 1.720

0 1 1 1 1 1 0 0 7C 1.730

0 1 1 1 1 1 0 1 7D 1.740

0 1 1 1 1 1 1 0 7E 1.750

0 1 1 1 1 1 1 1 7F 1.760

1 0 0 0 0 0 0 0 80 1.770

1 0 0 0 0 0 0 1 81 1.780

1 0 0 0 0 0 1 0 82 1.790

1 0 0 0 0 0 1 1 83 1.800

1 0 0 0 0 1 0 0 84 1.810

1 0 0 0 0 1 0 1 85 1.820

1 0 0 0 0 1 1 0 86 1.830

1 0 0 0 0 1 1 1 87 1.840

1 0 0 0 1 0 0 0 88 1.850

1 0 0 0 1 0 0 1 89 1.860

1 0 0 0 1 0 1 0 8A 1.870

1 0 0 0 1 0 1 1 8B 1.880

1 0 0 0 1 1 0 0 8C 1.890

1 0 0 0 1 1 0 1 8D 1.900

1 0 0 0 1 1 1 0 8E 1.910

1 0 0 0 1 1 1 1 8F 1.920

1 0 0 1 0 0 0 0 90 1.930

1 0 0 1 0 0 0 1 91 1.940

1 0 0 1 0 0 1 0 92 1.950

1 0 0 1 0 0 1 1 93 1.960

1 0 0 1 0 1 0 0 94 1.970

1 0 0 1 0 1 0 1 95 1.980

1 0 0 1 0 1 1 0 96 1.990

1 0 0 1 0 1 1 1 97 2.000

1 0 0 1 1 0 0 0 98 2.010

1 0 0 1 1 0 0 1 99 2.020

1 0 0 1 1 0 1 0 9A 2.030

1 0 0 1 1 0 1 1 9B 2.040

1 0 0 1 1 1 0 0 9C 2.050

1 0 0 1 1 1 0 1 9D 2.060

1 0 0 1 1 1 1 0 9E 2.070

1 0 0 1 1 1 1 1 9F 2.080

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RT8884B

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)

1 0 1 0 0 0 0 0 A0 2.090

1 0 1 0 0 0 0 1 A1 2.100

1 0 1 0 0 0 1 0 A2 2.110

1 0 1 0 0 0 1 1 A3 2.120

1 0 1 0 0 1 0 0 A4 2.130

1 0 1 0 0 1 0 1 A5 2.140

1 0 1 0 0 1 1 0 A6 2.150

1 0 1 0 0 1 1 1 A7 2.160

1 0 1 0 1 0 0 0 A8 2.170

1 0 1 0 1 0 0 1 A9 2.180

1 0 1 0 1 0 1 0 AA 2.190

1 0 1 0 1 0 1 1 AB 2.200

1 0 1 0 1 1 0 0 AC 2.210

1 0 1 0 1 1 0 1 AD 2.220

1 0 1 0 1 1 1 0 AE 2.230

1 0 1 0 1 1 1 1 AF 2.240

1 0 1 1 0 0 0 0 B0 2.250

1 0 1 1 0 0 0 1 B1 2.260

1 0 1 1 0 0 1 0 B2 2.270

1 0 1 1 0 0 1 1 B3 2.280

1 0 1 1 0 1 0 0 B4 2.290

1 0 1 1 0 1 0 1 B5 2.300

1 0 1 1 0 1 1 0 B6 2.310

1 0 1 1 0 1 1 1 B7 2.320

1 0 1 1 1 0 0 0 B8 2.330

1 0 1 1 1 0 0 1 B9 2.340

1 0 1 1 1 0 1 0 BA 2.350

1 0 1 1 1 0 1 1 BB 2.360

1 0 1 1 1 1 0 0 BC 2.370

1 0 1 1 1 1 0 1 BD 2.380

1 0 1 1 1 1 1 0 BE 2.390

1 0 1 1 1 1 1 1 BF 2.400

1 1 0 0 0 0 0 0 C0 2.410

1 1 0 0 0 0 0 1 C1 2.420

1 1 0 0 0 0 1 0 C2 2.430

1 1 0 0 0 0 1 1 C3 2.440

1 1 0 0 0 1 0 0 C4 2.450

1 1 0 0 0 1 0 1 C5 2.460

1 1 0 0 0 1 1 0 C6 2.470

1 1 0 0 0 1 1 1 C7 2.480

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RT8884B

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)

1 1 0 0 1 0 0 0 C8 2.490

1 1 0 0 1 0 0 1 C9 2.500

1 1 0 0 1 0 1 0 CA 2.510

1 1 0 0 1 0 1 1 CB 2.520

1 1 0 0 1 1 0 0 CC 2.530

1 1 0 0 1 1 0 1 CD 2.540

1 1 0 0 1 1 1 0 CE 2.550

1 1 0 0 1 1 1 1 CF 2.560

1 1 0 1 0 0 0 0 D0 2.570

1 1 0 1 0 0 0 1 D1 2.580

1 1 0 1 0 0 1 0 D2 2.590

1 1 0 1 0 0 1 1 D3 2.600

1 1 0 1 0 1 0 0 D4 2.610

1 1 0 1 0 1 0 1 D5 2.620

1 1 0 1 0 1 1 0 D6 2.630

1 1 0 1 0 1 1 1 D7 2.640

1 1 0 1 1 0 0 0 D8 2.650

1 1 0 1 1 0 0 1 D9 2.660

1 1 0 1 1 0 1 0 DA 2.670

1 1 0 1 1 0 1 1 DB 2.680

1 1 0 1 1 1 0 0 DC 2.690

1 1 0 1 1 1 0 1 DD 2.700

1 1 0 1 1 1 1 0 DE 2.710

1 1 0 1 1 1 1 1 DF 2.720

1 1 1 0 0 0 0 0 E0 2.730

1 1 1 0 0 0 0 1 E1 2.740

1 1 1 0 0 0 1 0 E2 2.750

1 1 1 0 0 0 1 1 E3 2.760

1 1 1 0 0 1 0 0 E4 2.770

1 1 1 0 0 1 0 1 E5 2.780

1 1 1 0 0 1 1 0 E6 2.790

1 1 1 0 0 1 1 1 E7 2.800

1 1 1 0 1 0 0 0 E8 2.810

1 1 1 0 1 0 0 1 E9 2.820

1 1 1 0 1 0 1 0 EA 2.830

1 1 1 0 1 0 1 1 EB 2.840

1 1 1 0 1 1 0 0 EC 2.850

1 1 1 0 1 1 0 1 ED 2.860

1 1 1 0 1 1 1 0 EE 2.870

1 1 1 0 1 1 1 1 EF 2.880

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RT8884B

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)

1 1 1 1 0 0 0 0 F0 2.890

1 1 1 1 0 0 0 1 F1 2.900

1 1 1 1 0 0 1 0 F2 2.910

1 1 1 1 0 0 1 1 F3 2.920

1 1 1 1 0 1 0 0 F4 2.930

1 1 1 1 0 1 0 1 F5 2.940

1 1 1 1 0 1 1 0 F6 2.950

1 1 1 1 0 1 1 1 F7 2.960

1 1 1 1 1 0 0 0 F8 2.970

1 1 1 1 1 0 0 1 F9 2.980

1 1 1 1 1 0 1 0 FA 2.990

1 1 1 1 1 0 1 1 FB 3.000

1 1 1 1 1 1 0 0 FC 3.010

1 1 1 1 1 1 0 1 FD 3.020

1 1 1 1 1 1 1 0 FE 3.030

1 1 1 1 1 1 1 1 FF 3.040

DS8884B-01 September 2013www.richtek.com

Table 2. Standard Serial VID Commands

RT8884B

Master

Code Commands

00h not supported N/A N/A N/A

01h SetVID_Fast VID code N/A

02h SetVID_Slow VID code N/A

03h SetVID_Decay VID code N/A

04h SetPS

Payload

Contents

Byte

indicating

power states

Slave

Payload

Contents

N/A

1. Set new target VID code, VR jumps to new VID target

with controlled default “fast” slew rate 12.5mV/μs.

2. Set VR_Settled when VR reaches target VID voltage.

1. Set new target VID code, VR jumps to new VID target

with controlled default “slow” slew rate 3.125mV/μs.

2. Set VR_Settled when VR reaches target VID voltage.

1. Set new target VID code, VR jumps to new VID target, but does not control the slew rate. The output voltage decays at a rate proportional to the load current.

2. Low side MOSFET is not allowed to sync current.

3. ACK 11b when target higher than current VOUT voltage.

4. ACK 10b when target lower than current VOUT voltage.

1. Set power state.

2. ACK 11b when not support.

3. ACK 10b even slave not change configuration.

4. ACK 11b for still running SetVID command.

5. VR remains in lower state when receiving SetVID (decay).

Description

Pointer of

05h SetRegADR

06h SetReg DAT

07h GetReg

08h to

1Fh

not supported N/A N/A N/A

registers in

data table

New data

content

N/A

Specified

Contents

1. Set the pointer of the data register.

2. ACK 11b for address outside of support.

3. NAK 01b for SetADR (all call).

1. Write the contents to the data register.

2. NAK 01b for SetReg (all call).

1. Slave returns the contents of the specified register as the payload.

2. ACK 11b for non support address.

3. NAK 01b for GetReg (all call).

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RT8884B

Table 3. SVID Data and Configuration Register

Index Register Name Description Access Default

00h Vendor ID Vendor ID RO, Vendor 1Eh

01h Product ID Product ID RO, Vendor 84h

02h Product Revision Product Revision RO, Vendor 00h

05h Protocol ID SVID Protocol ID RO, Vendor 02h

06h Capability

10h Status_1 Data register containing the status of VR.

11h Status-2 Data register containing the status of transmission.

12h

Temperature Zone

15h IOUT

1Ch Status_2_lastread The register contains a copy of the status_2.

21h ICC Max

22h Temp Max

24h SR-fast

25h SR-slow

30h VOUT Max

31h VID Setting Data register containing currently programmed VID. RW, Master 00h

32h Power State Register containing the current programmed power state. RW, Master 00h

33h Offset Set offset in VID steps. RW, Master 00h

34h

Multi VR Configuration

35h Pointer

Bit mapped register, identifies the SVID VR Capabilities and which of the optional telemetry register is supported.

Data register showing temperature zone that has been entered.

At PS0 to PS2, IOUT report data from ADC sense IMON voltage. When power state at PS3, the IOUT report data is fixed to 04h.

Data register containing the ICC max the platform supports. Binary format in A IE 64h = 100A.

Data register containing the temperature max the platform supports. Binary format in °C IE 64h = 100°C.

Data register containing the capability of fast slew rate the platform can sustain. Binary format in mV/μs IE 0Ah = 10 mV/μs.

Data register containing the capability of slow slew rate. Binary format in mV/μs IE 02h = 2mV/μs.

The register is programmed by master and sets the maximum VID.

Bit mapped data register which configures multiple VRs behavior on the same bus.

Scratch pad register for temporary storage of the SetRegADR pointer register.

RO, Vendor 81h

R-M,

W-PWM

R-M,

W-PWM

R-M,

W-PWM

R-M,

W-PWM

R-M,

W-PWM

RO,

Platform

RO,

Platform

00h

7Dh

64h

RO 0Ah

RO 02h

RW, Master B5h

RW, Master 00h

RW, Master 30h

Notes :

RO = Read Only

RW = Read/Write

R-M = Read by Master

W-PWM = Write by PWM Only

Vendor = Hard Coded by VR Vendor

Platform = Programmed by the Master

PWM = Programmed by the VR Control IC

DS8884B-01 September 2013www.richtek.com

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Richtek RT8884B User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual