3 TON ON-Time/Frequency Adjustment Input. Connect to GND with 56k to 100k.
4 ENTRIP2
5 FB2
6 PGOOD
7 BOOT2
8 UGATE2
9 PHASE2
SMPS1 Feedback Input. Connect FB1 to a resistive voltage divider from SMPS1
output to GND for adjustable output from 2V to 5.5V.
Channel 1 Enable and Current Limit Setting Input. Connect resistor to GND to set
the threshold for Channel 1 synchronous R
cur rent limit threshold is 1/10th the voltage seen at ENTRIP1 over a 0.5V to 3V
range. There is an internal 10A current source from LD O5 to ENT RIP1. Leave
ENTRIP1 floating or drive it above 4.5V to shut down channel 1.
Channel 2 Enable and Current Limit Setting Input. Connect resistor to GND to set
the threshold for Channel 2 synchronous R
cur rent limit threshold is 1/10th the voltage seen at ENTRIP2 over a 0.5V to 3V
range. There is an internal 10A current source from LD O5 to ENT RIP2. Leave
ENTRIP2 floating or drive it above 4.5V to shut down channel 2.
SMPS2 Feedback Input. Connect FB2 to a resistive voltage divider from SMPS2
output to GND for adjustable output from 2V to 5.5V.
Power Good Output for Channel 1 and Channel 2 (RT8243A).
Power Good Output for Channel 1, Channel 2 and SECFB (RT8243B/C).
Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor
according to the typical application circuits.
Upper Gate Driver Output for SMPS2. UGATE2 swings between PHASE2 and
BOOT2.
Switch Node for SMPS2. PHASE2 is the internal lower supply rail for the UGATE2
high side gate driver. PHASE2 is also the current sense input for the SMPS2.
sense. The GND-PHASE1
DS(ON)
sense. The GND-PHASE2
DS(ON)
10 LGATE2 Lower Gate Drive Output for SMSP2. LGATE2 swings between GND and LDO5.
11 VIN Supply Input for LDO5.
Master Enable Input. LDO5/LDO3 is enabled if it is within logic high level and
12 ENLDO
ENM
(RT8243A)
13
14 LDO5
15 LDO3
SECFB
(RT8243B/C)
disabled if it is less than the logic low level. Leave ENLDO floating to default
enable LDO5/LDO3.
Mode Selection with Enable Input. Pull up to LDO5 (Ultrasonic mode) or LDO3
(DEM) to turn on both switch Channels. Short to GND for shutdown.
Change Pump Feedback Pin. The SECFB is used to monitor the optional external
charge pump. Connect a resistive divider from the change pump output to GND to
detect the output. If SECFB drops below its feedback threshold, an ultrasonic
pulse occurs to refresh the charge pump driven by LGATE1 or LGATE2.
If SECFB drops below its UV threshold, the switcher channels stop working and
enter into discharge-mode. Pull up to LDO5 or LDO3 to disable SECFB UVP
function.
5V Linear Regulator Output. LDO5 is the supply voltage for the low side MOSFET
driver and also the analog supply voltage for the device. Bypass a minimum 4.7F
ceramic capacitor to GND
3.3V Linear Regulator Output. Bypass a minimum 4.7F ceramic capacitor to
GND.
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
20 BYP1 Switch Over Source Voltage Input for LDO5.
21 (Exposed Pad) GND
Function Block Diagram
BOOT1
UGATE1
PHASE1
LGATE1
FB1
ENTRIP1
TON
BYP1
LDO5
LDO5
10µA
Switch Over Threshold
+
-
Lower Gate Driver Output for SMPS1. LGATE1 swings between GND and
LDO5.
Switch Node SMPS1. PHASE1 is the internal lower supply rail for the UGATE1
high side gate driver. PHASE1 is also the current sense input for the SMPS1.
Upper Gate Driver Output for SMPS1. UGATE1 swings between PHASE1 and
BOOT 1.
Boost Flying Capacitor Connection for SMPS1. Connect to an external
capacitor according to the typical application circuits.
Analog Ground and Power Ground. The exposed pad must be soldered to a
large PCB and connected to GND for maximum power dissipation.
BOOT2
UGATE2
PHASE2
LGATE2
FB2
ENTRIP2
ENM (RT8243A)
SECFB (RT8243B/C)
PGOOD
SMPS1
PWM
Buck
Controller
On Time
SMPS2
PWM
Buck
Controller
LDO5
LDO5
10µA
GND
LDO5
LDO5
VIN
ENLDO
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.