Richtek RT8241 User Manual

RT8241

DS8241-03 January 2014 www.richtek.com

High Efficiency Single Synchronous Buck PWM Controller

General Description

The RT8241 PWM controller provides high efficiency, excellent transient response, a nd high DC output a ccuracy needed for stepping down high voltage batteries to generate low voltage CPU core, I/O, and chipset RAM supplies in notebook computers.

The RT8241 supports on chip voltage progra mming function between 0.675V and 0.9V by controlling GX digital inputs.

The constant-on-time PWM control sche me handles wide input/output voltage ratios with ea se and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency .

The RT8241 achieves high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current-mode PWMs. Efficiency is further enhanced by its ability to drive very large synchronous rectifier MOSFETs and enter diode emulation mode at light load condition. The buck conversion allows this device to directly step down high voltage batteries at the highest possible efficiency . The RT8241 is intended for CPU core, chipset, DRAM, or other low voltage supplies as low as

0.675V. The RT8241 is available in a WQFN-12L 2x2 pack age.

Features

z Meet Intel VCCSA Voltage Slew Rate z Built-in 1% Reference Voltage z 2-Bit Programma ble Output V oltage with Integrated

Tra n sition Support

z Quick Load-Step Response within 100ns z 4700ppm/

°°

°C Programmable Current Limit by Low

Side R

DS(ON)

Sensing

z 4.5V to 26V Battery Input Range z Internal Ramp Current Limit Soft-Start Control z Drives Large Synchronous Rectifier FET s z Integrated Boost Switch z Over/Under Voltage Protection z Thermal Shutdown z Power Good Indicator z RoHS Compliant and Halogen Free

Pin Configurations

(TOP VIEW)

WQFN-12L 2x2

Ordering Information

Applications

z Notebook Computers z CPU/GPU Core Supply z Chipset/RAM Supply z Generic DC/DC Power Regulator

Note : Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

LGATE PGOOD

UGATE

PHASE

BOOT

VCC

GNDCSFB

654

12 1011

1 2

9 8

GND

RT8241

Package Type QW : WQFN-12L 2x2 (W-Type)

Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free)

Switching Frequency Operation A : 300kHz B : 400kHz C : 500kHz

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RT8241

Typical Application Circuit

For Fixed V oltage Regulator :

For Adjustable Voltage Regulator :

VCC

RT8241

PGOOD

12, 13 (Exposed Pad)

GND

BOOT

1 7

UGATE

PHASE

LGATE

BYPASS

R5*

C2*

OUT

* : Optional

Chip Enable

VCC

RT8241

PGOOD

12, 13 (Exposed Pad)

GND

BOOT

1 7

UGATE

PHASE

LGATE

BYPASS

R5*

C2*

OUT

* : Optional

C3*

FB1

FB2

Chip Enable

Marking Information

30W

30 : Product Code W : Date Code

RT8241AGQW

41W 40W

41 : Product Code W : Date Code

40 : Product Code W : Date Code

30 : Product Code W : Date Code

41 : Product Code W : Date Code

40 : Product Code W : Date Code

RT8241BGQW RT8241CGQW

RT8241AZQW RT8241BZQW RT8241CZQW

G0 G1 VFB

0 0 0.9V 0 1 0.8V 1 0 0.725V 1 1 0.675V

Table 1. VID Table

30W 41W 40W

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RT8241

Functional Pin Description

Pin N o. Pin N am e Pin Fu nc t io n

1 LGATE Gate Dr ive Output for Low Side Ext er nal MOSFET.

2 PHASE

External Inductor Connection Pin for PWM Converter. It behaves as the current sense comparator input for low side MOSFET R

DS(ON)

sensing and

refere nce v ol tag e for on time gener at ion.

3 UGATE Gate Drive Output for the H igh Side External MOSFET. 4 BOOT

Supply Input for High Side Driver. Connect a capacitor to the floating node (PHASE ) pin .

5 VCC

Control Voltage Input. Provides the power for the buck controller, the low side dr iv er and t he bootstrap circuit for high side driver. Bypass to GND wi t h

a 4.7μF ceramic capa citor. 6 EN Chi p Enabl e (Ac tive Hi gh) . 7 G0 2-Bit Input Pin.

8 G1 2- Bit Input Pin. 9 PGOOD

Open Drain Power Good Indicator. High impedance indicates power is

good.

10 FB Output Vol tage Feedback Input . 11 CS

Current Limit Threshold Setting Input. Connect a setting resistor to GND

and the current limit threshold is equal to 1/8 of the voltage seen at this pin.

12, 13 (Exposed Pad) GND

Ground. The expos ed pad must be soldered to a large PCB and conn ecte d

to GND for maxi mu m pow er dissipation.

Function Block Diagram

DRV

1/8

10µA

Diode

Emuation

Min toff

TRIGQ

One shot

TRIG

On-time compute

PHASE

One shot

Thermal

Shutdown

85% V

REF

Voltage

Programmer

0.45V

S1 Q

Latch

1.1V

S1 Q

Latch

REF

COMP

TON

ZCD

OC threshold

leakage

LG R

DS(ON)

UG R

DS(ON)

BST switch resistance

VCC

PGOOD

GND

BOOT UGATE PHASE

LGATE

(Internal)

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RT8241

Electrical Characteristics

Absolute Maximum Ratings (Note 1)

z VCC, FB, PGOOD, EN, CS, G0, G1 to GN D----------------------------------------------------------------------- −0.3V to 6V z PHASE to GND

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 32V <20ns ------------------------------------------------------------------------------------------------------------------------ −8V to 38V

z BOOT to PHASE ----------------------------------------------------------------------------------------------------------- −0.3V to 6V z UGATE to PHASE

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V <20ns ------------------------------------------------------------------------------------------------------------------------ −5V to 7.5V

z LGATE to GND

z Power Dissipation, P

@ T

= 25°C

WQFN-12L 2x2 ------------------------------------------------------------------------------------------------------------ 0.606W

z Package Thermal Re sistance (Note 2)

WQFN-12L 2x2, θJA------------------------------------------------------------------------------------------------------- 165°C/W

z Junction T emperature----------------------------------------------------------------------------------------------------- 150°C z Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------------- 260°C z Storage T emperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C z ESD Susceptibility (Note 3)

HBM (Human Body Mode) ---------------------------------------------------------------------------------------------- 2kV MM (Ma chine Mode)------------------------------------------------------------------------------------------------------ 200V

Recommended Operating Conditions (Note 4)

z Supply Input V oltage, V

------------------------------------------------------------------------------------------------ 4.5V to 26V

z Control Voltage, V

------------------------------------------------------------------------------------------------------ 4.5V to 5.5V

z Junction T emperature Range-------------------------------------------------------------------------------------------- −40°C to 125°C z Ambient T emperature Range-------------------------------------------------------------------------------------------- −40°C to 85°C

= 5V, V

= 8V, V

= 5V, T

= 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

PWM Controller

VCC Quiescent Supply Current IQ

FB forced above the regulation point, V

= 5V

-- 500 1250 μA

VCC Shutdown Current I

SHDN

VCC current, V

= 0V -- -- 1 μA

CS Shutdown Current CS pull to GND -- -- 1 μA

TA = 25°C −1 0 1

FB Error Comparator Threshold VFB

= −40°C to 85°C (Note 5) −1.5 0 1.5

OUT

Voltage Rang e V

OUT

0.675 -- 3.3 V

RT8241A VFB = 0.9V (f

= 300kHz) -- 400 --

RT8241B VFB = 0.9V (f

= 400kHz) -- 300 -- On-Time, Pulse Width

RT8241C

tON

= 0.9V (f

= 500kHz) -- 240 --

Minimum Off-Time t

OFF

250 400 550 ns

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RT8241

Parameter Symbol Test Conditions Min Typ Max Unit

Current Sensing

CS Source Current 9 10 11 μA CS Source Current

Temperature Coefficient

-- 4700 -- ppm/°C

Zero Crossing Threshold

PHASE − GND −10

-- 5 mV

Protection Function

Current Limit Threshold Offset

GND − PHASE = VCS/8 −20 0 20 mV

Neg ative Cur ren t Limit Threshold Offset

PHASE − GND = VCS/8 -- 3 -- mV

Under Voltage Protection UVP Detect, Falling Edge 0.41 0.45 0.49 V UVP Fa ult Delay VFB = 0.375V -- 3.5 -- μs Over Voltage Protection OVP Detect, Rising Edge 1.065 1.1 1.133 V OVP F ault Delay VFB = 1.183V -- 5 -- μs

VCC Under Voltage Lockout (UVLO) Threshold

UVLO

Falling edge, PWM disabled below this level

3.5 3.7 3.9 V

VCC UVLO Hysteresis ΔV

UVLO

-- 100 -- mV

VOUT Soft-Start From EN = High to V

OUT

= 95% -- 0.8 - - ms Dynamic VID Slew Rat e SGX G0/G1 Transition 1.75 -- 10 mV/μs UVP Blank Time Fr om EN signal going high -- 3 - ms T herm al Shut d ow n TSD -- 150 --

T herm al Shut d ow n Hysteresis

ΔT

-- 10 --

°C

Driver On-Resistance

UGATE Driver Source

UGATEsr

BOOT−PHASE forced to 5V, U GATE Hig h St a t e

-- 1.8 3.6 Ω

UGATE Driver Sink

UGATEsk

BOOT−PHASE forced to 5V, UGATE Low State

-- 1.2 2.4 Ω

LGATE Driver Source

LGATEsr

LGATE, High State

-- 1.8 3.6 Ω

LGAT E Driver Sink

LGATEsk

LGATE, Low State

-- 0.8 1.34 Ω

LGATE Rising (V

PHASE

= 1.5V)

Dead Time

U GATE Ris ing

Internal Boost Charging Swit c h On- Re si sta nc e

VCC to BOOT, 10mA

EN Threshold

Logic-High

1.8 -- --

EN Threshold Voltage

Logic-Low

-- -- 0.5

Voltage Programming (G0, G1)

Logic-High 750 -- --

G0, G1 I nput Threshold Voltage

Logic-Low -- -- 300

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RT8241

Parameter Symbol Test Conditions Min Typ Max Unit

PGOOD (upper side threshold determined by OVP threshold)

Trip Threshold

Falling edge, measured at FB, with respect to reference, no load.

−19 −15 −11

Trip Hysteresis -- 3 --

Fa ult Pr opa gat ion Dela y

Fal lin g edge , FB forc ed bel ow PGOOD trip threshold

-- 2.5 --

μs

Output Low Voltage

SINK

= 1m A

-- -- 0.4

Leakage Current High State, forced to 5V -- -- 1

μA

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.

Note 2. θ

is measured in natural convection at TA = 25°C on a low effective thermal conductivity test board of JEDEC 51-3

thermal measurement standard.

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. Guaranteed by Design.

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RT8241

Typical Operating Characteristics

Efficiency vs. Output Current

100

0.001 0.01 0.1 1 10

Output Current (A)

Eff iciency (%)

= 8V , V

= V

= 5V , V

OUT

= 0.9V

Switching Frequenc y v s . Output Current

100

125

150

175

200

225

250

275

300

325

350

0.001 0.01 0.1 1 10

Output Current (A)

Swit ching Frequency (kHz) 1

= 8V , V

= V

= 5V , V

OUT

= 0.9V

Efficiency vs. Output Current

100

0.001 0.01 0.1 1 10

Output Current (A)

Eff iciency (%)

= 12V, V

= V

= 5V, V

OUT

= 0.9V

Switching Frequenc y vs. Output Current

100

125

150

175

200

225

250

275

300

325

350

0.001 0.01 0.1 1 10

Output Current (A)

Swit ching Frequency (kHz) 1

= 12V, V

= V

= 5V, V

OUT

= 0.9V

Efficiency vs. Output Current

100

0.001 0.01 0.1 1 10

Output Current (A)

Eff iciency (%)

= 20V, V

= V

= 5V, V

OUT

= 0.9V

Switching Frequency vs. Output Current

100

125

150

175

200

225

250

275

300

325

350

0.001 0.01 0.1 1 10

Output Cu rren t (A)

Swit ching Frequency (kHz) 1

= 20V, V

= V

= 5V, V

OUT

= 0.9V

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RT8241

Dynamic VID Down

Time (20μs/Div)

No Load, VIN = 12V, VCC = VEN = 5V, V

OUT

= 0.9V to 0.8V

G1 (5V/Div) UGATE

(20V/Div)

LGATE

(10V/Div)

0.8V

OUT

(50mV/Div)

0.9V

Dynamic VID Up

Time (20μs/Div)

(5V/Div)

0.8V

UGATE

(20V/Div)

LGATE

(10V/Div)

No Load, VIN = 12V, VCC = VEN = 5V, V

OUT

= 0.8V to 0.9V

OUT

(50mV/Div)

0.9V

Shutdown Current vs. Input Voltage

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

5 7 9 1113151719212325

Inpu t Voltage (V)

Shutdown Current (µ A) 1

No Load, EN = GND

Quiescent Current vs. Input Voltage

670

680

690

700

710

720

730

5 7 9 1113151719212325

Input Vol tage (V)

Quiescent Current (µA) 1

No Load, V

= 5V

Power On from EN

Time (400μs/Div)

VIN = 12V, VCC = VEN = 5V, V

OUT

= 0.9V,

PGOOD

(10V/Div)

OUT

(1V/Div)

PHASE

(10V/Div)

(5V/Div)

LOAD

= 0.1A

OUT

(1V/Div)

Power Off from V

Time (1ms/Div)

PHASE

(10V/Div)

(5V/Div)

VIN = 12V, VCC = VEN = 5V, V

OUT

= 0.9V, I

LOAD

= 0.1A

PGOOD

(10V/Div)

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RT8241

Load Transient Response

Time (100μs/Div)

VIN = 12V, VCC = VEN = 5V, V

OUT

= 0.9V, I

LOAD

= 0A to 6A

LOAD

(5A/Div)

OUT_ac

(20mV/Div)

LGATE

(10V/Div)

UGATE

(20V/Div)

Over Voltage Protection

PGOOD (5V/Div)

OUT

(500mV/Div)

LGATE

(5V/Div)

No Load, VIN = 12V, VCC = VEN = 5V, V

OUT

= 0.9V

Time (100μs/Div)

Under Voltage Protection

Time (100μs/Div)

PGOOD

(5V/Div)

OUT

(1V/Div)

LGATE

(5V/Div)

UGATE

(20V/Div)

No Load, VIN = 12V, VCC = VEN = 5V, V

OUT

= 0.9V

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RT8241

Application Information

The RT8241 is of a constant on-ti me PWM controller which provides four DC feedback voltages by controlling the G0 and G1 digital input. The constant on-time PWM control scheme handles wide input/output ratios with ease and provides 100ns “instant-on” response to load steps while maintaining a relatively constant operating frequency a nd inductor operating point over a wide range of input voltages. The topology circumvents the poor load transient timing problems of fixed-frequency current mode PWMs, while avoiding the problems caused by widely varying switching frequencies in conventional constant on-ti me and constant off-time PWM schemes. The DRVTM mode PWM modulator is specifically designed to have better noise immunity for such a single output application.

PWM Operation

The Mach ResponseTM, DRVTM mode controller relies on the output filter capacitor's Effective Series Resistance (ESR) to act as a current sense resistor, so the output ripple voltage provides the PWM ra mp signal. Referring to the function diagrams of the RT8241, the synchronous high side MOSFET is turned on at the beginning of eac h cycle. After the internal one-shot timer expires, the high side MOSFET is turned off. The pulse width of this one shot is determined by the converter's input and output voltages to keep the frequency fairly constant over the input voltage range. Another one-shot sets a minimum off-time (400ns typ.).

On-Time Control (TON)

The on-time one-shot comparator has two inputs. One input monitors the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this ca pacitor to charge from zero volts to V

OUT

, thereby making the on-time of the high side switch directly proportional to the output voltage and inversely proportional to the input voltage. The implementation results in a nearly constant switching frequency without the need of a clock generator.

Diode-Emulation Mode

RT8241 automatically reduces switching frequency at lightload conditions to maintain high efficiency . This reduction of frequency is achieved smoothly a nd without increasing V

OUT

ripple or load regulation. As the output current decrea ses from heavy load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low side MOSFET allows only partial negative current when the inductor freewheeling current becomes negative. As the load current is further decreased, it takes longer and longer to discharge the output capa citor to the level that is required for the next “ON” cycle. The on-time is kept the same as that in the heavy-load condition. In reverse, when the output current increa ses from light load to heavy load, the switching frequency increases to the preset value as the inductor current re aches the continuous condition. The transition load point to the light-load operation can be calculated a s follows (Figure 1) :

IN OUT

LOAD ON

(V V )

−

≈×

where tON is the on-time.

Figure 1. Boundary Condition of CCM/DCM

The switching waveforms may appear noisy and asynchronous when light loa ding causes diode-emulation operation, but this is a normal operating condition that results in high light-load efficiency . T rade-offs in DEM noise vs. light-load efficiency is made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. The disadvantages for using higher inductor values include

L_Peak

LOAD

= I

L_Peak

Slope = (VIN-V

OUT

) / L

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RT8241

FB1

OUT FB

FB2

VV(1 )

=×+

where VFB is as shown in Table 2.

Table 2. Feedback Voltage Selection

G0 State G1 State Feedback Voltage

0 0 VFB = 0.9V 0 1 VFB = 0.8V 1 0 VFB = 0.725V 1 1 VFB = 0.675V

Figure 2. Setting V

OUT

with a Resistor-Divider

Output Voltage Transition Operation

The digital input control pin Gx allows V

OUT

to transition to both higher and lower values. For a downward tra nsition, the rapid cha nge of Gx from high to low will suddenly cause VFB to drop to a new internal V

REF

. At this ti me the LGA TE will drive high to turn on the low side MOSFET and draw current from the output capa citor via the inductor . LGA TE will remain on until VFB falls to the new internal V

REF

, at which point a normal UGA TE switching cycle begins, as shown in Figure 3. For a down transition, the low side MOSFET remains on until VFB reaches the new internal V

REF

. Thus, the negative inductor current will be increa sed. If the negative current become large enough to trigger NOCP , the low side MOSFET will be turned of f to prevent

Figure 3. Output V oltage Down Tr ansition

LGATE

PHASE

UGATE

G0 G1

FB1

FB2

BOOT

OUT

For an upward transition (from lower to higher V

OUT

) as shown in Figure 4, Gx cha nges from low to high and causes VFB to rise to a new internal V

REF

. This quickly trips the VFB comparator regardless of whether DEM is active or not, generating an UGATE on-time and causing a subsequent LGATE to be turned on. At the end of the minimum off-time (400ns), if VFB is still below the new internal V

REF

, another UGA TE on-time will be started. This sequence continues until the FB pin exceeds the new internal V

REF

larger physical size and degraded load-tra nsient response (especially at low input voltage levels).

Output Voltage Setting (FB)

As Figure 2 shows, the output voltage can be adjusted from 0.675V to 3.3V by setting the feedback resistors R

FB1

and R

FB2

. Choose R

FB2

to be approximately 20kΩ,

and solve for R

FB1

using the equation :

large negative current from damaging the component. Refer to the Negative Over Current Limit se ction for a full description.

Figure 4. Output V oltage Up T ra nsition

OUT

UGATE

LGATE

REF

GND

Initial V

OUT

Final V

OUT

Initial V

REF

Final V

REF

GND

REF

Initial V

REF

Final V

REF

UGATE

LGATE

Initial V

OUT

Final V

OUT

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RT8241

If the V

OUT

change is significant, there can be several consecutive cycle of UGA TE on-time followed by minimum LGATE ti me. This ca n cause a rapid increase in inductor current: typically it only takes a few switching cycles for inductor current to rise up to the current limit. At some point the VFB will rise up to the new internal V

REF

and the UGATE pulses will cease, but the inductor's LI2 energy must then flow into the output capacitor. This can create a significant overshoot, a s shown in Figure 5.

Figure 5. Output V oltage Up Tra n sition with

Overshooting

This overshoot can be approximated by the following equation, where ICL is the current limit, V

FINAL

is the

desired set point for the final voltage, L is in μH and C

OUT

is in μF.

MAX FINAL

OUT

V()V

Current Limit Setting (OCP)

The RT8241 has a cycle-by-cycle current li miting control. The current limit circuit employs a unique “valley” current sensing algorithm. If the magnitude of the current sense signal at the CS pin is above the current limit threshold, the PWM is not allowed to initiate a new cycle (Figure.

6). In order to provide both good accuracy and a cost effective solution, the RT8241 supports temperature compensated MOSFET R

DS(ON)

sensing. The CS pin should be connected to GND through the trip voltage setting resistor, RCS. The 10μA CS terminal source current , ICS, and the trip voltage setting resistor, RCS, set the CS trip

CS CS

V(mV) = R(k)10(A)

Ω×

The Inductor current can be monitored by the voltage between GND and the PHASE pin. Hence, the PHASE pin should be connected to the drain terminal of the low side MOSFET. ICS has temperature coefficient to compensate the temperature dependency of the R

DS(ON)

. GND is used as the positive current sensing node, so GND should be connected to the source terminal of the bottom MOSFET .

While the comparison is being done during the OFF state, VCS sets the valley level of the inductor current. Thus, the load current at over-current threshold, I

LOAD_OC

, can be

calculated as f ollows :

ripple

LOAD_OC

DS(ON)

CS IN OUT OUT

DS(ON) SW IN

8R 2

V(VV)V

8R 2Lf V

−×

=+×

×××

In an over-current condition, the current to the load exceeds the current to the output capa citor , thus causing the output voltage to fall. Eventually the voltage crosses the under voltage protection threshold and the device shuts down.

Figure 6. “Vally” Current Limit

Negative Over Current Limit (PWM Only Mode)

The RT8241 supports cycle-by-cycle negative over current limiting in CCM Mode only . The over current limit is set to be negative but is the same absolute value a s the positive over current limit. If output voltage continues to rise, the low side MOSEFT remains on. Thus, the inductor current is reduced and reverses direction after it reaches zero. When there is too much negative current in the inductor, the low side MOSFET is turned off and the current flows towards VIN through the body diode of the high side MOSFET. Because this protection limits the discharge current of the output capacitor, the output voltage tends

L_Peak

LOAD

LIM

voltage, VCS, as in the f ollowing equation.

GND

REF

Initial V

REF

Final V

REF

UGATE

LGATE

Initial V

OUT

Final V

OUT

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RT8241

to rise, eventually hitting the over voltage protection threshold and shutting down the device. If the device hits the negative over current threshold again before output voltage is discharged to the target level, the low side MOSFET is turned off and the process rep eats. It ensures maximum allowable discharge capability when output voltage continues to rise. On the other hand, if the output is discharged to the target level before negative current threshold is reached, the low side MOSFET is turned off, the high side MOSFET is then turned on, and the device resumes normal operation.

MOSFET Gate Driver (UGATE, LGA TE)

The high side driver is designed to drive high current, low R

DS(ON)

N-MOSFET(s). When configured as a floating driver, 5V bias voltage is delivered from the VCC supply. The average drive current is proportional to the gate charge at VGS = 5V times switching frequency . The insta ntaneous drive current is supplied by the flying capacitor between the BOOT and PHASE pins. A dead time to prevent shoot through is internally generated between high side MOSFET off to low side MOSFET on, and low side MOSFET off to high side MOSFET on. The low side driver is designed to drive high current, low R

DS(ON)

NMOSFET(s). The internal pull-down tran sistor that drives LGA TE low is robust, with a 0.8Ω typical on resistance. A 5V bias voltage is delivered from the VCC supply. The instantaneous drive current is supplied by the flying capa citor between VCC a nd GND.

For high current applications, some combin ations of high and low side MOSFETs might be encountered that will cause excessive gate drain coupling, which can lead to efficiency killing, EMI-producing shoot through currents. This is often remedied by adding a resistor in series with BOOT, which increases the turn-on time of the high side MOSFET without degrading the turn-off time, a s shown in Figure 7.

Figure 7. Reducing the UGATE Rise Ti me

PHASE

UGATE

BOOT

Power Good Output (PGOOD)

The power good output is an open-drain output and requires a pull-up resistor. When the feedback voltage is above

1.1V or below 0.45V , PGOOD will be pulled low . PGOOD is allowed to be high until soft-start ends and the output reaches 89% of its set voltage. There is a 2.5μs delay built into PGOOD circuitry to prevent false tra nsition.

When Gx cha nges, PGOOD remains in its present state for 32 clock cycles. Mea nwhile, V

OUT

or VFB regulates to

the new level.

POR, UVLO and Soft-Start

Power On Reset (POR) occurs when VCC rises above

3.7V (typ.). After POR is triggered, the R T8241 will reset the fault latch and prepare the PWM for operation. Below

3.6V (typ.), the VCC Under Voltage Lockout (UVLO) circuitry inhibits switching by keeping UGA TE and LGA TE low. A built-in soft-start is used to prevent surge current from the power supply input after EN is ena bled. It clamps the ramping of the internal reference voltage which is compared with the FB signal. The typical soft-start duration is 0.8ms.

Over Voltage Protection (OVP)

The output voltage can be continuously monitored for over voltage protection. When VFB exceeds 1.1V , over voltage protection is triggered and the low side MOSFET is latched on. This activates the low side MOSFET to discharge the output capacitor. The RT8241 is latched once OVP is triggered and can only be rele ased by VCC or EN power on reset. There is a 5μs delay built into the over voltage protection circuit to prevent false transitions.

Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under voltage protection. When VFB is less than 0.45V, under voltage protection is triggered and then both UGA TE an d LGA TE gate drivers are forced low . In order to remove the residual charge on the output cap acitor during the under voltage period, if PHASE is greater than 1V, the LGATE is forced high until PHASE is lower than 1V. There is a

3.5μs delay built into the under voltage protection circuit to prevent false transitions. During soft-start, the UVP blanking time is 3ms.

DS8241-03 January 2014www.richtek.com

RT8241

ON IN OUT

LOAD(MAX)

T(VV)

LIR I

×−

where LIR is the ratio of peak-to-pea k ripple current to the maximum average inductor current. Select a low pass inductor having the lowest possible DC resistance that fits in the allowed dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (I

PEAK

) :

PEAK LOAD(MAX) LOAD(MAX)

LIR

II I

=+×

Output Capacitor Selection

The output filter cap acitor must have ESR low enough to meet output ripple and load tra nsient requirement, yet have high enough ESR to satisfy stability requirements. Also, the capa citance must be high enough to absorb the inductor energy going from a full load to no load condition without tripping the OVP circuit. For CPU core voltage converters and other a pplications where the output is subject to violent load transient, the output ca pa citor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite cap acita nce :

LOAD(MAX)

ESR

−

≤

In non-CPU applications, the output capacitor's size depends on how much ESR is needed to maintain at an acceptable level of output voltage ri pple :

LOAD(MAX)

ESR

LIR I

−

≤

Organic semiconductor capacitor(s) or special polymer cap acitor(s) are recommended.

Output Capacitor Stability

Stability is determined by the value of the ESR zero relative to the switching frequency. The point of instability is given by the following equation :

ESR

OUT

2ESRC 4

=≤

××

Do not put high value ceramic capacitors directly across the outputs without taking precautions to ensure sta bility . Large ceramic capacitors can have a high ESR zero frequency and cause erratic and unstable operation. However, it is easy to add sufficient series resistance by placing the ca pacitors a couple of inches down stream from the inductor and connecting FB divider close to the inductor. There are two related but distinct ways including double pulsing and feedback loop instability to identify the unstable operation. Double pulsing occurs due to noise on the output or because the ESR is too low such that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the 400ns minimum off-time period has expired. Double-pulsing is more annoying tha n harmful, resulting in nothing worse than increa sed output ripple. However, it may indicate the possible pre sence of loop instability , which is caused by insufficient ESR. Loop instability can result in oscillation at the output after line or load perturbations that can trip the over voltage protection latch or cause the output voltage to fall below the tolerance limit. The easiest method for stability checking is to apply a very zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It helps to si multaneously monitor the inductor current with an AC probe. Do not allow more than one ringing cycle after the initial step-response underor overshoot.

Thermal Considerations

For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and a mbient temperature. The maximum power dissipation can be calculated by the following formula :

D(MAX)

= (T

J(MAX)

− TA) / θ

where T

J(MAX)

is the maximum junction temperature, T

the ambient temperature, a nd θ

is the junction to ambient

thermal resistance. For recommended operating condition specifications of

the RT8241, the maximum junction temperature is 125°C

Output Inductor Selection

The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value a s follows :

DS8241-03 January 2014 www.richtek.com

RT8241

and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For WQF N12L 2x2 pack ages, the thermal resistance, θJA, is 165°C/ W on a standard JEDEC 51-3 single-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula :

D(MAX)

= (125°C − 25°C) / (165°C/W) = 0.606W for

WQF N-12L 2x2 pa ckage The maximum power dissipation depends on the operating

ambient temperature for fixed T

J(MAX)

and thermal resistance, θJA. For the RT8241 package, the derating curve in Figure 8 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.

Figure 8. Derating Curves for the RT8241 Pac kage

Layout Considerations

Layout is very important in high frequency switching converter design. If designed improperly , the PCB could radiate excessive noise and contribute to converter instability. For best performance of the RT8241, the following guidelines should be strictly followed.

` Connect an RC low-pa ss filter from VCC, (1μF a nd 10Ω

are recommended). Place the filter capacitor close to the IC.

` Keep current limit setting network a s close as possible

to the IC. Routing of the network should be kept away from high voltage switching nodes to prevent it from coupling.

` Connections from the drivers to the respective gate of

the high side or the low side MOSFET should be as short as possible to reduce stray inductance.

` All sensitive analog traces and components pertaining

to FB, GND, EN, PGOOD, CS and VCC should be placed away from high voltage switching nodes such a s PHASE, LGATE, UGA TE, or BOOT nodes to prevent it from coupling. Use internal layer(s) a s ground plane(s) and shield the feedback trace from power traces and components.

` Current sense connections must always be made using

Kelvin connections to ensure an accurate signal, with the current limit resistor located at the device.

` Power sections should connect directly to ground

plane(s) using multiple vias as required for current handling (including the chip power ground connection s). Power components should be placed to minimize loops and reduce losses.

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0 25 50 75 100 125

Ambient Temperature (°C)

mum

ower

(W)

Four-Layer PCB

DS8241-03 January 2014www.richtek.com

RT8241

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

Outline Dimension

Symbol

Dimensions In Millimeters Dimensions In Inches

Min Max Min Max

A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010

b 0.150 0.250 0.006 0.010 D 1.900 2.100 0.075 0.083 E 1.900 2.100 0.075 0.083

e 0.400 0.016

D2 0.850 0.950 0.033 0.037 E2 0.850 0.950 0.033 0.037

L 0.250 0.350

0.010 0.014

W-Type 12L QFN 2x2 Package

Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

1 2

Richtek RT8241 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual