Richtek RT8228AGQW, RT8228AZQW Schematic [ru]

Single Synchronous Buck PWM Controller

RT8228A

General Description

The constant on-time PWM control scheme ha ndles wide input/output voltage ratios with ea se and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency .

The RT8228A a chieves high eff iciency at a reduced cost by eliminating the current sense resistor found in traditional current mode PWMs. Efficiency is further enhanced by its ability to drive very large synchronous rectifier MOSFETs and enter diode emulation mode at light load condition. The buck conversion allows this device to directly step down high voltage batteries at the highest possible efficiency. The Audio Skipping Mode (ASM) setting maintains the switching frequency above 25kHz, which eliminates noise in audio a pplications. The RT8228A is intended for CPU core, chipset, DRAM, or other low voltage supplies as low a s 0.5V . The R T8228A is available in a WQFN-12L 2x2 package.

Ordering Information

RT8228A

Package Type QW : WQFN-12L 2x2 (W-Type)

Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free)

Note : Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Features

z Built in 1% 0.5V Reference Voltage z Adjustable 0.5V to 3.3V Output Range z Quick Load Step Response within 100ns z 4700ppm/

Side R

z 4.5V to 26V Battery Input Range z Resistor Programmable Frequency z Internal Ramp Current Limit Soft-Start Control z Drives Large Synchronous Re ctifier FETs z Integrated Boost Switch z Over/Under Voltage Protection z Thermal Shutdown z Power Good Indicator z RoHS Compliant and Halogen Free

°°

°C Programmable Current Limit by Low

°°

Sensing

DS(ON)

Applications

z Notebook Computers z CPU Core Supply z Chipset/RAM Supply a s Low as 0.5V z Generic DC/DC Power Regulator

Pin Configurations

(TOP VIEW)

GND

TON

12 1011

LGATE PGOOD

PHASE UGATE

GND

2 3

BOOT

WQFN-12L 2x2

9 8

VCC

MODE

654

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RT8228A

Marking Information

RT8228AGQW

CQ : Product Code

CQW CQW

W : Date Code

Typical Application Circuit

U P

Chip Enable

C 4

(

RT8228AZQW

C 0

CQ : Product Code W : Date Code

)

RT8228A-06 January 2014www.richtek.com

Functional Pin Description

Pin No. Pin Name Pin Function

1 LGATE Gate Drive Output for Low Side External MOSFET.

External Inductor Connection Pin for PWM Converter. It behaves as the current

2 PHASE

3 UGATE Gate Drive Output for High Side External MOSFET. 4 BOOT

5 VCC

6 FB

7 MODE

8 EN PWM Chip Enable. P ull low to GND to disable the PWM .

9 PGOOD Open Drain Power Good Indicator. High impedance indicates power is good. 10 CS 11 TON On-time Setting. Connect a resistor between this pin and VIN.

12,

13 (Exposed Pad)

GND

sense comparator input for Low Side MOSFET R voltage for on time generation.

Supply Input for High Side Driver. Connect through a capacitor to the floating node (PHASE) pin.

Control Voltage Input. Provides the power for the buck controller, the low side driver and the bootstrap circuit for high side driver. Bypass to GND with a 4.7μF ceramic capacitor.

Feedback Input. Connect FB to a resistive voltage divider from V

OUT

GND to adjust the output from 0.5V to 3.3V Pull Down t o G ND for F orced CCM Mode .

Pull Up to 2.5V for Audio Skipping Mode (ASM). Pull Up to 5V for Diode Emulation Mo d e (DEM).

Curr ent Limit Threshold Setting Input. Connect a setting resistor to GND and the current limit threshold is equal to 1/10 of the voltage at this pin.

Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.

RT8228A

sensing and reference

DS(ON)

OUT

Function Block Diagram

TRIG

Timer

On-time

Compute

1-SHOT

0.5V V

125% V

90% V

TON

VCC

PHASE

125% V

10µA

70% V

POR

PSR

REF

Latch

S1 Q

Latch

S1 Q

REF

Thermal

Shutdown

COMP

BOOT

PWM

Min. T

QTRIG

DEM/FCCM/ASM

OFF

1-SHOT

X(-1/10)

DRV

VCC

DRV

UGATE

PHASE

LGATE GND MODE PGOOD

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RT8228A

Absolute Maximum Ratings (Note 1)

z VCC to GND ---------------------------------------------------------------------------------------------------------–0.3V to 6V z FB, PGOOD, EN, CS, MODE to GND ------------------------------------------------------------------------–0.3V to (VCC + 0.3V) z TO N to G ND----------------------------------------------------------------------------------------------------------–0.3V to 32V z BOOT to PHASE ---------------------------------------------------------------------------------------------------–0.3V to 6.5V z PHASE to GND

DC----------------------------------------------------------------------------------------------------------------------−0.3V to 32V < 20ns ----------------------------------------------------------------------------------------------------------------−8V to 38V

z UGATE to PHASE

DC----------------------------------------------------------------------------------------------------------------------−0.3V to (VCC + 0.3V) < 20ns ----------------------------------------------------------------------------------------------------------------−5V to 7.5V

z LGA TE to GND

z Power Dissipation, P

WQFN-12L 2x2 -----------------------------------------------------------------------------------------------------0.606W

z Package Thermal Re sistance (Note 2)

WQF N-12L 2x2, θJA------------------------------------------------------------------------------------------------165°C/W

z Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------260°C z Junction T emperature----------------------------------------------------------------------------------------------150°C z Storage T emperature Range -------------------------------------------------------------------------------------−65°C to 150°C z ESD Susceptibility (Note 3)

HBM (Human Body Mode) ---------------------------------------------------------------------------------------2kV MM (Ma chine Mode)-----------------------------------------------------------------------------------------------200V

@ TA = 25°C

Recommended Operating Conditions (Note 4)

z Input V oltage, V z Control Voltage, V z Junction T emperature Range-------------------------------------------------------------------------------------−40°C to 125°C z Ambient T emperature Range-------------------------------------------------------------------------------------−40°C to 85°C

---------------------------------------------------------------------------------------------------4.5V to 26V

-----------------------------------------------------------------------------------------------4.5V to 5.5V

RT8228A-06 January 2014www.richtek.com

RT8228A

Electrical Characteristics

(VCC = 5V, VIN = 15V, VEN = 5V, V

Parameter Symbol Test Conditions Min Typ Max Unit

PWM Con tro ller

VCC Quiescent Supply Current IQ VCC Shutdown Current I

TON Operat ing Curre nt TON Shut dow n Curr ent R CS Shutdown Curr ent CS pul l to GND -- -- 1 μA

FB Error Compar at or Threshold Vol tage

FB Input Bias Cu rrent V Output V olta ge Ran ge 0.5 -- 3. 3 V

On-Time Minimum Off-Time

Current Sensing Threshold

CS Source C urrent VCS = 0.5V to 2V 9 10 11 μA CS Source Curr ent TC On the basis of 25°C -- 4700 -- ppm/°C

MODE

= 5V, R

= 500kΩ, T

TON

FB f orced above the regulati on point , V

VCC Current, V

SHDN

TON TON

CC FB

MODE

= 25°C, unless otherwise specified)

= 5V

= 500k

= 0V

-- 0.5 1.25 mA

-- -- 1

-- 30 --

μA μA

= 500k -- -- 1 μA

= 4.5V to 5.5V, D EM

495 500 505 mV

= 0.5V −1 0.1 1 μA

=15V, V

PHASE

= 0V

= 0V, FB = 0.45V

= 1.25V,

267 334 401 ns 250 400 550 ns

Zero Crossing Threshold V ASM Min Frequ ency

> 1.8V, PH ASE − GND −10 -- 5 mV

MODE

MODE =

2.5V

-- 25 -- kHz

Protection Func t i on

Current Limit Thr eshol d GND − PHASE, V

= 1V 85 100 115 mV

UV Threshold UVP Detect, FB Falling Edge 60 70 80 % OVP Threshold OVP Detect, FB Rising Edge 120 125 130 % OV Fault Delay FB f orced above OV threshold -- 5 -- μs

VCC Power O n Reset (P OR) Threshold

Rising Edge 3.7 3.9 4.2 V

POR Threshold Hysteresis -- 100 -- mV Current Limit Ramp at

Soft-Start

Enabl e to curr ent limit threshold = 50mV

-- 900 -- μs

UV Blank Ti me Fro m EN signa l goi ng high -- 4.5 -- ms Thermal S hut dow n Thermal S hut dow n Hyst er esis

T ΔT

-- 150 -- °C

-- 10 -- °C

Driver On -Resi st ance

UGATE Driver Source

UGATEsr

UGATE Dr iver Si nk R UGATEsk

BOOT − PHASE forced to 5V, UGATE High St at e

BOOT − PHASE fo rced to 5V, UGATE Low St ate

-- 2.5 5

-- 1.5 3 Ω

LGATE Driver So ur ce RLGATEsr LGATE High State -- 2.5 5 Ω LGATE Driver Sin k RLGATEsk L GATE Low St ate -- 0.8 1.5 Ω

Dead Time

LGATE Rising (Phase = 1.5V ) -- 30 --

UGATE Rising -- 30 --

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RT8228A

Parameter Symbol Test Conditions Min Typ Max Unit

Internal Boost Charging Switch on Resistance

EN Threshold

to BOOT, 10mA

-- -- 80

EN T hresh old Voltage

Logic-High VIH 1.2 -- -Logic-Low V

-- -- 0.4

Mode Threshold

DEM Threshold

− 0.5

-- -- V ASM Threshold 1.8 -- 2.9 V FCCM Threshold -- -- 0.4 V PGOOD (upper side threshold decided by OV threshold)

Trip Threshold (Falling)

Measured at FB, with respect to reference

−13 −10 −7

Trip Thre shol d Hystere sis -- 3 -- % Fault Propagation Delay Output Low Voltage

Leakage Curr ent High state, forced to 5V -- -- 1

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings, Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions.

is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of JEDEC 51-

3 thermal measurement standard.

Falling edge, FB forced below PGOOD trip thre sho ld

= 1mA

SINK

-- 2.5 -- μs

-- -- 0.4 V μA

RT8228A-06 January 2014www.richtek.com

Typical Operating Characteristics

RT8228A

Efficiency vs . Loa d Current

100

90 80 70 60 50 40

Efficiency (% )

30 20 10

0.001 0.01 0.1 1 10

DEM Mode

CCM Mode

VIN = 8V, V

Load Current (A)

Efficiency vs . Loa d Current

100

90 80 70 60 50 40

Eff iciency (%)

30 20 10

0.001 0.01 0.1 1 10

DEM Mode

CCM Mode

VIN = 20V , V

Load Curren t (A)

OUT

= 1V

Efficiency vs. Load Current

100

90 80 70 60 50 40

Eff iciency (%)

30 20 10

0.001 0.01 0.1 1 10

Switching Frequency vs . R

900 800 700 600 500 400 300 200

Switching Frequency (kHz) 1

100

100 200 300 400 500 600 700 800

DEM Mode

CCM Mode

VIN = 12V , V

Load Current (A)

CCM Mode, VIN = 12V , V

Resistance (k )

TON

Resistance

TON

= 1V , No Load

OUT

= 1V

Switching Frequency v s . Input Voltage

500 450 400 350 300 250 200 150 100

Switching Fr equency (kHz) 1

6 8 10 12 14 16 18 20 22 24 26

CCM Mode, V

Inpu t Voltage (V)

= 1V, No Load

OUT

Switching Frequency vs . Loa d Current

400

VIN = 12V , V

350 300 250 200 150 100

Switching Fr equency (kHz) 1

0.001 0.01 0.1 1 10

= 1V

OUT

CCM Mode

DEM Mode

Load Current (A)

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RT8228A

400 350 300 250 200 150 100

Swit ching Frequency (kHz) 1

UGATE

(20V/Div)

Switching Frequency vs. Load Current

VIN = 20V , V

0.001 0.01 0.1 1 10

= 1V

OUT

CCM Mode

DEM Mode

Load Current (A)

Power On from EN

UGATE

(20V/Div)

(5V/Div)

OUT

(500mV/Div)

PGOOD

(5V/Div)

UGATE

(20V/Div)

Power On from EN

CCM Mode, VIN = 12V , V

Time (1ms/Div)

OVP

= 1V , No Load

OUT

(5V/Div)

OUT

(500mV/Div)

PGOOD

(5V/Div)

UGATE

(50V/Div)

LGATE

(10V/Div)

OUT

(500mV/Div)

(10A/Div)

DEM Mode, VIN = 12V , V

Time (1ms/Div)

UVP

VIN = 12V, V

= 1V , No Load

OUT

= 1V, No Load

OUT

(500mV/Div)

LGATE

(5V/Div)

OUT_ac

(50mV/Div)

UGATE

(20V/Div)

LGATE

(5V/Div)

OUT

(10A/Div)

VIN = 12V, V

= 1V, No Load

OUT

Time (200μs/Div)

Load Transient Response

CCM Mode, VIN = 12V, V

= 1V, EN = VCC

OUT

Time (20μs/Div)

Time (100μs/Div)

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RT8228A

UGATE

(20V/Div)

MODE

(5V/Div)

OUT

(200mV/Div)

LGATE

(5V/Div)

Mode Transition CCM to DEM

VIN = 12V, V

Time (1ms/Div)

= 1V, No Load

OUT

UGATE

(20V/Div)

MODE

(5V/Div)

OUT

(200mV/Div)

LGATE

(5V/Div)

Mode Transition DEM to CCM

VIN = 12V, V

Time (1ms/Div)

= 1V, No Load

OUT

RT8228A-06 January 2014 www.richtek.com

RT8228A

)

Application Information

The RT8228A PWM controller provides high efficiency, excellent transient response, a nd high DC output a ccuracy needed for stepping down high voltage batteries to generate low voltage CPU core, I/O, and chipset RAM supplies in notebook computers. Richtek Mach ResponseTM technology is specifically designed for providing 100ns “instant-on” response to load steps while maintaining a relatively constant operating frequency a nd inductor operating point over a wide range of input voltages. The topology circumvents the poor load transient timing problems of fixed frequency current mode PWMs while avoiding the problems caused by widely varying switching frequencies in conventional constant on-ti me and consta nt off-time PWM schemes. The PSR PWM modulator is specifically designed to have better noise immunity for such a single output application.

PWM Operation

The Mach ResponseTM, PSR (Pulse Shaping Regulator) mode controller is suitable for low external component count configuration with appropri ate amount of Equivalent Series Resistance (ESR) capacitor(s) at the output. The output ripple valley voltage is monitored at a feedback point voltage. Refer to the function diagrams of the RT8228A, the synchronous high side MOSFET is turned on at the beginning of each cycle. After the intern al oneshot timer expires, the MOSFET is turned off. The pulse width of this one shot is determined by the converter's input and output voltages to keep the frequency fairly constant over the entire input voltage ra nge. Another oneshot sets a minimum off-time (400ns typ.).

On-Time Control

The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high side switch directly proportional to the output voltage and inversely proportional to the input voltage. The implementation results in a nearly constant switching

frequency without the need of a clock generator.

××

7.06p R V

t = 33ns

where R

TON

TON OUT

−

(V 0.9)

is the resistor connected from the input supply

(VIN) to the TON pin. And then the switching frequency is :

OUT

Frequency =

Mode Selection Operation

DEM (Diode Emulation Mode) and ASM (Audio Skipping Mode) operation can be enabled by driving the tri-state MODE pin to a logic high level. The RT8228A can switch operation into DEM when the MODE pin is pulled up to 5V. If MODE is pulled to 2.5V, the controller will switch operation into ASM. Finally, if the pin is pulled to GND, the RT8228A will operate in CCM mode.

Diode Emulation Mode

In diode emulation mode, the RT8228A automatically reduces switching frequency at light load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly a nd without increa sing VOUT ripple or load regulation. As the output current decreases from heavy load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low side MOSFET allows only partial of negative current when the inductor freewheeling current reach negative. As the loa d current is further decrea sed, it takes longer and longer to discharge the output capacitor to the level than requires the next “ON” cycle. The on-time is kept the same as that in the heavy load condition. In reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous condition. The tra n sition load point to the light load operation ca n be calculated as follows (Figure 1) :

−

(

IN OUT

≈×

LOAD ON

where tON is On-time.

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RT8228A

Slope = (VIN -V

OUT

) / L

PEAK

LOAD

= I

/ 2

PEAK

Figure 1. Boundary Condition of CCM/DEM

The switching waveforms may appear noisy and asynchronous when light loa ding causes diode emulation operation, but this is a normal operating condition that results in high light load efficiency. Trade offs in DEM noise vs. light load efficiency is made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. The disadvantages f or using higher inductor values include larger physical size and degrade load tra nsient response (especially at low input voltage levels).

waveform to become the complement of the high side gate drive waveform. This in turn causes the inductor current to reverse at light loads as the PWM loop to maintain a duty ratio V

OUT/VIN

. The benefit of forced-CCM mode is to keep the switching frequency fairly constant, but it comes at a cost. The no load battery current ca n be up to 10mA to 40mA, depending on the external MOSFETs.

Current Limit Setting (OCP)

The RT8228A ha s cycle-by-cycle current li miting control. The current limit circuit employs a unique “valley” current sensing algorithm. If PHASE voltage plus the current limit threshold is below zero, the PWM is not allowed to initiate a new cycle (Figure 2). In order to provide both good accuracy and a cost effective solution, the RT8228A supports temperature compensated MOSFET R

DS(ON)

sensing. The CS pin should be connected to GND through the trip voltage setting resistor, RCS. With the 10μA CS terminal source current, ICS, and the setting resistor , R

the CS trip voltage, VCS, can be calculated as shown in the following equation.

Audio Skipping Mode

When the MODE pin is pulled to 2.5V, the controller operates in audio skipping mode with a minimum switching frequency of 25kHz. This mode eliminates audio frequency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. In audio skipping mode, the low side switch gate driver signal is ORed with an internal oscillator (>25kHz). Once the internal oscillator is triggered, the audio skipping controller pulls LGA TE logic high, turning on the low side MOSFET to induce a negative inductor current. After the output voltage rises above V

, the controller turns off the low

REF

side MOSFET (LGATE pulled logic low) and triggers a constant on-time operation (UGATE driven logic high). When the on-time operation expires, the controller reenables the low side MOSFET until the inductor current drops below the zero crossing threshold.

VCS (mV) = RCS (kΩ) x 10 (μA) x (1 / 10) Inductor current is monitored by the voltage between the

PGND pin a nd the PHASE pin, so the PHASE pin should be connected to the drain terminal of the low side MOSFET. ICS has positive temperature coefficient to compensate the temperature dependency of the R

DS(ON)

PGND is used as the positive current sensing node so PGND should be connected to the source terminal of the bottom MOSFET .

As the comparison is done during the OFF state, V

sets the valley level of the inductor current. Thus, the load current at over current threshold, I

LOAD_OC

, can be

calculated as f ollows.

CS Ripple

I = +

LOAD_OC

= +

R2 x Lf V

DS(ON) IN

DS(ON)

−×

VV V

()

IN OUT OUT

Forced-CCM Mode

The low noise, forced-CCM mode (MODE = GND) disables the zero-crossing comparator, which controls the low side switch on-time. This causes the low side gate drive

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RT8228A

PEAK

LOAD

LIM

Figure 2. V alley Current Li mit

MOSFET Gate Driver (UGATE, LGA TE)

The high side driver is designed to drive high current, low R

N-MOSFET (s). When configured as a floating

DS(ON)

driver, 5V bi a s voltage is delivered from the V DDP supply . The average drive current is proportional to the gate charge at VGS = 5V times switching frequency . The insta ntaneous drive current is supplied by the flying capacitor between BOOT and PHASE pins. A dead time to prevent shoot through is internally generated between high side MOSFET off to low side MOSFET on and low side MOSFET off to high side MOSFET on. The low side driver is designed to drive high current, low R

N-MOSFET (s).

DS(ON)

The internal pull down transistor that drives LGA TE low is robust, with a 0.8Ω typical on resistance. A 5V bia s voltage is delivered from the V DDP supply . The instanta neous drive current is supplied by the flying cap acitor between VDDP and GND.

For high current application s, some combinations of high and low side MOSFETs might be encountered that will cause excessive gate drain coupling, which can lead to efficiency killing, EMI-producing shoot through currents. This is often remedied by adding a resistor in series with BOOT, which increases the turn-on time of the high side MOSFET without degrading the turn-off time (Figure 3).

BOOT

UGATE

Power Good Output (PGOOD)

The power good output is an open drain output a nd requires a pull-up resistor. When the output voltage is 25% a bove or 10% below its set voltage, PGOOD gets pulled low. It is held low until the output voltage returns to within these tolerances once more. In soft-start, PGOOD is actively held low and is allowed to tra nsition high until soft-start is over and the output rea ches 93% of its set voltage. There is a 2.5μs delay built into PGOOD circuitry to prevent false transitions.

POR, UVLO and Soft-Start

Power On Reset (POR) occurs when VCC rises above to

a pproximately 3.9V , the R T8228A will reset the fault latch and preparing the PWM for operation. Below 3.7V, the VCC Under Voltage Lockout (UVLO) circuitry inhibits

switching by keeping UGATE and LGATE low. A built-in soft-start is used to prevent surge current from power supply input after EN is enabled. A current ramping up limit threshold can elimin ate the V

folded-back in the soft-

OUT

start duration. The typical soft-start duration is 900μs.

Output Over Voltage Protection (OVP)

The output voltage can be continuously monitored for over voltage protection. When the output voltage exceeds 25% of the set voltage threshold, over voltage protection is triggered and the low side MOSFET is latched on. This activates the low side MOSFET to discharge the output cap acitor . The RT8228A is latched once OVP is triggered and ca n only be released by VCC or EN power on reset. There is a 5μs delay built into the over voltage protection circuit to prevent false transitions.

Output Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under voltage protection. When the output voltage is less than 70% of the set voltage threshold, under voltage protection is triggered and then both UGA TE and LGA TE gate drivers are forced low . During soft-start, the UVP bla nking time is

4.5ms.

PHASE

Output V oltage Setting (FB)

The output voltage can be adjusted from 0.5V to 3.3V by

Figure 3. Reducing the UGA TE Rise T ime

setting the feedback resistor R1 a nd R2 (Figure 4). Choose

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RT8228A

)

R2 to be approxi mately 10kΩ, and solve f or R1 using the equation :

⎛⎞

V = V 1+

OUT REF

where V

⎜⎟ ⎝⎠

is 0.5V.(typ.)

REF

UGATE PHASE

LGATE

GND

OUT

Figure 4. Setting VOUT with a Resistor Divider

Output Inductor Selection

The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value a s follows :

L =

IR LOAD(MAX)

×−

TVV

(

ON IN OUT

where LIR is the ratio of peak-of-pea k ripple current to the maximum average inductor current. Find a low pass inductor having the lowest possible DC resistance that fits in the allowed dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive an d can work well at 200kHz. The core must be large enough and not to saturate at the pea k inductor current (I

⎡⎤

⎛⎞

I = I + I

PEAK LOAD(MAX) LOAD(MAX)

⎢⎥ ⎣⎦

⎜⎟

⎝⎠

PEAK

) :

Output Capacitor Selection

The output filter ca pacitor must have low enough Equivalent Series Resistance (ESR) to meet output ripple a nd loa dtransient requirements, yet have high enough ESR to satisfy stability requirements. The output capacitance must also be high enough to absorb the inductor energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault latch.

by an external circuit to reduce the jitter level. The required signal level is approxi mately 15 mV at the comparing point. This generates V

RIPPLE

= (V

/ 0.5) x 15mV at the output

OUT

node. The output capacitor ESR should meet this requirement.

Thermal Considerations

For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to a mbient. The maximum power dissipation can be calculated by following formula :

P where T

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θ

is the junction to ambient thermal re sistance.

For recommended operating conditions specification of RT8228A, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For WQF N12L 2x2 pa ckage, the thermal resistance, θJA, is 165°C/ W on a standard JEDEC 51-3 single-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula :

= (125°C − 25°C) / (165°CW) = 0.606W for

D(MAX)

WQF N-12L 2x2 pa ckage The maximum power dissipation depends on the operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance, θJA. For the RT8228A package, the derating curve in Figure 5 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.

Although Mach Respon seTM DRVTM dual ramp valley mode provides many adva ntages such as ea se-of-use, minimum external component configuration, and extremely short response time, due to not employing a n error a mplifier in the loop, a sufficient feedback sign al needs to be provided

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RT8228A

0.65

0.60

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

Maximum Power Dissipation (W) 1

0.00 0 255075100125

Single-Layer PCB

Ambient Temperature (°C)

Figure 5. Derating Curves f or RT8228A Pa ckages

Layout Considerations

Layout is very important in high frequency switching converter design. If the layout is designed improperly , the PCB could radiate excessive noise a nd contribute to the converter instability . The following points must be followed for a proper layout of RT8228A.

` Connect a filter ca pacitor to VCC, 1μF to 4.7μF range is

recommended. Place the filter capacitor close to the IC.

` Keep current limit setting network a s close a s possible

to the IC. Routing of the network should avoid coupling to high voltage switching node.

` Connections from the drivers to the respective gate of

the high side or the low side MOSFET should be as short as possible to reduce stray inductance.

` All sensitive analog traces and components such as

MODE, FB, GND, EN, PGOOD, CS, VCC, and TON should be placed away from high voltage switching nodes such as PHASE, LGATE, UGATE, or BOOT nodes to avoid coupling. Use internal layer (s) a s ground plane (s) a nd shield the feedback trace from power tra ces and components.

` Current sense connections must always be made using

Kelvin connections to ensure an accurate signal, with the current limit resistor located at the device.

` Power sections should connect directly to ground plane

(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses.

www.richtek.com 14

RT8228A-06 January 2014

Outline Dimension

RT8228A

1 2

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010

b 0.150 0.250 0.006 0.010 D 1.900 2.100 0.075 0.083 E 1.900 2.100 0.075 0.083

e 0.400 0.016

D2 0.850 0.950 0.033 0.037

E2 0.850 0.950 0.033 0.037

L 0.250 0.350

W-Type 12L QFN 2x2 Package

0.010 0.014

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

RT8228A-06 January 2014 www.richtek.com

Richtek RT8228AGQW, RT8228AZQW Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual