Richtek RT8223LGQW, RT8223LZQW, RT8223MGQW, RT8223MZQW Schematic [ru]

High Efficiency, Main Power Supply Controller
for Notebook Computer

RT8223L/M

General Description

The RT8223L/M is a dual step-down, switch-mode power
supply controller generating logic-supply voltages in
battery-powered systems. It includes two Pulse Width
Modulation (PWM) controllers adjustable from 2V to 5.5V,
and also features fixed 5V/3.3V linear regulators. Each
linear regulator provides up to 100mA output current with
automatic linear regulator bootstrapping to the PWM
outputs. The RT8223L/M includes on-board power up
sequencing, a power good output, internal soft-start, and
soft-discharge output that prevents negative voltage during
shutdown.

The constant on-time PWM sche me can operate without
sense resistors and provide 100ns load tra nsient response
while maintaining nearly constant switching frequency . To
eliminate noise in audio a pplications, a n ultra sonic mode
is included, which maintains the switching frequency
above 25kHz. Moreover, the diode-emulation mode
maximizes efficiency for light load applications. The
RT8223L/M is available in a WQFN-24L 4x4 package.

Ordering Information

RT8223

Features

zz

z Constant On-time Control with 100ns Load Step

zz

Response

zz

z Wide Input Voltage Range : 6V to 25V

zz

zz

z Dual Adjustable Outputs from 2V to 5.5V

zz

zz

z Fixed 3.3V and 5V LDO Output : 100mA

zz

zz

z 2V Reference Voltage

zz

zz

z Frequency Selectable via TONSEL Setting

zz

zz

z 4700ppm/

zz

zz

z Programmable Current Limit Combined with

zz

°°

°C R

°°

Current Sensing

DS(ON)

Enable Control

zz

z Selectable PWM, DEM, or Ultrasonic Mode

zz

zz

z Internal Soft-Start and Soft-Discharge

zz

zz

z High Efficiency up to 97%

zz

zz

z 5mW Quiescent Power Dissipation

zz

zz

z Thermal Shutdown

zz

zz

z RoHS Compliant and Halogen Free

zz

Applications

z Notebook and Sub-Notebook Computers
z 3-Cell and 4-Cell Li+ Battery-Powered Devices

Package Type
QW : WQFN-24L 4x4 (W-Type)

Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)

Pin Function
L : Default
M : With ENC

Note :
Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

DS8223L/M-04 April 2011 www.richtek.com

1

RT8223L/M

Marking Information

RT8223LGQW RT8223MGQW

EP= : Product Code

EP=YM

DNN

YMDNN : Date Code

EQ=YM

DNN

EQ= : Product Code
YMDNN : Date Code

RT8223LZQW

EP : Product Code

EP YM

YMDNN : Date Code

DNN

Pin Configurations

VOUT1

PGOOD

BOOT1

FB1

REF

FB2

1
2
3
4
5
6

78910 1211

VOUT2

VREG3

GND

BOOT2

ENTRIP1

TONSEL

ENTRIP2

UGATE1

PHASE1

21 20 1924 2223

25

PHASE2

UGATE2

LGATE1

18
17
16
15
14
13

LGATE2

NC
VREG5
VIN
GND
SKIPSEL
EN

RT8223MZQW

(TOP VIEW)

EQ YM

DNN

EQ : Product Code
YMDNN : Date Code

FB1

REF

FB2

1
2
3
4
5
6

ENTRIP1

TONSEL

ENTRIP2

VOUT1

UGATE1

PGOOD

BOOT1

21 20 1924 2223

GND

25

78910 1211

VOUT2

VREG3

BOOT2

UGATE2

PHASE1

PHASE2

LGATE1

18
17
16
15
14
13

LGATE2

ENC
VREG5
VIN
GND
SKIPSEL
EN

WQFN-24L 4x4

RT8223L

WQFN-24L 4x4

RT8223M

DS8223L/M-04 April 2011www.richtek.com

2

Typical Application Circuit

1

C
0

µ

F

1

Q1

BSC119

N03S

1

L

H

µ

8

.

V

T

1

U

O

V

5

C

3

0

µ

F

2

2

1

C

1

.

0

6

5

R

BSC119

4

C

1

8

C

1

2

R
1

5

k

9

µ

1

3

R

F

1

0

k

e

q

u

e

F

r

M

/

E

M

D

P

W

Q3

N03S

V

c

y

n

U

/

l

REF

2V

C
r

t

0

n

t

o

a

n

o

s

ON

OFF

R
3

4

R

R

1

T

O

B

O

C

2

µ

F

1

.

5

1

C

.

F

2

2

µ

0

o

l

r

c

i

RT8223L/M

V

I

N

V

6

2

t

o

V

8

.

9

16

1

0

C

F

µ

1

0

.

0

21

0

22

20
19

24

2

3

4
14
13

VIN

UGATE1

BOOT1

PHASE1
LGATE1

VOUT1

FB1
REF

TONSEL
SKIPSEL
EN

RT8223L

UGATE2

BOOT2

PHASE2

LGATE2

GND

VOUT2

FB2

ENTRIP1

ENTRIP2

GND

VREG5

PGOOD

VREG3

10
9

11
12
15

7
5

1

6
25 (Exposed Pad)

17

23
8

0

1

R

0

0

R

B

O

2

O

T

Q2
BSC119

N03S

C

1

1

µ

1

0

.

F

Q4
BSC119

N03S

R

M

1

I

I

L

k

0

1

5

R

I

L

M

2

I

0

1

5

k

C

9

µ

7

.

4

F

5

R

6

k

0

0

1

P

C

6

1

.

4

µ

7

F

3

1

3

C

µ

1

0

L

2

H

µ

7

.

4

1

1

R

C

1

4

w

l

A

V

.

O

s

y

a

G

O

O

D

I

n

d

3

w

l

V

A

s

y

a

2

1

C

F

0

1

µ

F

C

1

2

2

1

4

R

k

5

6

.

1

5

R
1

k

0

n

i

a

c

r

o

t

O

n

5

V

O

2

U

T

V

3

.

3

7

0

µ

F

C

1

2

2

0

C

F

µ

1

.

0

V

I

N

V

6

2

t

o

V

R

C
µ

l

OFF

8

3

.

9

16

1

0

C

F

µ

1

0

.

R

0

4

21

0

22

R

O

T

1

O

B

2

F

20
19

24

2

5

1

C

.

F

2

2

µ

0

14
13

ON

18

VIN

UGATE1

BOOT1

PHASE1
LGATE1

VOUT1

FB1

3

REF

4

TONSEL
SKIPSEL
EN

ENC

RT8223M

UGATE2

BOOT2

PHASE2

LGATE2

GND

VOUT2

FB2

ENTRIP1

ENTRIP2

GND

VREG5

PGOOD

VREG3

10
9

11
12
15

7
5

1

6
25 (Exposed Pad)

17

23
8

1

C
0

µ

F

1

Q1

BSC119

N03S

1

L

H

µ

8

.

V

T

1

U

O

V

5

C

3

0

µ

F

2

2

1

C

1

.

0

6

5

R

BSC119

N03S

4

C

1

8

C

1

2

R
1

5

k

9

µ

1

3

R

F

1

0

k

e

q

u

n

e

F

r

M

/

E

M

D

P

W

1

0

.

Q3

V

REF

2V

r

n

t

o

C

o

c

y

c

a

n

o

s

i

U

l

/

r

t

ON

OFF

0

1

R

0

0

R

B

O

O

T

2

Q2
BSC119

N03S

C

1

1

µ

1

0

.

F

Q4
BSC119

N03S

R

1

M

I

I

L

k

0

1

5

R

2

M

I

I

L

0

1

5

k

9

C

7

.

4

F

µ

5

6

R

0

0

1

k

P

C

6

1

.

4

7

F

µ

3

1

3

C

µ

1

0

L

2

H

µ

7

.

4

1

1

R

C

1

4

l

A

V

s

y

a

w

O

G

O

O

D

I

n

d

V

A

3

.

s

y

a

w

l

2

1

C

F

0

1

µ

F

C

1

2

2

1

4

R

k

5

6

.

1

5

R
1

k

0

n

c

i

r

o

a

t

O

n

5

V

O

2

U

T

V

3

.

3

7

0

µ

F

C

1

2

2

0

C

F

µ

1

.

0

DS8223L/M-04 April 2011 www.richtek.com

3

RT8223L/M

Functional Pin Description

Pin No . Pin Na me Pin Function

Channel 1 Enable and Current Limit Setting Input. Connect a r esistor to GND to
set the thre shold for channel 1 synchr onous R

1 ENTRIP1

2 FB1

3 REF

4 TONSEL

5 FB2

6 ENTRIP2

7 VOUT2
8 VREG3 3.3V Linear Regulator Output.

9 BOOT2

10 UGATE2

11 PHASE2

12 LGATE2
13 EN

14 SKIPSEL

16 VIN Supply Input for 5V/3.3V LDO and Feed Forward On-Time circuitry.
17 VREG5

NC

18

19 LGATE1

(RT8223L)
ENC
(RT8223M)

current l imit threshold is 1/10th the vo ltage seen at ENTRIP1 over a 0.515V to 3V
range. There is an internal 10μA current source from VREG5 to ENTRIP1. Leave
ENTRIP 1 floati ng or drive it above 4.5V to shut down ch annel 1.

SMPS1 Feedback Input. Connect FB1 to a resistive voltage divider from VOUT1
to GND to adjust outpu t from 2V to 5.5V .

2V Refere nce Output. By pass to GND with a minimum 0.22μF capacitor . RE F can
source up to 100μA for external loads. Loading REF degrades FBx and output
accuracy accor ding to the REF load-regulation error.

Frequency Selectable Input for VOUT1/VOUT2 respectively.
400kHz/ 500kHz : Connect to VREG 5 or VREG3
300kHz/ 375kHz : Connect to REF
200kHz/ 250kHz : Connect to GND

SMPS2 Feedback Input. Connect FB2 to a resistive voltage divider from VOUT2
to GND to adjust outpu t voltage from 2V to 5.5V.

Channel 2 Enable and Current Limit Setting Input. Connect a r esistor to GND to
set the thre shold for channel 2 synchr onous R
current l imit threshold is 1/10th the volt age seen at ENTRI P2 over a 0.515V to 3V
range. There is an internal 10μA current source from VREG5 to ENTRIP2. Leave
ENTRIP 1 floati ng or drive it above 4.5V to shut down ch annel 2.

Bypass Pin for SMPS2. Connect to the SMPS2 output to bypass efficient power
for VREG3 pin . VOU T2 is also for the SMPS 2 out put soft-di schar ge.

Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor
according to the typical application circuits.
Upper Gate Driver Output for SMPS2. UGATE2 swings between PHASE2 and
BOOT2.
Switch Node for SMPS2. PHASE2 is the internal lower supply rail for the
UGATE2 high side gate driver. PHASE2 is also the current-sense input for the
SMPS2.
Lower Gate Driver Output for SMPS2. LGATE2 swings between GND and
VREG5.
Master Enable Input. The REF/VREG5/VREG3 are enabled if it is within logic
high level and disabled if it is less than the logic low level.
Operati on M ode Sel ect able Input .
Connect to VREG 5 or VREG3 : Ultraso nic Mode
Connect to REF : PWM Mode
Connect to GND : DEM Mode

5V Linear Regulator Output. VREG5 is also the supply voltage for the lower gate
driver and anal og supply voltage for the devi ce.

No Internal Connection.
SMPS Enable Inpu t. Pull up to VRE G 3 or VR EG 5 t o tu rn o n both switc h channels.

Sh or t to GND to shu td o w n the m .
Lower Gate Driver Output for SMPS1. LGATE1 swings between GND and
VREG5.

sense. The G ND − PHASE1

DS(ON)

sense. The G ND − PHASE2

DS(ON)

To be continued

DS8223L/M-04 April 2011www.richtek.com

4

Pin No. P in Name Pin Function

Switch Node for SMPS1. PHASE1 is the internal lower supply rail for the

20 PHASE1

UGATE1 high side gate driver. PHASE1 is also the current-sense input for the
SMPS1.

21 UGATE1

22 BOOT1

Upper Gate Driver Output for SMPS1. UGATE1 swings between P HASE1 and
BOOT1.

Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor
according to the typical application circuits.

23 PGOOD Power Good Output for Channel 1 and Channel 2. (Logical AND).
24 VOUT1

15,25

(Exposed Pad)

GND

Bypass Pin for SMPS1. Connect to the SMPS1 output to bypass effic ient power
for VREG5 pin. VOUT1 is also for the SMPS1 output soft-discharge.

Ground for SMPS Controller. The exposed pad must be soldered to a l arge PCB
and connected to GND for maximum power dissipation.

Function Block Diagram

TONSEL SKIPSEL

BOOT1

UGATE1
PHASE1

LGATE1

FB1

ENTRIP1

EN

ENC

VOUT1

VREG5

10µA

VREG5

SW5 Threshold

PWM Buck

Controller

Power-On
Sequence

Clear Fault Latch

SMPS1

SMPS2

PWM Buck

Controller

SW3 Threshold

VREG5

RT8223L/M

BOOT2

UGATE2
PHASE2

VREG5

LGATE2

10µA

VOUT2
FB2

ENTRIP2
PGOOD

GND

Thermal

Shutdown

VREG5

VIN

VREG5

REF

REF

VREG3

VREG3

DS8223L/M-04 April 2011 www.richtek.com

5

RT8223L/M

Absolute Maximum Ratings (Note 1)

z VIN, EN to GND------------------------------------------------------------------------------------------------- −0.3V to 30V
z PHASEx to GND

DC------------------------------------------------------------------------------------------------------------------ −0.3V to 30V
< 20ns ------------------------------------------------------------------------------------------------------------ −8V to 38V

z BOOTx to PHASEx-------------------------------------------------------------------------------------------- −0.3V to 6V
z ENTRIPx, SKIPSEL, TONSEL, PGOOD to GND------------------------------------------------------- −0.3V to 6V
z VREG5, VREG3, FBx , VOUTx, ENC, REF to G ND -------------------------------------------------- −0.3V to 6V
z UGATEx to PHASEx

DC------------------------------------------------------------------------------------------------------------------ −0.3V to (VREG5 + 0.3V)
< 20ns ------------------------------------------------------------------------------------------------------------ −5V to 7.5V

z LGATEx to GND

DC------------------------------------------------------------------------------------------------------------------ −0.3V to (VREG5 + 0.3V)
< 20ns ------------------------------------------------------------------------------------------------------------ −2.5V to 7.5V

z Power Dissipation, P

WQFN-24L 4x4 ------------------------------------------------------------------------------------------------- 1.923W

z Package Thermal Re sistance (Note 2)

WQF N-24L 4x4, θJA-------------------------------------------------------------------------------------------- 52°C/W
WQFN-24L 4x4, θJC------------------------------------------------------------------------------------------- 7°C/W

z Lead T e mperature (Soldering, 10 sec.)-------------------------------------------------------------------- 260°C
z Junction T emperature------------------------------------------------------------------------------------------ 15 0°C
z Storage T emperature Range --------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 3)

HBM (Human Body Mode) ----------------------------------------------------------------------------------- 2kV
MM (Ma chine Mode)------------------------------------------------------------------------------------------- 200V

@ TA = 25°C

D

Recommended Operating Conditions (Note 4)

z Supply Voltage, V

z Junction T emperature Range--------------------------------------------------------------------------------- −40°C to 125°C
z Ambient T emperature Range--------------------------------------------------------------------------------- −40°C to 85°C

-------------------------------------------------------------------------------------------- 6V to 25V

IN

DS8223L/M-04 April 2011www.richtek.com

6

RT8223L/M

Electrical Characteristics

(V

= 12V, V

IN

Parameter Symbol Test Conditions Min Typ Max Unit

Input Supply

VIN Standby Current I
VIN Shutdown Supply

Current
Quiescent Power

Consumption

SMPS Output and FB Voltage

EN

= V

ENC

= 5V, V

VIN_SBY

I

VIN_S HDN

P
+P

ENTRIP1

= V

= 2V, No Load, TA = 25°C, unless otherwise specified)

ENTRIP2

VIN = 6V to 25V, ENTRIPx = GND -- 200 -- μA

= 6V to 25V,

V

VIN

PVCC

IN

ENTRIPx = EN = GND
Bot h SM PS On, V

SK IPSEL = GND, V
(Note 5)

= 2.1V,

FBx

OUT1

= 5V, V

OUT2

= 3.3V

-- 20 40 μA

-- 5 7 mW

DEM Mode 1.975 2 2.025

FBx Voltag e V

Output Voltage Adjust
Range

V

Discharge

OUTx

Current

On-Time

On-Time Pulse W idth tON

Minimum Off-Time t
Ultrasonic Mode

Frequency

Soft-Start

Sof t -S t art Ti me t

Current Sense

ENTRIPx Source
Current
ENTRIPx Current
Temperature
Coefficient
ENTR IPx Adjust ment
Range
Current Limit
Threshold
Zero-Current
Threshold

FBx

PWM Mode (Note 6) -- 2 --

V

Ultrasonic Mode -- 2.032 --

V

SMPS1, SMPS2 2 -- 5.5 V

OUTx

V

OUTx

= 0.5V, V

TONSEL =
GND

TONSEL = REF

TONSEL =
VREG5

V

OFF

= 1.9V 200 300 400 ns

FBx

ENTRIPx

= 0V 10 45 -- mA

V

= 5.05V (200kHz) 1895 2105 2315

OUT1

V

= 3.33V (250kHz) 999 1110 1221

OUT2

= 5.05V (300kHz) 1227 1403 1579

V

OUT1

V

= 3.33V (375kHz) 647 740 833

OUT2

= 5.05V (400kHz) 895 1052 1209

V

OUT1

V

= 3.33V (500kHz) 475 555 635

OUT2

ns

SKIPSEL = VREG5 or VREG3 22 33 -- kHz

Internal Soft-Start -- 2 -- ms

SSx

I

ENTRIPx

TC

V
GND − PHASEx, V

V

IENTRIPx

ENTRIPx

= 0.9V 9.4 10 10.6 μA

In Comparison with 25°C (Note 6) -- 4700 -- ppm/°C

ENTRIPx

= I

ENTRIPx

x R

ENTRIPx

ENTRIPx

-- -- 3 V

= 2V 180 200 220 mV

GND − PHASEx in DEM -- 3 -- mV

To be continued

DS8223L/M-04 April 2011 www.richtek.com

7

RT8223L/M

Parameter Symbol Test Conditions Min Typ Max Unit

Internal Regulator and Reference

VREG5 Output Voltage V

VREG3 Output Voltage V

VREG5 Output Current I

VREG5

VREG3

VREG5

V

OUT1

V

OUT1

I

VREG5

V

OUT1

I

VREG5

V

OUT2

V

OUT2

I

VREG3

V

OUT2

I

VREG3

V

VREG5

= GND, I

< 100m A 4 .8 5 5.2

VREG5

= GN D , 6 .5V < VIN < 25V,

< 100mA

= GN D , 5 .5V < VIN < 25V,

< 50mA

= GND, I
= GN D , 6 .5V < VIN < 25V,

< 100mA

= GN D , 5 .5V < VIN < 25V,

< 50mA

= 4.5V, V

< 100mA 3.2 3.33 3.46

VREG3

= GND 100 175 250 mA

OUT1

4.75 5 5.25

4.75 5 5.25

3.13 3.33 3.5

3.13 3.33 3.5

V

V

VREG3 Output Current I
VREG5 Switch-over

Threshold to V

OUT1

VREG3 Switch-over
Threshold to V

OUT2

VREGx Switch-over
Eq uiv al ent R esi sta nc e

REF Output Voltage V
REF Load Regulation 0 < I

V

VREG3

V

V

SW5

V

SW3

VREGx to V

R

SWx

No External Load 1.98 2 2.02 V

REF

V
V
V

= 3V, V

VREG3

Rising Edge 4.6 4.75 4.9 V

OUT1

Falling Edge 4.3 4.4 4.5 V

OUT1

Rising Edge 2.975 3.125 3.25 V

OUT2

Falling Edge 2.775 2.875 2.975 V

OUT2

OUTx

< 100μA -- 10 -- mV

LOAD

= GND 100 175 250 mA

OUT2

, 10mA -- 1.5 3 Ω

REF Sink Current REF in Regulation 5 -- -- μA

UVLO

VREG5 Under Voltage
Lo c kout Threshold

VREG3 Under Voltage
Lo c kout Threshold

SMPSx off -- 2.5 -- V

Rising Edge -- 4.2 4.45
Falling Edge 3.7 3.9 4.1

Power Good

PGOOD Detect, FBx falling Edge 82 85 88

PGOOD Threshold

PGOOD Propagation
Delay

Falling Edge, 50mV Overdrive -- 10 -- μs

Hysteresis, Rising Edge with SS Delay
Time

-- 6 --

PGOOD Leakage Current High State, Forced to 5.5V -- -- 1 μA
PGOOD Output Low

Voltage

I

= 4mA -- -- 0.3 V

SINK

Fault Detection

Over Voltage Protection
Trip Threshold

Over Voltage Protection
Propagation Delay

Under Voltage Protection
Trip Threshold

V

FB_OVP

OVP Detect, FBx Rising Edge 109 112 116 %

FBx = 2.35V -- 5 -- μs

V

FB_UVP

UVP Detect, FBx Falling Edge 49 52 56 %

To be continued

DS8223L/M-04 April 2011www.richtek.com

8

V

%

RT8223L/M

Parameter Symbol Test Conditions Min Typ Max Unit

UVP Shutdown Blanking Time t

SHDN_UVP

Thermal Shutdown

Thermal Shutdown T

SHDN

Thermal Shutdown Hysteresis -- 10 -- °C

Logic Input

S K I PS EL I npu t Vol t age

ENTRIPx Input Voltage V

EN Threshold
Voltage

Logic-High VIH 2.4 -- -­Logic-Low V

ENTRIPx

-- -- 0.4

IL

EN Voltage VEN Floating, Default Enable 2.4 3.3 4.2 V

EN Current IEN

ENC Threshold

Logic-High V

IH_ENC

Voltage
(RT8223M)

Logic-Low V

IL_ENC

TONSEL Setting Voltage

Input Leakage Current

In ter nal BOO T Switch

In tern al B oos t Swit ch
On-Resistance

Power MOSFET Drivers

UGATEx On-Resistance

LGATEx On-Resistance

Dead Time

From ENTRIPx Enable -- 5 -- ms

-- 150 -- °C

Low Level (DEM Mode) -- -- 0.8

REF Lev el (PWM Mode) 1.8 -- 2.3

V
High Level (Ultrasonic Mode) 2.7 -- -­On Level (SMPS On) -- -- 3
High Level (SMPS Off) 4.5 -- --

V

V

V

= 0.2V, Source 1.5 3 5

EN

= 5V, Sink -- 3 8

V

EN

μA

2 -- --

V

-- -- 0.6
V

/ V

OUT1

V

/ V

OUT1

/ V

V

OUT1

V

TONSEL

V

= 0V or 5V −1 -- 1

ENC

= 200kHz/250kHz -- -- 0.8

OUT2

= 300kHz/375kHz 1.8 -- 2.3

OUT2

= 400kHz/500kHz 2.7 -- --

OUT2

, V

SKIPSEL

= 0V or 5V −1 -- 1

V

μA

VREG5 to BOOTx, 10mA -- 40 80 Ω

UGA TEx, Hig h State,
BOOTx to PHASEx Forced to 5V
UGA TEx, Low State,
BOOTx to PHASEx Forced to 5V

LG ATEx, Hi gh State -- 4 8

-- 4 8
Ω

-- 1.5 4

Ω

LGATEx, Low State -- 1.5 4
LGATEx Rising -- 30 -­UGATEx Rising -- 40 --

ns

DS8223L/M-04 April 2011 www.richtek.com

9

RT8223L/M

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. P
Note 6. Guaranteed by Design.

is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of

JA

JEDEC 51-7 thermal measurement standard. The measurement case position of θ
package.

+ P

VIN

VREG5

is on the exposed pad of the

JC

10

DS8223L/M-04 April 2011www.richtek.com

Typical Operating Characteristics

RT8223L/M

VOUT1 Efficiency vs. Load Current

100

90

DEM Mode

80
70
60
50
40

Eff iciency ( % ) 1

30
20
10

0

0.001 0.01 0.1 1 10

VIN = 8V , TONSEL = GND, EN = FLOA TING,

Ultrasonic Mode

PWM Mode

V

ENTRIP1

= 1.5V, V

ENTRIP2

Load Current (A)

VOUT1 Efficiency vs. Load Current

100

90

DEM Mode

80
70
60
50
40

Efficiency (%) 1

30
20
10

0

0.001 0.01 0.1 1 10

VIN = 20V

TONSEL = GND, EN = FLOA TING,

V

ENTRIP1

Load Curr ent (A)

Ultrasonic Mode

PWM Mode

= 1.5V, V

ENTRIP2

= 5V

= 5V

VOUT1 Efficiency vs. Load Current

100

90

DEM Mode

80
70

PWM Mode

= 1.5V, V

ENTRIP1

Ultrasonic Mode

ENTRIP2

60
50
40

Efficiency (%) 1

30
20
10

0

0.001 0.01 0.1 1 10

VIN = 12V
TONSEL = GND, EN = FLOA TING,

V

Load Curr ent (A)

VOUT2 Efficiency vs. Load Current

100

90

DEM Mode

80
70
60
50
40

Efficiency (%) 1

30
20
10

0

0.001 0.01 0.1 1 10

VIN = 8V
TONSEL = GND, EN = FLOA TING,
V

Load Curr ent (A)

PWM Mode

= 5V, V

ENTRIP1

Ultrasonic Mode

ENTRIP2

= 1.5V

= 5V

VOUT2 Efficiency vs. Load Current

100

90
80

DEM Mode

70
60
50
40

Efficiency (%) 1

30
20
10

0

0.001 0.01 0.1 1 10

VIN = 12V

TONSEL = GND, EN = FLOA TING,
V

ENTRIP1

Load Curr ent (A)

Ultrasonic Mode

PWM Mode

= 5V, V

ENTRIP2

= 1.5V

100

Efficiency (%) 1

VOUT2 Efficiency vs. Load Current

90
80
70
60
50
40
30
20
10

0

DEM Mode

Ultrasonic Mode

PWM Mode

VIN = 20V
TONSEL = GND,EN = FLOA TING,
V

= 5V, V

ENTRIP1

0.001 0.01 0.1 1 10

ENTRIP2

= 1.5V

Load Current (A)

DS8223L/M-04 April 2011 www.richtek.com

11

RT8223L/M

VOUT1 Switching Frequency vs. Load Current

220
200
180
160
140
120
100

80
60
40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

VIN = 8V
TONSEL = GND, EN = FLOA TING,
V

ENTRIP1

= 1.5V, V

ENTRIP2

= 5V

Ultrasonic Mode

DEM Mode

Load Current (A)

VOUT1 Switching Frequency vs. Load Current

220
200
180
160
140
120
100

80
60
40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

VIN = 20V
TONSEL = GND, EN = FLOA TING,
V

ENTRIP1

= 1.5V, V

ENTRIP2

= 5V

Ultrasonic Mode

DEM Mode

Load Current (A)

VOUT1 Switching Frequency vs. Load Current

220
200
180
160
140
120
100

80
60
40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

VIN = 12V
TONSEL = GND, EN = FLOA TING,

V

ENTRIP1

= 1.5V, V

ENTRIP2

= 5V

Ultrasonic Mode

DEM Mode

Load Current (A)

VOUT2 Switching Frequency vs. Load Current

280
260
240
220
200
180
160
140
120
100

80
60
40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

VIN = 8V
TONSEL = GND, EN = FLOA TING,
V

ENTRIP1

= 5V, V

ENTRIP2

= 1.5V

Ultrasonic Mode

DEM Mode

Load Current ( A)

VOUT2 Switching Frequency vs. Load Current

280

PWM Mode

VIN = 12V
TONSEL = GND, EN = FLOA TING,
V

ENTRIP1

= 5V, V

ENTRIP2

= 1.5V

Ultrasonic Mode

DEM Mode

Load Curr ent (A)

12

260
240
220
200
180
160
140
120
100

80
60
40

Swit ching Frequency ( kHz) 1

20

0

0.001 0.01 0.1 1 10

VOUT2 Switching Frequency vs. Load Current

280
260
240
220
200
180
160
140
120
100

80
60
40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

VIN = 20V
TONSEL = GND, EN = FLOA TING,
V

ENTRIP1

= 5V, V

ENTRIP2

= 1.5V

Ultrasonic Mode

DEM Mode

Load Curr ent (A)

DS8223L/M-04 April 2011www.richtek.com

RT8223L/M

VOUT1 Output Voltage vs. Loa d Current

5.090

5.084

5.078

5.072

5.066

5.060

5.054

5.048

5.042

5.036

5.030

5.024

Output Voltage (V) 1

5.018

5.012

5.006

5.000

0.001 0.01 0.1 1 10

VIN = 12V , TONSEL = GND, EN = FLOA TING,

Ultrasonic Mode

PWM Mode

DEM Mode

V

ENTRIP1

= 1.5V, V

Load Current (A)

VREG5 Output Voltage vs. Output Current

5.006

5.000

4.994

4.988

4.982

Output Voltage ( V ) 1

4.976

VIN = 12V , TONSEL = GND, EN = FLOA TING,

V

ENTRIP1

= V

ENTRIP2

ENTRIP2

= 5V

= 5V

VOUT2 Output Voltage vs. Load Current

3.446

3.440

3.434

3.428

3.422

3.416

3.410

3.404

3.398

Output Voltage (V) 1

3.392

3.386

3.380

0.001 0.01 0.1 1 10

VIN = 12V , TONSEL = GND, EN = FLOA TING,

Ultrasonic Mode

PWM Mode

DEM Mode

V

ENTRIP1

= 5V, V

ENTRIP2

Load Curr ent (A )

VREG3 Output Voltage vs. Output Current

3.358

3.354

3.350

3.346

3.342

3.338

Output Voltage (V) 1

3.334

VIN = 12V , TONSEL = GND, EN = FLOA TING,

V

ENTRIP1

= V

= 1.5V

ENTRIP2

= 5V

3.330
0 10203040506070

Output Current (mA)

Battery Current vs. Input Voltage

100.0

Batt ery Curr ent (mA) 1

No Load

PWM Mode

10.0

Ultrasonic Mode

1.0

DEM Mode

TONSEL = GND, EN = FLOA TING,

0.1
6 7 8 9 10 11 12 13 14 1516171819202122 23 24 25

V

ENTRIP1

= V

Inp ut Voltag e (V)

ENTRIP2

= 0.91V

2.0080

2.0072

2.0064

2.0056

2.0048

2.0040

2.0032

2.0024

2.0016

Reference Voltage (V) 1

2.0008

2.0000

4.970
0 20406080100

Output Current (mA)

Reference Voltage vs. Output Current

VIN = 12V , TONSEL = GND, EN = FLOA TING,

-10 0 10 20 30 40 50 60 70 80 90 100

Output Current (µA)

V

ENTRIP1

= V

ENTRIP2

= 5V

DS8223L/M-04 April 2011 www.richtek.com

13

RT8223L/M

Standby Input Current vs. Input Voltage

250
249
248
247
246
245
244
243
242

Standby I nput Current (µ A ) 1

241
240

7 8 9 101112131415161718192021222324

No Load,
EN = FLOATING, V

ENTRIP1

= V

Input Voltage ( V )

Reference Voltage vs. Temperature

2.011

2.008

2.005

2.002

1.999

1.996

1.993

ENTRIP2

= 5V

22
21
20
19
18
17
16
15
14
13
12
11
10

Shutdown Input Current (µA) 1

VREG5

(5V/Div)

VREG3

(2V/Div)

REF

(2V/Div)

Shutdown Input Current v s . Input Voltage

9
8

No Load, EN = GND, V

7 8 9 101112131415161718192021222324

ENTRIP1

= V

ENTRIP2

= 5V

Input Vol ta g e (V)

VREG5, VREG3 and REF Start Up

1.990

Reference Voltage (V) 1

1.987

1.984

V

OUT1

(5V/Div)

V

OUT2

(2V/Div)

PGOOD

(5V/Div)

ENC

(5V/Div)

VIN = 12V, V

EN = FLOA TING, TONSEL = GND

-50 -25 0 25 50 75 100 125

ENTRIP1

= V

ENTRIP2

= 5V,

Temperature (°C)

Power On From ENC (8223M)

No Load

VIN = 12V , T ONSEL = GND,

SKIPSEL = REF , EN = FLOATING,

V

= V

ENTRIP1

ENTRIP2

Time (1ms/Div)

= 1.5V, V

ENC

= 5V

EN

(2V/Div)

V

OUT1

(5V/Div)

V

OUT2

(2V/Div)

PGOOD

(5V/Div)

ENC

(5V/Div)

No Load, VIN = 12V, TONSEL = GND,

EN = FLOATING, V

ENTRIP1

= V

Time (400μs/Div)

Power Off From ENC (8223M)

No Load

VIN = 12V , T ONSEL = GND,

SKIPSEL = REF , EN = FLOATING,

V

= V

ENTRIP1

ENTRIP2

Time (4ms/Div)

= 1.5V, V

ENTRIP2

ENC

= 5V

= 5V

14

DS8223L/M-04 April 2011www.richtek.com

RT8223L/M

V

OUT1

(2V/Div)

PGOOD

(5V/Div)

ENTRIP1

(5V/Div)

V

OUT2

(2V/Div)

PGOOD

(5V/Div)

No Load

No Load

Power On from ENTRIP1

VIN = 12V , T ONSEL = GND,

SKIPSEL = REF , EN = FLOATING,

V

ENTRIP1

= V

ENTRIP2

Time (1ms/Div)

Power On from ENTRIP2

= 1.5V

V

OUT1

(2V/Div)

PGOOD
(5V/Div)

ENTRIP1

(5V/Div)

V

OUT2

(2V/Div)

PGOOD
(5V/Div)

Power Off from ENTRIP1

VIN = 12V , T ONSEL = GND,

SKIPSEL = REF , EN = FLOATING,

V

ENTRIP1

= V

ENTRIP2

Time (2ms/Div)

Power Off from ENTRIP2

No Load

= 1.5V

No Load

ENTRIP2

(5V/Div)

VIN = 12V , T ONSEL = GND,

SKIPSEL = REF , EN = FLOATING,

V

ENTRIP1

= V

ENTRIP2

= 1.5V

Time (1ms/Div)

VOUT1 PWM Mode Load Transient Response

V

OUT1_AC

(50mV/Div)

Inductor

Current
(5A/Div)

UGATE1

(20V/Div)

LGATE1

(5V/Div)

EN = FLOA TING, SKIPSEL = REF, I

VIN = 12V , T ONSEL = GND,

Time (20μs/Div)

OUT1

= 0A to 6A

ENTRIP2

(5V/Div)

VIN = 12V , T ONSEL = GND,

SKIPSEL = REF , EN = FLOATING,

V

ENTRIP1

= V

ENTRIP2

= 1.5V

Time (2ms/Div)

VOUT2 PWM Mode Load Transient Response

V

OUT2_AC

(50mV/Div)

Inductor

Current

(5A/Div)

UGATE2

(20V/Div)

LGATE2

(5V/Div)

EN = FLOA TING, SKIPSEL = REF, I

VIN = 12V , T ONSEL = GND,

Time (20μs/Div)

OUT2

= 0A to 6A

DS8223L/M-04 April 2011 www.richtek.com

15

RT8223L/M

V

OUT1

(2V/Div)

V

OUT2

(2V/Div)

PGOOD

(5V/Div)

OVP

No Load, VIN = 12V , T ONSEL = GND,

EN = FLOA TING, SKIPSEL = GND

Time (4ms/Div)

V

OUT1

(5V/Div)

PGOOD

(5V/Div)

UGATE1

(20V/Div)

LGATE1

(5V/Div)

UVP

VIN = 12V , TONSEL = GND,

Time (100μs/Div)

EN = FLOA TING,

SKIPSEL = REF

16

DS8223L/M-04 April 2011www.richtek.com

Application Information

RT8223L/M

The RT8223L/M is a dual, Ma ch ResponseTM DRVTM dual
ramp valley mode synchronous buck controller. The
controller is designed for low voltage power supplies for
notebook computers. Richtek's Mach Response

TM

technology is specifically designed for providing 100ns
“instant-on” response to load steps while maintaining a
relatively constant operating frequency and inductor
operating point over a wide range of input voltages. The
topology circumvents the poor load-transient timing
problems of fixed-frequency current mode PWMs while
avoiding the problems caused by widely varying switching
frequencies in conventional constant on-ti me and consta nt
off-time PWM schemes. The DRVTM mode PWM
modulator is specifically designed to have better noise
immunity for such a dual output application. The
RT8223L/M includes 5V (VREG5) a nd 3.3V (VREG3) linear
regulators. VREG5 linear regulator can step down the
battery voltage to supply both internal circuitry and gate
drivers. The synchronous-switch gate drivers are directly
powered from VREG5. When VOUT1 voltage is above

4.75V, an automatic circuit will switch the power of the
device from VREG5 linear regulator to VOUT1.

PWM Operation

TM

The Mach ResponseTM DRV

mode controller relies on
the output filter capacitor's effective series resistance
(ESR) to act as a current sense resistor, so the output
ripple voltage provides the PWM ra mp signal. Refer to the
RT8223L/M's function block diagram, the synchronous
high side MOSFET will be turned on at the beginning of
each cycle. After the internal one-shot timer expires, the
MOSFET will be turned off. The pulse width of this one
shot is determined by the converter's input voltage and
the output voltage to keep the frequency fairly constant
over the input voltage range. Another one shot sets a
minimum off-time (300ns typ.). The on-time one shot will
be triggered if the error comparator is high, the low side
switch current is below the current limit threshold, and
the minimum off-time one shot has timed out.

PWM Frequency and On-Time Control

The Mach ResponseTM control architecture runs with
pseudo constant frequency by feed-forwarding the in put

and output voltage into the on-time one-shot timer. The
high side switch on-time is inversely proportional to the
input voltage a s measured by VIN, and proportional to the
output voltage. There are two benefits of a constant
switching frequency. First, the frequency ca n be selected
to avoid noise-sensitive regions such as the 455kHz IF
band. Second, the inductor ripple current operating point
remains relatively constant, resulting in easy design
methodology and predictable output voltage ripple.
Frequency for the 3V SMPS is set at 1.25 times higher
than the frequency for 5V SMPS. This is done to prevent
audio-frequency “Beating” between the two sides, which
switch asynchronously f or each side. The frequencie s are
set by the TONSEL pin connection as shown in Table 1.
The on-time is given by :

t= K(V V)×

ON OUT IN

/

where “K”is set by the TONSEL pin connection (Table

1). The on-time guara nteed in the Electrical Characteristics
table is influenced by switching delays in the external
high side power MOSFET. Two external factors that
influence switching frequency accura cy are resistive drops
in the two conduction loops (including inductor and PC
board resistance) a nd the dead time effect. These effects
are the largest contributors to the change in frequency
with changing load current. The dea d-time effect increa ses
the effective on-time by reducing the switching frequency
. It occurs only in PWM mode (SKIPSEL= REF) when
the inductor current reverses at light or negative load
currents. With reversed inductor current, the inductor's
EMF causes PHASEx to go high earlier than normal, thus
extending the on-time by a period equal to the low-to­high dead time. For loads above the critical conduction
point, the actual switching frequency is :

f = (V V ) (t (V V V ))+×+−

OUT DROP1 ON IN DROP1 DROP2

where V

is the sum of the parasitic voltage drops in

DROP1

/

the inductor discharge path,which includes the
synchronous rectifier, inductor , and PC board resista nces.
V

is the sum of the resistances in the charging path,

DROP2

and tON is the on-time.

DS8223L/M-04 April 2011 www.richtek.com

17

RT8223L/M

Table 1. TONSEL Connection and Switching Frequency

TONSEL

SMPS 1

K-F a c t o r ( μs)

SMPS 1

Frequenc y (kHz)

SMP S 2

K-Fac tor (μs)

SMPS 2

Freq uency ( kHz)

Approximate

K-Factor Error (%)

GND 5 200 4 250 ±10

REF 3.33 300 2.67 375 ±10

VREG5 or

VREG3

2.5 400 2 500 ±10

Operation Mode Selection (SKIPSEL)

(V V )

−

The RT8223L/M supports three operation modes : Diode­Emulation Mode, Ultrasonic Mode, and Forced-CCM
Mode. User can set operation mode via the SKIPSEL pin.

Diode-Emulation Mode (SKIPSEL=GND)

In Diode-Emulation Mode, the RT8223L/M automatically
reduces switching frequency at light-load conditions to
maintain high efficiency. This reduction of frequency is
achieved smoothly . As the output current decrea ses from
heavy-load condition, the inductor current is also reduced
and eventually comes to the point when its valley touches
zero current, which is the boundary between continuous
conduction and discontinuous conduction modes. By
emulating the behavior of diodes, the low side MOSFET
allows only partial negative current when the inductor free­wheeling current becomes negative. As the load current
is further decreased, it ta kes longer and longer to discharge
the output capacitor to the level that requires the next
“ON” cycle. The on-time is kept the same as that in the
heavy-load condition. In reverse, when the output current
increases from light load to heavy-load, the switching
frequency increases to the preset value as the inductor
current reaches the continuous conduction. The tra nsition
load point to the light-load operation is shown a s f ollows
(Figure 1) :

I

L

Slope = (VIN -V

0

T

ON

OUT

) / L

I

Load

I

L, PEAK

= I

L, PEAK

t

/ 2

Figure 1. Boundary Condition of CCM/DEM

It

LOAD (SKIP) ON

where tON is the On-time.
The switching waveforms may appear noisy and

a synchronous when light loading causes Diode-Emulation
Mode operation. However this is normal and results in
high efficiency. Trade-offs in PFM noise vs. light load
efficiency is made by varying the inductor value. Generally ,
low inductor values produce a broader efficiency vs. load
curve, while higher values result in higher full-load efficiency
(assuming that the coil resista nce remains fixed) a nd less
output voltage ripple.

Penalties for using higher inductor values include larger
physical size and degraded load transient response
(especially at low input-voltage levels).

Ultrasonic Mode (SKIPSEL = V REG5 or VREG3)

The RT8223L/M activates a n unique Diode-Emulation Mode
with a minimum switching frequency of 25kHz, called the
Ultrasonic Mode. The Ultrasonic Mode avoids audio­frequency modulation that would otherwise be present
when a lightly loaded controller automatically skips
pulses. In Ultrasonic Mode, the high side switch gate driver
signal is OR with an internal oscillator (>25kHz). Once
the internal oscillator is triggered, the controller enters
constant off-time control. When output voltage reaches
the setting peak threshold, the controller turns on the low
side MOSFET until the controller detects that the inductor
current dropped has below the zero-crossing threshold.
The internal timer provides a constant of f-time control and
it is effective to regulate the output voltage under light
load conditions.

IN OUT

≈×

2L

18

DS8223L/M-04 April 2011www.richtek.com

RT8223L/M

Forced CCM Mode (SKIPSEL = REF)

The low noise, Forced CCM mode (SKIPSEL = REF)
disables the zero-crossing comparator, which controls the
low side switch on-time. This causes the low side gate­driver waveform to become the complement of the high
side gate-driver waveform. This in turn causes the inductor
current to reverse at light loads as the PWM loop to
maintain a duty ratio of V

OUT/VIN

. The benefit of Forced
CCM Mode is to keep the switching frequency fairly
constant, but it comes at a cost. The no load battery
current can be from 10mA to 40mA, depending on the
external MOSFETs.

Reference and linear Regulators (REF, VREGx)

The 2V reference (REF) is accurate within ±1% over the
entire operating temperature range, ma king REF useful
as a precision system reference. Bypass REF to GND
with a minimum 0.22μF cera mic cap acitor . REF can supply
up to 100μA for external loads. Loading REF reduces the
VOUTx output voltage slightly because of the reference
load-regulation error.

The RT8223L/M includes 5V (VREG5) a nd 3.3V (VREG3)
linear regulators. The VREG5 regulator supplies a total of
100mA for internal and external loads, including the
MOSFET gate driver and PWM controller. The VREG3
regulator supplies up to 100mA f or external loads. Bypa ss
VREG5 and VREG3 with a minimum 4.7μF ceramic
ca p acitor.

When the 5V main output voltage is above the VREG5
switch over threshold (4.75V), an internal 1.5Ω P-Channel
MOSFET switch connects VOUT1 to VREG5, while
simultaneously shutting down the VREG5 linear regulator .
Similarly , when the 3.3V main output voltage is above the
VREG3 switch over threshold (3.125V), an intern al 1.5Ω
P-Channel MOSFET switch connects VOUT2 to VREG3,
while simultaneously shutting down the VREG3 linear
regulator. It ca n decrea se the power dissi pation from the
same battery, because the converted efficiency of SMPS
is better than the converted efficiency of the linear
regulator.

Current-Limit Setting (ENTRIPx)

The RT8223L/M ha s a cycle-by-cycle current-limit control.
The current-limit circuit employs an unique “valley” current

sensing algorithm. If the magnitude of the current sense
signal at PHASEx is above the current-limit threshold, the
PWM is not allowed to initiate a new cycle (Figure 2).
The actual peak current is greater than the current-limit
threshold by an a mount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and
maximum load capability are functions of the sense
resistance, inductor value, a nd battery and output voltage.

I

L

I

L, PEAK

I

LOAD

I

LIM

0

t

Figure 2. “Valley” Current-Limit

The RT8223L/M uses the on-resistance of the synchronous
rectifier as the current-sense element and supports
temperature compensated MOSFET R
R

resistor between the ENTRIP

ILIMX

X

the current-limit threshold. The resistor R
to a current source from ENTRIPx

which is 10μA typically

,

sensing. The

DS(ON)

pin and GND sets

is connected

ILIMX

at room temperature. The current source ha s a 4700ppm/
°C temperature slope to compensate the temperature
dependency of the R

. When the voltage drop across

DS(ON)

the sense resistor or low side MOSFET equals 1/10 the
voltage across the R

resistor, positive current limit

ILIMX

will be activated. The high side MOSFET will not be turned
on until the voltage drop across the MOSFET falls below
1/10 the voltage across the R

ILIMX

resistor.
Choose a current limit resistor by following equations
V
R

ILIMx

ILIMx

= (R
= (I

x10μA)/10 = I

ILIMx

x R

ILIMx

DS(ON)

x R

ILIMx

) x 10/10μA

DS(ON)

Carefully observe the PC board layout guidelines to ensure
that noise and DC errors do not corrupt the current-sense
signal at PHASEx and GND. Mount or pla ce the IC close
to the low side MOSFET.

MOSFET Gate Driver (UGATEx, LGATEx)

The high side driver is designed to drive high-current, low
R

N-MOSFET(s). When conf igured as a floating driver ,

DS(ON)

a 5V bias voltage is delivered from the VREG5 supply.

DS8223L/M-04 April 2011 www.richtek.com

19

RT8223L/M

The average drive current is calculated by the gate charge
at VGS = 5V times the switching frequency. The
instantaneous drive current is supplied by the flying
cap acitor between the BOOTx and PHASEx pins. A dead
time to prevent shoot through is internally generated
between high side MOSFET off to the low side MOSFET
on, and the low side MOSFET of f to the high side MOSFET
on.

The low side driver is designed to drive high current, low
R
that drives LGA TE

N-MOSFET(s). The internal pull-down transist or

DS(ON)

low is robust, with a 1.5Ω typical on-

X

resistance. A 5V bia s voltage is delivered from the VREG5
supply . The instanta neous drive current is supplied by an
input cap acitor connected between V REG5 and GND.

For high current application s, some combinations of high
and low side MOSFETs might be encountered that will
cause excessive gate-drain coupling, which can lead to
efficiency killing, EMI-producing shoot-through currents.
This can be remedied by adding a resistor in series with
BOOTx, which increas es the turn-on time of the high side
MOSFET without degrading the turn-off time (Figure 3).

UVLO Protection

The RT8223L/M features VREG5 under voltage lockout
protection (UVLO). When the VREG5 voltage is lower tha n

3.9V (typ.) and the VREG3 voltage is lower than 2.5V
(typ.), both switch power supplies are shut off. This is
non-latch protection.

Power Good Output (PGOOD)

PGOOD is a n open-drain type output and requires a pull­up resistor. PGOOD is actively held low in soft-start,
standby, and shutdown. It is released when both output
voltages are above 91% of the nominal regulation point.
The PGOOD goes low if either output turns off or is 15%
below its nominal regulator point.

Output Over Voltage Protection (OVP)

The output voltage can be continuously monitored for over
voltage. If the output voltage exceeds 12% of its set voltage
threshold, the over voltage protection is triggered and the
LGA TEx low side gate drivers are forced high. This a ctivates
the low side MOSFET switch, which rapidly discharges
the output cap acitor and pulls the in put voltage downward.

V

IN

R

BOOTx

UGATEx

PHASEx

BOOT

Figure 3. Reducing the UGA TEx Rise T ime

Soft-Start

The RT8223L/M provides an interna l soft-start function to
prevent large inrush current and output voltage overshoot
when the converter starts up. The soft-start (SS)
automatically begins once the chip is enabled. During soft­start, it clamps the ramping of internal reference voltage
which is compared with FBx signal. The typical soft­start duration is 2 ms. A unique PWM duty limit control
that prevents output over voltage during soft-start period
is designed specifically for FBx floating.

The RT8223L/M is latched once OVP is triggered and ca n
only be relea sed by toggling EN, ENTRIPx or cycling VIN.
There is a 5μs delay built into the over voltage protection
circuit to prevent false alarm.

Note that the LGATEx latching high causes the output
voltage to dip slightly negative when energy has been
previously stored in the LC tank circuit. For loads that
cannot tolerate a negative voltage, pla ce a power Schottky
diode across the output to a ct a s a reverse polarity clamp.

If the over-voltage condition is caused by a short in the
high side switch, completely turning on the low side
MOSFET can create an electrical short between the
battery and GND, which will blow the fuse and disconnect
the battery from the output.

Output Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under
voltage protection. If the output is less than 52% of its set
voltage threshold, under voltage protection will be triggered,
and then both UGATEx and LGATEx gate drivers will be
forced low . The UVP will be ignored for at lea st 5ms (typ.)
after start-up or a rising edge on ENTRIPx. Toggle

20

DS8223L/M-04 April 2011www.richtek.com

RT8223L/M

ENTRIPx or cycle VIN to reset the UVP fault latch and
restart the controller.

Thermal Protection

The RT8223L/M features thermal shutdown protection to
prevent overheat damage to the device. Thermal shutdown
occurs when the die temperature exceeds +150°C. All
internal circuitry is ina ctive during thermal shutdown. The
RT8223L/M triggers thermal shutdown if VREGx is not
supplied from VOUTx, while the input voltage on VIN and
the drawing current from VREGx are too high. Even if
VREGx is supplied from VOUTx, large power dissipation
on automatic switches caused by overloading VREGx,
may also result in thermal shutdown.

Discharge Mode (Soft-Discharge)

When ENTRIPx is low and a transition to standby or
shutdown mode occurs, or the output under voltage fault
latch is set, the output discharge mode will be triggered.
During discharge mode, the output capacitors' residual
charge will be discharged to GND through an internal
switch.

Shutdown Mode

The RT8223L/M SMPS1, SMPS2, VREG3 and VREG5
have independent enabling controls. Drive EN, ENTRIP1
and ENTRIP2 below the precise input falling-edge tri p level
to place the RT8223L/M in its low power shutdown state.
The RT8223L/M consumes only 20μA of input current while
in shutdown. When shutdown mode is activated, the
reference turns off. The a ccurate 0.4V falling-edge threshold
on the EN pin can be used to detect a specific analog
voltage level as well as to shutdown the device. Once in
shutdown, the 2.4V rising-edge threshold activates,
providing sufficient hysteresis for most a pplication s.

Power Up Sequencing and On/Off Controls (ENC)

ENTRIP1 and ENTRIP2 control the SMPS power up
sequencing. When the RT8223L/M is in single channel
mode, ENTRIP1 or ENTRIP2 enables the respective output
when ENTRIPx voltage descends below 3V . Furthermore,
the RT8223M can also be in dual channel mode. In this
mode, outputs are enabled when ENC voltage rises above
2V.

Table 2. Operation Mode Truth Table

MODE Condition Comment

Tr ansitions to discharge mode after a VIN POR and after

P ower UP VREG x < UVLO threshold

REF becomes valid. VREG5, VREG3, and REF remain
active.

RUN

Over V oltage

Protection

Under

Voltage

Protection

Discharge

Standby

EN = high, VOUT1 or VOU T2
enabled

E ithe r out put > 111% o f t he nom inal
level.

Either output < 52% of the nominal
level afte r 3ms time-out ex pi res an d
output is enabled

Either SMP S out put is still high in
either st andby m ode or shutd own
mode

ENTRIP

<sta rtup th resh old, EN

X

=high.

Nor ma l Oper ation.
LGATEx is forced high. VREG3, VREG5 and REF active.

Exited by VIN POR or by toggling EN, EN TRIPx, ENC
Bot h UG A TEx and LGA TEx are forced low and ente r

discharge mode. VR EG3, VRE G5 and REF ar e activ e.
Exited by VIN POR or by toggling EN, EN TRIPx, ENC

During discharge mode, there is one path to discharge the
outputs capacitor residual charge. That is output capacitor
discharge to GND through an inter nal switch.

VR EG 3, VREG 5 and RE F are active.

Shutdown EN =low All circuitry off.

Thermal

Shutdown

> +150°C

T

J

All circuitry off. Exit by VIN POR or by toggling EN, ENTRIPx,
ENC

DS8223L/M-04 April 2011 www.richtek.com

21

RT8223L/M

Table 3. Power Up Sequencing

EN

(V)

ENC

(V)

ENTRIP1 ENTRIP2 REF VREG5 VREG3 SMPS1 SMPS2

Low Low X X Off Off Off Off Off

“>2.4V”

=> High

“>2.4V”

=> High

“>2.4V”

=> High

“>2.4V”

=> High

“>2.4V”

=> High

Output Voltage Setting (FBx)

Connect a resistor voltage-divider at the FBx pin between
VOUTx and GND to a djust the respective output voltage
between 2V and 5.5V (Figure 4). Referring to Figure 4 as
an example, choose R2 to be approximately 10kΩ, and
solve for R1 using the equation :

VV1

where V

=×+

OUTX FBX

is 2V .

FBX

Low X X On On On Off Off

“>2V”

=> High

“>2V”

=> High

“>2V”

=> High

“>2V”

=> High

Off Off On On On Off Off

Off On On On On Off On

On Off On On On On Off

On On On On On On On

where LIR is the ratio of the peak to pea k ripple current to
the average inductor current.

Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted di mensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and ca n work well at 200kHz. The core must

R1

⎛⎞

⎛⎞

⎜⎟

⎜⎟

R2

⎝⎠

⎝⎠

be large enough not to saturate at the peak inductor current
(I

) :

PEAK

II (LIR/2)I

=+×

PEAK LOAD(MAX) LOAD(MAX)

⎡⎤
⎣⎦

V

IN

V

UGATEx
PHASEx

LGATEx

VOUTx

FBx

Figure 4. Setting V

with a Resistor V oltage Divider

OUTX

OUTx

R1

R2

Output Inductor Selection

The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as shown in
the following equation :

×−

()

tVV

ON IN OUTx

=

L

22

×

LIR I

LOAD(MAX)

The calculation above shall serve a s a general reference.
To further improve the transient response, the output
inductance ca n be reduced even further. This needs to be
considered along with the selection of the output ca pacitor .

Output Capacitor Selection

The capacitor value and ESR determine the amount of
output voltage ripple and loa d transient response. Thus,
the capa citor value must be greater than the largest value
calculated from below equations :

V

OUTx

()

V

IN

⎡⎤

⎛⎞

−

VV

IN OUTx

⎢⎥

⎜⎟

V

⎝⎠

⎣⎦

IN

DS8223L/M-04 April 2011www.richtek.com

V

SAG

V

SOAR

(I ) L K t

Δ×××+

=

×× ×× −

2C V K t

OUT OUTx OFF(MIN)

(I ) L

Δ×

LOAD

=

2

CV

××

OUT OUTx

2

LOAD OFF(MIN)

2

RT8223L/M

V LIR I ESR

=× × +

P P LOAD(MAX)

−

⎛⎞
⎜⎟
⎝⎠

where V

SAG

and V

are the allowable amount of

SOAR

1

8C f

××

OUT

undershoot voltage the and overshoot voltage in load
transient, V

is the output ripple voltage, t

p-p

OFF(MIN)

is the

minimum off-time, and K is a factor listed in Ta ble 1.

Thermal Considerations

For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and a mbient temperature. The
maximum power dissipation can be calculated by the
following formula :

P
where T

the ambient te mperature, and θ

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

JA

is the maximum junction temperature, T

is the junction to ambient

JA

A

thermal resistance.
For recommended operating condition specifications of

the RT8223L/M, the maximum junction temperature is
125°C and TA is the ambient temperature. The junction to
a mbient thermal resistance, θJA, is layout dependent. For
WQF N-24L 4x4 pa ckages, the thermal resista nce, θJA, is
52°C/W on a standard JEDEC 51-7 f our-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :

P

= (125°C − 25°C) / (52°C/W) = 1.923W for

D(MAX)

WQF N-24L 4x4 pa ckage
The maximum power dissipation depends on the operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance, θJA. For the RT8223L/M package, the derating
curve in Figure 5 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.

2.1

1.8

1.5

1.2

0.9

0.6

0.3

Four-Layer PCB

Maximum Pow er Dissi pation (W) 1

0.0
0 25 50 75 100 125

Ambient Temperat ure (°C)

Figure 5. Derating Curve f or the RT8223L/M Package

Layout Considerations

Layout is very important in high frequency switching
converter designs, the PCB could radiate excessive noise

is

and contribute to the converter instability with improper
layout. Certain points must be considered before starting
a layout using the RT8223L/M.

` Place the filter capacitor close to the IC, within 12mm

(0.5 inch) if possible.

` Keep current limit setting network a s close a s possible

to the IC. Routing of the network should avoid coupling
to high voltage switching nodes.

` Connections from the drivers to the respective gate of

the high side or the low side MOSFET should be as
short as possible to reduce stray inductance. Use

0.65mm (25mils) or wider trace.

` All sensitive analog traces and components such as

VOUTx, FBx, GND, ENTRIPx, PGOOD, a nd T ONSEL
should be placed away from high voltage switching
nodes such as PHASEx, LGA TEx, UGA TEx, or BOOTx
nodes to avoid coupling. Use internal layer(s) a s ground
plane(s) and shield the feedba ck trace from power tra ces
and components.

` Place the ground terminal of VIN capacitor(s), VOUTx

cap acitor(s), a nd source of low side MOSFET s a s close
as possible. The PCB trace defined as PHASEX node,
which connects to source of high side MOSFET, drain
of low side MOSFET and high voltage side of the
inductor, should be as short and wide as possible.

DS8223L/M-04 April 2011 www.richtek.com

23

RT8223L/M

Outline Dimension

D

E

A

A3

A1

D2

SEE DETAIL A

1

be

E2

L

1
2

1

2

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 3.950 4.050 0.156 0.159
D2 2.300 2.750 0.091 0.108

E 3.950 4.050 0.156 0.159
E2 2.300 2.750 0.091 0.108

e 0.500 0.020
L 0.350 0.450

Richtek Technology Corporation

Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: [phone] Fax: [phone]

0.014 0.018

W-Type 24L QFN 4x4 Package

Richtek Technology Corporation

Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: [phone] Fax: [phone]
Email: [e-mail]

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

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24