Richtek RT8207PGQW, RT8561DGQW Schematic

®

RT8207P

Complete DDRII/DDRIII/Low-Power DDRIII/DDRIV Memory Power Supply Controller

General Description

The RT8207P provides a complete power supply for both

DDRII/DDRIII/Low-Power DDRIII/DDRIV memory systems.

It integrates a synchronous PWM buck controller with a

1.5A sink/source tracking linear regulator and buffered low

noise reference.

The PWM controller provides the high efficiency, excellent

transient response, and high DC output accuracy needed

for stepping down high voltage batteries to generate low

voltage chipset RAM supplies in notebook computers.

The constant-on-time PWM control scheme handles wide

input/output voltage ratios with ease and provides 100ns

“instant-on” response to load transients while maintaining

a relatively constant switching frequency.

The RT8207P achieves high efficiency at a reduced cost

by eliminating the current sense resistor found in

traditional current mode PWMs. Efficiency is further

enhanced by its ability to drive very large synchronous

rectifier MOSFETs. The buck conversion allows this device

to directly step down high voltage batteries for the highest

possible efficiency.

The 1.5A sink/source LDO maintains fast transient

response, only requiring 20μF of ceramic output

capacitance. In addition, the LDO supply input is available

externally to significantly reduce the total power losses.

The RT8207P supports all of the sleep state controls

placing VTT at high-Z in S3 and discharging VDDQ, VTT

and VTTREF (soft-off) in S4/S5.

The RT8207P has all of the protection features including

thermal shutdown and is available in a WQFN-20L 3x3

packages.

Features

zz

z PWM Controller

zz

``

` Resistor Progra mmable Current Limit by Low Side

``

R

``

` Quick Load Step Response Within 100ns

``

` 1% V

``

` Fixed 1.8V (DDRII), 1.5V (DDRIII) or Adjustable

``

DS(ON)

Sense

Accuracy Over Line and Load

VDDQ

0.75V to 3.3V Output Range for 1.35V (Low-Power DDRIII) and 1.2V (DDRIV)

``

` 4.5V to 26V Battery Input Range

``

` Resistor Programmable Frequency

``

` Over/Under Voltage Protection

``

` Internal Current Limit Ramp Soft-Start

``

` Drives Large Synchronous-Re ctifier FETs

``

` Power Good Indicator

``

zz

z 1.5A LDO (VTT), Buffered Reference (VTTREF)

zz

``

` Capable to Sink and Source 1.5A

``

` External Input Available to Minimize Power Losses

``

` Integrated Divider Tracks 1/2 VDDQ for Both VTT

``

and VTTREF

``

` Buffered Low Noise 10mA VTTREF Output

``

` Remote Sensing (VTTSNS)

``

±±

``

`

±20mV Accuracy for Both VTTREF and VTT

``

±±

``

` Supports High-Z in S3 and Soft-Off in S4/S5

``

zz

z RoHS Compliant and Halogen Free

zz

Ordering Information

RT8207P

Package Type QW : WQFN-20L 3x3 (W-Type)

Lead Plating System G : Green (Halogen Free and Pb Free)

Applications

z DDRI/II/III/Low-Power DDRIII/DDRIV Memory Power

Supplies

z Notebook Computers

z SSTL18, SSTL15 and HSTL Bus Termination

©

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

DS8207P-01 October 2013 www.richtek.com

1

RT8207P

Marking Information

4B= : Product Code

4B=YM

DNN

YMDNN : Date Code

Pin Configurations

(TOP VIEW)

VTT

VLDOIN

VTTGND

VTTSNS

VTTREF

1

2

3

GND

VDDQ VDD

GND

4

S3

FB

WQFN-20L 3x3

BOOT

S5

17181920

21

9876

UGATE

16

10

TON

PHASE

15

14

13

12

115

PGOOD

LGATE PGND CS VDDP

©

DS8207P-01 October 2013www.richtek.com

2

Typical Application Circuit

9

V

D

P

V

5

C

1

F

µ

1

2

R

k

0

1

D

O

G

P

V

T

/

T

R

E

F

C

o

n

V

D

Q

D

C

o

n

1

R

.

5

1

2

C

F

µ

1

o

l

r

t

r

t

o

l

3

,

2

1

E

x

p

(

1

2

1

3

R

k

6

.

5

1

3

1

0

7

8

o

s

e

P

d

a

d

)

1

4 1

R

T

O

N

V

D

P

D

V

S

C

D

O

G

O

P

S

3

S5

D

N

G

PGND VTTGND

RT8207P

V

I

N

4

.

5

t

V

2

o

6

R

N

T

O

6

2

0

k

5

8

2

0

7

P

1

B

O

T

U

P

L

V

T

V

T

1

G

A

T

E

1

H

A

S

E

1

G

A

T

E

6

F

B

1

L

D

N

O

I

5

D

V

D

Q

2

V

T

2

T

S

N

S

4

T

R

E

F

R

0

8

0

6

R

7

4

C 0

.

1

µ

F

6

5

Q

B

S

C

2

0

3

2

N

0

3

S

9

0

C

8

1

0

µ

F

C

3

n

F

V

C

9

1

0

x

F

µ

3

V

D

Q

2

1

.

Q

1

B

S

C

0

9

L

1

µ

4

N

0

3

S

p

O

*

:

t

V 0

x

2

H

R

7

*

C

6

5

C

o

i

n

a

l

T

.

6

V

R

*

6

R 1

*

8

k

C

9

0

k

9

0

.

V

7

C 2

2

0

µ

F

1

F

µ

Figure 1. Adjustable Voltage Regulator

V

I

N

4

5

t

.

V

o

2

6

R

T

N

O

6

2

0

k

R

T

8

2

0

7

9

T

O

V

P

D

V

5

C

1

F

µ

1

2

R

k

0

1

D

O

G

P

V

T

V

T

/

T

R

E

F

C

o

n

V

D

Q

C

o

n

1

R

.

1

5

2

C

µ

1

o

l

r

t

o

l

r

t

3

,

2

E

1

(

3

R

F

.

6

5

x

p

o

s

e

d

P

1

k

1

a

d

1

2

V

1

V

3

C

0

P

7

S

8

S5

)

G

4

PGND

1

VTTGND

N

D

P

D

S

O

G

3

D

N

P

1

B

U

G

P

H

L

G

D

O

V

L

V

T

V

T

8

O

T

1

7

A

T

E

1

6

A

S

E

1

5

A

T

E

5

D

Q

1

9

O

D

I

N

2

0

V

T

2

S

N

S

4

R

E

F

6

F

B

5

0

R

6

4

C 0

1

.

µ

F

Q

B

S

C

C 3

3

2

0

3

2

N

0

3

S

7

C 1

0

x

µ

F

3

n

F

V G

V

8

C 1

0

µ

F

x

2

V

D

Q

1

8

.

1

5

V

/

.

Q

1

B

S

C

0

9

L

1

µ

4

0

N

3

S

V

T

0

9

.

V

0

/

H

R

7

*

5

C

*

p

O

*

:

o

n

i

t

a

7

.

5

V

C

6

2

0

µ

F

l

2

o

f

r

D

R

I

V

D

P

D

N

o

f

D

I

r

D

I

R

I

Figure 2. Fixed Voltage Regulator for

DS8207P-01 October 2013 www.richtek.com

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3

RT8207P

Functional Pin Description

Pin No. Pin Name Pin Function

1 VTTGND Power Ground Output for VTT LDO.

2 VTTSNS

3,

21 (Exposed Pad)

4 VTTREF Buffered Reference Output.

5 VDDQ

6 FB

7 S3 S3 Signal Input.

8 S5 S5 Signal Input

9 TON Set the UGATE on time through a pull-up resistor connecting to VIN.

GND

Voltage Sense Input for VTT LDO. Connect to the terminal of the VTT LDO output capacitor.

Analog Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum thermal dissipation.

Reference Input for VTT and VTTREF. Discharge current sinking terminal for VDDQ non-tracking discharge. Output voltage feedback input for VDDQ output i f the FB pi n is connected to VDD or GND. VDDQ Output Setting. Connect to GND for DDR3 (V supply. Connect to VDD for DDR2 (V a resistive voltage divider from VDDQ to GND to adjust the output of PWM from

0.75V to 3.3V.

= 1.5V) power

VDD Q

= 1.8V) power supply. Or connect to

VDDQ

10 PGOOD

11 VDD Supply Input for Analog Supply.

12 VDDP Supply Input for LGATE Gate Driver.

13 CS

14 PGND Power Ground for Low Side MOSFET.

15 LGATE Low Side Gate Driver Output for VDDQ.

16 PHASE

17 UGATE High Side Gate Driver Output for VDDQ.

18 BOOT Boost Flying Capacitor Connection for VDDQ.

19 VLDOIN Power Supply for VTT LDO.

20 VTT Power Output for VTT LDO.

Power Good Open Drain Output. In High state when VDDQ output voltage is within the target range.

Current Limit Threshold Setting Input. Connect to VDD through the voltage setting resistor.

Switch Node. External inductor connection for VDDQ and behave as the current sense comparator input for Low Side MOSFET R

DS(ON)

sensing.

4

©

DS8207P-01 October 2013www.richtek.com

Function Block Diagram

Buck Controller

TRIG

0.75V V

On-time

Compute

1-SHOT

REF

VDDQ

TON

Comp

-

+

RT8207P

BOOT

R

PWM

QS

DRV

UGATE

FB

VDD

S5

VTT LDO

116%V

70% V

REF

+

-

+

-

90% V

SS Timer

OV

UV

S1 Q

REF

VDDQ

Latch

-

+

Thermal

Shutdown

Min. T

OFF

QTRIG

1-SHOT

Diode

Emulation

PGOOD

+ +

-

SS Int.

GM

PHASE

VDDP

DRV

+

-

10µA

LGATE

PGND

CS

S5

S3

VTTSNS

GND

©

Tracking

Discharge

110% V

90% V

VTTREF

Thermal

Shutdown

+

-

+

VTTREF

+

-

+

-

+

-

VLDOIN

VTT

VTTGND

DS8207P-01 October 2013 www.richtek.com

5

RT8207P

Absolute Maximum Ratings (Note 1)

z Supply Input Voltage, TON to GND------------------------------------------------------------------------------------- −0.3V to 32V

z BOOT to PHASE ----------------------------------------------------------------------------------------------------------- −0.3V to 6V

z VDD, VDDP, CS, S3, S5, VTTSNS, VDDQ, VTTREF, VTT, VLDOIN,

FB, PGOOD to GND ------------------------------------------------------------------------------------------------------- −0.3V to 6V

z PGND, VTTGND to GND -------------------------------------------------------------------------------------------------- −0.3V to 0.3V

z PHASE to GND

DC------------------------------------------------------------------------------------------------------------------------------ −1V to 32V

< 20ns ------------------------------------------------------------------------------------------------------------------------ −8V to 38V

z LGATE to GND

DC------------------------------------------------------------------------------------------------------------------------------ −0.3V to 6V

< 20ns ------------------------------------------------------------------------------------------------------------------------ −2.5V to 7.5V

z UGATE to PHASE

DC------------------------------------------------------------------------------------------------------------------------------ −0.3V to 6V

< 20ns ------------------------------------------------------------------------------------------------------------------------ −5V to 7.5V

z The Other Pins -------------------------------------------------------------------------------------------------------------- −0.3V to 6.5V

z Power Dissipation, P

WQFN-20L 3x3 ------------------------------------------------------------------------------------------------------------- 1.471W

z Package Thermal Resistance (Note 2)

WQFN-20L 3x3, θJA-------------------------------------------------------------------------------------------------------- 68°C/W

WQFN-20L 3x3, θJC------------------------------------------------------------------------------------------------------- 7.5°C/W

z Junction Temperature ------------------------------------------------------------------------------------------------------ 150°C

z Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------- 260°C

z Storage Temperature Range --------------------------------------------------------------------------------------------- − 65°C to 150°C

z ESD Susceptibility (Note 3)

HBM (Human Body Model)----------------------------------------------------------------------------------------------- 2kV

@ T

D

= 25°C

A

Recommended Operating Conditions (Note 4)

z Supply Input Voltage, VIN ------------------------------------------------------------------------------------------------ 4.5V to 26V

z Control Voltage, VDD, VDDP -------------------------------------------------------------------------------------------- 4.5V to 5.5V

z Junction Temperature Range --------------------------------------------------------------------------------------------- −40°C to 125°C

z Ambient Temperature Range --------------------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics

(V

= 15V, V

IN

PWM Controller

Quiescent Supply Current (V

+ V

DD

TON Operating Current R

I

VLDOIN

I

VLDOIN

6

©

DD

= V

VDDP

= 5V, R

TON

= 1MΩ, T

= 25°C, unless otherwise specified)

A

Parameter Symbol Test Conditions Min Typ Max Unit

DDP

)

BIAS Current V

Standby Current V

FB forced above the regulation point, V

= 5V, VS3 = 0V

S5

= 1MΩ -- 15 -- μA

TON

= VS3 = 5V, VTT = No Load -- 1 -- μA

S5

= 5V, V

= 0V, VTT = No Load -- 0.1 10 μA

S3

-- 470 1000 μA

DS8207P-01 October 2013www.richtek.com

RT8207P

Parameter Symbol Test Conditions Min Typ Max Unit

PWM Controller

VDD + V

Shutdown Current

= V

(V

S5

S3

= 0V)

FB Reference Voltage V

Fixed VDDQ Output Voltage

I

SHDN

V

REF

TON -- 0.1 5 S5/S3 = 0V −1 0.1 1

I

VLDOIN

= 4.5V to 5.5V 0.742 0.75 0.758 V

DD

FB = GND -- 1.5 --

FB = V

FB Input Bias Current FB = 0.75V −1 0.1 1 μA

VDDQ Voltage Range 0.75 -- 3.3 V

On-Time R

TON

= 1MΩ, V

Minimum Off-Time 250 400 550 ns VDDQ Input Resistance -- 100 -- kΩ

VDDQ Shutdown Discharge Resistance

V

= GND -- 15 -- Ω

S5

Current Sensing

CS Sink Current VCS > 4.5V 9 10 11 μA Current Limit Comparator

Offset

(V

VDD−CS

R

CS

= 10kΩ

Zero Crossing Threshold GND − PHASE −5 -- 10 mV

Current Limit Threshold Setting Range

V

– VCS 50 -- 200 mV

DD

Fault Protection

Under Voltage Protection Threshold Over Voltage Protection Threshold

Over Voltage Fault Delay

VDD POR Threshold

60 70 80 %

V

UVP

V

OVP

With respect to error comparator threshold FB forced above over voltage threshold Rising edge, hysteresis = 120mV, PWM disabled below this level

Under Voltage Blank Time From S5 signal going high -- 5 -- ms

Thermal Shutdown TSD -- 165 -- °C Thermal Shutdown

Hysteresis

-- 10 -- °C

ΔT

SD

Driver On-Resistance

UGATE Driver Source R

UGATE Driver Sink R

LGATE Driver Source R

LGATE Driver Sink R

Dead Time

UGATEsr

UGATEsk

LGAT Esr

LGAT Esk

BOOT − PHASE Forced to 5V -- 2.5 5 Ω

BOOT − PHASE Forced to 5V -- 1.5 3 Ω

DL, High State -- 2.5 5 Ω

DL, Low State -- 0.8 1.6 Ω

LGATE Rising (PHASE = 1.5V) -- 40 --

UGATE Rising -- 40 --

Internal Boost Charging Switch On Resistance

VDDP to BOOT, 10mA -- -- 80 Ω

-- 1 10

VDDP

μA

-- 0.1 1

V

-- 1.8 --

DD

= 1.25V 267 334 401 ns

VDDQ

– V

GND−PHAS E

),

−15 -- 15 mV

113 116 120 %

-- 20 -- μs

3.9 4.2 4.5 V

ns

DS8207P-01 October 2013 www.richtek.com

©

7

RT8207P

Parameter Symbol Test Conditions Min Typ Max Unit

Lo gic I/O

Logic Input Low Voltage S3, S5 Low -- -- 0.8 V

Logic Input High Voltage S3, S5 High 2 -- -- V Logic Input Current S3, S5 = VDD/GND −1 0 1 μA

PGOOD (upper side threshold decide by Over Voltage threshold)

Trip Threshold (Falling)

Trip Threshold (Hysteresis) -- 3 -- %

Fault Propagation Delay

Output Low Voltage I

Leakage Current I

High state, forced to 5V -- -- 1 μA

LEAK

VTT LDO

VTT Output Tolerance V

VTT Source Current Limit I

VTT Sink Current Limit I

VTTTOL

VTTOCLSRC

VTTOCLSNK

Measured at FB, with respect to reference, no load

Falling edge, FB forced below PGOOD trip threshold

= 1mA -- -- 0.4 V

SINK

V

= V

VDDQ

⎪= 0A

⎪ I

VTT

V ⎪ I

V0.95

PGOOD = High

V

V1.05

PGOOD = High

V

= V

VDDQ

⎪< 1A

VTT

= V

VDDQ

⎪< 1.2A

VTT

= V

VDDQ

⎪< 1.5A

VTT

V

⎛⎞

=×

TT

⎜⎟ ⎝⎠

= 0V -- 1.3 --

TT

V

⎛⎞

=×

TT

⎜⎟ ⎝⎠

= V

TT

VDDQ

= 1.2V/1.35/1.5V/1.8V,

LDOIN

= 1.2V/1.35/1.5V/1.8V,

LDOIN

= 1.2V/1.35,

LDOIN

= 1.5V/1.8V,

LDOIN

VDDQ

2

VDDQ

2

,

-- 1.3 --

−13 −10 −7 %

-- 2.5 -- μs

−20 -- 20

−30 -- 30

−40 -- 40

1.6 2.6 3.6

mV

A

V

⎛⎞

VTT Leakage Current I

VTTSNS Leakage Current I

VTT Discharge Current I

VTTREF Output Voltage V

VDDQS NS/2, VTTREF Output Voltage Tolerance

VTTR EF Source Current Limit

8

©

VTTLK

VTTSNSLK

DSCHRG

VTTREF

V

VTTREFTOL

I

VTTREFOCL

S5 = 5V, S3 = 0V,

I

V

= 1mA −1 -- 1 μA

SINK

VDDQ

V

VTT REF

V

LDOIN

⎪ I

VTTREF

V

LDOIN

⎪ I

VTTREF

V

TT

= 0V, V

=

= V

= 0.5V, S5 = S3 =0V 10 30 -- mA

TT

V

⎛⎞

VDDQ

⎜⎟

2

⎝⎠

= 1.5V,

VDDQ

⎪ <10mA

= V

VDDQ

= 1.8V,

⎪ <10mA

= 0V 10 40 80 mA

VDDQ

=

⎜⎟

2

⎝⎠

−10 -- 10 μA

0.9 /

--

0.75

−15 -- 15

−18 -- 18

DS8207P-01 October 2013www.richtek.com

-- V

mV

RT8207P

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These

are stress ratings only, and functional operation of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions.

is measured at T

JA

= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

A

measured at the exposed pad of the package.

DS8207P-01 October 2013 www.richtek.com

©

9

RT8207P

Typical Operating Characteristics

VDDQ Efficiency vs. Output Current

100

DDRII

90

80

70

60

50

40

Efficiency (%) 1

30

20

10

0

0.001 0.01 0.1 1 10

VIN = 8V, V

= 1.8V, S3 = GND, S5 = 5V

DDQ

Output Current (A)

VDDQ Efficiency vs. Output Current

100

DDRII

90

80

70

60

50

40

Efficiency (%) 1

30

20

10

0

0.001 0.01 0.1 1 10

VIN = 20V, V

Output Current (A)

= 1.8V, S3 = GND, S5 = 5V

DDQ

VDDQ Efficiency vs. Output Current

100

DDRII

90

80

70

60

50

40

Efficiency (%) 1

30

20

10

0

0.001 0.01 0.1 1 10

VIN = 12V, V

= 1.8V, S3 = GND, S5 = 5V

DDQ

Output Current (A)

VDDQ Efficiency vs. Ou t put Curren t

100

DDRIII

90

80

70

60

50

40

Efficiency (%) 1

30

20

10

0

0.001 0.01 0.1 1 10

VIN = 8V, V

DDQ

Output Current (A)

= 1.5V, S3 = GND, S5 = 5V

VDDQ Efficiency vs. Output Current

100

DDRIII

90

80

70

60

50

40

Efficiency (%) 1

30

20

10

0

0.001 0.01 0.1 1 10

VIN = 12V, V

= 1.5V, S3 = GND, S5 = 5V

DDQ

Output Current (A)

©

Efficiency (%) 1

VDDQ Efficiency vs. Output Current

100

DDRIII

90

80

70

60

50

40

30

20

10

0

0.001 0.01 0.1 1 10

VIN = 20V, V

Output Current (A)

= 1.5V, S3 = GND, S5 = 5V

DDQ

DS8207P-01 October 2013www.richtek.com

10

RT8207P

Switching Frequency vs. Output Current

500

DDRII, VIN = 8V, V

450

400

350

300

250

200

150

100

Switching Frequency (kHz) 1

50

0

0.001 0.01 0.1 1 10

= 1.8V, S3 = GND, S5 = 5V

DDQ

Output Current (A)

Switching Frequency vs . Output Current

500

DDRII, VIN = 20V, V

450

400

350

300

250

200

150

100

Switching Frequency (kHz) 1

50

0

0.001 0.01 0.1 1 10

= 1.8V, S3 = GND, S5 = 5V

DDQ

Output Current (A)

Switching Frequency vs. Output Current

500

DDRII, VIN = 12V, V

450

400

350

300

250

200

150

100

Switching Frequency (kHz) 1

50

0

0.001 0.01 0.1 1 10

= 1.8V, S3 = GND, S5 = 5V

DDQ

Output Current (A)

Switching Frequency vs. Output Current

500

DDRIII, VIN = 8V, V

450

400

350

300

250

200

150

100

Switching Frequency (kHz) 1

50

0

0.001 0.01 0.1 1 10

= 1.5V, S3 = GND, S5 = 5V

VDDQ

Output Current (A)

Switching Frequency vs. Output Current

500

DDRIII, VIN = 12V, V

450

400

350

300

250

200

150

100

Switching Frequency (kHz) 1

50

0

0.001 0.01 0.1 1 10

©

= 1.5V, S3 = GND, S5 = 5V

VDDQ

Output Current (A)

Switching Frequency vs. Output Current

500

DDRIII, VIN = 20V, V

450

400

350

300

250

200

150

100

Switching Frequency (kHz) 1

50

0

0.001 0.01 0.1 1 10

Output Current (A)

= 1.5V, S3 = GND, S5 = 5V

VDD Q

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11

RT8207P

VDDQ Output Voltage v s . Output Current

Output Voltage (V) 1

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

DDRII

VIN = 12V, V

0.001 0.01 0.1 1 10

= 1.8V, S3 = GND, S5 = 5V

DDQ

Output Current (A)

VTT Output Voltage v s . Output Current

0.9000

0.8995

0.8990

DDRII

VDDQ Output Voltage vs. Output Current

1.515

DDRIII

1.510

1.505

1.500

1.495

1.490

Output Voltage (V) 1

1.485

1.480

VIN = 12V, V

0.001 0.01 0.1 1 10

= 1.5V, S3 = GND, S5 = 5V

DDQ

Output Current (A)

VTT Output Voltage vs . Output Current

0.7480

0.7475

0.7470

DDRIII

0.8985

0.8980

Output Voltage (V) 1

0.8975

0.8970

VIN = 12V, V

-1.5 -1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2 1.5

= 1.8V, S3 = S5 = 5V

DDQ

Output Current (A)

VTTREF Output Voltage vs. Output Current

Output Voltage (V) 1

0.912

0.910

0.908

0.906

0.904

0.902

0.900

0.898

DDRII

VIN = 12V, V

-10-8-6-4-20246810

= 1.8V, S3 = S5 = 5V

DDQ

Output Current (mA)

0.7465

0.7460

Output Voltage (V) 1

0.7455

0.7450

VIN = 12V, V

-1.5 -1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2 1.5

= 1.5V, S3 = S5 = 5V

DDQ

Output Current (A)

VTTREF Output Voltage vs. Output Current

0.760

0.758

0.756

0.754

0.752

0.750

Output Voltage (V) 1

0.748

0.746

DDRIII

VIN = 12V, V

-10-8-6-4-2 0 2 4 6 810

= 1.5V, S3 = S5 = 5V

DDQ

Output Current (mA)

©

DS8207P-01 October 2013www.richtek.com

12

RT8207P

1.80000

1.79675

1.79350

1.79025

1.78700

1.78375

1.78050

VDDQ Voltage (V) 1

1.77725

1.77400

Standby Current vs. Input Voltage

600

No Load, S3 = GND, S5 = 5V

580

560

540

520

Standby Current (µA) 1

500

480

5 8 11 14 17 20 23 26

Input Voltage (V)

VDDQ Voltage vs. Temperature

DDRII

VIN = 12V, V

-50 -25 0 25 50 75 100 125

Temperature (°C)

= 1.8V, S3 = S5 = 5V

DDQ

Shutdown Current vs. Input Voltage

3.00

No Load, S3 = S5 = GND

2.50

2.00

1.50

1.00

Shutdown Current (µA) 1

0.50

0.00 5 8 11 14 17 20 23 26

Input Voltage (V)

VDDQ Voltage vs. Temperature

1.502

1.498

1.494

1.490

1.486

1.482

VDDQ Voltage (V) 1

1.478

1.474

DDRIII

VIN = 12V, V

-50 -25 0 25 50 75 100 125

= 1.5V, S3 = GND, S5 = 5V

DDQ

Temperature (°C)

VDDQ and VTT Start Up

No Load

V

DDQ

(1V/Div)

V

TT

(500mV/Div)

PGOOD

(5V/Div)

S5

(5V/Div)

VIN = 12V, V

= 1.5V, S3 = S5 = 5V

DDQ

Time (1ms/Div)

©

V

DDQ

(1V/Div)

I

L

(10A/Div)

UGATE

(20V/Div)

LGATE

(5V/Div)

VDDQ Start Up

VIN = 12V, V

S3 = GND, S5 = 5V, I

Time (400μs/Div)

DDQ LOAD

= 1.5V

= 10A

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13

RT8207P

V

DDQ

(1V/Div)

V

TT

(1V/Div)

V

TTREF

(500mV/Div)

S5

(5V/Div)

V

DDQ

(50mV/Div)

I

L

(10A/Div)

UGATE

(20V/Div)

LGATE

(10V/Div)

Shutdown

Tracking Mode

VIN = 12V V

= 1.5V, S3 = S5 = 5V

DDQ

Time (400μs/Div)

VDDQ Load Transient Response

DDRIII, VIN = 12V, V I

= 0.1A to 10A

LOAD

= 1.5V, S3 = GND, S5 = 5V

DDQ

No Load

V

DDQ

(50mV/Div)

I

L

(10A/Div)

UGATE

(20V/Div)

LGATE

(10V/Div)

V

TT

(20mV/Div)

V

TTREF

(20mV/Div)

I

VTT

(2A/Div)

VTT - V

TTREF

(20mV/Div)

VDDQ Load Transient Response

DDRII, VIN = 12V, V

I

= 0.1A to 10A

LOAD

= 1.8V, S3 = GND, S5 = 5V,

DDQ

Time (20μs/Div)

VTT Load Transient Response

DDRII, VIN = 12V, V I

= −1.5A to 1.5A

VTT

= 1.8V, S3 = S5 = 5V,

DDQ

Time (20μs/Div)

VTT Load Transient Response

DDRIII, VIN = 12V, V I

= −1.5A to 1.5A

V

TT

VTT

= 1.5V, S3 = S5 = 5V,

DDQ

No Load

Time (200μs/Div)

OVP

(20mV/Div)

V

TTREF

(20mV/Div)

I

VTT

(2A/Div)

VTT - V

TTREF

(20mV/Div)

Time (200μs/Div)

©

V

DDQ

(1V/Div)

PGOOD

(5V/Div)

LGATE

(5V/Div)

VIN = 12V, V

Time (40μs/Div)

= 1.5V, S3 = GND, S5 = 5V

DDQ

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14

V

DDQ

(2V/Div)

PGOOD

(5V/Div)

UGATE

(20V/Div)

LGATE

(5V/Div)

VIN = 12V, V

Time (40μs/Div)

UVP

= 1.5V, S3 = GND, S5 = 5V

DDQ

RT8207P

DS8207P-01 October 2013 www.richtek.com

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15

RT8207P

Application Information

The RT8207P PWM controller provides the high efficiency,

excellent transient response, and high DC output accuracy

needed for stepping down high voltage batteries to

generate low voltage chipset RAM supplies in notebook

computers. Richtek's Mach ResponseTM technology is

specifically designed for providing 100ns “instant-on”

response to load steps while maintaining a relatively

constant operating frequency and inductor operating point

over a wide range of input voltages. The topology

circumvents the poor load transient timing problems of

fixed-frequency current mode PWMs, while also avoiding

the problems caused by widely varying switching

frequencies in conventional constant-on-time and constant-

off-time PWM schemes. The DRVTM mode PWM

modulator is specifically designed to have better noise

immunity for such a single output application.

The 1.5A sink/source LDO maintains fast transient

response, only requiring 20μF of ceramic output

capacitance. In addition, the LDO supply input is available

externally to significantly reduce the total power losses.

The RT8207P supports all of the sleep state controls,

placing VTT at high-Z in S3 and discharging VDDQ, VTT

and VTTREF (soft-off) in S4/S5.

PWM Operation

The Mach Response

TM

DRVTM mode controller relies on

the output filter capacitor's Effective Series Resistance

(ESR) to act as a current-sense resistor, so the output

ripple voltage provides the PWM ramp signal. Referring to

the function diagrams of the RT8207P, the synchronous

high side MOSFET is turned on at the beginning of each

cycle. After the internal one-shot timer expires, the

MOSFET will be turned off. The pulse width of this one-

shot is determined by the converter's input and output

voltages to keep the frequency fairly constant over the

entire input voltage range. Another one-shot sets a

minimum off-time (400ns typ.).

On-Time Control

The on-time one-shot comparator has two inputs. One

input looks at the output voltage, while the other input

samples the input voltage and converts it to a current.

This input voltage proportional current is used to charge

an internal on-time capacitor. The on-time is the time

required for the voltage on this capacitor to charge from

zero volts to V

, thereby making the on-time of the

VDDQ

high side switch directly proportional to the output voltage

and inversely proportional to the input voltage. This

implementation results in a nearly constant switching

frequency without the need of a clock generator, as shown

below :

=−

t 3.85p x R x V / (V 0.5)

ON TON VDDQ IN

And then the switching frequency is :

=

f V / (V x t )

VDDQ IN ON

where R

is the resistor connected from VIN to the TON

TON

pin.

Diode-Emulation Mode

In diode-emulation mode, the RT8207P automatically

reduces switching frequency at light load conditions to

maintain high efficiency. This reduction of frequency is

achieved smoothly without increasing VDDQ ripples or load

regulation. As the output current decreases from heavy

load condition, the inductor current will also be reduced

and eventually come to the point where its valley touches

zero current, which is the boundary between continuous

conduction and discontinuous conduction modes. By

emulating the behavior of diodes, the low side MOSFET

allows only partial negative current to flow when the

inductor freewheeling current reaches negative. As the load

current is further decreased, it takes longer and longer

time to discharge the output capacitor to the level that

requires the next “ON” cycle. The on-time is kept the

same as that in the heavy load condition. In contrast, when

the output current increases from light load to heavy load,

the switching frequency increases to the preset value as

the inductor current reaches the continuous condition. The

transition load point to the light load operation is shown in

below figure and can be calculated as follows :

−

VV

IN VDDQ

I x t

LOAD(SKIP) ON

≈

2L

where tON is the on-time.

16

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DS8207P-01 October 2013www.richtek.com

RT8207P

A

I

L

Slope = (VIN - V

0

t

ON

VDDQ

) / L

I

PEAK

I

LOAD

= I

/ 2

PEAK

t

Figure 3. Boundary Condition of CCM/DCM

The switching waveforms may appear noisy and

asynchronous when light loading causes diode-emulation

operation, but this is a normal operating condition that

results in high light load efficiency. Trade offs in DEM

noise vs. light load efficiency is made by varying the

inductor value. Generally, low inductor values produce a

broader efficiency vs. load curve, while higher values result

in higher full load efficiency (assuming that the coil

resistance remains fixed) and less output voltage ripple.

The disadvantages for using higher inductor values include

larger physical size and degraded load transient response

(especially at low input voltage levels).

Current Limit Setting for V D DQ (CS)

The RT8207P provides cycle-by-cycle current limiting

control. The current limit circuit employs a unique “valley”

current sensing algorithm. If the magnitude of the current

sense signal at PHASE is above the current limit

threshold, the PWM is not allowed to initiate a new cycle

(Figure 4). The actual peak current is greater than the

current limit threshold by an amount equal to the inductor

ripple current. Therefore, the exact current limit

characteristic and maximum load capability are a function

of the sense resistance, inductor value, and battery and

output voltage.

I

L

I

PEAK

I

LOAD

I

LIM

0

t

Figure 4. “Valley” Current Limit

The RT8207P uses the on resistance of the synchronous

rectifier as the current sense element and supports

temperature compensated MOSFET R

setting resistor, R

, between the CS pin and VDD sets

ILIM

sensing. The

DS(ON)

the current limit threshold. The CS pin sinks an internal

10μA (typ.) current source at room temperature. This

current has a 4700ppm/°C temperature slope to

compensate the temperature dependency of R

DS(ON)

When the voltage drop across the low side MOSFET

equals the voltage across the R

setting resistor, the

ILIM

positive current limit will activate. The high side MOSFET

will not be turned on until the voltage drop across the low

side MOSFET falls below the current limit threshold.

Choose a current limit setting resistor via the following

equation :

=

RI x R /10μ

ILIM LIMIT DS(ON)

Carefully observe the PCB layout guidelines to ensure

that noise and DC errors do not corrupt the current-sense

signal seen by PHASE and PGND.

Current Protection for VTT

The LDO has an internally fixed constant over current

limiting of 2.6A while operating at normal condition. After

the first time VTT voltage comes to within 16% of its set

voltage, this over current point is reduced to 1.3A. From

then on, when the output voltage goes outside 20% of its

set voltage, the internal power good signal will transit from

high to low.

MOSFET Gate Driver (UGATE, LGA TE)

The high side driver is designed to drive high current, low

R

N-MOSFET(s). When configured as a floating

DS(ON)

driver, 5V bias voltage is delivered from the VDDP supply.

The average drive current is proportional to the gate charge

at VGS = 5V times switching frequency. The instantaneous

drive current is supplied by the flying capacitor between

the BOOT and PHASE pins.

A dead time to prevent shoot through is internally

generated between high side MOSFET off to low side

MOSFET on, and low side MOSFET off to high side

MOSFET on.

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17

RT8207P

The low side driver is designed to drive high current, low

R

N-MOSFET(s). The internal pull down transistor

DS(ON)

that drives LGATE low is robust, with a 0.8Ω typical on

resistance. A 5V bias voltage is delivered from the VDDP

supply. The instantaneous drive current is supplied by the

flying capacitor between VDDP and PGND.

For high current applications, some combinations of high

and low side MOSFETs may cause excessive gate drain

coupling, which leads to efficiency killing, EMI producing

shoot through currents. This is often remedied by adding

a resistor in series with BOOT, which increases the turn-

on rising time of the high side MOSFET without degrading

the turn-off time (Figure 5).

V

IN

BOOT

UGATE

PHASE

R

Figure 5. Increasing the UGATE Rise Time

Power Good Output (PGOOD)

The power good output is an open drain output that requires

a pull up resistor. When the output voltage is 15% above

or 10% below its set voltage, PGOOD gets pulled low. It

is held low until the output voltage returns to within these

tolerances once more. During soft-start, PGOOD is actively

held low and only allowed to transition high after soft-start

is over and the output reaches 93% of its set voltage.

There is a 2.5μs delay built into PGOOD circuitry to prevent

false transition.

POR Protection

The RT8207P has a VDDP supply power on reset

protection (POR). When the VDDP voltage is higher than

4.2V (typ.), VDDQ, VTT and VTTREF will be activated.

This is a non-latch protection.

Soft-Start

The RT8207P provides an internal soft-start function to

prevent large inrush current and output voltage overshoot

when the converter starts up. Soft-start (SS) automatically

begins once the chip is enabled. During soft-start, internal

current limit circuit gradually ramps up the inductor current

from zero. The maximum current-limit value is set

externally as described in previous section. The soft-start

time is determined by the current limit level and output

capacitor value. If the current limit threshold is set for

200mV, the typical soft-start duration is 3ms after S5 is

enabled.

The soft-start function of VTT is achieved by the current

limit and VTTREF voltage through the internal RC delay

ramp up after S3 is high. During VTT startup, the current

limit level is 2.6A. This allows the output to start up

smoothly and safely under enough source/sink ability.

Output Over Voltage Protection (OVP)

The output voltage can be continuously monitored for over

voltage. If the output exceeds 16% of its set voltage

threshold, over voltage protection is triggered and the

LGATE low side gate driver is forced high. This activates

the low side MOSFET switch which rapidly discharges

the output capacitor and reduces the input voltage. There

is a 5μs latch delay built into the over voltage protection

circuit. The RT8207P will be latched if the output voltage

remains above the OV threshold after the latch delay

period and can then only be released by VDD power on

reset or S5.

Note that latching the LGATE high will cause the output

voltage to dip slightly negative when energy has been

previously stored in the LC tank circuit. For loads that

cannot tolerate a negative voltage, place a power Schottky

diode across the output to act as a reverse polarity clamp.

If the over voltage condition is caused by a short in high

side switch, turning the low side MOSFET on 100% will

create an electrical short between the battery and GND,

hence blowing the fuse and disconnecting the battery from

the output.

Output Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under

voltage. When enabled, the under voltage protection is

triggered if the output is less than 70% of its set voltage

threshold. Then, both UGATE and LGATE gate drivers will

be forced low while entering soft discharge mode. During

soft-start, the UVP has a blanking time around 5ms.

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DS8207P-01 October 2013www.richtek.com

RT8207P

Thermal Protection

The RT8207P monitors the temperature of itself. If the

temperature exceeds the threshold value, 165°C (typ.),

the PWM output, VTTREF and VTT will be shut off. The

RT8207P is latched once thermal shutdown is triggered

and can only be released by VDD power on reset or S5.

Output V oltage Setting (FB)

The RT8207P can be used as DDR2 (V

DDR3 (V

output voltage (0.75V < V

= 1.5V) power supply or as an adjustable

VDDQ

< 3.3V) by connecting the

VDDQ

= 1.8V) and

VDDQ

FB pin according to Table 1.

Table 1. FB and output voltage setting

FB VDDQ (V)

VDD 1.8 V

GND 1.5 V

FB

Resistors

Adjustable V

VTTREF

and VTT

/ 2 DDR2

VDD Q

/2 DDR3

VDDQ

/ 2

VDD Q

NOTE

0.75V < V < 3.3V

VDDQ

Connect a resistive voltage divider at FB between VDDQ

and GND to adjust the respective output voltage between

0.75V and 3.3V (Figure 6). Choose R2 to be approximately

10kΩ and solve for R1 using the equation as follows :

⎛⎞

R1

VV x 1

where V

=+

VDDQ REF

is 0.75V (typ.).

REF

UGATE

PHASE

LGATE

VDDQ

⎛⎞

⎜⎟

R2

⎝⎠

V

IN

FB

GND

R1

R2

V

VDDQ

Figure 6. Setting VDDQ with a Resistive Voltage Divider

VTT Linear Regulator and VTTREF

The RT8207P integrates a high performance low dropout

linear regulator that is capable of sourcing and sinking

currents up to 1.5A. This VTT linear regulator employs

ultimate fast response feedback loop so that small ceramic

capacitors are enough for keeping track of VTTREF within

40mV at all conditions, including fast load transient. To

achieve tight regulation with minimum effect of wiring

resistance, a remote sensing terminal, VTTSNS, should

be connected to the positive node of the VTT output

capacitor(s) as a separate trace from the VTT pin. For

stable operation, total capacitance of the VTT output

terminal can be equal to or greater than 20μF. It is

recommended to attach two 10μF ceramic capacitors in

parallel to minimize the effect of ESR and ESL. If ESR of

the output capacitor is greater than 2mΩ, insert an RC

filter between the output and VTTSNS input to achieve

loop stability. The RC filter time constant should be almost

the same or slightly lower than the time constant made

by the output capacitor and its ESR. The VTTREF block

consists of on-chip 1/2 divider, LPF and buffer. This regulator

also has sink and source capability up to 10mA. Bypass

VTTREF to GND with a 33nF ceramic capacitor for stable

operation.

VDD sources the load of VTTREF to follow half voltage of

VDDQ. If VTTREF capacitor is so large that the VTTREF

is unable to follow half VDDQ voltage at time during soft

start period, VTTREF will sink large current from VDD which

causes large voltage drop at VDDP to VDD resistor and

has the opportunity of UVLO. The following equation

provides the maximum value of VTTREF capacitor

calculation.

V

0.03

1.1 R 12 2

×+

VDD

VC

T =

SS

C =

VTTREF

Where R

VDDQ OUT

0.03 R2L

DS

VDD

T = C

××

SS VTTREF

×

V

IN

t

+×

ON

2

V1.1R12 V

××

VDDQ VDD IN

0.03

×+

is the resistor between VDDP and VDD pin.

VDDQ

VC

VDDQ OUT

0.03 R2L

DS

RDS is the turn on resistor of low-side MOSFET. C

is the capacitor on the VTTREF pin. TSS is the soft start

time for VDDQ at the no load condition.

×

t

+×

ON

VTTREF

DS8207P-01 October 2013 www.richtek.com

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19

RT8207P

)

Output Management by S3, S5 Control

In DDR2/DDR3 memory applications, it is important to

always keep VDDQ higher than VTT/VTTREF, even during

start up and shutdown. The RT8207P provides this

management by simply connecting both S3 and S5

terminals to the sleep-mode signals such as SLP_S3 and

SLP_S5 in notebook PC system. All VDDQ, VTTREF and

VTT are turned on at S0 state (S3 = S5 = high). In S3

state (S3 = low, S5 = high), VDDQ and VTTREF voltages

are kept on while VTT is turned off and left at high

impedance (high-Z) state. The VTT output is floated and

does not sink or source current in this state. In S4/S5

states (S3 = S5 = low), all of the three outputs are

disabled. The code of each state represents the following:

S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend

to disk (STD), S5 = soft OFF. (See Table 2)

Table 2. S3 and S5 truth table

STATE S3 S5 VDDQ VTTREF VTT

S0 Hi Hi On On On

S3 Lo Hi On On Off (Hi-Z)

S4/S5 Lo Lo

Off

(Discharge)

Off

(Discharge)

Off

(Discharge

where LIR is the ratio of the peak-to-peak ripple current to

the maximum average inductor current.

Find a low loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite cores

are often the best choice, although powdered iron is

inexpensive and can work well at 200kHz. The core must

be large enough not to saturate at the peak inductor current

(I

) :

PEAK

=+

I I (L /2) x I

PEAK LOAD(MAX) IR LOAD(MAX)

⎡⎤ ⎣⎦

This inductor ripple current also impacts transient-response

performance, especially at low V

− V

IN

differences.

VDDQ

Low inductor values allow the inductor current to slew

faster, replenishing charge removed from the output filter

capacitors by a sudden load step. The peak amplitude of

the output transient (V

transient. V

also features a function of the maximum

SAG

) is also a function of the output

SAG

duty factor, which can be calculated from the on-time and

minimum off-time :

V

SAG

=

2 x C x V x V x t V x (t t )

OUT VDDQ IN ON VDDQ ON OFF(MIN)

()Δ+

2

I x L x (tt )

LOAD ON OFF(MIN)

⎡⎤ ⎣⎦

−+

VDDQ and VTT Discharge Control

The RT8207P discharges VDDQ, VTTREF and VTT outputs

when S5 is low or in the S4/S5 state.

When in tracking discharge mode, the RT8207P

discharges outputs through the internal VTT regulator

transistors and VTT output tracks half of the VDDQ voltage

during this discharge. Note that the VDDQ discharge

current flows via VLDOIN to VTTGND; thus VLDOIN must

be connected to VDDQ in this mode. The internal LDO

can handle up to 1.5A and discharge quickly. After VDDQ

is discharged down to 0.15V, the terminal LDO will be

turned off and the operation mode is changed to the non-

tracking discharge mode.

Output Inductor Selection

The switching frequency (on-time) and operating point (%

ripple or LIR) determine the inductor value as follows :

t x (V V )

ON IN VDDQ

=

L

L x I

IR LOAD(MAX)

−

where minimum off-time, t

OFF(MIN)

, is 400ns typically.

Output Capacitor Selection

The output filter capacitor must have low enough ESR to

meet output ripple and load-transient requirements, yet

have high enough ESR to satisfy stability requirements.

Also, the capacitance must be high enough to absorb the

inductor energy going from a full-load to no-load condition

without tripping the OVP circuit.

For CPU core voltage converters and other applications

where the output is subject to violent load transients, the

output capacitor's size depends on how much ESR is

needed to prevent the output from dipping too low under a

load transient. Ignoring the sag due to finite capacitance :

V

ESR

−≤PP

I

LOAD(MAX)

In non-CPU applications, the output capacitor's size

depends on how much ESR is needed to maintain an

acceptable level of output voltage ripple :

V

ESR

L x I

IR LOAD(MAX)

−≤PP

20

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DS8207P-01 October 2013www.richtek.com

RT8207P

where V

is the peak-to-peak output voltage ripple.

P−P

Organic semiconductor capacitor(s) or specialty polymer

capacitor(s) are recommended.

For low input-to-output voltage differentials (VIN/V

VDDQ

<

2), additional output capacitance is required to maintain

stability and good efficiency in ultrasonic mode.

The amount of overshoot due to stored inductor energy

can be calculated as :

2

PEAK

OUT VDDQ

V

SOAR

where I

(I ) x L

=

2 x C x V

is the peak inductor current.

PEAK

Output Capacitor Stability

Stability is determined by the value of the ESR zero relative

to the switching frequency. The point of instability is given

by the following equation :

=≤

f

ESR

2 x x ESR x C 4

1

π

OUT

f

SW

Do not put high value ceramic capacitors directly across

the outputs without taking precautions to ensure stability.

Large ceramic capacitors can have a high ESR zero

frequency and cause erratic, unstable operation. However,

it is easy to add enough series resistance by placing the

capacitors a couple of inches downstream from the

inductor and connecting VDDQ or the FB voltage divider

close to the inductor.

Unstable operation manifests itself in two related and

distinctly different ways: double-pulsing and feedback loop

instability.

Double-pulsing occurs due to noise on the output or

because the ESR is so low that there is not enough voltage

ramp in the output voltage signal. This

“fools” the error

comparator into triggering a new cycle immediately after

the 400ns minimum off-time period has expired. Double

pulsing is more annoying than harmful, resulting in nothing

worse than increased output ripple. However, it may

indicate the possible presence of loop instability, which

is caused by insufficient ESR.

The easiest method for checking stability is to apply a

very fast zero-to-max load transient and carefully observe

the output-voltage-ripple envelope for overshoot and ringing.

It helps to simultaneously monitor the inductor current

with an AC current probe. Do not allow more than one

cycle of ringing after the initial step-response under- or

over-shoot.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

D(MAX)

= (T

J(MAX)

P

where T

the ambient temperature, and θ

− TA) / θ

J(MAX)

JA

is the maximum junction temperature, T

is the junction to ambient

JA

A

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

ambient thermal resistance, θJA, is layout dependent. For

WQFN-20L 3x3 package, the thermal resistance, θJA, is

68°C/W on a standard JEDEC 51-7 four-layer thermal test

board. The maximum power dissipation at TA = 25°C can

be calculated by the following formula :

P

= (125°C − 25°C) / (68°C/W) = 1.471W for

D(MAX)

WQFN-20L 3x3 package

The maximum power dissipation depends on the operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance, θJA. The derating curves in Figure 7 allow the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

is

Loop instability can result in oscillations at the output in

the form of line or load perturbations, which can trip the

over voltage protection latch or cause the output voltage

to fall below the tolerance limit.

DS8207P-01 October 2013 www.richtek.com

©

21

RT8207P

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

Maximum Power Dissipation (W) 1

0.0 0 255075100125

Four-Layer PCB

Ambient Temperature (°C)

Figure 7. Derating Curve of Maximum Power Dissipation

Layout Considerations

Layout is very important in high frequency switching

converter design. If designed improperly, the PCB could

radiate excessive noise and contribute to the converter

instability. Certain points must be considered before

starting a layout for the RT8207P.

` Connect an RC low pass filter from VDDP to VDD; 1μF

and 5.1Ω are recommended. Place the filter capacitor

close to the IC.

` Keep current limit setting network as close as possible

to the IC. Routing of the network should avoid coupling

to high voltage switching node.

` Connections from the drivers to the respective gate of

the high side or the low side MOSFET should be as

short as possible to reduce stray inductance.

` All sensitive analog traces and components such as

VDDQ, FB, PGND, PGOOD, CS, VDD, and TON should

be placed away from high voltage switching nodes such

as PHASE, LGATE, UGATE, and BOOT to avoid

coupling. Use internal layer(s) as ground plane(s) and

shield the feedback trace from power traces and

components.

` VLDOIN should be connected to VDDQ output with short

and wide trace. If different power source is used for

VLDOIN, an input bypass capacitor should be placed as

close as possible to the pin with short and wide trace.

` The output capacitor for VTT should be placed close to

the pin with short and wide connection in order to avoid

additional ESR and/or ESL of the trace.

` It is strongly recommended to connect VTTSNS to the

positive node of VTT output capacitor(s) as a separate

trace from the high current power line to avoid additional

ESR and/or ESL. If it is needed to sense the voltage of

the point of the load, it is recommended to attach the

output capacitor(s) at that point. It is also recommended

to minimize any additional ESR and/or ESL of ground

trace between the GND pin and the output capacitor(s).

` Current sense connections must always be made using

Kelvin connections to ensure an accurate signal, with

the current limit resistor located at the device.

` Power sections should connect directly to ground

plane(s) using multiple vias as required for current

handling (including the chip power ground connections).

Power components should be placed as close to the IC

as possible to minimize loops and reduce losses.

22

©

DS8207P-01 October 2013www.richtek.com

Outline Dimension

RT8207P

1

2

DETAIL A

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimension s In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.150 0.250 0.006 0.010

D 2.900 3.100 0.114 0.122

D2 1.650 1.750 0.065 0.069

E 2.900 3.100 0.114 0.122

E2 1.650 1.750 0.065 0.069

1

2

e 0.400 0.016

L 0.350 0.450

0.014 0.018

W-Type 20L QFN 3x3 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS8207P-01 October 2013 www.richtek.com

23

Richtek RT8207PGQW, RT8561DGQW Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual