Richtek RT8206LGQW, RT8206LZQW, RT8206MGQW, RT8206MZQW Schematic

®

High Efficiency, Main Power Supply Controller for Notebook Computers

RT8206L/M

General Description

The RT8206L/M dual step-down, Switch-Mode Power-

Supply (SMPS) controller generates logic-supply voltages

in battery-powered systems. The RT8206L/M includes two

Pulse-Width Modulation (PWM) controllers fixed at 5V/

3.3V or adjustable from 2V to 5.5V. An optional external

charge pump can be monitored through SECFB (RT8206L).

This device also features a linear regulator providing a

fixed 5V output. The linear regulator provides up to 70mA

output current with automatic linear regulator bootstrapping

to the BYP input. The RT8206L/M includes on-board

power-up sequencing, the power good outputs, internal

soft-start, and internal soft-discharge output that prevents

negative voltages on shutdown.

A constant on-time PWM control scheme operates without

sense resistors and provides 100ns response to load

transients while maintaining a relatively constant switching

frequency. The unique ultrasonic mode maintains the

switching frequency above 25kHz, which eliminates noise

in audio applications. Other features include Diode-

Emulation Mode (DEM), which maximizes efficiency in

light-load applications, and fixed frequency PWM mode,

which reduces RF interference in sensitive application.

The RT8206L/M is available in a WQFN-32L 5x5 package.

Ordering Information

RT8206

Features

zz

z Wide Input Voltage Range 6V to 25V

zz

z Dual Fixed 5V/3.3V Outputs or Adjustable from 2V

zz

to 5.5V, 1.5% Accuracy

zz

z Secondary Feedback Input Maintains Charge Pump

zz

V oltage (RT8206L)

zz

z Independent Enable and Power Good

zz

z 5V Fixed LDO Output : 70mA

zz

z 2V Reference Voltage

zz

z Constant ON-Time Control with 100ns Load Step

zz

±±

±1% : 50

±±

μμ

μA

μμ

Response

zz

z Frequency Selectable via TON Setting

zz

z R

zz

Current Sensing and Progra mmable Current

DS(ON)

Limit

zz

z 4700ppm/

zz

z Selectable PWM, DEM or Ultrasonic Mode

zz

z Internal Soft-Start with Current Limiting and Soft-

zz

°°

°C R

°°

Current Sensing

DS(ON)

Discharge

zz

z High Efficiency Up to 97%

zz

z 5mW Quiescent Power Dissipation

zz

z Thermal Shutdown

zz

z RoHS Compliant and Halogen Free

zz

Applications

z Notebook and Sub-Notebook Computers

z 3-Cell and 4-Cell Li+ Battery-Powered Devices

Package Type QW : WQFN-32L 5x5 (W-Type)

Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free)

L : With SECFB M : Without SECFB

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

DS8206L/M-07 June 2012 www.richtek.com

©

1

RT8206L/M

Marking Information

RT8206LGQW

RT8206LGQW : Product Number

RT8206L

YMDNN : Date Code

GQW YMDNN

RT8206LZQW RT8206MZQW

RT8206LZQW : Product Number

RT8206L

YMDNN : Date Code

ZQW YMDNN

Pin Configurations

(TOP VIEW)

RT8206MGQW

RT8206M GQW YMDNN

RT8206M ZQW YMDNN

RT8206MGQW : Product Number

YMDNN : Date Code

RT8206MZQW : Product Number

YMDNN : Date Code

VOUT2

FB2

ILIM2

32 31 30 29

1

REF BOOT2

2

TON

3

VCC

NC

VIN

LDO

NC

4

5

6

7

8

9101112 1413

BYP

VOUT1

ENLDO

FB1

SKIP

GND

ILIM1

PGOOD2

28 27 26 25

PGOOD1

EN2

33

EN1

PHASE2

UGATE2

24

23

22

21

20

19

18

17

1615

PHASE1

UGATE1

WQFN-32L 5x5

RT8206L

LGATE2

PGND

GND

SECFB

PVCC

LGATE1

BOOT1

VOUT2

FB2

ILIM2

32 31 30 29

1

REF BOOT2

2

TON

3

VCC

NC

VIN

LDO

NC

4

5

6

7

8

9101112 1413

BYP

VOUT1

ENLDO

FB1

SKIP

GND

ILIM1

PGOOD2

28 27 26 25

PGOOD1

EN2

33

EN1

PHASE2

UGATE2

24

23

22

21

20

19

18

17

1615

PHASE1

UGATE1

WQFN-32L 5x5

RT8206M

LGATE2

PGND

GND

NC

PVCC

LGATE1

BOOT1

©

DS8206L/M-07 June 2012www.richtek.com

2

Typical Application Circuit

C

1

µ

F

0

Q1

L

1 µ

H

.

8

V

1

T

U

O

V

5

3

C

2

µ

F

0

2

6

5

R

4

C

6

C

0

.

8

C

0

.

2

D

1

µ

F

D

4

1

µ

F

CP

Q3

C

1

D

V

P

0

3

0

1

R

1

2

0

k

9

C

1

C

R

C

2

F

µ

1

.

0

5

.

1

µ

F

7

C

.

1

µ

F

2

1

R 3

9

k

R

7

RT8206L/M

V

N

I

o

t

6

V

2

5

4

1

R

.

9

3

8

1

C

F

µ

.

1

0

4

0

15

0

3

17

16

18

10

9

C

1

µ

F

20

11

32

19

6

1

C

0

1

C

6

VIN

UGATE1

BOOT1

PHASE1

LGATE1

9

BYP

VOUT1

3

VCC

SECFB/NC

FB1

FB2

PVCC

7

LDO

RT8206L/M

PGOOD1

PGOOD2

UGATE2

BOOT2

PHASE2

LGATE2

PGND

VOUT2

REF

EN1

EN2

ENLDO

ILIM1

ILIM2

TON

SKIP

GND

26

24

25

23

22

30 1

13

28

14

27

4

12

31

2

29

21, 33 (Exposed Pad)

9

R

0

8

0

R

Q2

C

1

0

1

.

µ

F

Q4

1

C

5

2

.

0

µ

F

2

5

E

V

n

a

b

e

l

3

.

n

E

a

V

b

l

e

L

D

O

C

o

r

t

n

e

F

r

q

W

P

M

R

6

1

0

k

1

R

3

1

0

k

l

R

1

8

0

k

R

2

1

8

0

k

u

e

n

c

C

o

y

n

o

r

t

E

D

/

l

t

U

M

/

s

a

r

1

3

C

1

R

C

1

0

µ

L

4

7

.

1

0

1

4

V

P

V

2

F

1

0

µ

F

2

µ

H

C

1

7

2

0

C

ON

OFF

V

N

I

l

o

n

c

i

V

O

U

T

2

V

3

.

3

µ

F

Figure 1. Fixed Voltage Regulator

DS8206L/M-07 June 2012 www.richtek.com

©

3

RT8206L/M

1

C

µ

F

0

1

L 8

.

V

1

T

U

O

V

5

C

3

µ

F

0

2

3

2

C

0

2

C

F

µ

.

1

0

6

C

6

1

0

F

µ

.

C

8

0

1

F

µ

.

CP

5

1

R

1

5

k

6

1

R

1

0

k

V

N

I

o

6

t

V

5

2

4

1

R

.

3

9

8

1

C

F

.

µ

0

1

R

0

Q1

4

R

C

1 µ

H

Q3

R

5

4

C

2

F

.

µ

0

1

15

0

3

17

16

18

10

C

5

1

D

1

0

F

µ

.

D

2

C

7

C

3

D

1

0

F

µ

.

4

D

1

R 2

0

k

9

1

C

9

1

F

µ

20

2

1

R 3

9

k

11

V

P

C

R

7

19

6

C

1

0

C

1

6

VIN

UGATE1

BOOT1

PHASE1

LGATE1

9

BYP

VOUT1

3

VCC

SECFB/NC

FB1

PVCC

7

LDO

RT8206L/M

UGATE2

BOOT2

PHASE2

LGATE2

PGND

VOUT2

FB2

REF

PGOOD1

PGOOD2

EN1

EN2

ENLDO

ILIM1

ILIM2

TON

SKIP

GND

R

9

26

24

25

0

R

0

8

C

1

0

µ

.

23

22

30

32

1

C

1

5

0

2

.

µ

F

13

28

5

E

V

n

a

e

l

14

27

4

12

31

2

29

b

3

.

E

V

n

a

b

e

l

L

D

o

C

O

o

r

n

l

t

1

e

F

r

q

u

e

n

P

W

D

/

M

21, 33 (Exposed Pad)

Q2

F

Q4

6

R

1

0

k

R

1

3

1

0

k

R

1

8

0

k

R

2

8

0

k

c

y

o

C

n

o

r

t

E

t

U

l

/

M

a

r

s

1

C

3

C

1

0

µ

L

2

4

7

H

µ

.

1

R

0

C

1

4

P

V

C

P

V

C

2

F

1

0

µ

F

1

C

7

2

0

R

1

7

.

k

6

5

R

1

8

k

0

1

ON

OFF

V

I

N

l

o

n

c

i

V

O

U

T

2

3

V

.

F

µ

2

C

2

C

2

1

0

1

F

µ

.

Figure 2. Adjustable Voltage Regulator

4

©

DS8206L/M-07 June 2012www.richtek.com

Function Block Diagram

RT8206L/M

TON SKIP

BOOT1

UGATE1

PHASE1

LGATE1

PGND

VOUT1

FB1

ILIM1

PGOOD1

GND

BYP

LDO

VIN

PV

VINTON

CC

LDO

SMPS1

PWM Buck

Controller

SW Threshold

Internal

Logic

Thermal

Shutdown

Function Block Diagram

SMPS2

PWM Buck

Controller

Power-On Sequence

Clear Fault Latch

REF

PV

BOOT2

UGATE2

PHASE2

CC

LGATE2

VOUT2

FB2 ILIM2 PGOOD2

VCC

PVCC ENLDO EN1 EN2

REF

VOUT

REF

FB

PGOOD

+

1.1 x V

0.55 x V

0.9 x V

+

-

REF

On-Time Compute

T

Comp

+

Over-Voltage

+

-

+

Under-Voltage

+

Q

1-Shot

R

TRIG

Q

ON

TRIG

Fault

Latch

Blanking

Time

SS

Time

25kHz

Detector

Zero

Detector

SKIP

PWM Controller (One Side)

T

OFF

1-Shot

+

-

+

-

Current

Limit

UGATE

LGATE

V

CC

+

ILIM

-

PHASE

©

DS8206L/M-07 June 2012 www.richtek.com

5

RT8206L/M

Functional Pin Description

REF (Pin 1)

2V Reference Output. Bypass to GND with a 0.22μF

capacitor. REF can source up to 50μA for external loads.

Loading REF degrades FBx and output accuracy according

to the REF load-regulation error.

TON (Pin 2)

Frequency Select Input. (VOUT1/VOUT2 switching

frequency, respectively) :

TON = VCC, (200kHz / 300kHz)

TON = REF, (300kHz / 400kHz)

TON = GND, (400kHz / 500kHz)

VCC (Pin 3)

Analog Supply Voltage Input for the PWM Core. Bypass

to GND with a 1μF ceramic capacitor

ENLDO (Pin 4)

LDO Enable Input. REF and LDO are enabled if ENLDO

is within logic high level and disabled if ENLDO is less

than the logic low level.

NC (Pin 5, 8)

No Internal Connection.

VIN (Pin 6)

Power Supply Input. VIN is used for the constant on-time

PWM one shot circuits. VIN is also used to power the

linear regulators. The linear regulators are powered by

SMPS1 if VOUT1 is set greater than 4.66V and BYP is

tied to VOUT1. Connect VIN to the battery input and

bypass with a 1μF capacitor.

LDO (Pin 7)

Linear-Regulator Output. LDO can provide a total of 70mA

external loads. The LDO regulates a fixed 5V output. When

the BYP is within 5V switchover threshold, the internal

regulator shuts down and the LDO output pin connects to

BYP through a 1.5Ω switch. Bypass LDO output with a

minimum of 4.7μF ceramic.

BYP (Pin 9)

Switchover Source Voltage Input for LDO.

VOUT1 (Pin 10)

SMPS1 Output Voltage Sense Input. Connect this pin to

the SMPS1 output. VOUT1 is an input to the constant

on-time-PWM one-shot circuit. It also serves as the

SMPS1 feedback input in fixed-voltage mode.

FB1 (Pin 1 1)

SMPS1 Feedback Input. Connect FB1 to VCC or GND for

fixed 5V operation. Connect FB1 to a resistive voltage-

divider from VOUT1 to GND to adjust output from 2V to

5.5V.

ILIM1 (Pin 12)

SMPS1 Current Limit Adjustment. The GND − PHASE1

current-limit threshold is 1/10th the voltage seen at ILIM1

over a 0.5V to 2.5V range. There is an internal 5μA current

source from VCC to ILIM1. The logic current limit threshold

defaults to 100mV if ILIM1 is higher than (VCC − 1V).

PGOOD1 (Pin 13)

SMPS1 Power Good Open-Drain Output. PGOOD1 is low

when the SMPS1 output voltage is more than 10% below

the normal regulation point or during soft-start. PGOOD1

is in high impedance when the output is in regulation and

the soft-start circuit has terminated. PGOOD1 is low in

shutdown.

EN1 (Pin 14)

SMPS1 Enable Input. The SMPS1 will be enabled if EN1

is greater than the logic high level and disabled if EN1 is

less than the logic low level. If EN1 is connected to REF,

SMPS1 starts after SMPS2 reaches regulation (delay

start). Drive EN1 below 0.8V to clear fault level and reset

the fault latches.

UGA TE1 (Pin 15)

High Side MOSFET Floating Gate-Driver Output for

SMPS1. UGATE1 swings between PHASE1 and BOOT1.

6

©

DS8206L/M-07 June 2012www.richtek.com

RT8206L/M

PHASE1 (Pin 16)

Inductor Connection for SMPS1. PHASE1 is the internal

lower supply rail for the UGATE1 high side gate driver.

PHASE1 is the current-sense input for the SMPS1.

BOOT1 (Pin 17)

Boost Flying Capacitor Connection for SMPS1. Connect

to an external capacitor according to the typical application

circuits.

LGA TE1 (Pin 18)

SMPS1 Synchronous-Rectifier Gate-drive Output. LGATE1

swings between PGND and PVCC.

PVCC (Pin 19)

Supply Voltage for Low Side MOSFET driver LGATEx.

Connect a 5V power source to the PVCC pin (bypass

with 1μF MLCC capacitor to PGND if necessary). There is

an internal 10Ω connecting from PVCC to VCC. Make

sure that both VCC and PVCC are bypassed with 1μF

MLCC capacitors.

SECFB (Pin 20) (RT8206L)

Charge Pump Feedback Input. The SECFB is used to

monitor the optional external charge pump. Connect a

resistive voltage-divider from the charge pump output to

GND to detect the output. If SECFB drops below the

threshold voltage, an ultrasonic pulse occurs to refresh

the external charge pump driven by LGATE1 or LGATE2

NC (Pin 20) (RT8206M)

No Internal Connection.

LGA TE2 (Pin 23)

SMPS2 Synchronous-Rectifier Gate-drive Output. LGATE2

swings between PGND and PVCC.

BOOT2 (Pin 24)

Boost Flying Capacitor Connection for SMPS2. Connect

this pin to an external capacitor according to the typical

application circuits.

PHASE2 (Pin 25)

Inductor Connection for SMPS2. PHASE2 is the internal

lower supply rail for the UGATE2 high side gate driver.

PHASE2 is the current sense input for the SMPS2.

UGA TE2 (Pin 26)

High Side MOSFET Floating Gate-Driver Output for

SMPS2. UGATE2 swings between PHASE2 and BOOT2.

EN2 (Pin 27)

SMPS2 Enable Input. The SMPS2 will be enabled if EN2

is greater than the logic high level and be disabled if EN2

is less than the logic low level. If EN2 is connected to

REF, the SMPS2 starts after the SMPS1 reaches

regulation (delay start). Drive EN2 below 0.8V to clear

fault level and reset the fault latches.

PGOOD2 (Pin 28)

SMPS2 Power Good Open-Drain Output. PGOOD2 is low

when the SMPS2 output voltage is more than 10% below

the normal regulation point or during soft-start. PGOOD2

is high impedance when the output is in regulation and

the soft-start circuit has terminated. PGOOD2 is low in

shutdown.

GND [Pin 21, 33 (Exposed Pad)]

Analog Ground for both SMPS and LDO. The exposed

pad must be soldered to a large PCB and connected to

GND for maximum power dissipation.

PGND (Pin 22)

Power Ground for SMPS Controller. Connect PGND

externally to the underside of the exposed pad.

DS8206L/M-07 June 2012 www.richtek.com

©

SKIP (Pin 29)

SMPS Operation Mode Control.

SKIP = GND : DEM Mode operation

SKIP = REF : Ultrasonic Mode operation

SKIP = VCC : PWM Mode operation.

7

RT8206L/M

VOUT2 (Pin 30)

SMPS2 Output Voltage Sense Input. Connect this pin to

the SMPS2 output. VOUT2 is an input to the constant

on-time-PWM one-shot circuit. It also serves as the

SMPS2 feedback input in fixed-voltage mode.

ILIM2 (Pin 31)

SMPS2 Current-Limit Adjustment. The GND − PHASE2

current limit threshold is 1/10th the voltage seen at ILIM2

over a 0.5V to 2.5V range. There is an internal 5μA current

source from VCC to ILIM2. The logic current limit threshold

is default to 100mV value if ILIM2 is higher than (VCC −

1V).

FB2 (Pin 32)

SMPS2 Feedback Input. Connect FB2 to VCC or GND for

fixed 3.3V operation. Connect FB2 to a resistive voltage-

divider from VOUT2 to GND to adjust output from 2V to

5.5V.

8

©

DS8206L/M-07 June 2012www.richtek.com

RT8206L/M

Absolute Maximum Ratings (Note 1)

z VIN, ENLDO to GND -------------------------------------------------------------------------------------------- –0.3V to 30V

z PHASEx to GND

DC ------------------------------------------------------------------------------------------------------------------- −0.3V to 30V

<20ns -------------------------------------------------------------------------------------------------------------- −8V to 38V

z BOOTx to PHASEx --------------------------------------------------------------------------------------------- −0.3V to 6V

z VCC, ENx, SKIP, TON, PVCC, PGOODx, to GND ----------------------------------------------------- −0.3V to 6V

z LDO, FBx, VOUTx, SECFB, REF, ILIMx to GND -------------------------------------------------------- −0.3V to (V

z UGATEx to PHASEx

DC ------------------------------------------------------------------------------------------------------------------- −0.3V to (PVCC + 0.3V)

<20ns -------------------------------------------------------------------------------------------------------------- −5V to 7.5V

z LGATEx, BYP to GND

DC ------------------------------------------------------------------------------------------------------------------- −0.3V to (PVCC + 0.3V)

<20ns -------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V

z PGND to GND ---------------------------------------------------------------------------------------------------- −0.3V to 0.3V

z Power Dissipation, P

@ TA = 25°C

D

WQFN-32L 5x5 -------------------------------------------------------------------------------------------------- 2.778W

z Package Thermal Resistance (Note 2)

WQFN-32L 5x5, θJA--------------------------------------------------------------------------------------------- 36°C/W

WQFN-32L 5x5, θJC-------------------------------------------------------------------------------------------- 6°C/W

z Junction Temperature ------------------------------------------------------------------------------------------- 150°C

z Lead Temperature (Soldering, 10 sec.)--------------------------------------------------------------------- 260°C

z Storage Temperature Range ---------------------------------------------------------------------------------- −65°C to 150°C

z ESD Susceptibility (Note 3)

HBM (Human Body Model)------------------------------------------------------------------------------------ 2kV

+ 0.3V)

CC

Recommended Operating Conditions (Note 4)

z Input Voltage, VIN ----------------------------------------------------------------------------------------------- 6V to 25V

z Junction Temperature Range ---------------------------------------------------------------------------------- −40°C to 125°C

z Ambient Temperature Range ---------------------------------------------------------------------------------- −40°C to 85°C

DS8206L/M-07 June 2012 www.richtek.com

©

9

RT8206L/M

Electrical Characteristics

(VIN = 12V, V

unless otherwise specified)

Input Supply

VIN Standby Supply Current I

VIN Shutdown Supply Current

Quiescent Power Consumption

SMPS Outp ut and FB Voltage

VOUT1 Output Voltage in Fixed Mode

VOUT2 Output Voltage in Fixed Mode

SECFB Voltage V

Output Voltage Adjust Range SMPS1, SMPS2 2 -- 5.5 V FBx Adjustable Mode

Threshold Voltage

FBx in Output Adjustable Mode

= V

EN1

EN2

CC

= 5V, V

= 5V, PVCC = 5V, V

BYP

= 5V, No Load on LDO, VOUT1, VOUT2 and REF, T

ENLDO

= 25°C,

A

Parameter Symbol Test Conditions Min Typ Max Unit

VIN_SBY

I

VIN_ SHDH

IN

V V ENx = ENLDO = GND

= 5V

ENLDO

= 6V to 25V,

IN

-- 180 250 μA

-- 20 40 μA

V

= 6V to 25V, Both SMPS Off,

Both SMPSs On,

I

Q

V

OUT1

V

OUT2

SECFB

V

LOAD

FB1 = SKIP = GND, FB2 = V V

= V

OUT1

= 3.5V (Note 5)

V

OUT2

V

= 6V to 25V, FB1= GND,

IN

V

= 5V

SKIP

= 6V to 25V, FB2 = VCC,

V

IN

V

= 5V

SKIP

= 5.3V,

BYP

VIN = 6V to 25V (RT8206L) 1.92 2 2.08 V

Fix e d or Adj- M o de com p ar a tor threshold

Either SMPS, SKIP = VCC

Either SMPS, SKIP = REF -- 2.012 -- V

CC

,

-- 5 7 mW

4.975 5.05 5.125 V

3.285 3.33 3.375 V

0.2 0.4 0.55 V

1.975 2 2.025 V

Either SMPS, SKIP = GND -- 2.012 -- V

Line Regulation V

Either SMPS, VIN = 6V to 25V -- 0.005 -- %/V

LINE

On-Time

SMPS1 = 5.05V (200kHz) 1895 2105 2315

SMPS2 = 3.33V (300kHz) 832.5 925 1018

SMPS1 = 5.05V (300kHz) 1227 1403 1579

ns

SMPS2 = 3.33V (400kHz) 606 694 782

SMPS1 = 5.05V (400kHz) 895 1052 1209

SMPS2 = 3.33V (500kHz) 475 555 635

On-Time Pulse Width tON

Minimum Off-Time t

OFF (MIN)

TON = V

CC

TON = REF

TON = GND

200 300 400 ns

Ultrasonic Mode Frequency SKIP = REF 25 33 -- kHz

Soft-Start

Soft-Start Time t

SSx

Zero to 200mV current limit threshold from ENx enable

-- 2 -- ms

Current Sense

Current Limit Threshold (Default)

Current Limit Current Source I

V

4.75 5 5.25 μA

LIMX

= VCC, GND − PHASEx 85 100 115 mV

ILIMx

10

©

DS8206L/M-07 June 2012www.richtek.com

RT8206L/M

Parameter Symbol Test Conditions Min Typ Max Unit

I

Current Temperature

LIM

Coefficient

I

Adjustment Range V

LIM

Current-Limit Threshold GND − PHASEx

Zero-Current Threshold

Internal Regulator and Reference

LDO Output Voltage V

LDO Output Current I

LDO Short-Circuit Current LDO = GND, BYP = GND -- 200 300 mA

LDO 5V Switchover Threshold to BYP LDO Sw itchover Equivalent Resistance

REF Output Voltage V

REF Load Regulation I REF Sink Current REF in Regulation 10 -- -- μA

On the basis of 25°C -- 4700 -- ppm/°C

= I

ILIMx

SKIP = GND or REF, GND − PHASEx

LDO

BYP = GND, VIN = 6V to 25V 70 -- -- mA

LDO

V

BYP

LDO to BYP, 10mA -- 1.5 3 Ω

R

SW

No External Load 1.98 2 2.02 V

REF

BYP = GND, 6V < V 0 < I

LDO

Falling Edge, Rising Edge with FB1 Regulation Point

= 0 to 50μA -- 10 -- mV

REF

× R

LIMx

< 70mA

0.5 -- 2 V

ILIMx

V

= 0.5V 40 50 60

ILIMx

V

= 1V 85 100 115

ILIMx

V

= 2V 180 200 220

ILIMx

mV

-- 3 -- mV

< 25V,

IN

4.9 5 5.1 V

4.53 4.66 4.79 V

UVLO

Rising Edge -- 4.35 4.5

PVCC UVLO Threshold V

UVLO

Falling Edge 3.9 4.05 4.2

V

Power Good

PGOODx Threshold PGOOD Detect, FBx Falling edge 86 90 94 %

PGOODx Hysteresis Rising Edge with Soft-Start Delay Time -- 3 -- %

PGOODx Propagation Delay

Falling Edge -- 10 -- μs

PGOODx Leakage Current High State, Forced to 5.5V -- -- 1 μA

PGOODx Output Low Volta ge

I

= 4mA -- -- 0.3 V

SINK

Fault Detection

OVP Trip Threshold V

FB_OVP

OVP Detect, FBx Rising edge 108 112 116 %

OVP Propagation Delay FBx with 50mV Overdrive -- 10 -- μs

UVP Trip Threshold UVP Detect, FBx Falling edge 50 55 60 %

UVP Shutdown Blanking Time

t

SHDN_UVP

From ENx Enable -- 5 -- ms

Thermal Shutdow n

Thermal Shutdown T

Thermal Shutdown Hysteresis

-- 150 -- °C

SHDN

ΔT

-- 10 -- °C

SHDN

DS8206L/M-07 June 2012 www.richtek.com

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11

RT8206L/M

Parameter Symbol Test Conditions Min Typ Max Unit

Logic Input

FB1/FB2

Input Voltage

Low-Level Internal Fixed V High-Level Internal Fixed V

SKIP Input Voltage

TON Setting Voltage

ENx Input Voltage

ENLDO Input Voltage V

ENLDO

Input Leakage Current

Internal BOOT Switch

-- -- 0.2

OUTx

V

OUTx

CC

− 1

-- --

Low Level (DEM Mode) -- -- 0.8

REF Level (Ultrasonic Mode) 1.8 -- 2.3

High Level (PWM Mode) 2.5 -- --

V

OUT1

V

OUT1

V

OUT1

/ V

(400kHz / 500kHz) -- -- 0.8

OUT2

(300kHz / 400kHz) 1.8 -- 2.3

OUT2

(200kHz / 300kHz) 2.5 -- --

OUT2

Clear Fault Level / SMPS Off Level -- -- 0.8

Delay Start 1.8 -- 2.3

SMPS On Level 2.5 -- --

Rising Edge 1.2 1.6 2.0

Falling Edge 0.94 1 1.06

V

= 0V or 25V −1 -- 3

ENLDO

= 0V or 5V −1 -- 1

ENx

, V

TON

= 0V or 5V −1 -- 1

FBx

SECFB

= 0V or 5V

SKIP

= 0V or 5V (RT8206L) −1 -- 1

−1 -- 1

V

μA

Internal Boost Charging Switch On-Resistance

PVCC to BOOTx -- 40 80 Ω

Power MOSFET Drivers

UGATEx On-Resistance

BOOTx to PHASEx Forced to 5V, High State -- 2.5 4 BOOTx to PHASEx Forced to 5V, Low State -- 1.5 3

Ω

LGATEx, High State -- 2.2 5

LGATEx On-Resistance

Ω

LGATEx, Low State -- 0.6 1.5

LGATE Rising -- 30 --

Dead Time

ns

UGATE Rising -- 40 --

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. P

is measured at T

JA

measured at the exposed pad of the package.

+ P

VIN

PVCC

= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

A

12

©

DS8206L/M-07 June 2012www.richtek.com

Typical Operating Characteristics

RT8206L/M

VOUT1 Efficiency vs. Load Current

100

DEM Mode

90

80

70

60

50

40

Efficiency (%)

30

20

10

0

0.001 0.01 0.1 1 10

Ultrasonic Mode

PWM Mode

VIN = 7V, TON = VCC, EN2 = GND, EN1 = VCC, ENLDO = V

, FB1 = GND

IN

Load Current (A)

VOUT1 Efficiency vs. Load Current

100

90

DEM Mode

80

70

60

50

40

Efficiency (%)

30

20

10

0

0.001 0.01 0.1 1 10

Load Current (A)

Ultrasonic Mode

PWM Mode

VIN = 25V, TON = VCC, EN2 = GND, EN1 = V ENLDO = V

, FB1 = GND

IN

CC

VOUT1 Effic iency vs. Load Current

100

90

DEM Mode

80

70

60

50

40

Efficiency (%)

30

20

10

0

0.001 0.01 0.1 1 10

Ultrasonic Mode

PWM Mode

VIN = 12V, TON = VCC, EN2 = GND, EN1 = V ENLDO = V

, FB1 = GND

IN

CC

,

Load Current (A)

VOUT2 Effic iency vs. Load Current

100

90

DEM Mode

80

70

60

50

40

Efficiency (%)

30

20

,

10

0

0.001 0.01 0.1 1 10

Ultrasonic Mode

PWM Mode

VIN = 7V, TON = VCC, EN2 = V

CC

ENLDO = V

Load Current (A)

, EN1 = GND,

, FB2 = GND

IN

VOUT2 Efficiency vs. Load Current

100

90

80

70

60

50

40

Efficiency (%)

30

20

10

0

©

DEM Mode

Ultrasonic Mode

PWM Mode

VIN = 12V, TON = VCC, EN2 = V ENLDO = VIN, FB2 = GND

0.001 0.01 0.1 1 10

, EN1 = GND,

CC

Load Current (A)

Efficiency (%)

VOUT2 Effic iency vs. Load Current

100

90

80

70

60

50

40

30

20

10

DEM Mode

Ultrasonic Mode

PWM Mode

VIN = 25V, TON = VCC, EN2 = V ENLDO = V

0

0.001 0.01 0.1 1 10

, EN1 = GND,

CC

, FB2 = GND

IN

Load Current (A)

DS8206L/M-07 June 2012 www.richtek.com

13

RT8206L/M

VOUT1 Switching Frequency vs. Load Current

250

VIN = 7V, TON = VCC, EN2 = GND, EN1 = VCC,

225

ENLDO = V

200

175

150

125

100

Switching Frequency (kHz) 1

PWM Mode

75

50

25

Ultrasonic Mode

0

0.001 0.01 0.1 1 10

, FB1 = GND

IN

DEM Mode

Load Current (A)

VOUT1 Switching Frequency vs. Load Current

250

VIN = 25V, TON = VCC, EN2 = GND, EN1 = VCC,

225

ENLDO = V

200

PWM Mode

175

150

125

100

75

50

Switching Frequency (kHz) 1

Ultrasonic Mode

25

0

0.001 0.01 0.1 1 10

, FB1 = GND

IN

Load Current (A)

DEM Mode

VOUT1 Switching Frequency vs. Load Current

250

VIN = 12V, TON = VCC, EN2 = GND, EN1 = VCC,

225

ENLDO = V

200

PWM Mode

175

150

125

100

75

50

Switching Frequency (kHz) 1

Ultrasonic Mode

25

0

0.001 0.01 0.1 1 10

, FB1 = GND

IN

DEM Mode

Load Current (A)

VOUT2 Switching Frequency vs . Loa d Current

350 325 300 275 250 225 200 175 150 125 100

Switching Frequency (kHz) 1

PWM Mode

VIN = 7V, TON = VCC, EN2 = VCC, EN1 = GND, ENLDO = V FB2 = GND

75

Ultrasonic Mode

50 25

0

0.001 0.01 0.1 1 10

,

IN

DEM Mode

Load Current (A)

VOUT2 Switching Frequency vs. Load Current

350 325 300 275 250 225 200 175 150 125 100

Switching Frequency (kHz) 1

PWM Mode

VIN = 12V, TON = VCC, EN2 = VCC, EN1 = GND, ENLDO = V FB2 = GND

75

Ultrasonic Mode

50 25

0

0.001 0.01 0.1 1 10

,

IN

DEM Mode

Load Current (A)

©

VOUT2 Switching Frequency vs. Load Current

350 325

PWM Mode

300 275 250

VIN = 25V, TON = VCC, EN2 = VCC,

225

EN1 = GND, ENLDO = V

200

FB2 = GND

175 150 125 100

75

Ultrasonic Mode

50

Switching Frequency (kHz) 1

25

0

0.001 0.01 0.1 1 10

Load Current (A)

,

IN

DEM Mode

DS8206L/M-07 June 2012www.richtek.com

14

LDO Output Voltage vs. Output Current

5.04

VIN = 12V, EN1 = EN2 = GND, ENLDO = V

5.036

RT8206L/M

V

vs. Output Current

IN

2.00500

2.00475

2.00450

VIN = 12V, EN1 = EN2 = GND, ENLDO = V

REF

IN

5.032

5.028

Output Voltage (V)

5.024

5.02 0 10203040506070

Output Current (mA)

No Load Battery Current vs. Input Voltage

100

TON = VCC, EN1 = EN2 = VCC, ENLDO = V

PWM Mode

10

Ultrasonic Mode

1

Battery Current (mA)

DEM Mode

0.1 7 9 11 13 15 17 19 21 23 25

Input Voltage (V)

2.00425

(V)

2.00400

REF

V

2.00375

2.00350

2.00325

2.00300

-10 0 10 20 30 40 50

Output Current (μA)

Standby Current vs. Input Voltage

216

IN

Standby Current (μA) 1

No Load, EN1 = EN2 = GND, ENLDO = V

214

212

210

208

206

204

202

200

198

7 9 11 13 15 17 19 21 23 25

Standby Current

Input Voltage (V)

IN

Shutdown Current vs . Input Voltage

27

No Load on VOUT1, VOUT2, LDO and REF,

25

EN1 = EN2 = GND, ENLDO = GND

23

21

19

17

15

13

Shutdown Current (μA) 1

11

9

7 9 11 13 15 17 19 21 23 25

Shutdown Current

Input Voltage (V)

©

2.05

2.04

2.03

2.02

2.01

(V)

2.00

REF

V

1.99

1.98

1.97

1.96

1.95

-40 -25 -10 5 20 35 50 65 80 95 110 125

V

vs. Te m pe rature

REF

Temp erature (°C)

VIN = 12.6V

DS8206L/M-07 June 2012 www.richtek.com

15

RT8206L/M

V

IN

(10V/Div)

LDO

(5V/Div)

REF

(2V/Div)

CP

(10V/Div)

EN1

(5V/Div)

V

OUT1

(5V/Div)

Power On from VIN

No Load, VIN = 12V, TON = V EN2 = GND, ENLDO = V

Time (400μs/Div)

Power On from EN1

PWM Mode

Power On from EN1

DEM Mode

EN1

(5V/Div)

V

OUT1

(5V/Div)

I

L1

(5A/Div)

PGOOD1

EN1 = VCC,

CC,

IN

(5V/Div)

TON = V

EN1 = VCC, EN2 = GND, ENLDO = V

CC,

No Load, VIN = 12V,

IN

Time (1ms/Div)

Power On from EN1

PWM Mode

EN1

(5V/Div)

V

OUT1

(5V/Div)

I

L1

(5A/Div)

PGOOD1

(5V/Div)

EN2

(5V/Div)

V

OUT2

(5V/Div)

I

L2

(5A/Div)

PGOOD2

(5V/Div)

TON = V

DEM Mode

TON = V

No Load, VIN = 12V,

EN1 = VCC, EN2 = GND, ENLDO = V

CC,

Time (1ms/Div)

Power On from EN2

No Load, VIN = 12V,

EN1 = GND, EN2 = VCC, ENLDO = V

CC,

I

L1

(5A/Div)

PGOOD1

IN

(5V/Div)

TON = V

EN1 = VCC, EN2 = GND, ENLDO = V

CC,

I

= 4A, VIN = 12V,

LOAD

IN

Time (1ms/Div)

Power On from EN2

PWM Mode

EN2

(5V/Div)

V

OUT2

(5V/Div)

I

L2

(5A/Div)

PGOOD2

(5V/Div)

IN

TON = V

EN1 = GND, EN2 = VCC, ENLDO = V

CC,

No Load, VIN = 12V,

IN

Time (1ms/Div)

©

Time (1ms/Div)

DS8206L/M-07 June 2012www.richtek.com

16

RT8206L/M

EN2

(5V/Div)

V

OUT2

(5V/Div)

I

L2

(5A/Div)

PGOOD2

(5V/Div)

EN1

(5V/Div)

EN2

(5V/Div)

Power On from EN2

PWM Mode

I

= 4A, VIN = 12V,

LOAD

TON = V

EN1 = GND, EN2 = VCC, ENLDO = V

CC,

Time (1ms/Div)

Power On from EN2 (Delay Start)

EN1 = REF

Power On from EN1 (Delay Start)

EN2 = REF

EN1

(5V/Div)

EN2

(5V/Div)

V

OUT1

(2V/Div)

V

OUT2

IN

(2V/Div)

VIN = 12V, TON = VCC, ENLDO = V

IN

Time (400μs/Div)

Power Off from EN1

EN1

(10V/Div)

V

OUT1

(5V/Div)

V

OUT1

(2V/Div)

V

OUT2

(2V/Div)

V

OUT1_ac-

coupled

(50mV/Div)

I

L1

(5A/Div)

LGATE1 (5V/Div)

VIN = 12V, TON = VCC, ENLDO = V

Time (400μs/Div)

VOUT1 Load Transient Response

PWM Mode, VIN = 12V

TON = VCC, SKIP = VCC, ENLDO = VIN, FB1 = V

Time (20μs/Div)

CC

UGATE1

(20V/Div)

LGATE1

IN

(5V/Div)

VIN = 12V, TON = VCC, SKIP = VCC, ENLDO = V

IN

Time (10ms/Div)

VOUT2 Load Transient Response

PWM Mode, VIN = 12V

V

OUT2_ac-

coupled

(50mV/Div)

I

L2

(2A/Div)

LGATE2 (5V/Div)

TON = VCC, SKIP = VCC, ENLDO = VIN, FB2 = V

Time (20μs/Div)

CC

©

DS8206L/M-07 June 2012 www.richtek.com

17

RT8206L/M

VOUT1

(5V/Div)

PGOOD1

(5V/Div)

VOUT2

(5V/Div)

PGOOD2

(5V/Div)

VOUT1

(500mV/Div)

I

L1

(10A/Div)

OVP

VIN = 12V, TON = VCC, SKIP = GND, ENLDO = V

Time (500μs/Div)

Power On in Short Circuit

V

= Short

OUT1

UVP

VOUT1

(5V/Div)

I

L1

(10A/Div)

UGATE1

(20V/Div)

LGATE1

IN

(5V/Div)

VIN = 12V, TON = VCC, SKIP = VCC, ENLDO = V

Time (10μs/Div)

IN

UGATE1

(20V/Div)

LGATE1

(5V/Div)

VIN = 12V, TON = VCC, SKIP = VCC, ENLDO = V

Time (400μs/Div)

IN

©

DS8206L/M-07 June 2012www.richtek.com

18

Application Information

RT8206L/M

The RT8206L/M is a dual, high efficiency, Mach

ResponseTM DRVTM dual ramp valley mode synchronous

buck controller. The controller is designed for low voltage

power supplies for notebook computers. Richtek Mach

ResponseTM technology is specifically designed for

providing 100ns “instant-on” response to load steps while

maintaining a relatively constant operating frequency and

inductor operating point over a wide range of input voltages.

The DRVTM mode PWM modulator is specifically designed

to have better noise immunity for such a dual output

application. The RT8206L/M achieves high efficiency at a

reduced cost by eliminating the current-sense resistor

found in traditional current-mode PWMs. Efficiency is

further enhanced by its ability to drive very large

synchronous rectifier MOSFETs. The RT8206L/M includes

5V (LDO) linear regulator which can step down the battery

voltage to supply both internal circuitry and gate drivers.

When V

voltage is above 4.66V, an automatic circuit

OUT1

turns off the linear regulator and powers the device from

V

through the BYP pin connected to V

OUT1

.

PWM Operation

TM

The Mach ResponseTM DRV

mode controller relies on

the output filter capacitor's Effective Series Resistance

(ESR) to act as a current-sense resistor, so the output

ripple voltage provides the PWM ramp signal. Refer to the

function block diagram, the UGATE driver will be turned

on at the beginning of each cycle. After the internal one-

shot timer expires, the UGATE driver will be turned off.

The pulse width of this one shot is determined by the

converter's input voltage and the output voltage to keep

the frequency fairly constant over the input voltage range.

Another one-shot sets a minimum off-time (300ns typ.).

The on-time one-shot is triggered if the error comparator

is high, the low-side switch current is below the current-

limit threshold, and the minimum off-time one-shot has

timed out.

PWM Frequency and On-Time Control

The Mach ResponseTM control architecture runs with

pseudo-constant frequency by feed-forwarding the input

and output voltage into the on-time one-shot timer. The

high-side switch on-time is inversely proportional to the

input voltage as measured by the VIN, and proportional to

the output voltage. The on-time is given by :

On-Time= K (V

OUT

/ VIN)

Where “K” is set by the TON pin-strap connector (Table

1). One-shot timing error increases for the shorter on-

time setting due to fixed propagation delays that is

approximately ±15% at high frequency and the ±10% at

low frequency. The on-time guaranteed in the Electrical

Characteristics tables is influenced by switching delays

in the external high side power MOSFET. Two external

factors that influence switching-frequency accuracy are

resistive drops in the two conduction loops (including

inductor and PC board resistance) and the dead-time effect.

These effects are the largest contributors to the change

of frequency with changing load current. The dead-time

effect increases the effective on-time, reducing the

switching frequency as one or both dead times. It occurs

only in PWM mode (SKIP = high) when the inductor

current reverses at light or negative load currents. With

reversed inductor current, the inductor's EMF causes

PHASEX to go high earlier than normal, extending the on-

time by a period equal to the low-to-high dead time. For

loads above the critical conduction point, the actual

switching frequency is :

fS = (V

V

DROP1

OUT

+V

) / tON x (VIN + V

DROP1

− V

DROP2

)

is the sum of the parasitic voltage drops in the

inductor discharge path, including synchronous rectifier,

inductor, and PC board resistances; V

DROP2

is the sum of

the resistances in the charging path; and tON is the on-

time calculated by the RT8206L/M.

Table 1. TON Setting and PWM Frequency Table

TON

V

OUT1

K-Factor

V

OUT1

Frequency

V

OUT2

K-Factor

V

OUT2

Frequency

Approximate

K-Factor Error

TON

= VCC

5μs 3.33μs 2.5μs

200kHz 300kHz 400kHz

4μs 2.67μs 2μs

300kHz 400kHz 500kHz

±10% ±12.5% ±15%

TON

= REF

TON

= GND

DS8206L/M-07 June 2012 www.richtek.com

©

19

RT8206L/M

Operation Mode Selection

The RT8206L/M supports three operation modes: Diode-

Emulation Mode, Ultrasonic Mode, and Forced-CCM

Mode. Users can set operation mode by SKIP pin. All of

the three operation modes will be introduced as follows.

Diode-Emulation Mode (SKIP = GND)

In Diode-Emulation mode, the RT8206L/M automatically

reduces switching frequency at light-load conditions to

maintain high efficiency. This reduction of frequency is

achieved smoothly and without the increase of V

OUTx

ripple

or load regulation. As the output current decreases from

heavy-load condition, the inductor current is also reduced,

and eventually comes to the point that its valley touches

zero current, which is the boundary between continuous

conduction and discontinuous conduction modes. By

emulating the behavior of diodes, the low side MOSFET

allows only partial negative current when the inductor free-

wheeling current becomes negative. As the load current

further decreases, it takes longer and longer to discharge

the output capacitor to the level that requires for the next

“ON” cycle. The on-time is kept the same as that in the

heavy-load condition. In reverse, when the output current

increases from light load to heavy load, the switching

frequency increases to the preset value as the inductor

current reaches the continuous conduction. The transition

load point to the light-load operation can be calculated as

the following equation.

(V V )

−

I t

LOAD ON

IN OUT

≈×

2L

The switching waveforms may appear noisy and

asynchronous when light loading causes Diode-Emulation

operation, but this is a normal operating condition that

results in high light-load efficiency. Trade-offs in PFM noise

vs. light-load efficiency is made by varying the inductor

value. Generally, low inductor values produce a broader

efficiency vs. load curve, while higher values result in higher

full-load efficiency (assuming that the coil resistance

remains fixed) and less output voltage ripple. Penalties

for using higher inductor values include larger physical

size and degraded load-transient response (especially at

low input-voltage levels).

Ultrasonic Mode (SKIP = REF)

Connecting SKIP to REF activates a unique Diode-

Emulation mode with a minimum switching frequency

above 25kHz. This ultrasonic mode eliminates audio-

frequency modulation that would otherwise be present

when a lightly loaded controller automatically skips

pulses. In ultrasonic mode, the low side switch gate-driver

signal is ORed with an internal oscillator (>25kHz). Once

the internal oscillator is triggered, the ultrasonic controller

forces the LGATEx high, turning on the low side MOSFET

to induce a negative inductor current. At the point that the

output voltage is higher than that of REF, the controller

turns off the low side MOSFET (LGATEx pulled low) and

triggers a constant on-time (UGATEx driven high). When

the on-time has expired, the controller re-enables the low-

side MOSFET until the controller detects that the inductor

current has dropped below the zero-crossing threshold.

where tON is the given On-time.

I

L

Slope = (VIN -V

OUT

) / L

i

L, peak

Forced-CCM Mode (SKIP = VCC)

The low noise, forced-CCM mode (SKIP = VCC) disables

the zero-crossing comparator, which controls the low side

switch on-time. This causes the low side gate-driver

waveform to become the complement of the high side

i

Load

= i

L, peak

/ 2

gate-driver waveform. This in turn causes the inductor

current to reverse at light loads as the PWM loop strives

0

t

ON

t

Figure 3. Boundary Condition of CCM/DEM

to maintain a duty ratio of V

OUT/VIN

forced-CCM mode is to keep the switching frequency fairly

constant, but it comes at a cost : The no-load battery

. The benefit of the

current can be from 10mA to 40mA, depending on the

external MOSFETs.

20

©

DS8206L/M-07 June 2012www.richtek.com

RT8206L/M

Reference and Linear Regulator (REF, LDO and 14V Charge Pump)

The 2V reference (REF) is accurate within ±1% over the

entire temperature range, making REF useful as a precision

system reference. Bypass REF to GND with as 0.22μF

(MIN)

capacitor. REF can supply up to 50μA for external loads.

Loading REF degrades FBx and output accuracy according

to the REF load-regulation error.

An internal regulator produces a fixed output voltage 5V.

The LDO regulator can supply up to 70mA for external

loads. Bypass LDO with a minimum 4.7μF ceramic

capacitor. When the output voltage of the V

OUT1

is higher

than the switchover threshold, an internal 1.5Ω N-Channel

MOSFET switch connects V

to LDO through BYP

OUT1

while simultaneously shutting down the internal linear

regulator.

In typical application circuit, the external 14V charge pump

is driven by LGATE1. When LGATE1 is low, D1 charges

C5 sourced from V

. C5 voltage is equal to V

OUT1

minus

a diode drop. When LGATE1 transitions to high, the charge

from C5 will transfer to C6 through D2 and charge it to

V

plus VC5. As LGATE1 transients low on the next

LGATE1

cycle, C6 will charge C7 to its voltage minus a diode drop

through D3. Finally, C7 charges C8 through D4 when

LGATE1 transitions to high. CP output voltage is :

VCP = V

OUT1

+2 x V

LGATE1

− 4 x V

D

where :

` V

is the peak voltage of the LGATE1 driver

LGATE1

is the forward diode dropped across the Schottkys

D

SECFB (RT8206L) is used to monitor the charge pump

via the resistive divider. In an event when SECFB drops

below 2V the controller forces ultrasonic mode operation

which keeps the switching frequency above 25kHz to

maintain charge pump voltage.

Reducing the CP decoupling capacitor and placing a small

ceramic capacitor C19 (10pF to 47pF) in parallel will the

upper leg of the SECFB resistor feedback network, R11,

will also increase the robustness of the charge pump.

Current Limit Setting (I

LIMx

)

The RT8206L/M has a cycle-by-cycle current limiting

control. The current limit circuit employs a unique “valley”

current sensing algorithm. If the magnitude of the current

sense signal at PHASEx is above the current limit

threshold, the PWM is not allowed to initiate a new cycle

(Figure 4). The actual peak current is greater than the

current limit threshold by an amount equal to the inductor

ripple current. Therefore, the exact current limit

characteristic and maximum load capability are a function

of the sense resistance, inductor value, battery voltage,

and output voltage.

I

L

I

L, peak

I

Load

I

LIM

0

t

Figure 4. Valley Current Limit

The RT8206L/M uses the on-resistance of the synchronous

rectifier as the current-sense element. Use the worse-

case maximum value for R

from the MOSFET

DS(ON)

datasheet, and add a margin of 0.5%/°C for the rise in

R

with temperature.

DS(ON)

The current limit threshold is adjusted with an external

resistor for the RT8206L/M at ILIMx. The current limit

threshold adjustment range is from 50mV to 200mV. In

the adjustment mode, the current limit threshold voltage

is precise to 1/10 the voltage seen at ILIMx. The threshold

defaults to 100mV when ILIMx is connected to VCC. The

logic threshold for switchover to the 100mV default value

is higher than VCC−1V.

Carefully observe the PC board layout guidelines to ensure

that noise and DC errors do not corrupt the current sense

signal at PHASEx and GND. Mount or place the IC close

to the low side MOSFET.

MOSFET Gate Driver (UGATEx, LGA TEx)

The high side driver is designed to drive high current, low

R

N-MOSFET(s). When configured as a floating driver

DS(ON)

the instantaneous drive current is supplied by the flying

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21

RT8206L/M

capacitor between BOOTx and PHASEx pins. A dead time

to prevent shoot through is internally generated between

high side MOSFET off to low side MOSFET on, and low

side MOSFET off to high side MOSFET on.

The low side driver is designed to drive high current low

R

N-MOSFET(s). The internal pulldown transistor

DS(ON)

that drives LGATEx low is robust, with a 0.6Ω typical on-

resistance. A 5V bias voltage is typically delivered from

PVCC through LDO supply. The instantaneous drive

current is supplied by an input capacitor connected

between PVCC and GND.

For high current applications, some combinations of high

and low side MOSFETs might be encountered that will

cause excessive gate-drain coupling, which can lead to

efficiency-killing, EMI-producing shoot-through currents.

This is often remedied by adding a resistor in series with

BOOTx, which increases the turn-on time of the high side

MOSFET without degrading the turn-off time (Figure 5).

V

IN

BOOTx

UGATEx

PHASEx

Figure 5. Reducing the UGATEx Rise Time

POR and UVLO

Power On Reset (POR) occurs when VIN rises above

approximately 5V (typ.), resetting the fault latches. PVCC

Under Voltage Lockout (UVLO) circuitry inhibits switching

by keeping UGATEx and LGATEx low when PVCC is

below 4.05V. The PWM outputs begin to ramp up once

PVCC exceeds its UVLO threshold and ENx is enabled.

Power Good Output (PGOODx)

The PGOODx is an open-drain type output. PGOODx is

actively held low in soft-start, standby, and shutdown. It is

released when the VOUTx voltage is above 90% of the

nominal regulation point. The PGOODx goes low if it is

10% below its nominal regulator point.

Output Over Voltage Protection (OVP)

The output voltage can be continuously monitored for over

voltage protection. When the output voltage of the VOUTx

is 12% above the set voltage, over voltage protection will

be enabled. If the output exceeds the over voltage

threshold, over voltage fault protection will be triggered

and the LGATEx low side gate drivers are forced high.

This activates the low side MOSFET switch, which rapidly

discharges the output capacitor and reduces the output

voltage. Once an over voltage fault condition is set, it can

only be reset by toggling ENLDO, ENx, or cycling VIN

(POR.)

Soft-Start

The RT8206L/M provides an internal soft-start function to

prevent large inrush current and output voltage overshoot

when the converter starts up. The soft-start (SS)

automatically begins once the chip is enabled. During

soft-start period, the internal current limit circuit gradually

ramps up the inductor current from zero. The maximum

current limit value is set externally as described in previous

section. The soft-star time is determined by the current

limit and output capacitor value. The current limit threshold

ramp up time is typically 2ms from zero to 200mV after

ENx is enabled. A unique PWM duty limit control that

prevents output over voltage during soft-start period is

designed specifically for FBx floating.

Output Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under

voltage protection. If the output is less than 55% of the

error-amplifier trip voltage, under voltage protection will be

triggered, and then both UGATEx and LGATEx gate drivers

will be forced low. The UVP will be ignored for at least

5ms (typ.) after start-up or after a rising edge on ENx.

Toggle ENx or cycle VIN (POR) to clear the under voltage

fault latch and restart the controller. The UVP only applies

to the PWM outputs.

Thermal Protection

The RT8206L/M has a thermal shutdown protection

function to prevent it from overheating. Thermal shutdown

occurs when the die temperature exceeds +150°C. All

22

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DS8206L/M-07 June 2012www.richtek.com

RT8206L/M

internal circuitry will be shut down during thermal shutdown.

The RT8206L/M may trigger thermal shutdown if the LDO

is not supplied from VOUTx, while input voltage on VIN

and drawing current from the LDO are too high. Even if

the LDO is supplied from VOUTx, overloading the LDO

causes large power dissipation on automatic switches,

which may result in thermal shutdown.

Discharge Mode

When standby or shutdown mode occurs, or the output

under voltage fault latch is set, the output discharge mode

is triggered. During discharge mode, the output capacitor

will be discharged to GND through an internal 20Ω switch.

Shutdown Mode

The RT8206L/M SMPS1, SMPS2 and LDO have

independent enabling control. Drive ENLDO, EN1 and EN2

below the precise input falling edge trip level to place the

RT8206L/M in its low power shutdown state. The

RT8206L/M consumes only 20μA of quiescent current

while in shutdown. When shutdown mode is activated,

the reference turns off. The accurate 1V falling-edge

threshold on the ENLDO can be used to detect a specific

analog voltage level and shutdown the device. Once in

shutdown, the 1.6V rising edge threshold activates,

providing sufficient hysteresis for most application.

Power Up Sequencing and On/Off Controls (ENx)

EN1 and EN2 control SMPS power-up sequencing. When

the RT8206L/M applies in the single channel mode, EN1

or EN2 enables the respective outputs when ENx voltage

rises above 2.5V, and disables the respective outputs when

ENx voltage falls below 1.8V.

Connecting one ENx to VCC and the other to REF will

force the latter one's output to start only after the former

one regulates.

If both ENx are connected to REF, each output will wait

for the regulation of the other one. However, in this situation,

neither of the two ENx will be in regulation.

Output Voltage Setting (FBx)

Connect FB1 directly to GND or VCC for a fixed 5V output

(VOUT1). Connect FB2 directly to GND or VCC for a fixed

3.3V output (VOUT2).

The output voltage can also be adjusted from 2V to 5.5V

with a resistor-divider network (Figure 6). The following

equation is for adjusting the output voltage. Choose R2 to

be approximately 10kΩ, and solve for R1 using the following

equation :

⎡⎤

R1

V = V 1

OUTx FBx

where V

is 2V (typ.).

FBx

UGATEx

PHASEx

LGATEx

VOUTx

GND

⎛⎞

×+

⎜⎟

⎢⎥

R2

⎝⎠

⎣⎦

V

IN

FBx

R1

R2

V

OUTx

Figure 6. Setting VOUTx with a Resistor-Divider

Output Inductor Selection

The switching frequency (on-time) and operating point (%

ripple or LIR) determine the inductor value as follows :

t(V - V)

×

ON IN OUT

L =

LI

×

IR LOAD(MAX)

where LIR is the ratio of the peak-to-peak ripple current to

the average inductor current.

Find a low-loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite cores

are often the best choice, because the powdered iron is

inexpensive and can work well at 200kHz. The core must

be large enough to prevent it from saturating at the peak

inductor current (I

I

= I

PEAK

LOAD(MAX)

) :

PEAK

+ [(LIR / 2) x I

LOAD(MAX)

]

This inductor ripple current also impacts transient-response

performance, especially at low V

IN

− V

differences.

OUTx

Low inductor values allow the inductor current to slew

faster, replenishing charge removed from the output filter

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23

RT8206L/M

capacitors by a sudden load step. The peak amplitude of

the output transient (V

) is also a function of the

SAG

maximum duty factor, which can be calculated from the

on-time and minimum off-time :

2

LOAD OFF(MIN)

V =

SAG

(I ) L K t

Δ×× +

2C V K t

×× × −

OUT OUTx OFF(MIN)

where minimum off-time (t

OFF(MIN)

OUTx

⎜⎟

V

IN

⎝⎠

⎡⎤

VV

−

⎛⎞

IN OUTx

⎜⎟

⎢⎥ ⎣⎦

V

⎝⎠

IN

) = 300ns (typ.) and K

V

⎛⎞

is from Table 1.

Output Capacitor Selection

The output filter capacitor must have low enough equivalent

series resistance (ESR) to meet output ripple and load-

transient requirements, yet have high enough ESR to

satisfy stability requirements. The output capacitance

must also be high enough to absorb the inductor energy

while transiting from full-load to no-load conditions without

tripping the overvoltage fault latch.

Although Mach ResponseTM DRVTM dual ramp valley mode

provides many advantages such as ease-of-use, minimum

external component configuration, and extremely short

response time, due to not employing an error amplifier in

the loop, a sufficient feedback signal needs to be provided

by an external circuit to reduce the jitter level. The required

signal level is approximately 15mV at the comparing point.

This generates V

RIPPLE

= (V

/ 2) x 15mV at the output

OUT

node. The output capacitor ESR should meet this

requirement.

Output Capacitor Stability

Stability is determined by the value of the ESR zero relative

to the switching frequency. The point of instability is given

by the following equation :

f =

ESR

1

2 ESR C 4

π

×× ×

OUT

f

SW

≤

Do not put high value ceramic capacitors directly across

the outputs without taking precautions to ensure stability.

Large ceramic capacitors can have a high ESR zero

frequency and cause erratic, unstable operation. However,

it is easy to add enough series resistance by placing the

capacitors a couple of inches downstream from the

inductor and connecting VOUTx or the FBx divider close

to the inductor.

There are two related but distinct factors, double-pulsing

and feedback loop instability, for unstable operation.

Double-pulsing occurs due to noise on the output or

because the ESR is so low that there is not enough voltage

ramp in the output voltage signal. This “fools” the error

comparator into triggering a new cycle immediately after

the 300ns minimum off-time period has expired. Double-

pulsing is more annoying than harmful, resulting in nothing

worse than increased output ripple. However, it may

indicate the possible presence of loop instability, which

is caused by insufficient ESR.

Loop instability can result in oscillations at the output

after line or load perturbations that can trip the over-voltage

protection latch or cause the output voltage to fall below

the tolerance limit.

The easiest method for checking stability is to apply a

very fast zero-to-max load transient and carefully observe

the output-voltage-ripple envelope for overshoot and ringing.

It helps to simultaneously monitor the inductor current

with an AC current probe. Do not allow more than one

cycle of ringing after the initial step-response under- or

overshoot.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum operation junction temperature. The maximum

power dissipation depends on the thermal resistance of

IC package, PCB layout, the rate of surroundings airflow

and temperature difference between junction to ambient.

The maximum power dissipation can be calculated by

following formula :

P

where T

temperature, T

D(MAX)

= ( T

J(MAX)

- TA ) / θ

J(MAX)

JA

is the maximum operation junction

is the ambient temperature and θJA is the

A

junction to ambient thermal resistance.

For recommended operating conditions specification, the

maximum junction temperature is 125°C. The junction to

ambient thermal resistance, θ

WQFN-32L 5x5 package, the thermal resistance, θ

is layout dependent. For

JA,

is

36°C/W on a standard JEDEC 51-7 four-layer thermal test

board. The maximum power dissipation at TA = 25°C can

be calculated by the following formula :

24

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DS8206L/M-07 June 2012www.richtek.com

RT8206L/M

P

= (125°C − 25°C) / (36°C/W) = 2.778W for

D(MAX)

WQFN-32L 5x5 package

The maximum power dissipation depends on operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance θJA. The derating curve in the Figure 7 allows

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

Maximum Power Dissipation (W)

0.0 0 25 50 75 100 125

Ambient Temperature (°C)

Four-Layer PCB

` All sensitive analog traces and components such as

VOUTx, FBx, GND, ENx, PGOODx, ILIMx, VCC, and

TON should be placed away from high voltage switching

nodes such as PHASEx, LGATEx, UGATEx or BOOTx

nodes to avoid coupling. Use internal layer(s) as ground

plane(s) and shield the feedback trace from power traces

and components.

` Gather ground terminal of VIN capacitor(s), VOUTx

capacitor(s), and source of low side MOSFETs as close

as possible. PCB trace of the PHASEx node, which

connects to source of high side MOSFET, drain of low

side MOSFET and high voltage side of the inductor,

should be as short and wide as possible.

Figure 7. Derating Curve of Maximum Power Dissipation

Layout Considerations

Layout is very important in high frequency switching

converter design. If the layout is designed improperly, the

PCB could radiate excessive noise and contribute to the

converter instability. The following guidelines must be

strictly followed for a proper layout of RT8206L/M.

` Connect an RC low-pass filter from PVCC to VCC. The

RC low-pass filter is composed of an external capacitor

and an internal 10Ω resistor. It is recommended to bypass

VCC to GND with a 1μF capacitor. Place the capacitor

close to the IC, within 12mm (0.5 inch) if possible.

` Keep current limit setting network as close as possible

to the IC. Routing of the network should avoid coupling

to high-voltage switching node.

` Connections from the drivers to the respective gate of

the high side or the low-side MOSFET should be as

short as possible to reduce stray inductance. Use

0.65mm (25 mils) or wider trace.

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25

RT8206L/M

Table 2. Operation Mode Truth Table

Mode Condition Comment

Power Up PVCC < UVLO threshold

RUN

Over voltage

Protection

Under voltage

Protection

Discharge

Standby

Shutdown EN1, EN2, ENLDO=low All circuitry off.

Thermal

Shutdown

ENLDO = high, EN1 or EN2 enabled

Either output > 112% of nominal level.

Either output < 55% of nominal level after 3ms time-out expires and output is enabled.

Either SMPS output is still high in either standby mode or shutdown mode.

ENx < startup threshold, ENLD O = high.

> +150°C

T

J

Transitions to discharge mode after VIN POR and REF become valid. LDO and REF remain active.

Normal Operation.

LGATEx is forced high. LDO and REF active. Exited by VIN POR or by toggling ENLDO, ENx.

Both UGATEx and LGATEx are forced low until discharge mode terminates. LDO and REF are active. Exited by VIN POR or by toggling ENLDO, EN1, or EN2.

During discharge mode, the output capacitor discharges to GND through an internal N-MOSFET switch.

LGATEx stays low. LDO and REF active.

All circuitry off. Exit by VIN POR or by toggling ENLDO, ENx.

Table 3. Power Up Sequencing

ENLDO (V) V

Low X X Off Off Off

“>2V” High Low Low

“>2V” High Low REF

“>2V” High Low High

“>2V” High REF Low

“>2V” High REF REF

“>2V” High REF High

“>2V” High High Low

“>2V” High High REF

“>2V” High High High

EN1

(V) V

(V) LDO 5V SMPS1 3V SMPS2

EN2

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

Off Off

Off On

Off Off

On

(after SMPS2 on)

On Off

On

On On

On

(aft er SMPS 1 o n )

26

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DS8206L/M-07 June 2012www.richtek.com

Outline Dimension

RT8206L/M

D

E

e

D2

SEE DETAIL A

1

b

L

E2

1 2

DETAIL A

A

A3

A1

Note : The configuration of the Pin #1 identifier is optional,

Pin #1 ID and Tie Bar Mark Options

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inch es

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 4.950 5.050 0.195 0.199

D2 3.400 3.750 0.134 0.148

E 4.950 5.050 0.195 0.199

E2 3.400 3.750 0.134 0.148

e 0.500 0.020

L 0.350 0.450

0.014 0.018

W-Type 32L QFN 5x5 Package

Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS8206L/M-07 June 2012 www.richtek.com

27

Richtek RT8206LGQW, RT8206LZQW, RT8206MGQW, RT8206MZQW Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual