Richtek RT8206AGQW, RT8206BGQW Schematic [ru]

High-Efficiency, Main Power Supply Controllers
for Notebook Computers

RT8206A/B

General Description

The RT8206A/B dual step-down, switch-mode power-

supply (SMPS) controller generates logic-supply voltages

in battery-powered systems. The RT8206A/B includes two

pulse-width modulation (PWM) controllers fixed at 5V/

3.3V or adjustable from 2V to 5.5V. An optional external

charge pump can be monitored through SECFB

(RT8206A). This device also features a linear regulator

providing a fixed 5V output. The linear regulator provides

up to 70mA output current with automatic linear-regulator

bootstrapping to the BYP input. The RT8206A/B includes

on-board power-up sequencing, the power-good outputs,

internal soft-start, and internal soft-discharge output that

prevents negative voltages on shutdown.

A constant on-time PWM control scheme operates without

sense resistors and provides 100ns response to load

transients while maintaining a relatively constant switching

frequency. The unique ultrasonic mode maintains the

switching frequency above 25kHz, which eliminates noise

in audio applications. Other features include diode-

emulation mode (DEM), which maximizes efficiency in

light-load applications, and fixed-frequency PWM mode,

which reduces RF interference in sensitive application.

The RT8206A/B is available in the WQFN-32L 5x5

package.

Features

zz

z Wide Input Voltage Range 6V to 25V

zz

zz

z Dual Fixed 5V/3.3V Outputs or Adjustable from 2V

zz

to 5.5V, 1.5% Accura cy

zz

z Secondary Feedback Input Maintains Charge Pump

zz

V oltage (RT8206A)

zz

z Independent Enable and Power Good

zz

zz

z 5V Fixed LDO Output : 70mA

zz

zz

z 2V Reference Voltage

zz

zz

z Constant ON-Time Control with 100ns Load Step

zz

±±

±1% : 50uA

±±

Response

zz

z Frequency Selectable via TON Setting

zz

zz

z R

zz

Current Sensing and Progra mmable Current

DS(ON)

Limit

zz

z Selectable PWM, DEM or Ultrasonic Mode

zz

zz

z Internal Soft-Start with 5 Steps Current Limiting and

zz

Soft-Discharge

zz

z High Efficiency Up to 97%

zz

zz

z 5mW Quiescent Power Dissipation

zz

zz

z Thermal Shutdown

zz

zz

z RoHS Compliant and Halogen Free

zz

Applications

z Notebook and Sub-Notebook Computers

z 3-Cell and 4-Cell Li+ Battery-Powered Devices

Ordering Information

RT8206

Marking Information

RT8206AGQW

RT8206AGQW : Product Number

Package Type
QW : WQFN-32L 5x5 (W-Type)

Lead Plating System

RT8206A
GQW
YMDNN

YMDNN : Date Code

G : Green (Halogen Free and Pb Free)

A : With SECFB
B : Without SECFB

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

DS8206A/B-05 May 2011 www.richtek.com

RT8206BGQW

RT8206B
GQW
YMDNN

RT8206BGQW : Product Number

YMDNN : Date Code

1

RT8206A/B

Pin Configurations

(TOP VIEW)

VOUT2

FB2

ILIM2

32 31 30 29

1

REF BOOT2

2

TON

3

VCC

NC

VIN

LDO

NC

4

5

6

7

8

9101112 1413

ENLDO

BYP

VOUT1

FB1

SKIP

GND

ILIM1

PGOOD2

28 27 26 25

PGOOD1

EN2

33

EN1

PHASE2

UGATE2

24

23

22

21

20

19

18

17

1615

PHASE1

UGATE1

WQFN-32L 5x5

RT8206A

Typical Application Circuit

1

C

1

µ

F

0

Q1

2

1

L

H

µ

8

.

V

1

T

U

O

V

5

3

C

µ

F

0

2

2

6

5

R

4

C

D

1

6

C

2

D

0

.

1

F

µ

D

3

D

8

C

0

4

F

µ

.

1

CP

1

R

1

0

0

2

1

C

R70

C
4

.

C

F

µ

.

0

1

Q3

5

C

F

0

µ

.

1

7

C

1

0

.

F

µ

k

1

2

R

9

3

9

0

1
7

k

C
1

µ

F

LGATE2

PGND

GND

SECFB

PVCC

LGATE1

BOOT1

R

1

.

3

C
0

R

0

4

R

3

6

1

µ

F

VOUT2

FB2

ILIM2

32 31 30 29

1

REF BOOT2

2

TON

3

VCC

NC

VIN

LDO

NC

4

5

6

7

8

9101112 1413

ENLDO

BYP

VOUT1

FB1

SKIP

GND

ILIM1

PGOOD2

28 27 26 25

PGOOD1

EN2

33

EN1

PHASE2

UGATE2

24

23

22

21

20

19

18

17

1615

PHASE1

UGATE1

LGATE2

PGND

GND

NC

PVCC

LGATE1

BOOT1

WQFN-32L 5x5

RT8206B

V

N

I

o

6

t

V

2

5

V

4

9

8

1

F

µ

.

1

15

0

17

16

18

10

6

VIN

UGATE1

BOOT1

PHASE1

LGATE1

9

BYP

VOUT1

RT8206A/B

UGATE2

BOOT2

PHASE2

LGATE2

PGND

VOUT2

REF

PGOOD1

PGOOD2

3

VCC

9

C

1

µ

F

EN1

EN2

ENLDO

20

SECFB/NC

11

FB1

32

FB2

19

PVCC

7

LDO

ILIM1

ILIM2

TON

SKIP

GND

R

9

0

26

R

0

8

24

C

1

1

0

.

1

25

µ

23

22

30
1

13

C

1

5

2

0

.

2

µ

F

28

5

E

n

a

V

l

e

14

27

4

12

31

2

29

b

V

.

3

E

3

L

l

n

a

e

b

O

D

r

n

t

C

o

l

o

1

1

F

r

n

q

u

e

e

M

P

W

D

/

21, Exposed Pad (33)

Q2

F

Q4

R

6

1

0

0

1

R

1

0

0

R

1

0

k

8

R

2
0

8

k

c

C

y

o

n

E

M

r

t

l

U

/

C

1

3

2

C

1

0

4

1

R

1

C

k

3

k

P

P

1

µ

F

0

µ

1

F

L

2

.

7

µ

H

0

4

V

C

C

V

C

C

ON

OFF

V

N

I

r

t

o

l

a

i

s

o

c

n

V

O

U

T

2

3

3

V

.

C

1

7

2

0

2

µ

F

Figure 1. Fixed Voltage Regulator

DS8206A/B-05 May 2011www.richtek.com

2

RT8206A/B

V

N

I

o

t

6

V

2

5

V

4

1

1

C

1

µ

0

F

Q1

1

L

H

.

µ

6

V

1

O

T

U

V

5

3

C

F

2

2

µ

0

3

C

2

0

2

C

F

µ

.

0

1

8

Q3

R

5

4

C

C

1

D

D

R70

1

C
4

.

7

0

3

0

1

R
2

0

C

0

µ

F

6

C

D

2

F

1

0

µ

.

4

D

C

8

.

1

0

F

µ

CP

5

R

1

5

k

1

6

R

1

1

0

k

R

9

.

3

8

C

1

F

µ

.

0

1

4

R

0

15

0

R

3

17

C

2

F

.

µ

0

1

5

µ

.

1

F

7

C

.

1

F

µ

1

k

0

9

1

C
1

µ

16

18

10

9

C

1

µ

F

20

2

1

R
3

9

k

11

19

6

1

F

6

VIN

UGATE1

BOOT1

PHASE1

LGATE1

9

BYP

VOUT1

3

VCC

SECFB/NC

FB1

PVCC

7

LDO

RT8206A/B

UGATE2

BOOT2

PHASE2

LGATE2

PGND

VOUT2

FB2

REF

PGOOD1

PGOOD2

EN1

EN2

ENLDO

ILIM1

ILIM2

TON

SKIP

GND

R

9

0

26

R

0

8

24

C

1

1

0

.

1

25

23

22

30

32

1

13

28

V

5

E

14

27

3

.

3

V

D

O

L

4

12

31

2

29

21, Exposed Pad (33)

µ

C

1

5

2

0

2

µ

.

F

n

a

b

l

e

E

n

a

e

b

l

r

n

t

o

o

C

l

1

1

F

r

e

n

q

u

e

M

W

P

D

/

Q2

F

Q4

R

6

1

0

0

k

R

1

3

1

0

0

k

R

1
0

k

8

2

R

0

k

8

c

y

o

C

n

/

E

M

U

l

r

t

a

C

1

3

2

C

C

C

µ

ON

1

F

1

0

µ

F

7

R

1

k

5

.

1

1

8

R

1

k

0

1

1

0

L

2

4

7

µ

.

H

R

1

0

4

C

1

P

V

C

P

V

C

OFF

V

N

I

r

t

o

l

s

c

i

o

n

V

O

T

U

2

3

3

V

.

C

1

7

2

2

0

µ

F

2

C

2

2

C

1

1

0

.

µ

F

Figure 2. Adjustable Voltage Regulator

DS8206A/B-05 May 2011 www.richtek.com

3

RT8206A/B

Function Block Diagram

TON SKIP

BOOT1

UGATE1

PHASE1

LGATE1

PGND

VOUT1

FB1

ILIM1

PGOOD1

GND

BYP

LDO

VIN

PV

CC

LDO

SMPS1

PWM Buck

Controller

SW Threshold

Function Block Diagram

Internal

Logic

Thermal

Shutdown

SMPS2

PWM Buck

Controller

Power-On
Sequence

Clear Fault Latch

REF

PV

BOOT2

UGATE2

PHASE2

CC

LGATE2

VOUT2

FB2
ILIM2
PGOOD2

VCC

PVCC
ENLDO
EN1
EN2

REF

VOUT

REF

FB

PGOOD

-

+

1.1 x V

0.7 x V

0.9 x V

+

-

REF

REF

REF

On-Time

Compute

VINTON

T

Comp

-

+

Over-Voltage

+

-

-

+

Under-Voltage

-

+

ON

Q

1-Shot

TRIG

Fault

Latch

Blanking

Time

R

25kHz

Detector

TRIG

SS

Time

Detector

Zero

T

1-Shot

Q

OFF

Current

+

-

+

-

Limit

UGATE

LGATE

V

CC

+

-

ILIM

PHASE

SKIP

PWM Controller (One Side)

DS8206A/B-05 May 2011www.richtek.com

4

Functional Pin Description

RT8206A/B

REF (Pin 1)

2V Reference Output. Bypass to GND with a 0.22uF

capacitor. REF can source up to 50uA for external loads.

Loading REF degrades FBx and output accuracy according

to the REF load-regulation error.

TON (Pin 2)

Frequency Select Input. (VOUT1/VOUT2 switching

frequency, respectively) :

TON = VCC, (200kHz / 250kHz)

TON = REF, (300kHz / 375kHz)

TON = GND, (400kHz / 500kHz)

VCC (Pin 3)

Analog Supply Voltage Input for the PWM Core. Bypass

to GND with a 1uF ceramic capacitor

ENLDO (Pin 4)

LDO Enable Input. The REF/LDO is enabled if ENLDO is

within logic high level and disable if ENLDO is less than

the logic low level.

NC (Pin 5, 8)

No Internal Connection.

VIN (Pin 6)

VOUT1 (Pin 10)

SMPS1 Output Voltage-Sense Input. Connect this pin to

the SMPS1 output. VOUT1 is an input to the Constant

on-time-PWM one-shot circuit. It also serves as the

SMPS1 feedback input in fixed-voltage mode.

FB1 (Pin 1 1)

SMPS1 Feedback Input. Connect FB1 to VCC or GND for

fixed 5V operation. Connect FB1 to a resistive voltage-

divider from VOUT1 to GND to adjust output from 2V to

5.5V.

ILIM1 (Pin 12)

SMPS1 Current-Limit Adjustment. The GND − PHASE1

current-limit threshold is 1/10th the voltage seen at ILIM1

over a 0.5V to 2V range. There is an internal 5uA current

source from VCC to ILIM1. The logic current limit threshold

is default to 100mV if ILIM1 is higher than (VCC − 1V).

PGOOD1 (Pin 13)

SMPS1 Power-Good Open-Drain Output. PGOOD1 is low

when the SMPS1 output voltage is more than 7.5% below

the normal regulation point or during soft-start. PGOOD1

is high impedance when the output is in regulation and

the soft-start circuit has terminated. PGOOD1 is low in

shutdown.

Power-supply Input. VIN is used for the constant on-time

PWM one shot circuits. VIN is also used to power the

linear regulators. The linear regulators are powered by

SMPS1 if VOUT1 is set greater than 4.66V and BYP is

tied to VOUT1. Connect VIN to the battery input and

bypass with a 1uF capacitor.

LDO (Pin 7)

Linear-Regulator Output. LDO can provide a total of 70mA

external loads. The LDO regulates a fixed 5V output. When

the BYP is within 5V switchover threshold, the internal

regulator shuts down and the LDO output pin connects to

BYP through a 1.5Ω switch. Bypass LDO output with a

minimum of 4.7uF ceramic.

BYP (Pin 9)

BYP is the switchover source voltage input for the LDO.

DS8206A/B-05 May 2011 www.richtek.com

EN1 (Pin 14)

SMPS1 Enable Input. The SMPS1 will be enabled if EN1

is greater than the logic high level and disabled if EN1 is

less than the logic low level. If EN1 is connected to REF,

the SMPS1 starts after the SMPS2 reaches regulation

(delay start). Drive EN1 below 0.8V to clear fault level and

reset the fault latches.

UGA TE1 (Pin 15)

High-Side MOSFET Floating Gate-Driver Output for

SMPS1. UGATE1 swings between PHASE1 and BOOT1.

PHASE1 (Pin 16)

Inductor Connection for SMPS1. PHASE1 is the internal

lower supply rail for the UGATE1 high-side gate driver.

PHASE1 is the current-sense input for the SMPS1.

5

RT8206A/B

BOOT1 (Pin 17)

Boost Flying Capacitor Connection for SMPS1. Connect

to an external capacitor according to the typical application

circuits.

LGATE1 (Pin 18)

SMPS1 Synchronous-Rectifier Gate-drive Output. LGATE1

swings between PGND and PVCC.

PVCC (Pin 19)

PVCC is the supply voltage for the low-side MOSFET

driver LGATEx. Connect a 5V power source to the PVCC

pin (bypass with 1uF MLCC capacitor to PGND if

necessary). There is an internal 10Ω connecting from

PVCC to VCC. Make sure that both VCC and PVCC are

bypassed with 1uF MLCC capacitors.

SECFB (Pin 20) (RT8206A)

The SECFB is used to monitor the optional external 14V

charge pump. Connect a resistive voltage-divider from the

14V charge pump output to GND to detect the output. If

SECFB drops below the threshold voltage, LGATE1 will

be turned on for 300ns. This will refresh the external charge

pump driven by LGATE1 without over-discharging the

output voltage.

NC (Pin 20) (RT8206B)

No Internal Connection.

PHASE2 (Pin 25)

Inductor Connection for SMPS2. PHASE2 is the internal

lower supply rail for the UGATE2 high-side gate driver.

PHASE2 is the current-sense input for the SMPS2.

UGA TE2 (Pin 26)

High-Side MOSFET Floating Gate-Driver Output for

SMPS2. UGATE2 swings between PHASE2 and BOOT2.

EN2 (Pin 27)

SMPS2 Enable Input. The SMPS2 will be enabled if EN2

is greater than the logic high level and be disabled if EN2

is less than the logic low level. If EN2 is connected to

REF, the SMPS2 starts after the SMPS1 reaches

regulation (delay start). Drive EN2 below 0.8V to clear

fault level and reset the fault latches.

PGOOD2 (Pin 28)

SMPS2 Power-Good Open-Drain Output. PGOOD2 is low

when the SMPS2 output voltage is more than 7.5% below

the normal regulation point or during soft-start. PGOOD2

is high impedance when the output is in regulation and

the soft-start circuit has terminated. PGOOD2 is low in

shutdown.

SKIP (Pin 29)

SMPS Operation Mode Control.

SKIP = GND : DEM operation

GND [Pin 21, Exposed Pad (33)]

Analog Ground for both SMPS and LDO. The exposed

pad must be soldered to a large PCB and connected to

GND for maximum power dissipation.

PGND (Pin 22)

Power Ground for SMPS controller. Connect PGND

externally to the underside of the exposed pad.

LGATE2 (Pin 23)

SMPS2 Synchronous-Rectifier Gate-drive Output. LGATE2

swings between PGND and PVCC.

BOOT2 (Pin 24)

Boost Flying Capacitor Connection for SMPS2. Connect

this pin to an external capacitor according to the typical

application circuits.

6

SKIP = REF : Ultrasonic Mode operation

SKIP = VCC : PWM operation.

VOUT2 (Pin 30)

SMPS2 Output Voltage-Sense Input. Connect this pin to

the SMPS2 output. VOUT2 is an input to the constant

on-time-PWM one-shot circuit. It also serves as the

SMPS2 feedback input in fixed-voltage mode.

ILIM2 (Pin 31)

SMPS2 Current-Limit Adjustment. The GND − PHASE2

current-limit threshold is 1/10th the voltage seen at ILIM2

over a 0.5V to 2V range. There is an internal 5uA current

source from VCC to ILIM2. The logic current limit threshold

is default to 100mV value if ILIM2 is higher than (VCC −

1V).

DS8206A/B-05 May 2011www.richtek.com

FB2 (Pin 32)

SMPS2 Feedback Input. Connect FB2 to VCC or GND for

fixed 3.3V operation. Connect FB2 to a resistive voltage-

divider from VOUT2 to GND to adjust output from 2V to

5.5V.

RT8206A/B

DS8206A/B-05 May 2011 www.richtek.com

7

RT8206A/B

Absolute Maximum Ratings (Note 1)

z VIN, ENLDO to GND ---------------------------------------------------------------------------------------------- –0.3V to 30V

z PHASEx to GND

DC --------------------------------------------------------------------------------------------------------------------- –0.3V to 30V
<20ns ---------------------------------------------------------------------------------------------------------------- –8V to 38V

z BOOTx to PHASEx ----------------------------------------------------------------------------------------------- –0.3V to 6V
z VCC, ENx, SKIP, TON, PVCC, PGOODx, to GND ------------------------------------------------------- –0.3V to 6V
z LDO, FBx, VOUTx, SECFB, REF, ILIMx to GND ---------------------------------------------------------- –0.3V to (V

z UGATEx to PHASEx

DC --------------------------------------------------------------------------------------------------------------------- –0.3V to (PV
<20ns ---------------------------------------------------------------------------------------------------------------- –5V to 7.5V

z LGATEx, BYP to GND

DC --------------------------------------------------------------------------------------------------------------------- –0.3V to (PV
<20ns ---------------------------------------------------------------------------------------------------------------- –2.5V to 7.5V

z PGND to GND ------------------------------------------------------------------------------------------------------ –0.3V to 0.3V

z Power Dissipation, P

@ TA = 25°C

D

WQFN-32L 5x5 ---------------------------------------------------------------------------------------------------- 2.778W

z Package Thermal Resistance (Note 2)

WQFN-32L 5x5, θJA----------------------------------------------------------------------------------------------- 36°C/W

WQFN-32L 5x5, θJC---------------------------------------------------------------------------------------------- 7°C/W

z Junction Temperature --------------------------------------------------------------------------------------------- 150°C

z Lead Temperature (Soldering, 10 sec.)----------------------------------------------------------------------- 260°C

z Storage Temperature Range ------------------------------------------------------------------------------------ –65°C to 150°C

z ESD Susceptibility (Note 3)

HBM (Human Body Mode) -------------------------------------------------------------------------------------- 2kV

MM (Machine Mode) ---------------------------------------------------------------------------------------------- 200V

CC

CC

CC

+ 0.3V)

+ 0.3V)

+ 0.3V)

Recommended Operating Conditions (Note 4)

z Input Voltage, V
z Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C

8

------------------------------------------------------------------------------------------------------ 6V to 25V

IN

DS8206A/B-05 May 2011www.richtek.com

To be continued

RT8206A/B

Electrical Characteristics

(VIN = 12V, EN1 = EN2 = VCC, V

unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

Input Supply

VIN Standby Supply Current I

VIN Shutdown Supply
Current

Quiescent Power
Consumption

SMPS Output and FB Voltage

VOUT1 Output Voltage in
Fixed Mode

VOUT2 Output Voltage in
Fixed Mode

FBx in Output Adjustable
Mode

SECFB Voltage SECFB VIN = 6V to 25V (RT8206A) 1.92 2 2.08 V

Output Voltage Adjust
Range
FBx Adjustable-mode
Threshold Voltage

DC Load Regulation V

= 5V, PVCC = 5V, V

BYP

V

VIN_SBY

I

VIN_SHDH

ENLDO = 5V
V
ENx = ENLDO = GND

= 6V to 25V, Both SMPS Off ,

IN

= 6V to 25V,

IN

= 5V, No Load on LDO, VOUT1, VOUT2 and REF, T

ENLDO

-- 180 250 μA

-- 20 40 μA

= 25°C,

A

Both SMPSs On,

V

OUT1

V

OUT2

FBx V

FB1 = S KIP = GND, FB2 = V
V

= BYP = 5.3V,

OU T1

= 3.5V (Note 5)

V

OU T2

V

= 6V to 25V, FB1= GND,

IN

SKIP = 5V

= 6V to 25V, FB2 = VCC,

V

IN

SKIP = 5V

= 6V to 25V 1.975 2 2.025 V

IN

CC

,

-- 5 7 mW

4.975 5.05 5.125 V

3.285 3.33 3.375 V

SMPS1, SMPS 2 2 -- 5.5 V

Fixed or Adj-Mode comparator
threshold

0.2 0.4 0.55 V

Either SMPS , SKIP = VCC, 0 to 5A -- −0.1 --

LOAD

Either SMPS, SKIP = REF, 0 to 5A

-- −1. 7 - -

Either SMPS, SKIP = GND, 0 to 5A -- −1.5 --

%

Line Regulation V

E ither SMPS, VIN = 6V to 25V -- 0.005 -- %/V

LINE

On Time

SMPS1 = 5.05V (200kHz) 1895 2105 2315

SMPS2 = 3.33V (250kHz) 999 1110 1221

SMPS1 = 5.05V (300kHz) 1227 1403 1579

SMPS2 = 3.33V (375kHz) 647 740 833

SMPS1 = 5.05V (400kHz) 895 1052 1209

SMPS2 = 3.33V (500kHz) 475 555 635

ns

On-Time Pulse Width t

Minimum Off-Time t

TON =
V

CC

TON =

UGATEx

REF

TON =
GND

200 300 400 ns

LGATEx

Ultrasonic Mode Frequency SKIP = REF 25 33 -- kHz

Soft Start

Soft-Start Time t

Zero to full limit from ENx Enable -- 2 -- ms

SSx

Current Sense

Current Limit Threshold
(Default)

Current Limit Current
Source

I

4.75 5 5.25 μA

I

LIMX

= VCC, GND − P HASEx 90 100 110 mV

LIMx

To be continued

DS8206A/B-05 May 2011 www.richtek.com

9

RT8206A/B

Parameter Symbol Test Conditions Min Typ Max Unit

I

Adjustment Range V

LIM

Current-Limit Threshold

Zero-Current Threshold SKIP = GND or REF, GND − PHASEx -- 3 -- mV

Internal Regulator and Reference

= I

ILIMx

LIMx

GND

− PHASEx

× R

V

V

V

0.5 -- 2 V

ILIMx

= 0.5V 40 50 60

ILIMx

= 1V 90 100 110

ILIMx

= 2V 180 200 220

ILIMx

mV

LDO Output Voltage V

LDO Output Current I

LDO

BYP = GND, VIN = 6V to 25V 70 -- -- mA

LDO

0 < I

LDO

< 70mA

BYP = GND, 6V < V

< 25V,

IN

4.9 5 5.1 V

LDO Short-Circuit Current LDO = GND, BYP = GND -- 200 300 mA

LDO 5V Switchover
Threshold to BYP

LDO Switchover Equivalent
Resistance

REF Output Voltage V

V

BYP

R

LDO to BYP, 10mA -- 1.5 3 Ω

SW

No External Load 1.98 2 2.02 V

REF

REF Load Regulation I

Falling Edge, Rising Edge at BYP
Regulation Point

= 0 to 50uA -- 10 -- mV

REF

4.53 4.66 4.79 V

REF Sink Current REF in Regulation 10 -- -- μA

UVLO

Rising Edge -- 4.35 4.5

PVCC UVLO Threshold PVCC

V

Falling Edge 3.9 4.05 --

Power Good

FBx with Respect to Internal

PGOODx Threshold

Reference, Falling Edge,

−11 −7.5 −4 %

Hyste r esi s = 1%

PGOODx Propagation Delay Falling Edge -- 10 -- μs
PGOODx Leakage Current High State, Forced to 5.5V -- -- 1 μA

PGOODx Output Low
Voltage

I

= 4mA -- -- 0.3 V

SINK

Fault Detection

OVP Trip Threshold V

FB_OVP

FBx with Respect to Internal Ref. 108 111 115 %

OVP Propagation Delay FBx with 50mV Overdrive -- 10 -- μs

UVP Trip Threshold FBx with Respect to Internal Ref. 65 70 75 %

UVP Shutdown Blanking
Time

t

SHDN_UVP

From ENx Enable -- 3 -- ms

T hermal Shutdown

Thermal Shutdown T
Thermal Shutdown

Hysteresis

-- 150 -- °C

SH DN

-- 10 -- °C

Logic Input

FB1/FB2 Input Voltage

Low Level (Internal Fixed V

High Level (Internal Fixed V

) -- -- 0.2

OUT x

) VCC−1 -- --

OUT x

To be continued

DS8206A/B-05 May 2011www.richtek.com

10

V

Parameter Symbol Test Conditions Min Typ Max Unit

SKIP Input Voltage

TON Setting Voltage

ENx Input Voltage

ENLDO Input Voltage V

ENLDO

RT8206A/B

Low Level (DEM) -- -- 0.8

REF Level (Ultrasonic Mode) 1.8 -- 2.3

High Level (PWM Mode) 2.5 -- --

V

/ V

OUT 1

V

/ V

OUT 1

V

/ V

OUT 1

Clear Fault Level / SMPS Off Level -- -- 0.8

Delay Start 1.8 -- 2.3

SMPS On Level 2.5 -- --

Rising Edge 1.2 1.6 2.0

Falling Edge 0.94 1 1.06
ENLDO = 0V or 25V −1 -- +3
ENx = 0V or 5V −1 -- +1

(400kHz / 500kHz) -- -- 0.8

OUT 2

(300kHz / 375kHz) 1.8 -- 2.3

OUT 2

(200kHz / 250kHz) 2.5 -- --

OUT 2

V

V

V

V

Input Leakage Current

TON, SKIP = 0V or 5V

−1 -- +1

μA

FBx = 0V or 5V −1 -- +1
SECFB = 0V or 5V (RT8206A) −1 -- +1

Internal BOOT Switch

Internal Boost Charging
Switch On-Resistance

PVCC to BOOTx -- 20 -- Ω

Power MOSFET Drivers

UGATEx Driver Sink/Source
Current

LGATEx Driver Source
Current

UGATEx Forced to 2V -- 2 -- A

LGATEx Forc ed to 2V -- 1.7 -- A

LGATEx Driver Sink Current LGATEx Forced to 2V -- 3.3 -- A
UGATEx On-Resistance B OOTx to PHA SEx F orced to 5V -- 1.5 4 Ω

LGATEx, High State -- 2.2 5

LGATEx On-Resistance

Ω

LGATEx, Low State -- 0.6 1.5

Dead Time

LG Rising -- 30 --

ns

UG Rising -- 40 --

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. P

is measured in the natural convection at T

JA

JEDEC 51-7 thermal measurement standard.

+ P

VIN

PVCC

= 25°C on a high effective four layers thermal conductivity test board of

A

DS8206A/B-05 May 2011 www.richtek.com

11

RT8206A/B

Typical Operating Characteristics

VOUT1 Efficiency v s. Load Current

100

DEM Mode

90

80

70

60

50

40

Efficiency (%)

30

20

10

0

0.001 0.01 0.1 1 10

Ultrasonic Mode

PWM Mode

VIN = 7V, TON = VCC,
EN2 = GND, EN1 = V
ENLDO = VIN, FB1 = GND

Load Current (A)

VOUT1 Efficiency vs. Load Current

100

90

DEM Mode

80

70

60

50

40

Efficiency (%)

30

20

10

0

0.001 0.01 0.1 1 10

Load Current (A)

Ultrasonic Mode

PWM Mode

VIN = 25V, TON = VCC,
EN2 = GND, EN1 = V
ENLDO = VIN, FB1 = GND

CC

CC

VOUT1 Efficienc y vs. Load Current

100

90

DEM Mode

80

70

60

50

40

Efficiency (%)

30

20

,

10

0

0.001 0.01 0.1 1 10

Ultrasonic Mode

PWM Mode

VIN = 12V, TON = VCC,
EN2 = GND, EN1 = V
ENLDO = V

, FB1 = GND

IN

CC

,

Load Current (A)

VOUT2 Efficiency vs. Load Current

100

90

80

70

60

50

40

Efficiency (%)

30

20

,

10

DEM Mode

Ultrasonic Mode

PWM Mode

VIN = 7V, TON = VCC,
EN2 = V
ENLDO = VIN, FB2 = GND

0

0.001 0.01 0.1 1 10

, EN1 = GND,

CC

Load Current (A)

12

VOUT2 Efficiency vs. Load Current

100

90

80

70

60

50

40

Efficiency (%)

30

20

10

0

0.001 0.01 0.1 1 10

DEM Mode

Ultrasonic Mode

PWM Mode

VIN = 12V, TON = VCC,
EN2 = VCC, EN1 = GND,
ENLDO = V

Load Current (A)

, FB2 = GND

IN

VOUT2 Efficiency vs. Load Current

100

90

80

70

60

50

40

Efficiency (%)

30

20

10

DEM Mode

Ultrasonic Mode

PWM Mode

VIN = 25V, TON = VCC,
EN2 = VCC, EN1 = GND,
ENLDO = V

0

0.001 0.01 0.1 1 10

, FB2 = GND

IN

Load Current (A)

DS8206A/B-05 May 2011www.richtek.com

RT8206A/B

VOUT1 Switching Frequency vs. Load Current

250

VIN = 7V, TON = VCC, EN2 = GND, EN1 = VCC,

225

ENLDO = V

200

PWM Mode

175

150

125

100

75

50

Switching Frequency (kHz)

Ultrasonic Mode

25

0

0.001 0.01 0.1 1 10

, FB1 = GND

IN

DEM Mode

Load Current (A)

VOUT1 Switching Frequency vs. Load Current

250

VIN = 25V, TON = VCC, EN2 = GND, EN1 = VCC,

225

ENLDO = VIN, FB1 = GND

200

PWM Mode

175

150

125

100

75

50

Ultrasonic Mode

Switching FrequencyY (kHz)

25

0

0.001 0.01 0.1 1 10

Load Current (A)

DEM Mode

VOUT1 Switching Frequency vs. Load Current

250

VIN = 12V, TON = VCC, EN2 = GND, EN1 = VCC,

225

ENLDO = V

200

PWM Mode

175

150

125

100

75

50

Ultrasonic Mode

Switching Frequency (kHz)

25

0

0.001 0.01 0.1 1 10

, FB1 = GND

IN

DEM Mode

Load Current (A)

VOUT2 Switching Frequency vs. Load Current

300

VIN = 7V, TON = VCC, EN2 = VCC, EN1 = GND,

275

ENLDO = VIN, FB2 = GND

250

PWM Mode

225

200

175

150

125

100

75

Ultrasonic Mode

50

Switching Frequency (kHz)

25

0

0.001 0.01 0.1 1 10

DEM Mode

Load Current (A)

VOUT2 Switching Frequency vs. Load Current

300

VIN = 12V, TON = VCC, EN2 = VCC, EN1 = GND,

275

ENLDO = VIN, FB2 = GND

250

PWM Mode

225

200

175

150

125

100

75

Ultrasonic Mode

50

Switching Frequency (kHz)

25

0

0.001 0.01 0.1 1 10

Load Current (A)

DEM Mode

VOUT2 Switching Frequency vs. Load Current

300

VIN = 25V, TON = VCC, EN2 = VCC, EN1 = GND,

275

ENLDO = VIN, FB2 = GND

250

PWM Mode

225

200

175

150

125

100

75

Ultrasonic Mode

50

Switching Frequency (kHz)

25

0

0.001 0.01 0.1 1 10

Load Current (A)

DEM Mode

DS8206A/B-05 May 2011 www.richtek.com

13

RT8206A/B

LDO Output Voltage vs. Output Current

5.04

VIN = 12V, EN1 = EN2 = GND, ENLDO = V

5.036

V

vs. Output Current

IN

2.00500

2.00475

2.00450

VIN = 12V, EN1 = EN2 = GND, ENLDO = V

REF

IN

5.032

5.028

Output Voltage (V)

5.024

5.02
0 10203040506070

Output Current (mA)

No Load Battery Current vs. Input Voltage

100

TON = VCC, EN1 = EN2 = VCC, ENLDO = V

PWM Mode

10

Ultrasonic Mode

1

Battery Current (mA)

DEM Mode

0.1
7 9 11 13 15 17 19 21 23 25

Input Voltage (V)

2.00425

(V)

2.00400

REF

V

2.00375

2.00350

2.00325

2.00300

-10 0 10 20 30 40 50

Output Current (uA)

Standby Current vs. Input Voltage

216

IN

Standby Current (uA)

No Load, EN1 = EN2 = GND, ENLDO = V

214

212

210

208

206

204

202

200

198

7 9 11 13 15 17 19 21 23 25

Standby Current

Input Voltage (V)

IN

14

Shutdown Current vs. Input Voltage

27

No Load on VOUT1, VOUT2, LDO and REF,
EN1 = EN2 = GND, ENLDO = GND

25

23

21

19

17

15

13

Shutdown Current (uA)

11

9

7 9 11 13 15 17 19 21 23 25

Shutdown Current

Input Voltage (V)

V

vs. Temperature

2.05

2.04

2.03

2.02

2.01

(V)

2.00

REF

1.99

V

1.98

1.97

1.96

1.95

-40 -25 -10 5 20 35 50 65 80 95 110 125

REF

Temperature

(°C)

DS8206A/B-05 May 2011www.richtek.com

VIN = 12.6V

RT8206A/B

V

IN

(10V/Div)

LDO

(5V/Div)

REF

(2V/Div)

CP

(10V/Div)

EN1

(5V/Div)

V

OUT1

(5V/Div)

Power On from VIN

No Load, VIN = 12V, TON = V
EN2 = GND, ENLDO = V

Time (400μs/Div)

Power On from EN1

PWM Mode

Power On from EN1

DEM Mode

EN1

(5V/Div)

V

OUT1

(5V/Div)

I

L1

(2A/Div)

PGOOD1

EN1 = VCC,

CC,

IN

(5V/Div)

TON = V

EN1 = VCC, EN2 = GND, ENLDO = V

CC,

No Load, VIN = 12V,

IN

Time (1ms/Div)

Power On from EN1

PWM Mode

EN1

(5V/Div)

V

OUT1

(5V/Div)

I

L1

(2A/Div)

PGOOD1

(5V/Div)

EN2

(5V/Div)

V

OUT2

(5V/Div)

I

L2

(2A/Div)

PGOOD2

(5V/Div)

TON = V

DEM Mode

TON = V

No Load, VIN = 12V,

EN1 = VCC, EN2 = GND, ENLDO = V

CC,

Time (1ms/Div)

Power On from EN2

No Load, VIN = 12V,

EN1 = GND, EN2 = VCC, ENLDO = V

CC,

Time (1ms/Div)

I

L1

(2A/Div)

PGOOD1

IN

(5V/Div)

TON = V

EN1 = VCC, EN2 = GND, ENLDO = V

CC,

I

= 4A, VIN = 12V,

LOAD

IN

Time (1ms/Div)

Power On from EN2

PWM Mode

EN2

(5V/Div)

V

OUT2

(5V/Div)

I

L2

(2A/Div)

PGOOD2

(5V/Div)

IN

TON = V

EN1 = GND, EN2 = VCC, ENLDO = V

CC,

Time (1ms/Div)

No Load, VIN = 12V,

IN

DS8206A/B-05 May 2011 www.richtek.com

15

RT8206A/B

EN2

(5V/Div)

V

OUT2

(5V/Div)

I

L2

(2A/Div)

PGOOD2

(5V/Div)

EN1

(5V/Div)

EN2

(5V/Div)

Power On from EN2

PWM Mode

I

= 4A, VIN = 12V,

LOAD

TON = V

EN1 = GND, EN2 = VCC, ENLDO = V

CC,

Time (1ms/Div)

Power On from EN2 (Delay Start)

EN1 = REF

Power On from EN1 (Delay Start)

EN2 = REF

EN1

(5V/Div)

EN2

(5V/Div)

V

OUT1

(2V/Div)

V

OUT2

IN

(2V/Div)

VIN = 12V, TON = VCC, ENLDO = V

IN

Time (400μs/Div)

Power Off from EN1

EN1

(10V/Div)

V

OUT1

(5V/Div)

V

OUT1

(2V/Div)

V

OUT2

(2V/Div)

V

OUT1_ac-

coupled

(50mV/Div)

I

L1

(5A/Div)

LGATE1

(5V/Div)

VIN = 12V, TON = VCC, ENLDO = V

Time (400μs/Div)

VOUT1 Load Transient Response

PWM Mode, VIN = 12V

TON = VCC, SKIP = VCC, ENLDO = VIN, FB1 = V

CC

UGATE1

(20V/Div)

LGATE1

IN

(5V/Div)

VIN = 12V, TON = VCC, SKIP = VCC, ENLDO = V

IN

Time (10ms/Div)

VOUT2 Load Transient Response

PWM Mode, VIN = 12V

V

OUT2_ac-

coupled

(50mV/Div)

I

L2

(2A/Div)

LGATE2

(5V/Div)

TON = VCC, SKIP = VCC, ENLDO = VIN, FB2 = V

CC

16

Time (20μs/Div)

Time (20μs/Div)

DS8206A/B-05 May 2011www.richtek.com

RT8206A/B

VOUT1

(5V/Div)

PGOOD1

(5V/Div)

VOUT2

(5V/Div)

PGOOD2

(5V/Div)

VOUT1

(1V/Div)

I

L1

(5A/Div)

OVP

VIN = 12V, TON = VCC, SKIP = GND, ENLDO = V

Time (500μs/Div)

Power On in Short Circuit

V

= Short

OUT1

UVP

VOUT1

(5V/Div)

I

L1

(10A/Div)

UGATE1

(20V/Div)

LGATE1

IN

(5V/Div)

VIN = 12V, TON = VCC, SKIP = VCC, ENLDO = V

Time (10μs/Div)

IN

UGATE1

(20V/Div)

LGATE1

(5V/Div)

VIN = 12V, TON = VCC, SKIP = VCC, ENLDO = V

Time (400μs/Div)

IN

DS8206A/B-05 May 2011 www.richtek.com

17

RT8206A/B

Application Information

The RT8206A/B is a dual, high efficiency, Mach

ResponseTM DRVTM dual ramp valley mode synchronous

buck controller. The controller is designed for low-voltage

power supplies for notebook computers. Richtek Mach

ResponseTM technology is specifically designed for

providing 100ns “instant-on” response to load steps while

maintaining a relatively constant operating frequency and

inductor operating point over a wide range of input voltages.

The DRVTM mode PWM modulator is specifically designed

to have better noise immunity for such a dual output

application. The RT8206A/B achieves high efficiency at a

reduced cost by eliminating the current-sense resistor

found in traditional current-mode PWMs. Efficiency is

further enhanced by its ability to drive very large

synchronous rectifier MOSFETs. The RT8206A/B includes

5V (LDO) linear regulator which can step down the battery

voltage to supply both internal circuitry and gate drivers.

When V

voltage is above 4.66V, an automatic circuit

OUT1

turns off the linear regulator and powers the device from

V

through BYP pin connected to V

OUT1

OUT1

.

PWM Operation

TM

The Mach ResponseTM DRV

mode controller relies on

the output filter capacitor's effective series resistance

(ESR) to act as a current-sense resistor, so the output

ripple voltage provides the PWM ramp signal. Refer to the

function block diagram, the UGATE driver will be turned

on at the beginning of each cycle. After the internal one-

shot timer expires, the UGATE driver will be turned off.

The pulse width of this one shot is determined by the

converter's input voltage and the output voltage to keep

the frequency fairly constant over the input voltage range.

Another one-shot sets a minimum off-time (300ns typ.).

The on-time one-shot is triggered if the error comparator

is high, the low-side switch current is below the current-

limit threshold, and the minimum off-time one-shot has

timed out.

PWM Frequency and On-Time Control

The Mach ResponseTM control architecture runs with

pseudo-constant frequency by feed-forwarding the input

and output voltage into the on-time one-shot timer. The

high-side switch on-time is inversely proportional to the

input voltage as measured by the VIN, and proportional to

the output voltage. The on-time is given by :

On-Time= K (V

OUT

/ VIN)

There “K” is set by the TON pin-strap connector (Table

1). One-shot timing error increases for the shorter on-

time setting due to fixed propagation delays that is

approximately ±15% at high frequency and the ±10% at

low frequency. The on-time guaranteed in the Electrical

Characteristics tables is influenced by switching delays

in the external high-side power MOSFET. Two external

factors that influence switching-frequency accuracy are

resistive drops in the two conduction loops (including

inductor and PC board resistance) and the dead-time effect.

These effects are the largest contributors to the change

of frequency with changing load current. The dead-time

effect increases the effective on-time, reducing the

switching frequency as one or both dead times. It occurs

only in PWM mode (SKIP = high) when the inductor

current reverses at light or negative load currents. With

reversed inductor current, the inductor's EMF causes

PHASEX to go high earlier than normal, extending the on-

time by a period equal to the low-to-high dead time. For

loads above the critical conduction point, the actual

switching frequency is :

FS = (V

The V

+V

OUT

is the sum of the parasitic voltage drops in the

DROP1

) / TON x (VIN + V

DROP1

DROP1

− V

DROP2

)

inductor discharge path, including synchronous rectifier,

inductor, and PC board resistances; V

DROP2

is the sum of

the resistances in the charging path; and TON is the on-

time calculated by the RT8206A/B.

Table 1. TON Setting and PWM Frequency Table

TON

V

OUT1

K-Factor

V

OUT1

Frequency

V

OUT2

K-Factor

V

OUT2

Frequency

Approximate

K-Factor Error

TON

= VCC

5μs 3.33μs 2.5μs

200kHz 300kHz 400kHz

4μs 2.67μs 2μs

250kHz 375kHz 500kHz

±10% ±12.5% ±15%

TON

= REF

TON

= GND

18

DS8206A/B-05 May 2011www.richtek.com

RT8206A/B

Operation Mode Selection

The RT8206A/B supports three operation modes: Diode-

Emulation Mode, Ultrasonic Mode, and Forced-CCM

Mode. Users can set operation mode by SKIP pin. All of

the three operation modes will be introduced as follows.

Diode-Emulation Mode (SKIP = GND)

In Diode-Emulation mode, the RT8206A/B automatically

reduces switching frequency at light-load conditions to

maintain high efficiency. This reduction of frequency is

achieved smoothly and without the increase of V

OUTx

ripple

or load regulation. As the output current decreases from

heavy-load condition, the inductor current is also reduced,

and eventually comes to the point that its valley touches

zero current, which is the boundary between continuous

conduction and discontinuous conduction modes. By

emulating the behavior of diodes, the low-side MOSFET

allows only partial of negative current when the inductor

free-wheeling current reach negative. As the load current

further decreases, it takes longer and longer to discharge

the output capacitor to the level that requires for the next

“ON” cycle. The on-time is kept the same as that in the

heavy-load condition. In reverse, when the output current

increases from light load to heavy load, the switching

frequency increases to the preset value as the inductor

current reaches the continuous conduction. The transition

load point to the light-load operation can be calculated as

following equation.

(V V )

−

I T

LOAD ON

IN OUT

≈×

2L

The switching waveforms may appear noisy and

asynchronous when light loading causes Diode-Emulation

operation, but this is a normal operating condition that

results in high light-load efficiency. Trade-offs in PFM noise

vs. light-load efficiency is made by varying the inductor

value. Generally, low inductor values produce a broader

efficiency vs. load curve, while higher values result in higher

full-load efficiency (assuming that the coil resistance

remains fixed) and less output voltage ripple. Penalties

for using higher inductor values include larger physical

size and degraded load-transient response (especially at

low input-voltage levels).

Ultrasonic Mode (SKIP = REF)

Connecting SKIP to REF activates a unique Diode-

Emulation mode with a minimum switching frequency

above 25kHz. This ultrasonic mode eliminates audio-

frequency modulation that would otherwise be present

when a lightly loaded controller automatically skips

pulses. In ultrasonic mode, the low-side switch gate-driver

signal is OR with an internal oscillator (>25kHz). Once

the internal oscillator is triggered, the ultrasonic controller

forces the LGATEx high, turning on the low-side MOSFET

to induce a negative inductor current. At the point that the

output voltage is higher than that of REF, the controller

turns off the low-side MOSFET (LGATEx pulled low) and

triggers a constant on-time (UGATEx driven high). When

the on-time has expired, the controller re-enables the low-

side MOSFET until the controller detects that the inductor

current dropped below the zero-crossing threshold.

where TON is the given On-time.

I

L

Slope = (VIN -V

OUT

) / L

i

L, peak

Forced-CCM Mode (SKIP = VCC)

The low-noise, forced-CCM mode (SKIP = VCC) disables

the zero-crossing comparator, which controls the low-side

switch on-time. This causes the low-side gate-driver

waveform to become the complement of the high-side gate-

i

Load

= i

L, peak

/ 2

driver waveform. This in turn causes the inductor current

to reverse at light loads as the PWM loop strives to

0

t

ON

t

Figure 3. Boundary Condition of CCM/DEM

maintain a duty ratio of V

CCM mode is to keep the switching frequency fairly

constant, but it comes at a cost : The no-load battery

. The benefit of the forced-

OUT/VIN

current can be 10mA to 40mA, depending on the external

MOSFETs.

DS8206A/B-05 May 2011 www.richtek.com

19

RT8206A/B

Reference and Linear Regulator (REF, LDO and 14V
Charge Pump)

The 2V reference (REF) is accurate within ±1% over

temperature, making REF useful as a precision system

reference. Bypass REF to GND with 0.22uF

(MIN)

capacitor.

REF can supply up to 50uA for external loads. Loading

REF degrades FBx and output accuracy according to the

REF load-regulation error.

An internal regulator produces a fixed output voltage 5V.

The LDO regulator can supply up to 70mA for external

loads. Bypass LDO with a minimum 4.7μF ceramic

capacitor. When the output voltage of the V

OUT1

is higher

than the switchover threshold, an internal 1.5Ω N-Channel

MOSFET switch connects V

to LDO through BYP

OUT1

while simultaneously shutting down the internal linear

regulator.

In typical application circuit figure, the external 14V charge

pump is driven by LGATE1. When LGATE1 is low, D1

charge C5 sourced from V

V

minus a diode drop. When LGATE1 transitions to

OUT1

. C5 voltage is equal to

OUT1

high, the charge from C5 will transfer to C6 through D2

and charge it to V

plus VC5. As LGATE1 transients

LGATE1

low on the next cycle, C6 will charge C7 to its voltage

minus a diode drop through D3. Finally, C7 charges C8

through D4 when LGATE1 transi switched to high. CP

output voltage is :

CP = V

OUT1

+2 x V

LGATE1

− 4 x V

D

Where :

of Figure 3), will also increase the robustness of the charge

pump.

Current-Limit Setting (ILIMx)

The RT8206A/B has a cycle-by-cycle current limiting

control. The current-limit circuit employs a unique “valley”

current sensing algorithm. If the magnitude of the current-

sense signal at PHASEx is above the current-limit

threshold, the PWM is not allowed to initiate a new cycle

(Figure 4). The actual peak current is greater than the

current-limit threshold by an amount equal to the inductor

ripple current. Therefore, the exact current-limit

characteristic and maximum load capability are a function

of the sense resistance, inductor value, battery voltage,

and output voltage.

I

L

I

L, peak

I

Load

I

LIM

0

t

Figure 4. Valley Current-Limit

The RT8206A/B uses the on-resistance of the synchronous

rectifier as the current-sense element. Use the worse-

case maximum value for R

from the MOSFET

DS(ON)

datasheet, and add a margin of 0.5%/°C for the rise in

R

with temperature.

DS(ON)

` V

` V

is the peak voltage of the LGATE1 driver

LGATE1

is the forward diode dropped across the Schottkys

D

SECFB (RT8206A) is used to monitor the charge pump

through resistive divider. In an event when SECFB drops

below 2V, the detection circuit forces the LGATE1 on for

300ns to allow CP to recharge and the SECFB rise above

2V. In the event of an overload on CP where SECFB can

not reach more than 2V, the monitor will be deactivated.

The SECFB pin has a 17mV of hysteresis so the ripple

should be enough to bring the SECFB voltage above the

threshold by ~3x the hysteresis, or (3 x 17mV) = 51mV.

Reducing the CP decoupling capacitor and placing a small

ceramic capacitor C19 (10pF to 47pF) in parallel will the

upper leg of the SECFB resistor feedback network (R11

20

The current-limit threshold is adjusted with an external

resistor for the RT8206A/B at ILIMx. The current-limit

threshold adjustment range is from 50mV to 200mV. In

the adjustment mode, the current-limit threshold voltage

is precise to 1/10 the voltage seen at ILIMx. The threshold

defaults to 100mV when ILIMx is connected to VCC. The

logic threshold for switchover to the 100mV default value

is higher than VCC−1V.

Carefully observe the PC board layout guidelines to ensure

that noise and DC errors do not corrupt the current-sense

signal at PHASEx and GND. Mount or place the IC close

to the low-side MOSFET.

DS8206A/B-05 May 2011www.richtek.com

RT8206A/B

MOSFET Gate Driver (UGATEx, LGA TEx)

The high-side driver is designed to drive high-current, low

R

N-MOSFET(s). When configured as a floating driver

DS(ON)

the instantaneous drive current is supplied by the flying

capacitor between BOOTx and PHASEx pins. A dead time

to prevent shoot through is internally generated between

high-side MOSFET off to low-side MOSFET on, and low-

side MOSFET off to high-side MOSFET on.

The low-side driver is designed to drive high current low

R

N-MOSFET(s). The internal pulldown transistor

DS(ON)

that drives LGATEx low is robust, with a 0.6Ω typical on-

resistance. A 5V bias voltage is typically delivered from

PVCC through LDO supply. The instantaneous drive

current is supplied by an input capacitor connected

between PVCC and GND.

For high-current applications, some combinations of high-

and low-side MOSFETs might be encountered that will

cause excessive gate-drain coupling, which can lead to

efficiency-killing, EMI-producing shoot-through currents.

This is often remedied by adding a resistor in series with

BOOTx, which increases the turn-on time of the high-side

MOSFET without degrading the turn-off time (Figure 5).

V

IN

BOOTx

UGATEx

PHASEx

10

Figure 5. Reducing the UGATEx Rise Time

Soft-Start

A built-in soft-start is used to prevent surge current from

power supply input after ENx is enabled. The typical soft-

start duration is 2ms period. The maximum allowed current

limit is segmented in 5 steps : 20%, 40%, 60%, 80% and

100% during this period. The current limit steps can

eliminate the V

folded-back in the soft-start duration.

OUT

POR and UVLO

Power-on reset (POR) occurs when VIN rises above

approximately 3.7V (typ.), resetting the fault latches.

PVCC undervoltage-lockout (UVLO) circuitry inhibits

switching by keeping UGATEx and LGATEx low when

PVCC is below 4V. The PWM outputs begin to ramp up

once PVCC exceeds its UVLO threshold and ENx is

enable.

Power-Good Output (PGOODx)

The PGOODx is an open-drain type output. PGOODx is

actively held low in soft-start, standby, and shutdown. It is

released when the VOUTx voltage is above than 92.5% of

the nominal regulation point. The PGOODx goes low if it

is 7.5% below its nominal regulator point.

Output Over voltage Protection (OVP)

The output voltage can be continuously monitored for over

voltage protection. When the output voltage of the VOUTx

is 11% above the set voltage, over voltage protection will

be enabled, if the output exceeds the over voltage

threshold, over voltage fault protection will be triggered

and the LGATEx low-side gate drivers are forced high.

This activates the low-side MOSFET switch, which rapidly

discharges the output capacitor and reduces the output

voltage. Once an over-voltage fault condition is set, it can

only be reset by toggling ENLDO, ENx, or cycling VIN

(POR.)

Output Under-Voltage Protection (UVP)

The output voltage can be continuously monitored for under

voltage protection. If the output is less than 70% of the

error-amplifier trip voltage, under voltage protection will be

triggered, and then both UGATEx and LGATEx gate drivers

will be forced low. The UVP will be ignored for at least

3ms (typ.) after start-up or after a rising edge on ENx.

Toggle ENx or cycle VIN (POR) to clear the under-voltage

fault latch and restart the controller. The UVP only applies

to the BUCK outputs.

Thermal Protection

The RT8206A/B has a thermal shutdown protection

function to prevent it from overheating. Thermal shutdown

occurs when the die temperature exceeds +150°C. All

internal circuitry will be shut down during thermal shutdown.

The RT8206A/B may trigger thermal shutdown if the LDO

were not supplied from VOUTx, while input voltage is on

VIN and drawing current that is too high from the LDO.

Even if the LDO is supplied from VOUTx, overloading the

DS8206A/B-05 May 2011 www.richtek.com

21

RT8206A/B

LDO causes large power dissipation on automatic

switches, which may result in thermal shutdown.

Discharge Mode

When standby or shutdown mode occurs, or the output

under voltage fault latch is set, the outputs discharge mode

is triggered. During discharge mode, the output capacitor

will be discharged to GND through an internal 20Ω switch.

Shutdown Mode

The RT8206A/B SMPS1, SMPS2 and LDO have

independent enabling control. Drive ENLDO, EN1 and EN2

below the precise input falling-edge trip level to place the

RT8206A/B in its low-power shutdown state. The

RT8206A/B consumes only 20uA of quiescent current while

in shutdown. When shutdown mode is activated, the

reference turns off. The accurate 1V falling-edge threshold

on the ENLDO can be used to detect a specific analog

voltage level and shutdown the device. Once in shutdown,

the 1.6V rising-edge threshold activates, providing sufficient

hysteresis for most application.

⎡⎤

R1

V = V 1

OUTx FBx

Where V

is 2V (typ.).

FBx

UGATEx

PHASEx

LGATEx

VOUTx

GND

⎛⎞

×+

⎜⎟

⎢⎥

R2

⎝⎠

⎣⎦

V

IN

FBx

R1

R2

V

OUTx

Figure 6. Setting VOUTx with a Resistor-Divider

Output Inductor Selection

The switching frequency (on-time) and operating point (%

ripple or LIR) determine the inductor value as follows :

T(V - V)

×

ON IN OUT

L =

LI

×

IR LOAD(MAX)

Where LIR is the ratio of the peak-to-peak ripple current

to the average inductor current.

Power-Up Sequencing and On/Off Controls (ENx)

EN1 and EN2 control SMPS power-up sequencing. When

the RT8206A/B applies in the single channel mode, EN1

or EN2 enables the respective outputs when ENx voltage

rising above 2.5V, and disables the respective outputs

when ENx voltage falling below 1.8V.

Connecting one of ENx to VCC and the other one to REF

can force the latter one output starts after the former one

regulates.

If both of ENx forced to connect to REF, both outputs will

always wait for the regulation of the other one. However,

in this situation, neither of the two ENx will be in regulation.

Output Voltage Setting (FBx)

Connect FB1 directly to GND or VCC for a fixed 5V output

(VOUT1). Connect FB2 directly to GND or VCC for a fixed

3.3V output (VOUT2).

The output voltage can also be adjusted from 2V to 5.5V

with a resistor-divider network (Figure 6). The following

equation is for adjusting the output voltage. Choose R2 to

be approximately 10kΩ, and solve for R1 using the following

equation :

Find a low-loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite cores

are often the best choice, although the powdered iron is

inexpensive and can work well at 200kHz. The core must

be large enough to prevent it from saturating at the peak

inductor current (I

I

= I

PEAK

LOAD(MAX)

) :

PEAK

+ [(LIR / 2) x I

LOAD(MAX)

]

This inductor ripple current also impacts transient-response

performance, especially at low V

IN

− V

differences.

OUTx

Low inductor values allow the inductor current to slew

faster, replenishing charge removed from the output filter

capacitors by a sudden load step. The peak amplitude of

the output transient. The V

the output transient (V

also features a function of

SAG

) is also a function of the

SAG

maximum duty factor, which can be calculated from the

on-time and minimum off-time :

2

LOAD OFF(MIN)

V =

SAG

(I ) L K T

Δ×× +

2C V K T

×× × −

OUT OUTx OFF(MIN)

Where minimun off-time (T

OFF(MIN)

OUTx

⎜⎟

V

IN

⎝⎠

⎡⎤

VV

−

⎛⎞

IN OUTx

⎜⎟

⎢⎥
⎣⎦

V

⎝⎠

IN

) = 300ns (typ.) and K

V

⎛⎞

is from Table 1.

22

DS8206A/B-05 May 2011www.richtek.com

RT8206A/B

Output Capacitor Selection

The output filter capacitor must have low enough equivalent

series resistance (ESR) to meet output ripple and load-

transient requirements, yet have high enough ESR to

satisfy stability requirements. The output capacitance

must also be high enough to absorb the inductor energy

while transiting from full-load to no-load conditions without

tripping the overvoltage fault latch.

Although Mach ResponseTM DRVTM dual ramp valley mode

provides many advantages such as ease-of-use, minimum

external component configuration, and extremely short

response time, due to not employing an error amplifier in

the loop, a sufficient feedback signal needs to be provided

by an external circuit to reduce the jitter level. The required

signal level is approximately 15mV at the comparing point.

This generates V

RIPPLE

= (V

/ 0.75) x 15mV at the

OUT

output node. The output capacitor ESR should meet this

requirement.

Output Capacitor Stability

Stability is determined by the value of the ESR zero relative

to the switching frequency. The point of instability is given

by the following equation :

f =

ESR

1

2 ESR C 4

π

×× ×

OUT

f

SW

≤

Do not put high-value ceramic capacitors directly across

the outputs without taking precautions to ensure stability.

Large ceramic capacitors can have a high- ESR zero

frequency and cause erratic, unstable operation. However,

it is easy to add enough series resistance by placing the

capacitors a couple of inches downstream from the

inductor and connecting VOUTx or the FBx divider close

to the inductor.

There are two related but distinct ways including double-

pulsing and feedback loop instability in the unstable

operation.

Double-pulsing occurs due to noise on the output or

because the ESR is too low that there is not enough

voltage ramp in the output voltage signal. This “fools”

the error comparator into triggering a new cycle

immediately after the 300ns minimum off-time period has

expired. Double-pulsing is more annoying than harmful,

resulting in nothing worse than increased output ripple.

However, it may indicate the possible presence of loop

instability, which is caused by insufficient ESR.

Loop instability can result in oscillations at the output

after line or load perturbations that can trip the over-voltage

protection latch or cause the output voltage to fall below

the tolerance limit.

The easiest method for checking stability is to apply a

very fast zero-to-max load transient and carefully observe

the output-voltage-ripple envelope for overshoot and ringing.

It helps to simultaneously monitor the inductor current

with an AC current probe. Do not allow more than one

cycle of ringing after the initial step-response under- or

overshoot.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum operation junction temperature. The maximum

power dissipation depends on the thermal resistance of

IC package, PCB layout, the rate of surroundings airflow

and temperature difference between junction to ambient.

The maximum power dissipation can be calculated by

following formula :

P

Where T

temperature, T

D(MAX)

= ( T

J(MAX)

- TA ) / θ

J(MAX)

JA

is the maximum operation junction

is the ambient temperature and the θ

A

JA

the junction to ambient thermal resistance.

For recommended operating conditions specification of

RT8206, the maximum junction temperature is 125°C. The

junction to ambient thermal resistance θJA is layout

dependent. For WQFN-32L 5x5 packages, the thermal

resistance θJA is 36°C/W on the standard JEDEC 51-7

four layers thermal test board. The maximum power

dissipation at TA = 25°C can be calculated by following

formula :

P

= (125°C − 25°C) / (36°C/W) = 2.778W for

D(MAX)

WQFN-32L 5x5 packages

The maximum power dissipation depends on operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance θJA. For RT8206A/B packages, the Figure 7

of derating curves allows the designer to see the effect of

rising ambient temperature on the maximum power

allowed.

is

DS8206A/B-05 May 2011 www.richtek.com

23

RT8206A/B

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

Maximum Power Dissipation (W)

0.0
0 25 50 75 100 125

WQFN -32L 5x5

Four Layers PCB

Ambient Temperature (°C)

Figure 7. Derating Curves for RT8206A/B Packages

Layout Considerations

Layout is very important in high frequency switching

converter design. If the layout is designed improperly, the

PCB could radiate excessive noise and contribute to the

converter instability. The following points must be followed

for a proper layout of RT8206A/B.

TON should be placed away from high-voltage switching

nodes such as PHASEx, LGATEx, UGATEx or BOOTx

nodes to avoid coupling. Use internal layer(s) as ground

plane(s) and shield the feedback trace from power traces

and components.

` Gather ground terminal of VIN capacitor(s), VOUTx

capacitor(s), and source of low-side MOSFETs as close

as possible. PCB trace defined as PHASEx node, which

connects to source of high-side MOSFET, drain of low-

side MOSFET and high-voltage side of the inductor,

should be as short and wide as possible.

` Connect RC low-pass filter from PVCC to VCC, the RC

low-pass filter is composed of an external capacitor and

an internal 10Ω resistor. Bypass VCC to GND with a

capacitor 1uF is recommended. Place the capacitor

close to the IC, within 12mm (0.5 inch) if possible.

` Keep current limit setting network as close as possible

to the IC. Routing of the network should avoid coupling

to high-voltage switching node.

` Connections from the drivers to the respective gate of

the high-side or the low-side MOSFET should be as

short as possible to reduce stray inductance. Use

0.65mm (25 mils) or wider trace.

` All sensitive analog traces and components such as

VOUTx, FBx, GND, ENx, PGOODx, ILIMx, VCC, and

24

DS8206A/B-05 May 2011www.richtek.com

RT8206A/B

V

Table 2. Operation Mode Truth Table

Mode Condition Comment

Power-UP PVCC < UVLO threshold

RUN ENLDO = high, EN1 or EN2 enabled Normal Operation.

Over voltage

Protection

Under voltage

Protection

Discharge

Standby

Shutdown EN1, EN2, ENLDO=low All circuitry off.

Thermal Shutdown TJ > +150°C All circuitry off. Exit by VIN POR or by toggling ENLDO.

Either output > 111% of nominal
level.

Either output<70% of nominal level
after 3ms time-out expires and output
is enabled.

Either SMPS output is still high in
either standby mode or shutdown
mode.
ENx < startup threshold,
ENLDO = high.

Transitions to discharge mode after a VIN POR and
after REF becomes valid. LDO and REF remain active.

LGATEx is forced high. LDO and REF active. Exited by
VIN POR or by toggling ENLDO.
Both UGATEx and LGATEx are forced low until enter
discharge mode terminates. LDO and REF are active.
Exited by VIN POR or by toggling ENLDO, EN1, or
EN2.

During discharge mode, the output capacitor
discharges to GND through an internal 20Ω switch.

LGATEx stays low. LDO and REF active.

Table 3. Power-Up Sequencing

ENLDO (V) V

Low X X Off Off Off

“>2V” H igh Lo w Low

“>2V” H igh Lo w REF

“>2V” H igh Lo w High

“>2V” H igh REF Low

“>2V” H igh REF REF

“>2V” H igh REF High

“>2V” H igh High Low

“>2V” H igh High REF

“>2V” H igh High High

EN1

(V)

(V) LDO 5V SMPS1 3V SMPS2

EN2

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

On

(after REF powers up)

(after SMPS2 on)

Off Off

Off Off

Off On

Off Off

Off Off

On

On Off

On

On On

(aft er SMPS1 on )

On

On

DS8206A/B-05 May 2011 www.richtek.com

25

RT8206A/B

Outline Dimension

D

E

e

D2

SEE DETAIL A

1

E2

b

L

1
2

1

2

DETAIL A

A

A3

A1

Note : The configuration of the Pin #1 identifier is optional,

Pin #1 ID and Tie Bar Mark Options

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inch es

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 4.950 5.050 0.195 0.199

D2 3.400 3.750 0.134 0.148

E 4.950 5.050 0.195 0.199

E2 3.400 3.750 0.134 0.148

e 0.500 0.020

L 0.350 0.450

Richtek Technology Corporation

Headquarter

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: [phone] Fax: [phone]

0.014 0.018

W-Type 32L QFN 5x5 Package

Richtek Technology Corporation

Taipei Office (Marketing)

5F, No. 95, Minchiuan Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: [phone] Fax: [phone]

Email: [e-mail]

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit

design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be

guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

DS8206A/B-05 May 2011www.richtek.com

26