Richtek RT8205L, RT8205M Datasheet

High Efficiency, Main Power Supply Controller
for Notebook Computer

RT8205L/M

General Description

The RT8205L/M is a dual step-down, switch mode power

supply controller generating logic-supply voltages in

battery powered systems. It includes two Pulse-Width

Modulation (PWM) controllers adjustable from 2V to 5.5V,

and also features fixed 5V/3.3V linear regulators. Each

linear regulator provides up to 100mA output current with

automatic linear regulator bootstrapping to the PWM

outputs. An optional external charge pump can be

monitored through SECFB (RT8205M). The RT8205L/M

includes on-board power up sequencing, a power good

output, internal soft-start, and internal soft-discharge

output that prevents negative voltage during shutdown.

The constant on-time PWM control scheme operates

without sense resistors and provides 100ns response to

load transient response while maintaining nearly constant

switching frequency. To eliminate noise in audio

applications, an ultrasonic mode is included, which

maintains the switching frequency above 25kHz. Moreover,

the diode-emulation mode maximizes efficiency for light

load applications. The RT8205L/M is available in a

WQFN-24L 4x4 package.

Ordering Information

RT8205

Package Type
QW : WQFN-24L 4x4 (W-Type)

Features

zz

z Constant On-time Control with 100ns Load Step

zz

Response

zz

z Wide Input Voltage Range : 6V to 25V

zz

zz

z Dual Adjustable Outputs from 2V to 5.5V

zz

zz

z Secondary Feedback Input Maintains Charge Pump

zz

V oltage (RT8205M)

zz

z Fixed 3.3V and 5V LDO Output : 100mA

zz

zz

z 2V Reference Voltage

zz

zz

z Frequency Selectable via TONSEL Setting

zz

zz

z 4700ppm/

zz

zz

z Programmable Current Limit Combined with

zz

°°

°C R

°°

Current Sensing

DS(ON)

Enable Control

zz

z Selectable PWM, DEM, or Ultrasonic Mode

zz

zz

z Internal Soft-Start and Soft-Discharge

zz

zz

z High Efficiency up to 97%

zz

zz

z 5mW Quiescent Power Dissipation

zz

zz

z Thermal Shutdown

zz

zz

z RoHS Compliant and Halogen Free

zz

Applications

z Notebook and Sub-Notebook Computers

z 3-Cell and 4-Cell Li+ Battery-Powered Devices

Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)

Pin Function
L : Default
M : With SECFB

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

DS8205L/M-05 June 2011 www.richtek.com

1

RT8205L/M

Marking Information

EM= : Product Code

EM=YM

DNN

EM YM

DNN

Pin Configurations

ENTRIP1

TONSEL

ENTRIP2

YMDNN : Date Code

EM : Product Code

YMDNN : Date Code

VOUT1

1

2

FB1

3

REF

4

5

FB2

6

78910 1211

PGOOD

BOOT1

21 20 1924 2223

GND

UGATE1

25

RT8205MGQWRT8205LGQW

EN= : Product Code

EN=YM

YMDNN : Date Code

DNN

RT8205MZQWRT8205LZQW

EN : Product Code

EN YM

YMDNN : Date Code

DNN

(TOP VIEW)

LGATE1

PHASE1

18

NC

17

VREG5

16

VIN

15

GND

14

SKIPSEL

13

EN

ENTRIP1

FB1

REF

TONSEL

FB2

ENTRIP2

VOUT1

1

2

3

4

5

6

78910 1211

PGOOD

BOOT1

21 20 1924 2223

GND

UGATE1

PHASE1

25

LGATE1

18

17

16

15

14

13

SECFB
VREG5
VIN
GND
SKIPSEL
EN

VOUT2

VREG3

BOOT2

PHASE2

UGATE2

WQFN-24L 4x4

RT8205L

VOUT2

VREG3

LGATE2

BOOT2

LGATE2

PHASE2

UGATE2

WQFN-24L 4x4

RT8205M

DS8205L/M-05 June 2011www.richtek.com

2

Typical Application Circuit

1

C

1

0

µ

F

o

ON

R

R

T

O

O

B

C

2

0

.

F

1

µ

C

1

0

.

2

2

µ

l

o

t

r

c

i

n

Q1

BSC119

N03S

L

1

6

8

.

µ

V

O

U

1

T

5

V

C

3

2

2

0

µ

F

C

1

8

C

1

9

1

F

µ

0

.

H

r

M

BSC119

e

q

u

/

D

E

N03S

e

n

M

Q3

V

REF

2V

o

n

c

y

C

/

t

U

r

l

a

s

R

5

C

4

R

1

2

k

1

5

R

1

3

k

1

0

F

P

W

OFF

RT8205L/M

V

N

I

5

2

o

t

V

6

8

R
3

.

9

16

C

1

0

0

.

F

1

µ

0

4

21

0

1

22

VIN

UGATE1

BOOT1

RT8205L

UGATE2

BOOT2

PHASE2

LGATE2

GND

20

19

24

PHASE1

LGATE1

VOUT1

VOUT2

FB2

ENTRIP1

ENTRIP2

2

FB1

3

4

14

13

REF

TONSEL

SKIPSEL

EN

5
F

GND

VREG5

PGOOD

VREG3

R

0

1

10

9

11

0

R

0

B

O

O

T

2

C
0

12

15

7

5

R

1

M

L

I

I

1

k

0

1

6

5

R

2

M

L

I

I

k

0

5

1

25 (Exposed Pad)

17

C

9

F

µ

.

7

4

23

8

6

1

C

F

µ

.

7

4

Q2
BSC119

N03S

1

1

µ

1

F

.

Q4
BSC119

N03S

V

5

R

6

0

k

0

1

P

G

3

.

3

3

1

C

1

2

L

4

µ

7

.

R

1

1

4

1

C

l

A

w

y

a

O

D

O

I

A

V

l

w

a

C

2

1

F

µ

0

µ

0

F

1

H

7

1

C

0

2

2

1

4

R

5

k

6

.

1

5

R

k

1

0

s

O

n

i

d

n

r

o

c

t

a

y

n

O

s

V

V

O

T

U

2

V

.

3

3

F

µ

C

2

1

C

2

0

F

1

µ

0

.

V

N

I

5

2

o

t

V

6

8

1

C

1

0

F

µ

Q1

BSC119

N03S

L

1

8

.

µ

H

V

O

U

1

T

V

5

C

3

2

0

µ

F

2

C

1

9

1

0

.

6

R

5

BSC119

C

4

8

C

1

R

1

2

k

1

5

R

1

F

µ

3

1

0

k

C

6

µ

F

1

.

0

8

C

1

.

0

µ

F

Q3

N03S

2

D

4

D

A

B

0

D

1

D

3

2

5

T

4

CP

ON

OFF

R
3

.

9

16

0

C

1

0

.

1

F

µ

R

0

4

R

O

O

1

T

B

C

2

.

1

F

µ

21

0

22

20

19

24

2

C

5

0

µ

F

1

.

VIN

UGATE1

BOOT1

PHASE1

LGATE1

VOUT1

FB1

RT8205M

UGATE2

BOOT2

PHASE2

LGATE2

GND

VOUT2

FB2

ENTRIP1

ENTRIP2

GND

VREG5

7

C

F

µ

.

1

0

PGOOD

R

6

0

0

k

2

18

SECFB

R

7

k

9

3

13

EN

VREG3

REF

TONSEL

SKIPSEL

R

0

1

10

9

11

0

R

0

O

2

T

O

B

C
0

12

15

7

5

R

L

I

I

1

M

0

5

1

1

6

k

R

L

I

I

2

M

k

0

5

1

25 (Exposed Pad)

17

C

9

F

µ

.

7

4

23

8

C

6

1
.

7

4

F

µ

3

C

5

1

µ

2

2

.

0

4

14

Q2
BSC119

N03S

1

1

µ

F

1

.

Q4
BSC119

N03S

V

5

R

6

k

0

0

1

P

3

V
2V

G

.

3

REF

F

r

F

q

e

c

n

e

u

y

n

C

o

M

W

P

l

r

U

t

/

/

a

D

M

E

3

1

C

1

2

L

4

µ

7

.

R

1

1

4

1

C

l

A

w

y

a

s

I

D

O

O

l

A

V

w

a

l

r

t

o

i

s

c

n

o

C

2

1

F

µ

0

µ

F

0

1

H

1

C

7

0

2

2

1

4

R

5

k

6

.

1

5

R
1

0

k

O

n

d

n

r

i

t

o

c

a

y

s

O

n

V

V

O

T

U

2

V

.

3

3

F

µ

C

2

1

C

2

0

0

.

1

F

µ

DS8205L/M-05 June 2011 www.richtek.com

3

RT8205L/M

Functional Pin Description

Pin No. Pin Name Pin Function

Channel 1 Enable and Current Limit Setting Input. Connect a resistor to GND to
set the threshold for channel 1 synchronous R

1 ENTRIP1

2 FB1

3 REF

4 TON SEL

5 FB2

6 ENTRIP2

7 VOUT2

8 VREG3 3.3V Linear Regulator Output.

9 BOOT2

10 UGATE2

11 PHASE2

12 LGATE2

13 EN

14 SKIPSEL

15,

25 (Exposed Pad)

16 VIN Supply Input for 5V/3.3V LDO and Feed Forward On Time Circuitry.

17 VREG5

GND

current limit threshold is 1/10th the voltage seen at ENTRIP1 over a 0.515V to 3V
range. There is an internal 10μA current source from VREG5 to ENTRIP1. Leave
ENTRIP1 floating or drive it above 4.5V to shutdown channel 1.

SMPS1 Feedback Input. Connect FB1 to a resistive voltage divider from VOUT1
to GND to adjust output from 2V to 5.5V.

2V Reference Output. Bypass to GND with a minimum 0.22μF capacitor. REF
can source up to 100μA for external loads. Loading REF degrades FBx and
output accuracy according to the REF load regulation error.

Frequency Selectable Input for VOUT1/VOUT2 respectively.
400kHz/500kHz : Connect to VREG5 or VREG3
300kHz/375kHz : Connect to REF

200kHz/250kHz : Connect to GND
SMPS2 Feedback Input. Connect FB2 to a resistive voltage divider from VOUT2

to GND to adjust output from 2V to 5.5V.

Channel 2 Enable and Current Limit Setting Input. Connect a resistor to GND to
set the threshold for channel 2 synchronous R
current limit threshold is 1/10th the voltage seen at ENTRIP2 over a 0.515V to 3V
range. There is an internal 10μA current source from VREG5 to ENTRIP2. Leave
ENTRIP2 floating or drive it above 4.5V to shutdown channel 1.

Bypass Pin for SMPS2. Connect to the SMPS2 output to bypass efficient power
for VREG3 pin. VOUT2 is also for the SMPS2 output soft-discharge.

Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor
according to the typical application circuits.

Upper Gate Driver Output for SMPS2. UGATE2 swings between PHASE2 and
BOOT2.

Switch Node for SMPS2. PHASE2 is the internal lower supply rail for the
UGATE2 high side gate driver. PHASE2 is also the current sense input for the
SMPS 2.
Lower Gate Drive Output for SMPS2. LGATE2 swings between GND and
VREG 5.

Master Enable Input. The REF/VREG5/VREG3 are enabled if it is within logic
high level and disabled if it is less than the logic low level.

Operation Mode Selectable Input.
Connect to VREG5 or VREG3 : Ultrasonic Mode
Connect to REF : DEM Mode

Connect to GND : PWM Mode
Ground for SMPS Controller. The exposed pad must be soldered to a large PCB

and connected to GND for maximum power dissipation.

5V Linear Regulator Output. VREG5 is also the supply voltage for the lower gate
driver and analog supply voltage for the device.

sense. The GND − PHASE1

DS(ON)

sense. The GND − PHASE2

DS(ON)

T o be continued

DS8205L/M-05 June 2011www.richtek.com

4

RT8205L/M

Pin No. Pin Name Pin Function

NC
(RT8205L)

18

SECF B
(RT8205M)

19 LGATE1 Lower Gate Drive Output for SMPS1. L GATE1 swings b etween GND and VREG5.

20 PHAS E1

21 UGATE1 Upper Gate Driver Output for SMPS1. UGATE1 swings between PHASE1 and BOOT1.

22 BOOT1

23 PGOOD Po wer Good Output for Channel 1 and Channel 2. (Logical AND)

24 VOUT1

Function Block Diagram

No Int ernal Co nnection.

Charge Pump Co ntrol Pin . The SECFB is used to mon itor the opt ional external 14V
cha rge pump. Connect a resistive voltage d ivi der from the 14 V charge pump ou tput to
GND to detect the output. If SECFB drops below the threshold volt age, LGATE1 will
provide 33kHz switching frequency for the ch arge pump. This will refresh t he ext ernal
cha rge pump driven by LGATE1 without o ver disc harging the output voltage.

Switch Node for SMPS1. PHASE1 is the internal lower supply rail for the UGATE1 high
side gate driver. PHASE1 is also the current sense input for the SMPS1.

Boost Flying Ca pacito r Conne ction f or SMPS1. Conne ct t o an external capa ci tor
according to the typical application circuits.

Bypass Pin for SMPS1. Connect to the SMPS1 output to bypass efficient power for
VREG5 pin. VOUT1 is also f or the SMPS1 output s oft-discharge.

TONSEL SKIPSEL

BOOT1

UGATE1

PHASE1

LGATE1

FB1

ENTRIP1

EN

VOUT1

VREG5

VREG5

VREG5

SW5 Threshold

Power-On
Sequence

Clear Fault Latch

VREG5

SMPS1

PWM Buck

Controller

Thermal

Shutdown

SMPS2

PWM Buck

Controller

SW3 Threshold

REF

VREG5

VREG3

VREG5

BOOT2

UGATE2

PHASE2

LGATE2

VOUT2
FB2
ENTRIP2

PGOOD

GND

VREG3

VIN

REF

DS8205L/M-05 June 2011 www.richtek.com

5

RT8205L/M

Absolute Maximum Ratings (Note 1)

z VIN, EN to GND ----------------------------------------------------------------------------------------------- −0.3V to 30V

z PHASEx to GND

DC---------------------------------------------------------------------------------------------------------------- −0.3V to 30V

< 20ns ----------------------------------------------------------------------------------------------------------- −8V to 38V

z BOOTx to PHASEx ------------------------------------------------------------------------------------------ −0.3V to 6V

z ENTRIPx, SKIPSEL, TONSEL, PGOOD to GND ------------------------------------------------------ −0.3V to 6V

z VREG5, VREG3, FBx , VOUTx, SECFB, REF to GND ---------------------------------------------- −0.3V to 6V

z UGATEx to PHASEx

DC---------------------------------------------------------------------------------------------------------------- −0.3V to (VREG5 + 0.3V)

< 20ns ----------------------------------------------------------------------------------------------------------- −5V to 7.5V

z LGATEx to GND

DC---------------------------------------------------------------------------------------------------------------- −0.3V to (VREG5 + 0.3V)

< 20ns ----------------------------------------------------------------------------------------------------------- −2.5V to 7.5V

z Power Dissipation, P

WQFN-24L-4x4 ------------------------------------------------------------------------------------------------ 1.923W

z Package Thermal Resistance (Note 2)

WQFN-24L-4x4, θJA------------------------------------------------------------------------------------------ 52°C/W

WQFN-24L-4x4, θJC------------------------------------------------------------------------------------------ 7°C/W

z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------ 260°C

z Junction Temperature ---------------------------------------------------------------------------------------- 150°C

z Storage Temperature Range -------------------------------------------------------------------------------- −65°C to 150°C

z ESD Susceptibility (Note 3)

HBM (Human Body Mode) ---------------------------------------------------------------------------------- 2kV

MM (Machine Mode) ----------------------------------------------------------------------------------------- 200V

@ TA = 25°C

D

Recommended Operating Conditions (Note 4)

z Supply Input Voltage, V

z Junction Temperature Range ------------------------------------------------------------------------------- −40°C to 125°C

z Ambient Temperature Range ------------------------------------------------------------------------------- −40°C to 85°C

----------------------------------------------------------------------------------- 6V to 25V

IN

DS8205L/M-05 June 2011www.richtek.com

6

Electrical Characteristics

(VIN = 12V, VEN = 5V, V

Parameter Symbol Test Conditions Min Typ Max Unit

Input Supply

ENTRIP1

= V

ENTRIP2

= 2V, No Load, T

= 25°C, unless otherwise specified)

A

RT8205L/M

VIN Standby Current I

VIN Shutdown Supply
Current

Quiescent Power
Consumption

VIN_SBY

I

VIN_SHDN

P

VIN

+P

PVCC

SMPS Output and FB Voltage

FBx Volt age V

SECFB Voltage V

Output Voltage Adjust
Range

V

Dischar ge

OUTx

Curr ent

FB x

SECFB

V

OU Tx

V

On-Time

On-Time Pulse Width tON

VIN = 6V to 25V, ENTRIPx = GND -- 200 -- μA

V

= 6V to 25V,

IN

ENTRIPx = EN = GND

Both SMPS On, V
SKIPSEL = REF, V

= 3.3V (Note 5)

V

OUT2

= 2.1V,

FBx

OUT1

= 5V,

-- 20 40 μA

-- 5 7 mW

DEM Mode 1.975 2 2.025

PWM Mode (Note 6) -- 2 --

V

Ultrasonic Mode -- 2.032 --

1.92 2 2.08 V

SMPS1, SMPS2 2 -- 5.5 V

= 0.5V, V

OUTx

TONSEL = G ND

TONSEL = REF

TONSEL =
VREG 5

ENTRIPx

= 0V 10 45 -- mA

V

= 5.05V ( 200kHz) 189 5 210 5 2315

OUT1

= 3.33V (250kHz) 999 1110 1221

V

OUT2

V

= 5.05V ( 300kHz) 122 7 140 3 1579

OUT1

= 3.33V (375kHz) 647 740 833

V

OUT2

V

= 5.05V ( 400kHz) 895 105 2 1209

OUT1

= 3.33V (500kHz) 475 555 635

V

OUT2

ns

Minimum Off-Time t
Ultrasonic Mode

Frequency

FBx = 1.9V 200 300 400 ns

OFF

SKIPSEL = VREG5 or VREG3 22 33 -- kHz

Soft-Start

Soft-Start Time t

Internal Soft-Start -- 2 -- ms

SSx

Current Sen se

ENTRIPx Source
Curr ent

I

ENTRIPx

V

ENTRIPx

= 0.9V 9.4 10 10.6 μA

ENTRIPx Current
Temperature

TC

IENTRIPx

In Comparison w ith 25°C ( Note 6) -- 4700 -- ppm/°C

Coefficient
ENTRIPx Adjustment

Range
Curr ent Limit

Threshold
Zero-Current
Threshold

V

ENTRIPx

GND − PHASEx, V

= I

ENTRIPx

x R

ENTRIPx

ENTRIPx

0.515 -- 3 V

= 2V 180 200 220 mV

GND − PHASEx in DEM -- 3 -- mV

T o be continued

DS8205L/M-05 June 2011 www.richtek.com

7

RT8205L/M

Parameter Symbol Test Conditions Min Typ Max Unit

Internal Regulator and Reference

V

OUT1

V

VREG5 Output Voltage V

VREG3 Output Voltage V

VREG5 Output Current I

VREG3 Output Current I

VREG5 Switchover
Threshold to V

OUT1

VREG3 Switchover
Threshold to V

OUT2

VREGx Switchover Equivalent
Resistance

REF Output Voltage V

VREG5

VREG3

V

VREG5

V

VREG3

V

SW5

V

SW3

R

VREGx to V

SWx

No External Load 1.98 2 2.02 V

REF

OUT1

I

VREG5

V

OUT1

I

VREG5

V

OUT2

V

OUT2

I

VREG3

V

OUT2

I

VREG3

VREG5

VREG3

V

OUT1

V

OUT1

V

OUT2

V

OUT2

REF Load Regulation 0 < I

= GND, I

= GND, 6.5V < VIN < 25V,

< 100mA

= GND, 5.5V < VIN < 25V,

< 50mA

= GND, I

= GND, 6.5V < VIN < 25V,

< 100mA

= GND, 5.5V < VIN < 25V,

< 50mA

= 4.5V, V

= 3V, V

Rising Edge 4.6 4.75 4.9

Falling Edge 4.3 4.4 4.5

Rising Edge 2.975 3.125 3.25

Falling Edge 2.775 2.875 2.975

OUTx

< 100μA -- 10 -- mV

LOAD

< 100mA 4.8 5 5.2

VREG5

4.75 5 5.25

4.75 5 5.25

< 100mA 3.2 3.33 3.46

VREG3

3.13 3.33 3.5

3.13 3.33 3.5

= GND 100 175 250 mA

OUT1

= GND 100 175 250 mA

OUT2

, 10mA -- 1.5 3 Ω

V

V

V

V

REF Sink Current REF in Regulation 5 -- -- μA
UVLO

VREG5 Under Voltage
Lockout Threshold

VREG3 Under Voltage
Lockout Threshold

SMPSx off -- 2.5 -- V

Rising Edge -- 4.20 4.35

V

Falling Edge 3.7 3.9 4.1

Power Good

PGOOD Detect, FBx Falling Edge 82 85 88

PGOOD Threshold

Hysteresis, Rising Edge with SS
Delay Time

-- 6 --

%

PGOOD Propagation Delay Falling Edge, 50mV Overdrive -- 10 -- μs

PGOOD Leakage Current High State, Forced to 5.5V -- -- 1 μA

PGOOD Output Low Voltage I

= 4mA -- -- 0.3 V

SINK

Fault Detection

Over Voltage Protection Trip
Threshold

Over Voltage Protection
Propagation Delay

Under Voltage Protection Trip
Threshold

UVP Shutdown Blanking Time t

V

FB_OVP

FBx = 2.35V -- 5 -- μs

V

FB_UVP

SHDN_ UVP

OVP Detect, FBx Rising Edge 109 112 116 %

UVP Detect, FBx Falling Edge 49 52 56 %

From ENTRIPx Enable -- 5 -- ms

T o be continued

DS8205L/M-05 June 2011www.richtek.com

8

Parameter Symbol Test Conditions Min Typ Max Unit

Thermal Shutdown

RT8205L/M

Thermal Shutdown T

Thermal Shutdown

Hysteresis

SHDN

-- 10 -- °C

Logic Input

SKIPSEL Input Voltage

EN Threshold
Voltage

Logic-High VIH 1 -- --

Logic-Low V

ENTRI Px

IL

EN Voltage VEN

EN Current IEN

Input Leakage Current

Internal BOOT Switch

Internal Boost Switch
On-Resistance

Power MOSFET Drive rs

-- 150 -- °C

Low Level (PWM Mode) -- -- 0.8

REF Level (DEM Mode) 1.8 -- 2.3

V

High Level (Ultrasonic Mode) 2.7 -- --

Low Level (SMPS Off) -- -- 0.25

On Level (SMPS On) 0.515 -- 3 ENTRIPx Input Voltage V

V

High Level (SMPS Off) 4.5 -- --

V

-- -- 0.4

Floating, Default Enable 2.4 3.3 4.2

V

= 0.2V, Source 1.5 3 5

EN

V

= 5V, Sink -- 3 8

EN

V

OUT1

V

OUT1

V

OUT1

V

TONSEL

V

SECFB

/ V

/ V

/ V

= 0V or 5V −1 -- 1

= 200kHz / 250kHz -- -- 0.8

OUT2

= 300kHz / 375kHz 1.8 -- 2.3 TONSEL Setting Voltage

OUT2

= 400kHz / 500kHz 2.7 -- --

OUT2

, V

SKIPSEL

= 0V or 5V −1 -- 1

V

μA

V

μA

VREG5 to BOOTx, 10mA -- 40 80 Ω

UGATEx On-Resistance

UGATEx, High State,
BOOTx to PHASEx F orced to 5V
UGATEx, Low State,
BOOTx to PHASEx F orced to 5V

-- 4 8

Ω

-- 1.5 4

LGATEx, High State -- 4 8

LGATEx On-Resistance

Ω

LGATEx, Low State -- 1.5 4

LGATEx Rising -- 30 --

Dead Time

ns

UGATEx Rising -- 40 --

DS8205L/M-05 June 2011 www.richtek.com

9

RT8205L/M

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. P
Note 6. Guaranteed by Design.

is measured in natural convection at TA = 25°C on a high effective four layers thermal conductivity four-layer test

JA

board of JEDEC 51-7 thermal measurement standard. The measurement case position of θ

of the package.

+ P

VIN

VREG5

is on the exposed pad

JC

10

DS8205L/M-05 June 2011www.richtek.com

Typical Operating Characteristics

RT8205L/M

VOUT1 Efficiency vs. Load Current

100

DEM Mode

90

80

70

60

Ultrasonic Mode

50

40

Efficiency (%)

30

20

10

0

0.001 0.01 0.1 1 10

VIN = 8V, TONSEL = GND, V
ENTRIP2 = GND, EN = FLOATING

PWM Mode

ENTRIP1

Load Current (A)

VOUT1 Efficiency vs. Load Current

100

90

DEM Mode

80

70

60

50

40

Efficiency (%)

Ultrasonic Mode

30

20

10

0

0.001 0.01 0.1 1 10

Load Current (A)

PWM Mode

VIN = 20V, TONSEL = GND,
V
EN = FLOATING

= 1.5V, ENTRIP2 = GND,

ENTRIP1

= 1.5V,

VOUT1 Efficiency vs. Load Current

100

90

80

70

60

50

40

Efficiency (%)

30

20

10

DEM Mode

Ultrasonic Mode

0

0.001 0.01 0.1 1 10

PWM Mode

VIN = 12V, TONSEL = GND,
V
EN = FLOATING

= 1.5V, ENTRIP2 = GND,

ENTRIP1

Load Current (A)

VOUT2 Efficiency v s. Loa d Current

100

90

80

DEM Mode

70

60

50

40

Ultrasonic Mode

Efficiency (%)

30

20

10

0

0.0010.010.1110

PWM Mode

VIN = 8V, TONSEL = GND,
ENTRIP1 = GND, V
EN = FLOATING

Load Current (A)

ENTRIP2

= 1.5V,

VOUT2 Efficiency vs. Load Current

100

90

80

DEM Mode

70

60

50

40

Efficiency (%)

30

Ultrasonic Mode

20

10

0

0.001 0.01 0.1 1 10

Load Current (A)

PWM Mode

VIN = 12V, TONSEL = GND,
ENTRIP1 = GND, V
EN = FLOATING

ENTRIP2

100

Efficiency (%)

= 1.5V,

VOUT2 Efficiency vs. Load Current

90

80

DEM Mode

70

60

50

40

30

20

10

0

0.00 1 0.01 0.1 1 10

Ultrasonic
Mode

VIN = 20V, TONSEL = GND,
ENTRIP1 = GND, V
EN = FLOATING

Load Current (A)

PWM Mode

ENTRIP2

= 1.5V,

DS8205L/M-05 June 2011 www.richtek.com

11

RT8205L/M

VOUT1 Switching Frequency vs. Load Current

220

200

180

160

140

120

100

80

60

40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

Ultrasonic Mode

VIN = 8V,
TONSEL = GND,
EN = FLOATING,
V
ENTRIP2 = GNDDEM Mode

ENTRIP1

= 1.5V,

Load Current (A)

VOUT1 Switching Frequency vs. Load Current

220

200

180

160

140

120

100

80

60

40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

Ultrasonic Mode

DEM Mode

Load Current (A)

VIN = 20V,
TONSEL = GND,
EN = FLOATING,
V

= 1.5V,

ENTRIP1

ENTRIP2 = GND

VOUT1 Switching Frequency vs. Load Current

220

200

180

160

140

120

100

80

60

40

Switching Frequency (kHz) 1

20

PWM Mode

VIN = 12V,

Ultrasonic Mode

DEM Mode

0

0.001 0.01 0.1 1 10

TONSEL = GND,
EN = FLOATING,
V
ENTRIP2 = GND

ENTRIP1

= 1.5V,

Load Current (A)

VOUT2 Switching Frequency vs. Load Current

280
260
240
220
200
180
160
140
120
100

80
60
40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

Ultrasonic Mode

DEM Mode

Load Current (A)

VIN = 8V,
TONSEL = GND,
EN = FLOATING,
ENTRIP1 = GND,
V

ENTRIP2

= 1.5V

VOUT2 Switching Frequency vs. Load Current

280
260
240
220
200
180
160
140
120
100

Switching Frequency (kHz) 1

12

PWM Mode

80
60

Ultrasonic Mode

40
20

DEM Mode

0

0.001 0.01 0 .1 1 10

VIN = 12V,
TONSEL = GND,
EN = FLOATING,
ENTRIP1 = GND,
V

ENTRIP2

Load Current (A)

= 1.5V

VOUT2 Switching Frequency vs. Load Current

280
260
240
220
200
180
160
140
120
100

80
60
40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

Ultrasonic Mode

DEM Mode

Load Current (A)

DS8205L/M-05 June 2011www.richtek.com

VIN = 20V,
TONSEL = GND,
EN = FLOATING,
ENTRIP1 = GND,
V

ENTRIP2

= 1.5V

RT8205L/M

)

VOUT1 Output Voltage vs. Load Current

5.090

5.084

5.078

5.072

5.066

5.060

5.054

5.048

5.042

5.036

5.030

5.024

Output Voltage (V)

5.018

5.012

5.006

5.000

0.001 0.01 0.1 1 10

Ultrasonic Mode

PWM Mode

DEM Mode

Load Current (A)

VIN = 12V,
TONSEL = GND,
EN = FLOATING,
V

ENTRIP1

ENTRIP2 = GND

VREG5 Output Voltage vs. Output Current

5.006

5.002

4.998

4.994

4.990

= 1.5V,

VOUT2 Output Voltage vs. Load Current

3.446

3.440

3.434

3.428

3.422

3.416

3.410

3.404

3.398

Output Voltage (V)

3.392

3.386

3.380

0.001 0.01 0.1 1 10

Ultrasonic Mode

PWM Mode

DEM Mode

Load Current (A)

VIN = 12V,
TONSEL = GND,
EN = FLOATING,
ENTRIP2 = GND,
V

ENTRIP1

VREG3 Output Voltage vs. Output Current

3.358

3.354

3.350

3.346

= 1.5V

Output Voltage (V)

2.0080

2.0072

2.0064

2.0056

2.0048

2.0040

2.0032

2.0024

Reference Voltage (V)

2.0016

2.0008

2.0000

4.986

4.982

4.978

4.974

4.970
0 102030405060708090100

VIN = 12V, ENTRIP1 = ENTRIP2 = GND,
EN = FLOATING, TONSEL = GND

Output Current (mA)

Reference Voltage vs. Output Current

VIN = 12V, ENTRIP1 = ENTRIP2 = GND,
EN = FLOATING, TONSEL = GND

-10 0 10 20 30 40 50 60 70 80 90 100

Output Current (μA)

Output Voltage (V)

Battery Current (mA

3.342

3.338

3.334

3.330
0 10203040506070

VIN = 12V, ENTRIP1 = ENTRIP2 = GND,
EN = FLOATING, TONSEL = GND

Output Current (mA)

Battery Current vs . Input Voltage

100.0

PWM Mode

10.0

Ultrasonic Mode

1.0

DEM Mode

V
TONSEL = GND, EN = FLOATING

0.1
678910111213141516171819202122232425

Input Voltage (V)

ENTRIP1

= V

ENTRIP2

= 0.91V,

DS8205L/M-05 June 2011 www.richtek.com

13

RT8205L/M

Reference Voltage (V)

Standby Input Current vs. Input Voltage

250

249

248

247

246

245

244

243

242

Standby Input Current (μA) 1

241

240

7 8 9 101112131415161718192021222324

ENTRIP1 = ENTRIP2 = GND,
EN = FLOATING, No Load

Input Voltage (V)

Reference Voltage vs. Temperature

2.011

2.008

2.005

2.002

1.999

1.996

1.993

1.990

1.987

1.984

-50 -25 0 25 50 75 100 125

VIN = 12V, ENTRIP1 = ENTRIP2 = GND,
EN = FLOATING, TONSEL = GND

Tempe rature (°C)

Shutdown Input Current vs. Input Voltage

22

20

18

16

14

12

10

Shutdown Input Current (μA) 1

8

7 9 11 13 15 17 19 21 23 25

ENTRIP1 = ENTRIP2 = EN = GND, No Load

Input Voltage (V)

VREG5, VREG3 and REF Start Up

ENTRIP1 = ENTRIP2 = GND, EN = FLOATING

VREG5

(5V/Div)

VREG3

(2V/Div)

REF

(2V/Div)

EN

(5V/Div)

VIN = 12V, TONSEL = GND, No Load

Time (400μs/Div)

V

(1V/Div)

PGOOD

(5V/Div)

ENTRIP1

(1V/Div)

14

OUT1

VOUT1 Start Up

V

= 1.5V, ENTRIP2 = GND,

ENTRIP1

EN = FLOATING, VIN = 12V,
TONSEL = GND, SKIPSEL = GND,
No Load

Time (1ms/Div)

V

OUT2

(1V/Div)

PGOOD

(5V/Div)

ENTRIP2

(1V/Div)

VOUT2 Start Up

ENTRIP1 = GND, V
EN = FLOATING, VIN = 12V,
TONSEL = GND, SKIPSEL = GND,
No Load

Time (1ms/Div)

DS8205L/M-05 June 2011www.richtek.com

ENTRIP2

= 1.5V,

RT8205L/M

V

OUT1

(5V/Div)

CP

(10V/Div)

UGATE

(20V/Div)

LGATE

(10V/Div)

V

OUT1

(2V/Div)

V

OUT2

(1V/Div)

ENTRIP1

(2V/Div)

ENTRIP2

(2V/Div)

CP Start Up

V

= V

ENTRIP1

VIN = 12V, TONSEL = GND, SKIPSEL = REF,
No Load

= 1.5V, EN = FLOATING,

ENTRIP2

Time (2ms/Div)

VOUT2 Delay-Start

VIN = 12V, TONSEL = GND,
EN = FLOATING, SKIPSEL = GND,
No Load

V

OUT1

(2V/Div)

V

OUT2

(1V/Div)

ENTRIP1

(2V/Div)

ENTRIP2

(2V/Div)

V

OUT1

(2V/Div)

PGOOD

(5V/Div)

ENTRIP1

(2V/Div)

LGATE1
(5V/Div)

VOUT1 Delay-Start

VIN = 12V, TONSEL = GND,
EN = FLOATING, SKIPSEL = GND,
No Load

Time (2ms/Div)

Power Off from ENTRIP1

VIN = 12V, TONSEL = GND,
SKIPSEL = GND,
EN = FLOATING

No Load on VOUT1, VOUT2,
VREG5, VREG3 and REF

Time (2ms/Div)

Power Off from ENTRIP2

VOUT1 PWM-Mode Load Transient Response

V

OUT1_ac

Time (4ms/Div)

(50mV/Div)

V

OUT2

(2V/Div)
PGOOD
(5V/Div)

Inductor

Current

(5A/Div)

ENTRIP2

(2V/Div)

LGATE2

(5V/Div)

VIN = 12V, TONSEL = GND, SKIPSEL = GND,
EN = FLOATING, No Load on VOUT1, VOUT2,
VREG5, VREG3 and REF

Time (4ms/Div)

UGATE1

(20V/Div)

LGATE1
(5V/Div)

VIN = 12V, TONSEL = GND, SKIPSEL = GND

EN = FLOATING, I

OUT1

= 0A to 6A

Time (20μs/Div)

DS8205L/M-05 June 2011 www.richtek.com

15

RT8205L/M

VOUT2 PWM-Mode Load Transient Response

V

OUT2_ac

(50mV/Div)

Inductor

Current
(5A/Div)

UGATE

(20V/Div)

VIN = 12V, TONSEL = GND, SKIPSEL = GND

LGATE

(5V/Div)

EN = FLOATING, I

OUT2

= 0A to 6A

Time (20μs/Div)

UVP

VIN = 12V,
TONSEL = GND,
SKIPSEL = GND,
EN = FLOATING,

V

OUT1

(2V/Div)

PGOOD

(5V/Div)

UGATE

(20V/Div)

No Load

V

OUT1

(2V/Div)

V

OUT2

(2V/Div)

PGOOD

(5V/Div)

OVP

VIN = 12V, TONSEL = GND, SKIPSEL = REF,
EN = FLOATING, No Load

Time (4ms/Div)

LGATE
(5V/Div)

Time (100μs/Div)

16

DS8205L/M-05 June 2011www.richtek.com

Application Information

RT8205L/M

The RT8205L/M is a dual, Mach ResponseTM DRVTM dual

ramp valley mode synchronous buck controller. The

controller is designed for low-voltage power supplies for

notebook computers. Richtek's Mach Response

TM

technology is specifically designed for providing 100ns

“instant-on” response to load steps while maintaining a

relatively constant operating frequency and inductor

operating point over a wide range of input voltages. The

topology circumvents the poor load-transient timing

problems of fixed-frequency current-mode PWMs while

avoiding the problems caused by widely varying switching

frequencies in conventional constant-on-time and constant-

off-time PWM schemes. The DRVTM mode PWM

modulator is specifically designed to have better noise

immunity for such a dual output application. The RT8205L/

M includes 5V (VREG5) and 3.3V (VREG3) linear

regulators. VREG5 linear regulator can step down the

battery voltage to supply both internal circuitry and gate

drivers. The synchronous-switch gate drivers are directly

powered from VREG5. When VOUT1 voltage is above

4.66V, an automatic circuit will switch the power of the

device from VREG5 linear regulator to VOUT1.

PWM Operation

TM

The Mach ResponseTM DRV

mode controller relies on

the output filter capacitor's Effective Series Resistance

(ESR) to act as a current-sense resistor, so the output

ripple voltage provides the PWM ramp signal. Referring to

the RT8205L/M's function block diagram, the synchronous

high side MOSFET will be turned on at the beginning of

each cycle. After the internal one-shot timer expires, the

MOSFET will be turned off. The pulse width of this one

shot is determined by the converter's input voltage and

the output voltage to keep the frequency fairly constant

over the input voltage range. Another one-shot sets a

minimum off-time (300ns typ.). The on-time one-shot will

be triggered if the error comparator is high, the low side

switch current is below the current limit threshold, and

the minimum off-time one-shot has timed out.

PWM Frequency and On-Time Control

The Mach ResponseTM control architecture runs with

pseudo constant frequency by feed forwarding the input

and output voltage into the on-time one shot timer. The

high side switch on-time is inversely proportional to the

input voltage as measured by VIN, and proportional to the

output voltage. There are two benefits of a constant

switching frequency. First, the frequency can be selected

to avoid noise-sensitive regions such as the 455kHz IF

band. Second, the inductor ripple-current operating point

remains relatively constant, resulting in easy design

methodology and predictable output voltage ripple.

Frequency for the 3V SMPS is set at 1.25 times higher

than the frequency for 5V SMPS. This is done to prevent

audio frequency “beating” between the two sides, which

switches asynchronously for each side. The frequencies

are set by the TONSEL pin connection as shown in Table

1. The on-time is given by :

tK(V V)=×

ON OUT IN

/

where “K” is set by the TONSEL pin connection (Table

1).

The on-time guaranteed in the Electrical Characteristics

table is influenced by switching delays in the external

high side power MOSFET. Two external factors that

influence switching frequency accuracy are resistive drops

in the two conduction loops (including inductor and PC

board resistance) and the dead time effect. These effects

are the largest contributors to the change frequency with

changing load current. The dead time effect increases the

effective on-time by reducing the switching frequency. It

occurs only in PWM mode (SKIPSEL = GND) when the

inductor current reverses at light or negative load currents.

With reversed inductor current, the inductor's EMF causes

PHASEx to go high earlier than normal, thus extending

the on-time by a period equal to the low-to-high dead time.

For loads above the critical conduction point, the actual

switching frequency is :

f(V V )(t (V V V ))=+ ×+ −

OUT DROP1 ON IN DROP1 DROP2

where V

is the sum of the parasitic voltage drops in

DROP1

/

the inductor discharge path, which includes the

synchronous rectifier, inductor, and PC board resistances.

V

is the sum of the resistances in the charging path;

DROP2

and tON is the on-time.

DS8205L/M-05 June 2011 www.richtek.com

17

RT8205L/M

Table 1. TONSEL Connection and Switching Frequency

TONSEL

SMPS 1

K-Fact or (μs)

GND 5 200 4 250 ±10

REF 3.33 300 2.67 375 ±10

VREG5 or

VREG3

2.5 400 2 500 ±10

Operation Mode Selection (SKIPSEL)

The RT8205L/M supports three operation modes: Diode-

Emulation Mode, Ultrasonic Mode, and Forced-CCM

Mode. User can set operation mode via the SKIPSEL pin.

Diode-Emulation Mode (SKIPSEL = REF)

In Diode-Emulation Mode, the RT8205L/M automatically

reduces switching frequency at light load conditions to

maintain high efficiency. This reduction of frequency is

achieved smoothly. As the output current decreases from

heavy load condition, the inductor current is also reduced

and eventually comes to the point when its valley touches

zero current, which is the boundary between continuous

conduction and discontinuous conduction modes. By

emulating the behavior of diodes, the low side MOSFET

allows only partial negative current when the inductor free

wheeling current becomes negative. As the load current

is further decreased, it takes longer and longer to discharge

the output capacitor to the level that requires the next

“ON” cycle. The on-time is kept the same as that in the

heavy-load condition. In reverse, when the output current

increases from light load to heavy load, the switching

frequency increases to the preset value as the inductor

current reaches the continuous conduction. The transition

load point to the light load operation as follows (Figure 1) :

I

L

Slope = (VIN -V

OUT

) / L

SMPS 1

Frequency (kHz)

I

L, PEAK

I

= I

Load

L, PEAK

K-Factor (μs)

/ 2

SMPS 2

It

LOAD(SKIP) ON

SMPS 2

Approximate K-Factor

Frequency (kHz)

(V V )

−

IN OUT

≈×

2L

Err or (%)

where tON is the On-time.

The switching waveforms may appear noisy and

asynchronous when light loading causes Diode-Emulation

Mode operation. However, this is normal and results in

high efficiency. Trade offs in PFM noise vs. light load

efficiency is made by varying the inductor value. Generally,

low inductor values produce a broader efficiency vs. load

curve, while higher values result in higher full load efficiency

(assuming that the coil resistance remains fixed) and less

output voltage ripple. Penalties for using higher inductor

values include larger physical size and degraded load

transient response (especially at low input voltage levels).

Ultrasonic Mode (SKIPSEL = VREG5 or VREG3)

The RT8205L/M activates an unique Diode-Emulation Mode

with a minimum switching frequency of 25kHz, called the

Ultrasonic Mode. The Ultrasonic Mode avoids audio-

frequency modulation that would otherwise be present

when a lightly loaded controller automatically skips

pulses. In Ultrasonic Mode, the high side switch gate driver

signal is ORed with an internal oscillator (>25kHz). Once

the internal oscillator is triggered, the controller enters

constant off-time control. When output voltage reaches

the setting peak threshold, the controller turns on the low

side MOSFET until the controller detects that the inductor

current has dropped below the zero crossing threshold.

The internal circuitry provides a constant off-time control,

and it is effective to regulate the output voltage under light

load condition.

0

t

ON

Figure 1. Boundary Condition of CCM/DEM

18

Forced CCM Mode (SKIPSEL = GND)

t

The low noise, Forced CCM mode (SKIPSEL = GND)

disables the zero crossing comparator, which controls

the low side switch on-time. This causes the low side

DS8205L/M-05 June 2011www.richtek.com

RT8205L/M

μ

μ

gate driver waveform to become the complement of the

high side gate driver waveform. This in turn causes the

inductor current to reverse at light loads as the PWM loop

to maintain a duty ratio of V

OUT/VIN

. The benefit of forced

CCM mode is to keep the switching frequency fairly

constant, but it comes at a cost. The no-load battery

current can be from 10mA to 40mA, depending on the

external MOSFETs.

Reference and Linear Regulators (REF, VREGx)

The 2V reference (REF) is accurate within ±1% over the

entire operating temperature range, making REF useful

as a precision system reference. Bypass REF to GND

with a minimum 0.22μF ceramic capacitor. REF can supply

up to 100μA for external loads. Loading REF reduces the

VOUTx output voltage slightly because of the reference

load regulation error.

The RT8205L/M includes 5V (VREG5) and 3.3V (VREG3)

linear regulators. The VREG5 regulator supplies a total of

100mA for internal and external loads, including the

MOSFET gate driver and PWM controller. The VREG3

regulator supplies up to 100mA for external loads. Bypass

VREG5 and VREG3 with a minimum 4.7μF ceramic

capacitor.

When the 5V main output voltage is above the VREG5

switchover threshold (4.75V), an internal 1.5Ω P- MOSFET

switch connects VOUT1 to VREG5, while simultaneously

shutting down the VREG5 linear regulator. Similarly, when

the 3.3V main output voltage is above the VREG3

switchover threshold (3.125V), an internal 1.5Ω

P-MOSFET switch connects VOUT2 to VREG3, while

simultaneously shutting down the VREG3 linear regulator.

It can decrease the power dissipation from the same

battery, because the converted efficiency of SMPS is

better than the converted efficiency of the linear regulator.

Therefore, the exact current limit characteristic and

maximum load capability are functions of the sense

resistance, inductor value, and battery and output voltage.

I

L

I

L, peak

I

Load

I

LIM

0

t

Figure 2. “ Valley”Current Limit

The RT8205L/M uses the on resistance of the synchronous

rectifier as the current sense element and supports

temperature compensated MOSFET R

R

resistor between the ENTRIPx pin and GND sets

ILIMx

the current limit threshold. The resistor R

DS(ON)

ILIMx

sensing. The

is connected

to a current source from ENTRIPx, which is typically10μA

at room temperature. The current source has a 4700ppm/

°C temperature slope to compensate the temperature

dependency of the R

. When the voltage drop across

DS(ON)

the sense resistor or low side MOSFET equals 1/10 the

voltage across the R

resistor, positive current limit

ILIMx

will be activated. The high side MOSFET will not be turned

on until the voltage drop across the MOSFET falls below

1/10 the voltage across the R

ILIMx

resistor.

Choose a current limit resistor by following equation :

V(R10A)/10IR

=× =×

ILIMx ILIMx ILIMx DS(ON)

R(IR)1010A

=× ×

ILIMx ILIMx DS(ON)

/

Carefully observe the PC board layout guidelines to

ensures that noise and DC errors do not corrupt the current

sense signal at PHASEx and GND. Mount or place the IC

close to the low side MOSFET.

Current Limit Setting (ENTRIPx)

The RT8205L/M has a cycle-by-cycle current limit control.

The current limit circuit employs an unique “Valley” current

sensing algorithm. If the magnitude of the current sense

signal at PHASEx is above the current limit threshold,

the PWM is not allowed to initiate a new cycle (Figure 2).

The actual peak current is greater than the current limit

threshold by an amount equal to the inductor ripple current.

DS8205L/M-05 June 2011 www.richtek.com

Charge Pump (SECFB)

The external 14V charge pump is driven by LGATEx (Figure

3). When LGATEx is low, C1 will be charged by D1 from

V

. C1 voltage is equal to VOUT1 minus a diode drop.

OUT1

When LGATEx transitions to high, the charges from C1

will transfer to C2 through D2 and charge it to V

LGATEX

plus

VC1. As LGATEx transitions low on the next cycle, C2

will charge C3 to its voltage minus a diode drop through

19

RT8205L/M

D3. Finally, C3 charges C4 through D4 when LGATEx

switches to high. So, VCP voltage is :

VVOUT12V 4V=+× −×

CP LGATEX D

where V

is the peak voltage of LGATEx driver and is

LGATEX

equal to the VREG5; VD is the forward diode dropped

across the Schottky.

SECFB in the RT8205M is used to monitor the charge

pump through the resistive divider (Figure 3) to generate

approximately 14V DC voltage and the clock driver uses

VOUT1 as its power supply. In the event when SECFB

drops below its feedback threshold, an ultrasonic pulse

will occur to refresh the charge pump driven by LGATEx.

In the event of an overload on charge pump where SECFB

can not reach more than its feedback threshold, the

controller will enter the ultrasonic mode. Special care

should be taken to ensure enough normal ripple voltage

on each cycle as to prevent charge pump shutdown.

Reducing the charge pump decoupling capacitor and

placing a small ceramic capacitor (47 pF to 220pF) (CF of

Figure 3) in parallel with the upper leg of the SECFB

resistor feedback network (R

of Figure 3) will also

CP1

increase the robustness of the charge pump.

The low side driver is designed to drive high current, low

R

N-MOSFET(s). The internal pull down transistor

DS(ON)

that drives LGATEx low is robust, with a 1.5Ω typical on

resistance. A 5V bias voltage is delivered from the VREG5

supply. The instantaneous drive current is supplied by an

input capacitor connected between VREG5 and GND.

For high current applications, some combinations of high

and low side MOSFETs might be encountered that will

cause excessive gate drain coupling, which can lead to

efficiency killing, EMI producing shoot through currents.

This can be remedied by adding a resistor in series with

BOOTx, which increases the turn-on time of the high side

MOSFET without degrading the turn-off time (Figure 4).

V

IN

R

BOOTx

UGATEx

PHASEx

BOOT

Figure 4. Reducing the UGATEx Rise Time

SECFB

LGATE1

C1

D1

V

OUT1

D2

C2

D3

C3

D4

R

CP2

C

F

R

CP1

CP

C4

Figure 3. Charge Pump Circuit Connected to SECFB

MOSFET Gate Driver (UGATEx, LGA TEx)

The high side driver is designed to drive high current, low

R

N-MOSFET(s). When configured as a floating driver,

DS(ON)

a 5V bias voltage is delivered from the VREG5 supply.

The average drive current is calculated by the gate charge

at VGS = 5V times the switching frequency. The

instantaneous drive current is supplied by the flying

capacitor between the BOOTx and PHASEx pins. A dead

time to prevent shoot through is internally generated

between the high side MOSFET off to, the low side

MOSFET on, and the low side MOSFET off to the high

side MOSFET on.

Soft-Start

The RT8205L/M provides internal soft-start function to

prevent large inrush current and output voltage overshoot

when the converter starts up. The soft-start (SS)

automatically begins once the chip is enabled. During soft-

start, the voltage is clamped to the ramping of internal

reference voltage which is compared with FBx signal. The

typical soft-start duration is 2ms. An unique PWM duty

limit control that prevents output over voltage during soft-

start period is designed specifically for FBx floating.

UVLO Protection

The RT8205L/M features VREG5 under voltage lockout

protection (UVLO). When the VREG5 voltage is lower than

3.9V (typ.) and the VREG3 voltage is lower than 2.5V

(typ.), both switch power supplies are shut off. This is

non-latch protection.

Power Good Output (PGOOD)

PGOOD is an open-drain type output and requires a pull-

up resistor. PGOOD is actively held low in soft-start,

20

DS8205L/M-05 June 2011www.richtek.com

RT8205L/M

standby, and shutdown. It is released when both output

voltages are above 91% of the nominal regulation point.

The PGOOD goes low if either output turns off or is 15%

below its nominal regulator point.

Output Over V oltage Protection (OVP)

The output voltage can be continuously monitored for over

voltage. If the output voltage exceeds 12% of its set voltage

threshold, the over voltage protection is triggered and the

LGATEx low side gate drivers are forced high. This

activates the low side MOSFET switch, which rapidly

discharges the output capacitor and pulls the input voltage

downward.

The RT8205L/M is latched once OVP is triggered and can

only be released by toggling EN, ENTRIPx or cycling VIN.

There is a 5μs delay built into the over voltage protection

circuit to prevent false alarm.

Note that the latching LGATEx high causes the output

voltage to dip slightly negative when energy has been

previously stored in the LC tank circuit. For loads that

cannot tolerate a negative voltage, place a power Schottky

diode across the output to act as a reverse polarity clamp.

If the over voltage condition is caused by a short in the

high side switch, completely turning on the low side

MOSFET can create an electrical short between the

battery and GND, which will blow the fuse and disconnect

the battery from the output.

Output Under V oltage Prote ction (UVP)

The output voltage can be continuously monitored for under

voltage protection. If the output is less than 52% of its set

voltage threshold, under voltage protection will be triggered,

and then both UGATEx and LGATEx gate drivers will be

forced low. The UVP will be ignored for at least 5ms (typ.)

after start up or a rising edge on ENTRIPx. Toggle ENTRIPx

or cycle VIN to reset the UVP fault latch and restart the

controller.

Thermal Protection

The RT8205L/M features thermal shutdown protection to

prevent overheat damage to the device. Thermal shutdown

occurs when the die temperature exceeds 150°C. All

internal circuitry is inactive during thermal shutdown. The

RT8205L/M triggers thermal shutdown if VREGx is not

supplied from VOUTx, while the input voltage on VIN and

the drawing current from VREGx are too high. Even if

VREGx is supplied from VOUTx, large power dissipation

on automatic switches caused by overloading VREGx,

which may also result in thermal shutdown.

Discharge Mode (Soft-Discharge)

When ENTRIPx is low and a transition to standby or

shutdown mode occurs, or the output under voltage fault

latch is set, the output discharge mode will be triggered.

During discharge mode, the output capacitors' residual

charge will be discharge to GND through an internal switch.

Shutdown Mode

The RT8205L/M SMPS1, SMPS2, VREG3 and VREG5

have independent enabling control. Drive EN, ENTRIP1

and ENTRIP2 below the precise input falling edge trip level

to place the RT8205L/M in its low power shutdown state.

The RT8205L/M consumes only 20μA of input current while

in shutdown. When shutdown mode is activated, the

reference turns off. The accurate 0.4V falling edge threshold

on the EN pin can be used to detect a specific analog

voltage level as well as to shutdown the device. Once in

shutdown, the 1V rising edge threshold activates, providing

sufficient hysteresis for most applications.

Power Up Sequencing and On/Off Controls
(ENTRIPx)

ENTRIP1 and ENTRIP2 control the SMPS power up

sequencing. When the RT8205L/M is in single channel

mode, ENTRIP1 or ENTRIP2 enables the respective

outputs when ENTRIPx voltage rises above 0.515V.

Since current source form ENTRIPx has 4700ppm/°C

temperature slope, please make sure that ENTRIPx voltage

is high enough to enable the respective output in low

temperature application.

If ENTRIPx pin becomes higher than the enable threshold

voltage while another channel is starting up, soft-start is

postponed until the other channel's soft-start has

completed. If both ENTRIP1 and ENTRIP2 become higher

than the enable threshold voltage simultaneously (within

60μs), both channels will be start up simultaneously. The

timing diagrams of the power sequence is shown below

(Figure 5).

DS8205L/M-05 June 2011 www.richtek.com

21

RT8205L/M

V

ENTRIPx

V

ENTRIPy

V

V

OUTx

OUTy

< 60µs

0.515V

0.515V

V

ENTRIPx

V

ENTRIPy

> 60µs

0.515V

0.515V

V

OUTx

V

OUTy 2ms

≈

(a). Start-Up at the Same Time (b). Delay Start Mode

Figure 5. Time Diagrams of Power Sequence

Table 2. Operation Mode Truth Table

Mode Condition Comment

POR and after

IN

Power UP VREGX < UVLO threshold

Transitions to discharge mode after a V
REF becomes valid. VREG5, VREG3, and REF remain
active.

RUN

Over Voltage

Protection

Under

Vol ta ge

Protection

Disc harge

Standby

EN = high, VOUT1 or VOUT2
enabled

Either output > 111% of the nominal
level.

Either output < 5 2% of th e no m inal
level after 3ms time out expires and
output is enabled

Either SMPS output is still high in
either standby mode or shutdown
mode

ENTRIPx < startup threshold,
EN = high.

Normal Operation.

LGATEx is forced high. VREG3, VREG5 and REF active.
Exited by VIN POR or by toggling EN, ENTRIPx

Both UGATEx and LGATEx are forced low and enter
discharge mode. VREG3, VREG5 and REF are active.
Exited by VIN POR or by toggling EN, ENTRIPx

During discharge mode, there is one path to discharge the
outputs capacitor residual charge. That is output capacitor
discharge to GND through an internal switch.

VREG3, VREG5 and REF are active.

Shutdown EN = low All circuitry off.

Thermal

Shutdown

22

T

> 150°C All circuitry off. Exit by VIN POR or by toggling EN, ENTRIPx

J

DS8205L/M-05 June 2011www.richtek.com

RT8205L/M

Table 3. Power Up Sequencing

EN

(V)

Low X X Off Off Off Off Off

ENTRIP1 ENTRIP2 REF VREG5 VREG3 SMPS1 SMPS2

“>1V”

=> High

“>1V”

=> High

“>1V”

=> High

X X On On On Off Off

Off Off On On On Off Off

Off On On On On Off On

On

“>1V”

=> High

(after

ENTRIP2 is

On without

On On On On

60μs)

“>1V”

=> High

On Off On On On On Off

On

“>1V”

=> High

On

(after ENTRIP1

is On without

On On On On

60μs)

“>1V”

=> High

On On On On On On On

Output V oltage Setting (FBx)

Connect a resistor voltage divider at the FBx pin between

VOUTx and GND to adjust the respective output voltage

between 2V and 5.5V (Figure 6). Refering to Figure 5 as

an example, choose R2 to be approximately 10kΩ, and

solve for R1 using the equation :

R1

⎛⎞

VV1

=×+

OUTx FBX

⎛⎞

⎜⎟

⎜⎟

R2

⎝⎠

⎝⎠

On

(after SMPS2

On

is on)

On

(after SMPS1

is on)

Output Inductor Selection

The switching frequency (on-time) and operating point (%

ripple or LIR) determine the inductor value as shown in

the following equation :

t(VV )

×−

ON IN OUTx

L

=

LIR I

×

LOAD(MAX)

where LIR is the ratio of the peak to peak ripple current to

the average inductor current.

where V

is 2V.

FBX

UGATEx

PHASEx

LGATEx

VOUTx

FBx

Find a low loss inductor having the lowest possible DC

V

IN

V

OUTx

resistance that fits in the allotted dimensions. Ferrite cores

are often the best choice, although powdered iron is

inexpensive and can work well at 200kHz. The core must

be large enough not to saturate at the peak inductor current

(I

) :

R1

R2

PEAK

⎡⎤

=+×

II (LIR2I

PEAK LOAD(MAX) LOAD(MAX)

/)

⎣⎦

The calculation above shall serve as a general reference.

To further improve the transient response, the output

inductance can be reduced even further. This needs to be

Figure 6. Setting V

DS8205L/M-05 June 2011 www.richtek.com

with resistor divider

OUTx

considered along with the selection of the output capacitor.

23

RT8205L/M

Output Capa citor Sele ction

The capacitor value and ESR determine the amount of

output voltage ripple and load transient response. Thus,

the capacitor value must be greater than the largest value

calculated from below equations :

(I ) L (K t )

Δ×× +

V

=

SAG

2C V K t

×× × −

OUT OUTx OFF(MIN)

(I ) L

Δ×

V

SOAR

=× × +

V LIR I ESR

P P LOAD(MAX)

−

where V

LOAD

=

2C V

××

OUT OUTx

and V

SAG

2

LOAD OFF(MIN)

2

are the allowable amount of

SOAR

V

OUTx

V

IN

⎡⎤

⎛⎞

VV

−

IN OUTx

⎢⎥

⎜⎟

V

⎝⎠

⎣⎦

⎛⎞
⎜⎟
⎝⎠

IN

1

××

8C f

OUT

undershoot voltage and overshoot voltage in the load

transient, V

is the output ripple voltage, t

p-p

OFF(MIN)

is the

minimum off-time, and K is a factor listed in from Table 1.

Thermal Considerations

The maximum power dissipation depends on the operating

ambient temperature for fixed T

J (MAX)

and thermal

resistance, θJA. For the RT8205L/M package, the derating

curve in Figure 7 allows the designer to see the effect of

rising ambient temperature on the maximum power

dissipation.

2.0

1.6

1.2

0.8

0.4

Maximum Power Dissipation (W) 1

0.0
0 25 50 75 100 125

Ambient Temperature (°C)

Four-Layer PCB

Figure 7. Derating Curve for the RT8205L/M Package

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

P

where T

the ambient temperature, and θ

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

JA

is the maximum junction temperature, TA is

is the junction to ambient

JA

thermal resistance.

For recommended operating condition specifications of

the RT8205L/M, the maximum junction temperature is

125°C and TA is the ambient temperature. The junction to

ambient thermal resistance, θJA, is layout dependent. For

WQFN-24L 4x4 packages, the thermal resistance, θJA, is

52°C/W on a standard JEDEC 51-7 four-layer thermal test

board. The maximum power dissipation at TA = 25°C can

be calculated by the following formula :

D(MAX)

= (125°C − 25°C) / (52°C/W) = 1.923W for

P

WQFN-24L 4x4 package

Layout Considerations

Layout is very important in high frequency switching

converter designs, the PCB could radiate excessive noise

and contribute to the converter instability with improper

layout. Certain points must be considered before starting

a layout using the RT8205L/M.

` Place the filter capacitor close to the IC, within 12 mm

(0.5 inch) if possible.

` Keep current limit setting network as close as possible

to the IC. Routing of the network should avoid coupling

to high voltage switching node.

` Connections from the drivers to the respective gate of

the high side or the low side MOSFET should be as

short as possible to reduce stray inductance. Use 0.65

mm (25 mils) or wider trace.

` All sensitive analog traces and components such as

V

, FBX, GND, ENTRIPx, PGOOD, and TONSEL

OUTx

should be placed away from high voltage switching

nodes such as PHASEx, LGATEx, UGATEx, or BOOTx

nodes to avoid coupling. Use internal layer(s) as ground

plane(s) and shield the feedback trace from power traces

and components.

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DS8205L/M-05 June 2011www.richtek.com

RT8205L/M

` Place the ground terminal of VIN capacitor(s), V

capacitor(s), and source of low side MOSFETs as close

as possible. The PCB trace defined as PHASEx node,

which connects to source of high side MOSFET, drain

of low side MOSFET and high voltage side of the

inductor, should be as short and wide as possible.

OUTx

DS8205L/M-05 June 2011 www.richtek.com

25

RT8205L/M

Outline Dimension

D

E

A

A3

A1

D2

SEE DETAIL A

1

be

E2

L

1
2

1

2

DET AIL A

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 3.950 4.050 0.156 0.159

D2 2.300 2.750 0.091 0.108

E 3.950 4.050 0.156 0.159

E2 2.300 2.750 0.091 0.108

e 0.500 0.020

L 0.350 0.450

Richtek Technology Corporation

Headquarter

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: [phone] Fax: [phone]

0.014 0.018

W-Type 24L QFN 4x4 Package

Richtek Technology Corporation

Taipei Office (Marketing)

5F, No. 95, Minchiuan Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: [phone] Fax: [phone]

Email: [e-mail]

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit

design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be

guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

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26