Single Synchronous Buck Controller
RT8202L/M
General Description
The RT8202L/M PWM controller provides the high
efficiency, excellent transient response, and high DC output
accuracy needed for stepping down high voltage batteries
to generate low voltage CPU core, I/O, and chipset RAM
supplies in notebook computers.
The constant-on-time PWM control scheme handles wide
input/output voltage ratios with ease and provides 100ns
“instant-on” response to load transients while maintaining
a relatively constant switching frequency.
The RT8202L/M achieves high efficiency at a reduced cost
by eliminating the current-sense resistor found in
traditional current mode PWMs. Efficiency is further
enhanced by its ability to drive very large synchronous
rectifier MOSFETs. The RT8202L is available in a
WQFN-16L 4x4 package and the RT8202M is available in
a WQFN-16L 3x3 package.
Ordering Information
RT8202L/M
Package Type
QW : WQFN-16L 4x4 (W-Type)
QW : WQFN-16L 3x3 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
L : WQFN-16L 4x4
M : WQFN-16L 3x3
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Features
zz
Ultra-High Efficiency
z
zz
zz
z Resistor Programmable Current Limit by Low Side
zz
R
zz
z 4700ppm/
zz
zz
z Quick Load Step Response within 100ns
zz
zz
z 1% V
zz
zz
z Adjustable 0.75V to 3.3V Output Voltage Range
zz
zz
z 3V to 26V Battery Input Voltage Range
zz
zz
z Resistor Programmable Frequency
zz
zz
z Integrated Bootstrap Switch
zz
zz
z Over Voltage Protection
zz
zz
z Under Voltage Protection
zz
zz
z Voltage Ramp Soft-Start
zz
zz
z Built In Soft Discharge Output
zz
zz
z Power Good Indicator
zz
zz
z RoHS Compliant and 100% Halogen Free
zz
Sense (Lossless Limit)
DS(ON)
°°
°C R
°°
Accuracy over Line and Load
FB
Current Sensing
DS(ON)
Applications
z Notebook Computers
z CPU Core Supply
z Chipset/RAM Supply as Low as 0.75V
Pin Configurations
(TOP VIEW)
EN/DEM
GND
NC
1316 1415
17
PGND
BOOT
12
11
10
9
LGATE
UGATE
PHASE
OC
VDDP
VOUT
VDD
FB
PGOOD
TON
1
2
GND
3
4
5678
NC
WQFN-16L 4x4 (RT8202L)/
WQFN-16L 3x3 (RT8202M)
DS8202L/M-04 April 2011 www.richtek.com
1
RT8202L/M
Marking Information
RT8202LGQW RT8202MGQW
EK= : Product Code
EK=YM
DNN
YMDNN : Date Code
JJ=YM
DNN
JJ= : Product Code
YMDNN : Date Code
RT8202LZQW
EK : Product Code
EK YM
YMDNN : Date Code
DNN
Typical Application Circuit
1
6
T
V
P
D
D
V
5
D
O
G
O
P
C
C
D
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/
M
1
C
1
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6
,
1
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7
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9
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2
R
2
V
2
C
4
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1
5
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e
d
P
a
d
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G
7
PGND
RT8202MZQW
JJ : Product Code
JJ YM
YMDNN : Date Code
DNN
V
N
I
3
V
6
2
o
t
V
R
T
O
N
C
R
2
T
8
L
M
0
2
/
B
O
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D
P
D
D
D
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O
G
N
D
E
/
M
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O
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G
A
T
P
H
A
S
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A
T
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F
V
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U
R
3
1
3
T
C
R
4
1
2
E
1
1
E
8
E
R
L
I
I
M
1
0
C
3
B
1
T
3
4
V
O
T
U
Q
1
Q
2
L
1
R
5
*
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C
5
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6
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7
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6
C
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8
7
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a
l
DS8202L/M-04 April 2011www.richtek.com
2
Function Block Diagram
TRIG
+
+
GM
-
-
SS Ramp
On-time
Compute
1-SHOT
+
-
+
-
VOUT
TON
FB
VDD
GND
SS (Internal)
115% V
70% V
REF
REF
OV
UV
90% V
+
Latch
S1 Q
Latch
S1 Q
REF
Thermal
Shutdown
Comp
+
R
QS
Min. T
OFF
QTRIG
1-SHOT
Emulation
PWM
Diode
RT8202L/M
DRV
DRV
20µA
+
-
BOOT
UGATE
PHASE
VDDP
LGATE
PGND
OC
EN/DEM
PGOOD
DS8202L/M-04 April 2011 www.richtek.com
3
RT8202L/M
Functional Pin Description
Pin No. Pin Name Pin Function
1 VOUT
2 VDD
3 FB
4 PGOOD
5, 14 NC No Internal Connection.
6,
17 (Exposed Pad)
7 PGND Power Ground.
8 LGATE
9 VDDP
10 OC
11 PHASE
12 UGATE
13 BOOT
15 EN/DEM
16 TON
GND
Output Voltage Sense Pin. Connect this pin to the output of PWM converter.
VOUT is also for the output soft discharge when shutdown.
Analog Supply Voltage Input for Internal Analog Integrated Circuit. Bypass this
pin to GND with a 1μF ceramic capacitor.
Feedback Input of PWM Controller. Connect FB to a resistor voltage divider from
VOUT to GND to adjust the output voltage from 0.75V to 3.3V.
Power Good Signal Open-Drain Output of PWM Controller. This pin will be
pulled high when the output voltage is within the target range.
Analog Ground. The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
Low Side N-MOSFET Gate-Drive Output for PWM. This pin swings between
PGND to VDDP.
Gate Driver Supply for External MOSFETs. Bypass this pin to PGND with a 1μF
ceramic capacitor.
PWM Current Limit Setting and Sense. Connect a resistor between OC to
PHASE for current limit setting.
Inductor Connection. This pin is not only the zero-current-sense input for the
PWM converter, but also the UGATE high side gate driver return.
High Side N-MOSFET Floating Gate-Driver Output for PWM controller. This pin
swings between PHASE and BOOT.
Boost Capacitor connection for PWM Controller. Connect an external ceramic
capacitor from this pin to PHASE.
PWM Enable and Operation Mode Selection Input. Connect this pin to VDD for
diode-emulation mode, connect this pin to GND for shutdown mode and floating
the pin for CCM mode.
On Time/Frequency Adjustment Pin. Connect this pin to V
TON is an input of the PWM controller.
through a resistor.
IN
DS8202L/M-04 April 2011www.richtek.com
4
RT8202L/M
Absolute Maximum Ratings (Note 1)
z Input Voltage, TON to GND ------------------------------------------------------------------------------------------------ –0.3V to 32V
z BOOT to PHASE ------------------------------------------------------------------------------------------------------------ –0.3V to 6V
z UGATE to PHASE
DC------------------------------------------------------------------------------------------------------------------------------- –0.3V to 6V
< 20ns ------------------------------------------------------------------------------------------------------------------------- −5V to 7.5V
z LGATEx to GND
DC------------------------------------------------------------------------------------------------------------------------------- –0.3V to 6V
< 20ns ------------------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V
z PHASE to GND
DC------------------------------------------------------------------------------------------------------------------------------- –0.3V to 32V
< 20ns ------------------------------------------------------------------------------------------------------------------------- −8V to 38V
z PGND to GND ---------------------------------------------------------------------------------------------------------------- –0.3V to 0.3V
z VDD, VDDP, VOUT, EN/DEM, FB, PGOOD to GND ---------------------------------------------------------------- –0.3V to 6V
z OC to GND -------------------------------------------------------------------------------------------------------------------- –0.3V to 28V
z Power Dissipation, P
WQFN-16L 3x3 -------------------------------------------------------------------------------------------------------------- 1.471W
WQFN-16L 4x4 -------------------------------------------------------------------------------------------------------------- 1.852W
z Package Thermal Resistance (Note 2)
WQFN-16L 3x3, θJA--------------------------------------------------------------------------------------------------------- 68°C/W
WQFN-16L 3x3, θJC-------------------------------------------------------------------------------------------------------- 7.5°C/W
WQFN-16L 4x4, θJA--------------------------------------------------------------------------------------------------------- 54°C/W
WQFN-16L 4x4, θJC-------------------------------------------------------------------------------------------------------- 7°C/W
z Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------------- 260°C
z Junction Temperature ------------------------------------------------------------------------------------------------------- 150°C
z Storage Temperature Range ---------------------------------------------------------------------------------------------- –65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------------ 2kV
MM (Machine Mode) -------------------------------------------------------------------------------------------------------- 200V
@ TA = 25°C
D
Recommended Operating Conditions (Note 4)
z Input Voltage, V
z Supply Voltage, V
z Junction Temperature Range--------------------------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range --------------------------------------------------------------------------------------------- −40°C to 85°C
DS8202L/M-04 April 2011 www.richtek.com
------------------------------------------------------------------------------------------------------------ 3V to 26V
IN
, V
DD
------------------------------------------------------------------------------------------------ 4.5V to 5.5V
DDP
5
RT8202L/M
Electrical Characteristics
(VDD = V
Quiescent Current IQ
TON Operating Current -- 15 --
Shutdown Current I
FB Referenc e Volta ge VFB V
FB Input Bias Current VFB = 0.75V −1 0.1 1 μA
Output Voltage Range V
On-Time tON V
Minimum Off-Time t
VOUT Shutdown Discharge
Resistance
Current Sensing
Current Limit Source
Current
Current Limiter Temperature
Coefficient
Current Comparator Offset
Voltage
Zero Crossing Threshold
Voltage
Fault Prote cti on
= 5V, VIN = 15V, V
DDP
EN/DEM
= VDD, R
= 1MΩ, T
TON
= 25°C, unless otherwise specified)
A
Parameter Symbol Test Conditions Min Typ Max Unit
SHDN
+ I
I
VDD
above the regulation point
I
+ I
VDD
I
-- 1 5
TON
, VFB = 0.8V, forced
VDDP
-- 1 10
VDDP
-- -- 1250 μA
EN/DEM = 0V −10 −1 -- μA
= 4.5V to 5.5V 0.742 0.75 0.758 V
DD
0.75 -- 3.3 V
OUT
= 15V, V
IN
250 400 550 ns
OFF
EN/DEM = GND, V
= 1.25V 267 334 401 ns
OUT
= 0.5V -- 20 -- Ω
OUT
LGATE = High 18 20 22 μA
On the basis of 25°C -- 4700 -- ppm/°C
TC
ICS
GND to OC −10 -- 10 mV
PHASE to GND, EN/DEM = 5V −10 -- 5 mV
μA
Current Limit Sense Voltage GND − PHASE, R
Output Under Voltage
Threshold
Over Voltage Protection
Threshold
Over Voltage Fault Delay
Under Voltage Lockout
Threshold
Under Voltage Lockout
Hysteresis
Soft-Start Ramp Time tSS
UVP detect, FB falling edge 60 70 80 %
V
UVP
V
OVP detect, FB rising edge 110 115 120 %
OVP
FB forced above
threshol d
V
UVLO
ΔV
UVLO
Falling edge, PWM disabled below
this level
-- 150 -- mV
From E N hi gh to in ternal VREF
reaches 0.71V (0Æ95%)
= 10kΩ 170 200 230 mV
ILIM
over voltage
-- 20 -- μs
3.7 3 .9 4.1 V
1.5 -- ms
Under Voltage Blank Time From EN signal going high -- 4.5 -- ms
Thermal Shutdown TSD -- 155 °C
Thermal Shutdown
Hysteresis
ΔT
-- 10 -- °C
SD
Driver On-Resistance
UGATE Driver Source R
UGATE Driver Sink R
UGATEs r
UGATEs k
UGATE, High State, BOOT to PHASE
forced to 5V
UGATE, Low State, BOOT to PHASE
forced to 5V
-- 2 -- Ω
-- 1.5 -- Ω
To be continued
DS8202L/M-04 April 2011www.richtek.com
6
RT8202L/M
Parameter Symbol Test Conditions Min Typ Max Unit
LGATE Driver Source R
LGATE Driver Si nk R
Internal BOOT Charging
Switch On-Resistance
LGATE sr
LGATE sk
VDDP to BOOT, 10mA -- -- 90 Ω
Dead Time
Logic I/O
Logic Input Current
PGOOD (upper side threshold decide by OV threshold)
Trip Threshold (falling)
Fault Propagation Delay
Output Low Voltage I
Leakage Current High state, forced to 5V -- -- 1 μA
LGATE, High State -- 1.5 -- Ω
LGATE, Low State -- 0.7 -- Ω
LGATE Rising (V
= 1.5V) -- 30 --
PH AS E
ns
UGATE Rising -- 30 --
EN/D EM Low -- -- 0.8
EN/D EM High 2.9 -- -- Logic Input Voltage
V
EN/DEM Float -- 2 --
EN/D EM = VDD -- 1 10
μA
EN/D EM = 0 −10 1 --
Measured at FB, with respect to
reference, Hysteresis = 3%
Falling edge, FB forced below PGOOD
trip threshold
= 1mA -- -- 0.4 V
SINK
87 90 93 %
-- 2.5 -- μs
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θ
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
is measured in natural convection at T
JA
JEDEC 51-7 thermal measurement standard. The case measurement position of θ
package.
= 25°C on a high effective thermal conductivity four-layer test board of
A
is on the exposed pad of the
JC
DS8202L/M-04 April 2011 www.richtek.com
7
RT8202L/M
Typical Operating Characteristics
Efficiency vs. Output Current
100
90
80
70
60
50
40
Efficiency (%)
30
20
10
0
0.001 0.01 0.1 1 10 100
DEM
PWM
VIN = 8V, V
OUT
Output Current (A)
Efficiency vs. Output Current
100
90
80
70
60
50
40
Efficiency (%)
30
20
10
0
0.001 0.01 0.1 1 10 100
DEM
PWM
VIN = 12V, V
Output Current (A)
OUT
= 1.05V
= 1.05V
Switching Frequency vs. Output Current
350
325
300
275
250
225
200
175
150
125
100
75
Switching Frequency (kHz) 1
50
25
0
0.001 0.01 0.1 1 10 100
PWM
DEM
VIN = 8V, V
OUT
Output Current (A)
Switching Frequency vs. Output Current
350
325
300
275
250
225
200
175
150
125
100
75
Switching Frequency (kHz) 1
50
25
0
0.001 0.01 0.1 1 10 100
PWM
VIN = 12V, V
Output Current (A)
DEM
OUT
= 1.05V
= 1.05V
Efficiency vs. Output Current
100
90
80
70
60
50
40
Efficiency (%)
30
20
10
0
0.001 0.01 0.1 1 10 100
DEM
PWM
VIN = 20V, V
Output Current (A)
OUT
= 1.05V
Switching Frequency vs. Output Current
350
325
300
275
250
225
200
175
150
125
100
75
Switching Frequency (kHz) 1
50
25
0
0.001 0.01 0.1 1 10 100
PWM
VIN = 20V, V
Output Current (A)
DEM
OUT
= 1.05V
DS8202L/M-04 April 2011www.richtek.com
8
RT8202L/M
520
500
480
460
440
Standby Current (μA) 1
420
400
V
OUT
(1V/Div)
Standby Current vs. Input voltage
V
= 5V, No Load
EN/DEM
7 9 11 13 15 17 19 21 23 25
Input Voltage (V)
Power On from EN_PWM Mode
10
Shutdown Current (μA) 1
V
OUT
(1V/Div)
Shutdown Current vs. Input voltage
9
8
7
6
5
4
3
2
1
0
7 9 11 13 15 17 19 21 23 25
EN/DEM = GND, No Load
Input Voltage (V)
Power On from EN_DEM Mode
V
PHASE
(10V/Div)
V
EN/DEM
(2V/Div)
V
PGOOD
(5V/Div)
V
OUT
(1V/Div)
V
EN/DEM
(2V/Div)
V
UGATE
(20V/Div)
V
LGATE
(5V/Div)
VIN = 12V, EN/DEM = Floating, No Load
Time (1ms/Div)
Power Off from EN
VIN = 12V, EN/DEM = Floating, No Load
V
PHASE
(10V/Div)
V
EN/DEM
(5V/Div)
V
PGOOD
(5V/Div)
V
OUT
(50mV/Div)
I
L
(20A/Div)
V
UGATE
(20V/Div)
V
LGATE
(5V/Div)
VIN = 12V, V
= 5V, No Load
EN/DEM
Time (1ms/Div)
Load Transient Response
VIN = 12V, EN/DEM = Floating, I
OUT
= 0A to20A
Time (10ms/Div)
Time (40μs/Div)
DS8202L/M-04 April 2011 www.richtek.com
9
RT8202L/M
V
OUT
(1V/Div)
V
PGOOD
(5V/Div)
V
LGATE
(5V/Div)
Over Voltage Protection
VIN = 12V, V
Time (40μs/Div)
EN/DEM
= 5V, No Load
V
OUT
(1V/Div)
V
PGOOD
(5V/Div)
V
UGATE
(20V/Div)
V
LGATE
(5V/Div)
Under Voltage Protection
VIN = 12V, EN/DEM = Floating, No Load
Time (40μs/Div)
10
DS8202L/M-04 April 2011www.richtek.com
Applications Information
RT8202L/M
The RT8202L/M PWM controller provides the high
efficiency, excellent transient response, and high DC output
accuracy needed for stepping down high voltage batteries
to generate low voltage CPU core, I/O, and chipset RAM
supplies in notebook computers. RichTek's Mach
ResponseTM technology is specifically designed for
providing 100ns “instant-on” response to load steps while
maintaining a relatively constant operating frequency and
inductor operating point over a wide range of input voltages.
The topology circumvents the poor load transient timing
problems of fixed frequency current mode PWMs while
also avoiding the problems caused by widely varying
switching frequencies in conventional constant-on-time and
constant- off-time PWM schemes. The DRVTM mode PWM
modulator is specifically designed to have better noise
immunity for such a single output application.
PWM Operation
The Mach Response
TM
DRVTM mode controller relies on
,
the output filter capacitor's effective series resistance
(ESR) to act as a current-sense resistor, so the output
ripple voltage provides the PWM ramp signal. Referring to
the function diagrams of the RT8202L/M, the synchronous
high side MOSFET is turned on at the beginning of each
cycle. After the internal one-shot timer expires, the
MOSFET is turned off. The pulse width of this one shot is
determined by the converter's input and output voltages
to keep the frequency fairly constant over the input voltage
range. Another one-shot sets a minimum off-time (400ns
typ.).
On-Time Control (TON)
The on-time one-shot comparator has two inputs. One
input looks at the output voltage, while the other input
samples the input voltage and converts it to a current.
This input voltage proportional current is used to charge
an internal on-time capacitor. The on-time is the time
required for the voltage on this capacitor to charge from
zero volts to V
, thereby making the on-time of the high
OUT
side switch directly proportional to the output voltage and
inversely proportional to the input voltage. The
implementation results in a nearly constant switching
frequency without the need of a clock generator.
t =
ON
3.85p x R x V
TON OUT
(V 0.5)−
IN
And then the switching frequency is :
V
Frequency =
R
is a resistor connected from the input supply (VIN)
TON
OUT
(V x t
IN ON
)
to the TON pin.
Mode Selection (EN/DEM) Operation
The EN/DEM pin enables the supply. When EN/DEM is
tied to VDD, the controller is enabled and operates in
diode-emulation mode. When the EN/DEM pin is floating,
the RT8202L/M will operate in forced-CCM mode.
Diode-Emulation Mode (EN/DEM = High)
In diode-emulation mode, the RT8202L/M automatically
reduces switching frequency at light load conditions to
maintain high efficiency. This reduction of frequency is
achieved smoothly and without increasing VOUT ripple or
load regulation. As the output current decreases from
heavy-load condition, the inductor current is also reduced,
and eventually comes to the point when its valley touches
zero current, which is the boundary between continuous
conduction and discontinuous conduction modes. By
emulating the behavior of diodes, the low side MOSFET
allows only partial negative current when the inductor
freewheeling current becomes negative. As the load current
is further decreased, it takes longer and longer to discharge
the output capacitor to the level that requires the next
“ON” cycle. The on-time is kept the same as that in the
heavy-load condition. In reverse, when the output current
increases from light load to heavy load, the switching
frequency increases to the preset value as the inductor
current reaches the continuous condition. The transition
load point to the light load operation can be calculated as
follows (Figure 1) :
(V V )
−
I x t
LOAD ON
≈
IN OUT
2L
where tON is the On-time.
DS8202L/M-04 April 2011 www.richtek.com
11
RT8202L/M
I
L
Slope = (VIN -V
0
t
ON
OUT
) / L
I
L, PEAK
I
LOAD
t
= I
L, PEAK
/ 2
Figure 1. Boundary Condition of CCM/DEM
The switching waveforms may appear noisy and
asynchronous when light loading causes diode-emulation
operation, however, this is a normal operating condition
that results in high light load efficiency. Trade-offs in DEM
noise vs. light load efficiency are made by varying the
inductor value. Generally, low inductor values produce a
broader efficiency vs. load curve, while higher values result
in higher full load efficiency (assuming that the coil
resistance remains fixed) and less output voltage ripple.
The disadvantages for using higher inductor values include
larger physical size and degraded load transient response
(especially at low input voltage levels).
I
L
I
L, PEAK
I
LOAD
I
LIM
0
t
Figure 2. Valley Current Limit
Current sensing of the RT8202L/M can be accomplished
in two ways. Users can either use a current sense resistor
or the on-state of the low side MOSFET (R
DS(ON)
). For
resistor sensing, a sense resistor is placed between the
source of low side MOSFET and PGND (Figure 3(a)).
R
sensing is more efficient and less expensive (Figure
DS(ON)
3(b)). However, there is a compromise between current
limit accuracy and sense resistor power dissipation.
PHASE
LGATE
Forced-CCM Mode (EN/DEM = floating)
The low noise, forced-CCM mode (EN/DEM = floating)
disables the zero crossing comparator, which controls
the low side switch on-time. This causes the low side
gate-drive waveform to become the complement of the
high side gate-drive waveform. This in turn causes the
inductor current to reverse at light loads as the PWM loop
to maintain a duty ratio V
OUT/VIN
. The benefit of forced-
CCM mode is to keep the switching frequency fairly
constant, but it comes at a cost. The no load battery
current can be as high as 10mA to 40mA, depending on
the external MOSFETs.
Current Limit Setting (OCP)
The RT8202L/M has a cycle-by-cycle current limiting
control. The current limit circuit employs a unique“valley”
current sensing algorithm. If the magnitude of the current
sense signal at OC is above the current limit threshold,
the PWM is not allowed to initiate a new cycle (Figure 2).
OC
R
ILIM
(a)
PHASE
LGATE
OC
R
ILIM
(b)
Figure 3. Current Sense Methods
In both cases, the R
resistor between the OC pin and
ILIM
PHASE pin sets the over current threshold. This resistor
R
is connected to a 20μA current source within the
ILIM
RT8202L/M which is turned on when the low side MOSFET
turns on. When the voltage drop across the sense resistor
or low side MOSFET equals the voltage across the R
ILIM
12
DS8202L/M-04 April 2011www.richtek.com
RT8202L/M
resistor, positive current limit will activate. The high side
MOSFET will not be turned on until the voltage drop across
the sense element (resistor or MOSFET) falls below the
voltage across the R
resistor.
ILIM
Choose a current limit resistor by the following equation :
I x R
R =
ILIM
LIMIT SENSE
20μA
Carefully observe the PC board layout guidelines to ensure
that noise and DC errors do not corrupt the current sense
signal seen by OC and PGND. Mount the IC close to the
low-side MOSFET and sense resistor with short, direct
traces, making a Kelvin sense connection to the sense
resistor.
MOSFET Gate Driver (UGATE, LGA TE)
The high side driver is designed to drive high current, low
R
N-MOSFET(s). When configured as a floating driver,
DS(ON)
5V bias voltage is delivered from the VDDP supply. The
average drive current is proportional to the gate charge at
VGS = 5V times the switching frequency. The instantaneous
drive current is supplied by the flying capacitor between
the BOOT and PHASE pins.
A dead time to prevent shoot through is internally
generated between high side MOSFET off to low side
MOSFET on, and low side MOSFET off to high side
MOSFET on.
The low side driver is designed to drive high current, low
R
N-MOSFET(s). The internal pull down transistor
DS(ON)
that drives LGATE low is robust, with a 0.7Ω typical on
resistance. A 5V bias voltage is delivered form VDDP
supply. The instantaneous drive current is supplied by the
flying capacitor between VDDP and PGND.
V
IN
BOOT
UGATE
PHASE
+5V
R
Figure 4. Reducing the UGATE Rise Time
Power Good Output (PGOOD)
The power good output is an open-drain output and requires
a pull up resistor. When the output voltage is 15% above
or 10% below its set voltage, PGOOD gets pulled low. It
is held low until the output voltage returns to within these
tolerances once more. In soft-start, PGOOD is actively
held low and is allowed to transition high until soft-start is
over and the output reaches 93% of its set voltage. There
is a 2.5μs delay built into PGOOD circuitry to prevent
false transition.
POR, UVLO and Soft-Start
Power on reset (POR) occurs when VDD rises above to
approximately 4.1V. The RT8202L/M will reset the fault
latch and prepare the PWM for operation. At below 3.7V
(min), the VDD undervoltage lockout (UVLO) circuitry
inhibits switching by keeping UGATE and LGATE low.
A built in soft-start is used to prevent surge current from
power supply input after EN/DEM is enabled. It clamps
the ramping of internal reference voltage which is compared
with the FB signal. The typical soft-start duration is 1.5ms.
Output Over Voltage Protection (OVP)
For high current applications, some combinations of high
and low side MOSFETs might be encountered that will
cause excessive gate-drain coupling, which can lead to
efficiency-killing, EMI producing shoot through currents.
This is often remedied by adding a resistor in series with
BOOT, which increases the turn-on time of the high side
MOSFET without degrading the turn-off time (Figure 4).
The output voltage can be continuously monitored for over
voltage protection. When the output voltage exceeds 15%
of its set voltage threshold, over voltage protection is
triggered and the low side MOSFET is latched on. This
activates the low side MOSFET to discharge the output
capacitor.
The RT8202L/M is latched once OVP is triggered and can
only be released by VDD or EN/DEM power on reset. There
is a 20μs delay built into the over voltage protection circuit
to prevent false transitions.
DS8202L/M-04 April 2011 www.richtek.com
13
RT8202L/M
Output Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage protection. When the output voltage is less than
70% of its set voltage threshold, under voltage protection
is triggered and then both UGATE and LGATE gate drivers
are forced low. In order to remove the residual charge on
the output capacitor during the under voltage period, if
PHASE is greater than 1V, the LGATE is forced high until
PHASE is lower than 1V. There is 2.5μs delay built into
the under voltage protection circuit to prevent false
transitions. During soft-start, the UVP will be blanked
around 4.5ms.
Output V oltage Setting (FB)
The output voltage can be adjusted from 0.75V to 3.3V by
setting the feedback resistors R6 and R7 (Figure 5).
Choose R7 to be approximately 10kΩ, and solve for R6
using the equation :
R6
V = V x 1 +
OUT FB
⎛⎞
⎜⎟
R7
⎝⎠
where VFB is 0.75V.
V
IN
UGATE
PHASE
V
OUT
be large enough not to saturate at the peak inductor current
(I
) :
PEAK
LIR
I = I + x I
PEAK LOAD(MAX) LOAD(MAX)
⎛⎞
⎜⎟
2
⎝⎠
Output Capacitor Selection
The output filter capacitor must have ESR low enough to
meet output ripple and load transient requirement, yet have
high enough ESR to satisfy stability requirements. Also,
the capacitance value must be high enough to absorb the
inductor energy going from a full load to no load condition
without tripping the OVP circuit.
For CPU core voltage converters and other applications
where the output is subject to violent load transient, the
output capacitor's size depends on how much ESR is
needed to prevent the output from dipping too low under a
load transient. Ignoring the sag due to finite capacitance :
V
P P
ESR
≤
−
I
LOAD(MAX)
In non-CPU applications, the output capacitor's size
depends on how much ESR is needed to maintain at an
acceptable level of output voltage ripple :
V
P P
ESR
≤
LIR x I
−
LOAD(MAX)
Organic semiconductor capacitor(s) or special polymer
capacitor(s) are recommended.
LGATE
VOUT
FB
GND
R6
R7
Figure 5. Setting The Output Voltage
Output Inductor Selection
The switching frequency (on-time) and operating point
(% ripple or LIR) determine the inductor value as follows :
t x (V V )
ON IN OUT
L =
LIR x I
−
LOAD(MAX)
Find a low pass inductor having the lowest possible DC
resistance that fits in the allowed dimensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and can work well at 200kHz. The core must
14
Output Capacitor Stability
Stability is determined by the value of the ESR zero relative
to the switching frequency. The point of instability is given
by the following equation :
f = <
2 x x ESR x C 4
1
π
OUT
f
SW
Do not put high value ceramic capacitors directly across
the outputs without taking precautions to ensure stability.
Large ceramic capacitors can have a high ESR zero
frequency and cause erratic and unstable operation.
However, it is easy to add sufficient series resistance by
placing the capacitors a couple of inches downstream from
the inductor and connecting VOUT or the FB divider close
to the inductor.
There are two related but distinct ways, double pulsing
and feedback loop instability to identify the unstable
operation.
DS8202L/M-04 April 2011www.richtek.com
RT8202L/M
Double pulsing occurs due to noise on the output or
because the ESR is too low such that there is not enough
voltage ramp in the output voltage signal. This“fools” the
error comparator into triggering a new cycle immediately
after the 400ns minimum off-time period has expired.
Double pulsing is more annoying than harmful, resulting
in nothing worse than increased output ripple. However, it
may indicate the possible presence of loop instability,
which is caused by insufficient ESR.
Loop instability can result in oscillation at the output after
line or load perturbations and trip the over voltage
protection latch or cause the output voltage to fall below
the tolerance limit.
The easiest method for stability checking is to apply a
zero-to-max load transient and carefully observe the output
voltage ripple envelope for overshoot and ringing. It helps
to simultaneously monitor the inductor current with an AC
probe. Do not allow more than one ringing cycle after the
initial step response under shoot or over shoot.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
where T
the ambient temperature, and θ
D(MAX)
= (T
J(MAX)
− TA) / θ
J(MAX)
JA
is the maximum junction temperature, T
is the junction to ambient
JA
A
thermal resistance.
For recommended operating condition specifications of
the RT8202L/M, the maximum junction temperature is
125°C and TA is the ambient temperature. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-16L 3x3 packages, the thermal resistance, θJA, is
68°C/W on a standard JEDEC 51-7 four-layer thermal test
board. For WQFN-16L 4x4 packages, the thermal
resistance, θJA, is 54°C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
dissipation at T
= 25°C can be calculated by the following
A
formula :
P
= (125°C − 25°C) / (68°C/W) = 1.471W for
D(MAX)
WQFN-16L 3x3 package
P
= (125°C− 25°C) / (54°C/W) = 1.852W for
D(MAX)
WQFN-16L 4x4 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
resistance, θJA. For the RT8202L/M package, the derating
curves in Figure 6 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
Maximum Power Dissipation (W)1
0.1
0.0
WQFN-16L 3x3
0 25 50 75 100 125
Four-Layer PCB
WQFN-16L 4x4
Ambient Temperature (°C)
Figure 6. Derating Curve for the RT8202L/M Package
Layout Consideration
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to converter
instability. Certain points must be considered before
is
starting a layout for the RT8202L/M.
` Connect RC low-pass filter from VDDP to VDD, 1μF and
20Ω are recommended. Place the filter capacitor close
to the IC.
` Keep current limit setting network as close as possible
to the IC. Routing of the network should avoid coupling
to high-voltage switching node.
` Connections from the drivers to the respective gate of
the high side or low side MOSFET should be as short
as possible to reduce stray inductance.
and thermal
DS8202L/M-04 April 2011 www.richtek.com
15
RT8202L/M
` All sensitive analog traces and components such as
VOUT, FB, GND, EN/DEM, PGOOD, OC, VDD, and
TON should be placed away from high voltage switching
nodes such as PHASE, LGATE, UGATE, or BOOT
nodes to avoid coupling. Use internal layer(s) as ground
plane(s) and shield the feedback trace from power traces
and components.
` Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.
` Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed to minimize loops
and reduce losses.
16
DS8202L/M-04 April 2011www.richtek.com
Outline Dimension
RT8202L/M
D
E
A
A3
A1
D2
e
SEE DETAIL A
1
E2
b
L
1
2
1
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters Dimensions In Inches
Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 2.950 3.050 0.116 0.120
D2 1.300 1.750 0.051 0.069
E 2.950 3.050 0.116 0.120
E2 1.300 1.750 0.051 0.069
e 0.500 0.020
L 0.350 0.450
0.014 0.018
W-Type 16L QFN 3x3 Package
DS8202L/M-04 April 2011 www.richtek.com
17
RT8202L/M
D
D2
L
SEE DETAIL A
1
E
e
A
A3
A1
E2
1
b
2
1
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters Dimensions In Inches
Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.250 0.380 0.010 0.015
D 3.950 4.050 0.156 0.159
D2 2.000 2.450 0.079 0.096
E 3.950 4.050 0.156 0.159
E2 2.000 2.450 0.079 0.096
e 0.650 0.026
L 0.500 0.600
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
0.020 0.024
W-Type 16L QFN 4x4 Package
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
DS8202L/M-04 April 2011www.richtek.com
18
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