Richtek RT8061AZQW Schematic [ru]

3A, 1MHz, Synchronous Step-Down Converter

RT8061A

General Description

The RT8061A is a high efficiency synchronous, step-down DC/DC converter. Its input voltage ra nge from 2.7V to 5.5V that provides an adjustable regulated output voltage from

0.6V to V

while delivering up to 3A of output current.

The internal synchronous low on resistance power switches increase efficiency and eliminate the need for an external Schottky diode. The switching frequency is fixed internally at 1MHz. The 100% duty cycle provides low dropout operation, hence extending battery life in portable systems. Current mode operation with internal compensation allows the transient response to be optimized over a wide range of loa ds and output ca pacitors. The RT8061A is operated in PWM/PSM mode to a chieve high efficiency for a wide load range. The RT8061A is available in a W DFN-10L 3x3 pack age.

Ordering Information

RT8061A

Package Type QW : WDFN-10L 3x3 (W-Type)

Lead Plating System Z : ECO (Ecological Element with Halogen Free and Pb free)

Note : Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Features

High Efficiency : Up to 95%

z Low R

Internal Switches : 69m

DS(ON)

ΩΩ

Ω/49m

ΩΩ

= 5V

z Fixed Frequency : 1MHz

z No Schottky Diode Required

z 0.6V Reference Allows Low Output Voltage

z PWM/PSM Mode Operation

z Low Dropout Operation : 100% Duty Cycle

z OCP, UVP, OVP, OTP

z RoHS Compliant and Halogen Free

Applications

z Portable Instruments z Battery-Powered Equipment z Notebook Computers z Distributed Power Systems z IP Phones z Digital Camera s

Pin Configurations

(TOP VIEW)

GND

PVIN

SVIN

LX LX

PGOOD

WDFN-10L 3x3

1 2 3 4 5

ΩΩ

Ω at V

ΩΩ

Marking Information

11 : Product Code

11 YM

DNN

DS8061A-04 September 2012 www.richtek.com

YMDNN : Date Code

RT8061A

Typical Application Circuit

RT8061A

PGOOD

Chip Enable

PGOOD

9, 10

PVIN SVIN

11 (Exposed Pad)

GND

Functional Pin Description

Pin No. Pin Name Pin Function

1, 7 NC No Internal Connection. 2, 3 LX Switch Node. Connection this pin to the inductor.

2, 3

OUT

FB1

FB2

OUT

4 PGOOD

Power Good Indicator. This pin is an open drain logic output that is pulled to ground when the output voltage is less than 90% of the target output voltage.

5 EN Enable Control. Pull high to turn on. Do not float. 6 FB

Feed back . Th is pin rec eiv es the fe edb ac k vol tag e fro m a resi stiv e vo lta ge div id er connected across the output.

8 SVIN Signal Input. Decouple this pin to GND with at least 1μF ceramic cap.

9, 10 PVIN Power Input. Decouple this pin to GND with at least 4.7μF ceramic cap.

11 (Exposed Pad) GND

The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.

Function Block Diagram

0.6V

PGOOD

Output Clamp

OSC

Slope Com

ISEN

Limit

PVIN

Int-SS

0.72V OV

0.54V

POR

SVIN

0.4V

PGOOD

Control

Logic

OTP

REF

Driver

NISEN

Zero Current

DS8061A-04 September 2012www.richtek.com

RT8061A

Absolute Maximum Ratings (Note 1)

z Supply Input V oltage, PVIN, SVIN-------------------------------------------------------------------------------- −0.3V to 6.5V z LX Pin V oltage--------------------------------------------------------------------------------------------------------- (V z Other I/O Pin Voltage------------------------------------------------------------------------------------------------ −0.3V to 6.5V z Power Dissipation, P

@ TA = 25°C

WDNF-10L 3x3-------------------------------------------------------------------------------------------------------- 1.429W

z Package Thermal Resistance (Note 2)

W DFN-10L 3x3, θJA-------------------------------------------------------------------------------------------------- 70°C/W WDFN-10L 3x3

z Junction T emperature------------------------------------------------------------------------------------------------ 150°C z Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------------- 260°C z Storage T emperature Range --------------------------------------------------------------------------------------- −65°C to 150°C z ESD Susceptibility (Note 3)

-------------------------------------------------------------------------------------------------- 8.2°C/W

θJC

HBM (Human Body Model)----------------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

0.3V) to 6.8V

IN +

z Supply Input V oltage, PVIN, SVIN-------------------------------------------------------------------------------- z Junction T emperature Range--------------------------------------------------------------------------------------- z Ambient T emperature Range---------------------------------------------------------------------------------------

2.7V to 5.5V

−40°C to 125°C

−40°C to 85°C

Electrical Characteristics

(VIN = 3.3V, T

Feedback Reference Voltage V Feedback Leakage Current IFB -- 0.1 0.4 μA

DC Bias Current

Output Voltage Line Regulation V Output Voltage Load Regulation I Switch Leakage Current VEN = 0A -- -- 1 μA Switching Frequency 0.8 1 1.2 MHz

Switch On Resistance, High R Switch On Resistance, Low R PMOS Current Lim it (latch-off) I

Under Voltage Lock out Threshold

= 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

0.594 0.6 0.606 V

REF

Active , V

0.7V, Not Switching -- 110 140

FB =

μA

Shutdown -- -- 1

2.7V to 5.5V I

IN =

= 0A to 3A −1 -- 1 %

OUT

DS(ON)_P

DS(ON)_N

LIM

V V

4 -- -- A

5V -- 69 -- mΩ

IN =

5V -- 49 -- mΩ

IN =

= 0A -- 0.3 -- %/V

OUT

VIN Rising 2.2 2.4 2.6

UVLO

IN Falling 2 2.2 2.4

EN Threshold Voltage

Logic-High VIH 1.6 -- -Logic-Low V

-- -- 0.4

EN Pull Low Resistance -- 500 -- kΩ

DS8061A-04 September 2012 www.richtek.com

RT8061A

Parameter Symbol Test Conditions Min Typ Max Unit

Ove r T emperature Protection (latch-off)

Soft-Start Time tSS 500 -- -- μs V

Discharge Resistance -- 1 00 -- Ω

OUT

Over Vol tage

OUT

Protection (latch-off, delay time = 10μs) V

Under Vol tage

OUT

Lockout Threshold (latch-off)

Power Good Measured FB, With Respect to V Power Good Hysteresis -- 5 -- %

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions.

is measured at T

measured at the exposed pad of the package.

= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

-- 150 -- °C

115 120 130 %

57 66 75 %

85 90 -- %

REF

DS8061A-04 September 2012www.richtek.com

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