Richtek RT8055GQW, RT8055GSP, RT8055ZQW Schematic [ru]

Download

3A, 2MHz, Synchronous Step-Down Converter

RT8055

General Description

The RT8055 is a high efficiency synchronous, step-down DC/DC converter. Its input voltage range is from 2.6V to

5.5V and provides a n adjustable regulated output voltage from 0.8V to 5V while delivering up to 3A of output current.

The internal synchronous low on-resistance power switches increase efficiency and eliminate the need for an exter

set by an external resistor . The 100% duty cycle provides low dropout operation extending battery life in portable systems. Current mode operation with external compensation allows the transient response to be optimized over a wide range of loa ds and output ca pacitors.

The RT8055 is operated in forced continuous PWM Mode which minimizes ripple voltage a nd reduces the noise and RF interference.

The RT8055 is available in the WDFN-10L 3x3 and SOP-8 (Exposed Pad) packages.

nal Schottky diode. The switching frequency is

Features

High Efficiency : Up to 95%

z Low R

z Programmable Frequency : 300kHz to 2MHz

z No Schottky Diode Required

z 0.8V Reference Voltage Allows for Low Output

Internal Switches : 100m

DS(ON)

ΩΩ

Voltage

z Forced Continuous Mode Operation

z 100% Duty Cycle Operation

z Input Over Voltage Protection

z RoHS Compliant and Halogen Free

Applications

z Portable Instruments z Battery-Powered Equipment z Notebook Computers z Distributed Power Systems z IP Phones z Digital Camera s z 3G/3.5G Data Card

Ordering Information

RT8055

Package Type QW : WDFN-10L 3x3 (W-Type) SP : SOP-8 (Exposed Pad-Option 2)

Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free)

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Pin Configurations

(TOP VIEW)

SHDN/RT

GND

PGND

1 2

GND

PGND

WDFN-10L 3x3

GND

SOP-8 (Exposed Pad)

GND

COMP

VDD

PVDD

COMP

VDD

PVDD

DS8055-05 November 2012 www.richtek.com

RT8055

Marking Information

RT8055GQW RT8055GSP

JN= : Product Code

JN=YM

YMDNN : Date Code

DNN

RT8055ZQW

JN : Product Code

JN YM

YMDNN : Date Code

DNN

Typical Application Circuit

22µF

0.1µF

R 180k

OSC

PVDD

RT8055

VDD

SHDN/RT GND

PGND

COMP

RT8055 GSPYMDNN

2µH

R 30k

COMP

470pF

RT8055GSP : Product Number YMDNN : Date Code

OUT

3.3V/3A

OUT

R1 75k

R2 24k

C 22µF x 2

Table 1. Recommended Component Selection

R1 (kΩ) R2 (kΩ) R

OUT

COMP

(kΩ) C

(nF) L1 (μH) C

COMP

OUT

(μF)

3.3 75 24 30 0.47 2.2 22 x 2

2.5 51 24 27 0.47 2.2 22 x 2

1.8 30 24 22 0.47 2.2 22 x 2

1.5 21 24 18 0.47 2.2 22 x 2

1.2 12 24 15 0.47 1.0 22 x 2

1.0 6 24 13 0.47 1.0 22 x 2

DS8055-05 November 2012www.richtek.com

Functional Pin Description

RT8055

Pin No.

WDFN-10L 3x3 SOP-8

1 1 SHDN/RT

11 (Exposed Pad)

9 (Expos ed Pad)

3, 4 3 LX

5 4 PGND

6, 7 5 PVDD Powe r Supp ly Input. D eco upl e this pin to P G ND with a cap aci tor .

8 6 VDD

9 7 FB

10 8 COMP

Pin Name Pin Function

Shutdown Control or Frequency Setting Input. Connect a resistor to ground from this pin sets the switching frequency. Force t hi s pin to V

or GND caus es the dev ice to be shu t dow n.

Signal Ground. All small-signal components and compensation com pon ent s sh ou ld b e co nn ect ed t o th is g ro und , wh ich in t urn

GND

connects to PGND at one point. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Internal Power MOSFET Switches Output. Connect this pin to the inductor. Powe r Ground. Conne ct this pin cl ose to the neg ativ e termin al of C

and C

OUT

Signal Supply Input. Dec ouple this pin to GND with a capac itor. Generally, V

is equal to PVDD.

Feedback Pin. This pin receives the feedback voltage from a resistive d ivider connected acr oss the output. Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Connect external compens ation elem ents to this pin to stabilize the control loop.

Function Block Diagram

COMP

0.8V

Internal Soft Star

POR

VDD

SHDN/RT

Output Clamp

0.7V

0.4V

OSC

Slope

Comp.

Control

Logic

OTP

VREF

ISEN

Limit

Driver

NISEN

N-MOSFET I

PVDD

PGND

LIM

GND

DS8055-05 November 2012 www.richtek.com

RT8055

Absolute Maximum Ratings (Note 1)

z Supply Input V oltage, V DD, PV DD ----------------------------------------------------------------------------−0.3V to 6.5V z LX Pin Switch Voltage --------------------------------------------------------------------------------------------−0.3V to (PVDD + 0.3V)

<10ns ----------------------------------------------------------------------------------------------------------------−5V to 8.5V

z Other I/O Pin Voltages -------------------------------------------------------------------------------------------−0.3V to 6.5V z LX Pin Switch Current -------------------------------------------------------------------------------------------- 4A z Power Dissipation, P

W D FN-10L 3x3-----------------------------------------------------------------------------------------------------1.667W

SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------------1.333W

z Package Thermal Re sistance (Note 2)

W DFN-10L 3x3, θJA-----------------------------------------------------------------------------------------------6 0 °C/W

WDFN-10L 3x3, θJC-----------------------------------------------------------------------------------------------7.8°C/W SOP-8 (Exposed Pad), θJA-------------------------------------------------------------------------------------7 5 °C/W SOP-8 (Exposed Pad), θJC-------------------------------------------------------------------------------------1 5 °C/W

z Junction T emperature---------------------------------------------------------------------------------------------150°C z Lead Temperature (Soldering, 10 sec.)-----------------------------------------------------------------------260°C z Storage T emperature Range ------------------------------------------------------------------------------------−65°C to 150°C z ESD Susceptibility (Note 3)

HBM (Human Body Model)--------------------------------------------------------------------------------------2kV

@ TA = 25°C

Recommended Operating Conditions (Note 4)

z Supply Input V oltage----------------------------------------------------------------------------------------------2.6V to 5.5V z Junction T emperature Range------------------------------------------------------------------------------------ z Ambient T emperature Range------------------------------------------------------------------------------------

−40°C to 125°C

−40°C to 85°C

Electrical Characteristics

= 3.3V, T

Input Voltage Range VDD 2.6 -- 5.5 V Feedback Reference Voltage V Feedback Leakage Current IFB V

DC Bias Current

Output Voltage Line Regulation ΔV Output Voltage Load Regulation ΔV Error Amplifier

Transconductance

= 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

0.784 0.8 0.816 V

REF

= 3.3V -- -- 0.1 μA

Active , VFB = 0.7V, Not Switchin g -- 500 - - μA Shutdown -- -- 1 μA

VIN = 2.6V to 5.5V -- 0.1 -- %/V

LINE

LOAD

= 5V, V

= 0A to 3A

OUT

= 3.3V,

OUT

-- 0.4 -- %

gm -- 400 -- μA/V

Current Sense Transresistance RS -- 0.4 -- Ω RT Leakage Current SHDN/RT = VIN = 5.5V -- -- 1 μA

DS8055-05 November 2012www.richtek.com

Parameter Symbol Test Conditions Min Typ Max Unit

Switch ing Frequency

RT8055

= 180kΩ 1.44 1.8 2.16

OSC

Adjustable Switching Frequency Range

0.3 -- 2

MHz

Switch On Resistance, High R Switch On Resistance, Low R Peak Current Limit I

Under Voltage Lockout Threshold (Note 5)

Shutdown Threshold V

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design.

is measured at T

measured at the exposed pad of the package.

DS(ON)_P ISW DS(ON)_N ISW

3.5 -- -- A

LIM

V V

SHDN

= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

= 0.3A -- 100 160 mΩ = 0.3A -- 100 170 mΩ

Rising @Full Temperature 2.33 2.4 2.57

Falling @Full Temperature 1.98 2.2 2.37

Rising -- VIN − 0.85 VIN − 0. 4 V

SHDN

DS8055-05 November 2012 www.richtek.com

RT8055

Typical Operating Characteristics

Efficiency vs. Output Current

100

90 80 70 60 50 40

Efficiency (% )

30 20 10

0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0

VIN = 5V, V

Output Current (A)

Output Voltage vs. Output Current

3.38

3.37

3.36

3.35

3.34

3.33

3.32

3.31

3.30

Output Voltage (V)

3.29

3.28

3.27

3.26

0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0

Output Current (A)

VIN = 5V, V

OUT

= 3.3V

Output Voltage vs. Input Voltage

3.36

3.35

3.34

3.33

3.32

Output V oltage (V)

3.31

= 0A, V

3.30

3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

OUT

Inpu t Voltage (V)

VIN UVLO vs. Te m perature

2.50

2.45

2.40

2.35

2.30

2.25

UVLO (V)

2.20

2.15

2.10

2.05

2.00

-50 -25 0 25 50 75 100 125

Rising

Falling

Tempera ture (°C)

OUT

= 3.3V

Switching Frequency vs. Input Voltage

2.1

2.0

1.9

1.8

1.7

1.6

Switching Frequency (MH z) 1

1.5

3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

Inpu t Volta ge (V)

VIN = 5V, V I

= 0.3A, fSW = 1.8MHz

OUT

= 3.3V

Switching Frequency vs. Temperature

2.1

2.0

1.9

1.8

1.7

1.6

Switching Frequency (MH z) 1

1.5

-50 -25 0 25 50 75 100 125

Tempera ture (°C)

VIN = 5V, V I

= 0.3A, fSW = 1.8MHz

OUT

= 3.3V

DS8055-05 November 2012www.richtek.com

RT8055

)

Output Current Limit vs. Input Voltage

6.0

5.5

5.0

4.5

4.0

3.5

3.0

Output Current Limit (A

2.5

2.0

3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

Input Voltage (V)

Output Voltage vs. Temperature

3.40

3.38

3.36

3.34

3.32

3.30

3.28

3.26

Output Voltage (V)

3.24

3.22

3.20

-50 -25 0 25 50 75 100 125

Tempera ture (°C)

VIN = 5V, V I

= 0A

OUT

= 3.3V

Output Current Limit vs. Temperature

6.0

5.5

5.0

4.5

4.0

3.5

3.0

Output C urrent Lim it (A

2.5

2.0

-50 -25 0 25 50 75 100 125

VIN = 5V, V

Tempera ture (°C)

Reference Voltage vs. Temperature

0.840

0.832

0.824

0.816

0.808

0.800

0.792

0.784

0.776

Refer ence Voltage (V)

0.768

0.760

-50 -25 0 25 50 75 100 125

Temperature (°C)

OUT

= 3.3V

Output Ripple

(5V/Div)

OUT

(5mV/Div)

VIN = 5V, V I

= 3A

OUT

= 3.3V

Time (500ns/Div)

(5V/Div)

OUT

(5mV/Div)

Output Ripple

VIN = 5V, V I

= 0A

OUT

Time (500ns/Div)

OUT

= 3.3V

DS8055-05 November 2012 www.richtek.com

RT8055

OUT

(200mV/Div)

OUT

(1A/Div)

(5V/Div)

Load Transient Response

VIN = 5V, V I

OUT

Time (100μs/Div)

Power On from V

OUT

= 0A to 3A

= 3.3V

OUT

(200mV/Div)

OUT

(1A/Div)

(5V/Div)

Load Transient Response

VIN = 5V, V I

OUT

Time (100μs/Div)

OUT

= 0A to 2A

UVP Shutdown

= 3.3V

(2V/Div)

OUT

(1V/Div)

VIN = 5V, V I

OUT

Time (1ms/Div)

= 0A

OUT

= 3.3V

OUT

(1V/Div)

VIN = 5V, V

Time (10μs/Div)

OUT

= 3.3V

DS8055-05 November 2012www.richtek.com

Application Information

RT8055

The basic R T8055 application circuit is shown in Typical Application Circuit. External component selection is determined by the maximum load current a nd begins with the selection of the inductor value and operating frequency followed by CIN and C

OUT

Output Voltage Setting

The output voltage is set by an external resistive divider according to the f ollowing equation :

⎞

+×=

1VV

⎟

⎠

where V

⎛ ⎜

REFOUT

⎝

equals to 0.8V typical.

REF

The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure 1.

OUT

RT8055

GND

Figure 1. Setting the Output Voltage

Soft-Start

The RT8055 contains an internal soft-start clamp that gradually raises the cla mp on the COMP pin.

Operating Frequency

3.0

2.5

RRT = 180k for 1.8MHz

2.0

1.5

1.0

0.5

Switching Frequency (MHz) 1

0.0 0 200 400 600 800 1000

(K )

(kΩ)

OSC

Figure 2

100% Duty Cycle Operation

When the input supply voltage decrea ses toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle.

The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-MOSFET and the inductor .

Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequency improves efficiency by reducing internal gate charge and switching losses but requires larger inductance a nd/or capa cita nce to maintain low output ripple voltage.

The operating frequency of the RT8055 is determined by

Low Supply Operation

The RT8055 is designed to operate down to an input supply voltage of 2.6V . One importa nt consideration at low input supply voltages is that the R

of the P-Channel a nd

DS(ON)

N-Channel power switches increases. The user should calculate the power dissipation when the RT8055 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded.

an external resistor that is connected between the SHDN/ RT pin a nd GND. The value of the resistor sets the ra m p current that is used to charge and discharge an internal timing ca pacitor within the oscillator . The RT resistor value can be determined by examining the frequency vs. R

curve. Although frequencies a s high a s 2MHz are possible, the minimum on-time of the RT8055 imposes a minimum limit on the operating duty cycle. The minimum on-time is typically 110ns. Therefore, the minimum duty cycle is equal to 100 x 1 10n s x f (Hz).

DS8055-05 November 2012 www.richtek.com

Slope Compensation and Inductor Peak Current

Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. It is accomplished internally by a dding a compensating ra mp to the inductor current signal. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the RT8055, however, separated inductor current signals are used to monitor over current condition.

RT8055

This keeps the maximum output current relatively constant regardless of duty cycle.

Short Circuit Protection

When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. A current runaway detector is used to monitor inductor current. As current increa sing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring.

Inductor Selection

The inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current ΔI

increases with higher V

and decrea ses with higher inducta nce.

⎡⎤⎡ ⎤

OUT OUT

I = 1

Δ×−

⎢⎥⎢ ⎥

fL V

⎣⎦⎣ ⎦

Having a lower ripple current reduces not only the ESR losses in the output capa citors but also the output voltage ripple. However , it requires a large inductor to achieve this goal.

For the ripple current selection, the value of ΔI

= 0.4(I

MAX

will be a reasonable starting point. The largest ripple

current occurs at the highest VIN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation :

⎡⎤⎡ ⎤

L = 1

OUT OUT

⎢⎥⎢ ⎥

fI V

×Δ

L(MAX) IN(MAX)

⎣⎦⎣ ⎦

×−

The inductor's current rating (caused a 40°C temperature rising from 25°C ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit pea k current li mit.

This formula has a maximum at VIN = 2V I

RMS

= I

/2. This simple worst-case condition is

OUT

commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required.

Several cap acitors may also be paralleled to meet size or height requirements in the design.

The selection of C

is determined by the effective series

OUT

resistance (ESR) that is required to mini mize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient re sponse as described in a later section. The output ripple, ΔV

⎡

ESRIV

LOUT

⎢

⎣

, is determined by :

OUT

⎤

+Δ≤Δ

8fC

OUT

⎥

⎦

The output ripple is highest at maximum input voltage since ΔIL increa ses with input voltage. Multiple ca pacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic a nd cera mic capa citors are all available in surface mount pa ckages. Speci al polymer

)

ca pacitors offer very low ESR but have lower ca pa citance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but ca n be used in cost-sensitive application s provided that consideration is given to ripple current ratings and long term relia bility. Cera mic ca pacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric ef fects. The high Q of ceramic capacitors with trace inductance can also lead to signif ica nt ringing.

OUT

, where

CIN and C

The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by :

OUT(MAX)RMS

Selection

OUT

Using Ceramic In put and Output Capacitors

Higher values, lower cost ceramic capacitors are now becoming available in smaller ca se sizes. Their high ripple current, high voltage rating and low ESR ma ke them ideal for switching regulator a pplications. However , care must be taken when these ca pacitors are used at the in put and

−=

output. When a ceramic capacitor is used at the input

DS8055-05 November 2012www.richtek.com

RT8055

and the power is supplied by a wall ad a pter through long wires, a load step at the output can induce ringing at the input, VDD. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part.

Thermal Considerations

For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and a mbient temperature. The maximum power dissipation can be calculated by the following formula :

P where T

the ambient temperature, a nd θ

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

is the maximum junction temperature, TA is

is the junction to ambient

thermal resistance. For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to a mbient thermal resistance, θJA, is layout dependent. For SOP-8 (Exposed Pad) pack ages, the thermal resistance,

, is 75°C/W on a standard JEDEC 51-7 four-layer

thermal test board. For WDFN-10L 3x3 packages, the thermal resistance, θJA, is 70°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula s :

= (125°C − 25°C) / (75°C/W) = 1.333W for

D(MAX)

SOP-8 (Exposed Pad) package

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

Maximum Power Dissipation (W)

0.1

0.0

SOP-8 (Exposed Pad)

0 25 50 75 100 125

WDFN-10L 3x3

Four-Layer PCB

Ambient Temperature ( °C)

Figure 3. Derating Curve of Maxi mum Power Dissi pation

Layout Considerations

Follow the PCB layout guidelines for optimal performa nce of RT8055.

` A ground pla ne is recommended. If a ground plane layer

is not used, the signal and power grounds should be segregated with all small-signal components returning to the GND pin at one point that is then connected to the PGND pin close to the IC. The exposed pad should be connected to GND.

` Connect the terminal of the input capacitor(s), C

, as close as possible to the PVDD pin. This capacitor provides the AC current into the internal power MOSFETs.

` LX node is with high frequency voltage swing and should

be kept within small area. Keep all sensitive small-signal nodes away from the LX node to prevent stray capa citive noise pick-up.

P W DF N-10L 3x3 pa ckage

The maximum power dissipation depends on the operating ambient temperature for fixed T resistance, θJA. The derating curves in Figure 3 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation.

= (125°C − 25°C) / (70°C/W) = 1.429W for

D(MAX)

and thermal

J(MAX)

` Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise of powercomponents.

Y ou can connect the copper area s to a ny DC net (PV DD, V DD, VOUT, PGND, GND, or any other DC rail in your system).

` Connect the FB pin directly to the feedback resistors.

The resistor divider must be connected between V

OUT

and GND.

DS8055-05 November 2012 www.richtek.com

RT8055

LX should be connected to Inductor by wide and short trace, keep sensitive compontents away from this trace

Connect the FB pin directly to feedback resistor s. The resistor divider must be connected between V

OSC

OUT

GND

LX LX

PGND

1 2 3 4 5

SHDN/RT

OUT

Output capacitor must be near RT8055

GND

COMP

VDD

GND

PVDD

CIN must be placed between VDD and GND as closer as possible

COMP

and GND.

OUT

Figure 4. PCB Layout Guide

Recommended component selection for T ypical Application

Table 2. Inductors

Component Supplier Series Inductance (μH) DCR (mΩ) Current Rating (mA) Dimensions (mm)

TAIYO YUDEN NR 8040 2 9 7800 8x8x4

Table 3. Capacitors for CIN and C

OUT

Component Supplier Part No. Capacitance (μF) Case Size

TDK C3225X5R0J226M 22 1210

TDK C2012X5R0J106M 10 0805 Panasonic ECJ4YB0J226M 22 1210 Panasonic ECJ4YB1A106M 10 1210

TAIYO YUDEN LMK325BJ226ML 22 1210 TAIYO YUDEN JMK316BJ226ML 22 1206 TAIYO YUDEN JMK212BJ106ML 10 0805

DS8055-05 November 2012www.richtek.com

Outline Dimension

RT8055

SEE DETAIL A

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 2.950 3.050 0.116 0.120

D2 2.300 2.650 0.091 0.104

E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069

e 0.500 0.020

L 0.350 0.450

W-Type 10L DFN 3x3 Package

0.014 0.018

DS8055-05 November 2012 www.richtek.com

RT8055

EXPOSED THERMAL PAD (Bottom of Package)

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 4.801 5.004 0.189 0.197

B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020

F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010

I 0.000 0.152 0.000 0.006

J 5.791 6.200 0.228 0.244

M 0.406 1.270 0.016 0.050

X 2.000 2.300 0.079 0.091

Option 1

Y 2.000 2.300 0.079 0.091

X 2.100 2.500 0.083 0.098

Option 2

Y 3.000 3.500 0.118 0.138

8-Lead SOP (Exposed Pad) Plastic Package

Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS8055-05 November 2012www.richtek.com

Richtek RT8055GQW, RT8055GSP, RT8055ZQW Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual