RT7297B
11
DS7297B-02 September 2012 www.richtek.com
©
Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
OUT
IN
RMS OUT(MAX)
IN OUT
V
V
I = I 1
VV
−
CIN and C
OUT
Selection
The input capacitance, CIN, is needed to filter the
trapezoidal current at the source of the high side MOSFET.
T o prevent large ripple current, a low ESR in put capa citor
sized for the maximum RMS current should be used. The
approxi mate RMS current is given :
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/ 2. This simple worst case condition is
commonly used for design because even significant
deviations do not offer much relief. Choose a capacitor
rated at a higher temperature than required. Several
cap acitors may also be paralleled to meet size or height
requirements in the design. For the input capacitor, two
10μF low ESR ceramic ca pa citors are suggested. For the
suggested
capacitor, please refer to Table 3 for more details. The
selection of C
OUT
is determined by the required ESR to
minimize voltage ripple. Moreover, the amount of bulk
capacitance is also a key for C
OUT
selection to ensure
that the control loop is stable. Loop stability can be
checked by viewing the load transient response as
described in a later section.
The output ripple, ΔV
OUT
, is determined by :
OUT L
OUT
1
VIESR
8fC
⎡⎤
Δ≤Δ +
⎢⎥
⎣⎦
The output ripple will be the highest at the maximum input
voltage since ΔIL increases with input voltage. Multiple
cap a citors pla ced in parallel may be needed to meet the
ESR and RMS current handling require ment. Higher values,
lower cost ceramic ca pa citors are now becoming available
in smaller case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal f or switching regulator
applications. However, care must be taken when these
cap acitors are used at in put and output. When a cera mic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
output can induce ringing at the input, VIN. At best, this
ringing can couple to the output and be mista ken a s loop
instability. At worst, a sudden inrush of current through
the long wires can potentially cause a voltage spike at
VIN large enough to damage the part.
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to a mbient.
The maximum power dissipation can be calculated by
following formula :
P
D(MAX)
= (T
J(MAX)
− TA ) / θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature , T
A
is the ambient temperature a nd the θ
JA
is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT7297B, the maximum junction temperature is 125°C.
The junction to ambient thermal resistance θJA is layout
dependent. For SOP-8 (Exposed Pad) package, the
thermal resistance θJA is 75°C/W on the standard JEDEC
51-7 four-layers thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by following
formula :
P
D(MAX)
= (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
P
D(MAX)
= (125°C − 25°C) / (49° C/W) = 2.04W
(70mm2copper area PCB layout)
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to
increase thermal perf ormance by the PCB layout copper
design. The thermal resistance θ
JA
can be decreased by
adding copper area under the exposed pad of SOP-8
(Exposed Pad) package.
As shown in Figure 7, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 7.a), θ
JA
is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 7.b) reduces the θ
JA
to 64°C/W. Even further ,
increa sing the copper area of pad to 70mm2 (Figure 7.e)
reduces the θ
JA
to 49°C/W.