Richtek RT7291AGQUF, RT7291BGQUF Schematic [ru]

RT7291A/B

6A, 23V, 500kHz, ACOTTM Synchronous Buck Converter with LDO for System 5V

General Description

The RT7291A/B is a synchronous Buck converter with Advanced Consta nt On-Time (ACOTTM) mode control. The main control loop of RT7291A/B uses an ACOTTM mode control which provides a very fast tra nsient response with no external compensators. The RT7291A/B operates from 5V to 23V input voltage, provides a 5V LDO a nd a 300kHz CLK to drive an external charge pump. OCP, UVP and OVP are included in the RT7291A/B. This IC also provides a 1.5ms internal soft-start function and a n open-drain power good indicator.

Applications

 Laptop Computers  T a blet PCs  Networking Systems  Servers  Personal Video Recorders  Flat Panel Television and Monitors  Distributed Power Systems

Features



 5V to 23V Input Voltage Range



 Up to 98% Duty for 2S Battery Application



 PWM Frequency Fixed 500kHz



 ACOT



 Integrated MOSFET s



 Support Output MLCC Stable



 Internal Soft-Start (1.5ms typ)



 Built-in OVP/UVP/OCP



 Power Good Indicator



 Fixed 300kHz VCLK to Support Charge Pump



 Individual EN for PWM and LDO



 Thermal Shutdown



Mode Performs Fast T ra nsient Re sponse

ΩΩ



 31m

Ω of High-Side MOSFET



ΩΩ



 20m

Ω of Low-Side MOSFET



ΩΩ

Simplified Application Circuit

OUT

C1 C2

LDO

OUT

LDO

BYP

DS7291A/B-02 September 2015 www.richtek.com

D2 D3

VIN

EN LDO

VBYP

BYP

ENLDO

C3 C4

CLK

RT7291A/B

AGND

BOOT

VOUT PGND

PGOOD

VCC

PGOOD

VCC

OUT

RT7291A/B

Ordering Information

Pin Configurations

RT7291A/B

Package Type

QUF : UQFN-16L 3x3 (FC) (U-Type) Lead Plating System

G : Green (Halogen Free and Pb Free) Output Voltage

A : 5V

Note : Richtek products are :

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

B : 5.1V

Marking Information

RT7291AGQUF RT7291BGQUF

39= : Product Code

39=YM

DNN

YMDNN : Date Code

4M=YM

DNN

(TOP VIEW)

AGND

14 13 12 11 10

VIN

PGND

3 4 5 6 7

VBYP

PGOOD

UQFN-16L 3x3 (FC)

4M= : Product Code YMDNN : Date Code

ENLDO

CLK

VCC

BOOT

LDO

VOUT

Functional Pin Description

Pin No. Pin Name Pin Function

1 VIN Power Input Connect t o High- S ide MOSFET Drain. 2 PGND Power Ground.

Switch Over Source Voltage for VCC. A low pass fil ter should be connected to

3 VBYP

4 PGOOD Open-Drain P ower Good Indicator Output. 5 CLK 300kHz Clock Output t o Drive the External Charge Pump. 6 LDO 5V Linear Regulator Output. Decouple with a minimum 4.7F ceramic capacitor.

7 VOUT

8, 9, 15, 16 SW Switch Node.

10 BOOT

11 VCC

12 ENLDO

AGND, if VBYP is applied. If VBYP is not used, then connect to AGND. Do not connect to VCC pin.

Output Voltage Sense Input. A n internal discharging ci rcuit is connected to thi s pin.

Bootstrap Supply for High-Side Gate Driver. A capacitor is needed to drive the power switch's gate abov e the supply voltage. It is connected bet ween the SW and BOOT pins to form a floati ng suppl y across the power switch driv er.

5V Linear Regulator Output for Internal Cont rol Circuit. A capacitor (typical 2.2F) should be connected to AGND. VCC can only supply internal circuits. Do not connect to external loads.

Enable Control Input for Linear Regulator. This pin is internally pulled up to high by

10A. 13 EN Enable Control I nput. Do not leave this pin floating. 14 AGND Analog Ground.

DS7291A/B-02 September 2015www.richtek.com

Function Block Diagram

RT7291A/B

VOUT

CLK

Soft-Start

REF

120% x V

90% x V

OUT

CLK

Generator

Reference

+ +

REF

OVP

REF

VCC

POR &

POK

60% x V

Regulator

VBYP

Switch-Over

On-Time One shot

Min off Time

OUT

REF

VIN LDO

OCP

UVP

LDO

Control

ENLDO

Gate

Control

Logic

Fault Logic

BSTREG

LDO

Switch-Over

OUT

BOOT

PGND

PGOOD

AGND

Operation

Overall

The RT7291A/B is a synchronous step-down converter with advanced consta nt on-time control mode. Using the ACOTTM control mode can reduce the output ca pa citance and provide fast transient response. It can minimize the component size without additional external compensation network.

Internal VCC Regulator

The regulator provides 5V power to supply the internal control circuit. Connecting a 2.2μF cera mic capa citor for decoupling and stability is required.

Soft-Start

In order to prevent the converter output voltage from overshooting during the startup period, the soft-start function is necessary . The soft-start time is internal setting and the duration is around 1.5ms

OCP

The inductor valley current is monitored via the internal switches in cycle-by-cycle. Once the output voltage drops below UV threshold, the device enters latch mode.

Power Good

After soft-start is finished, the power good function will be activated. The PGOOD pin is a n open-drain output.

CLK Generator

Provide a 300kHz clock to drive external charge pump.

VCC Switch-Over

The internal regulator output will switch over to VBYP if VBYP level is higher than 4.6V.

LDO

Built-in 5V , 100mA LDO with 1% a ccuracy . The LDO output will switch over to VOUT once PGOOD goes high.

DS7291A/B-02 September 2015 www.richtek.com

RT7291A/B

Absolute Maximum Ratings (Note 1)

 Supply Input Voltage, VIN ---------------------------------------------------------------------------------- −0.3V to 27V  Switch Voltage, SW ----------------------------------------------------------------------------------------- −0.3V to (V

<30ns ----------------------------------------------------------------------------------------------------------- −5V to 28V

 BOOT Switch Voltage ---------------------------------------------------------------------------------------(V  EN, ENLDO Pin Voltages ---------------------------------------------------------------------------------- −0.3V to 27V  Other I/O Pin Voltages -------------------------------------------------------------------------------------- −0.3V to 6V  Power Dissi pation, P

@ T

= 25°C

UQF N-16L 3x3 (FC)------------------------------------------------------------------------------------------1.4W

 Package Thermal Re sistance (Note 2)

UQF N-16L 3x3 (FC), θJA------------------------------------------------------------------------------------70°C/W UQF N-16L 3x3 (FC), θJC------------------------------------------------------------------------------------15°C/W

 Lead T e mperature (Soldering, 10 sec.)------------------------------------------------------------------260°C  Junction T emperature----------------------------------------------------------------------------------------150°C  Storage T emperature Range ------------------------------------------------------------------------------- − 65°C to 150°C  ESD Susceptibility (Note 3)

HBM (Human Body Model)---------------------------------------------------------------------------------2kV MM (Machine Model) ---------------------------------------------------------------------------------------- 200V

− 0.3V) to (VSW + 6V)

+ 0.3V)

Recommended Operating Conditions (Note 4)

 Supply Input V oltage, VIN ----------------------------------------------------------------------------------5V to 23V  Junction T emperature Range------------------------------------------------------------------------------- − 40°C to 125°C  Ambient T emperature Range------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics

= 12V, TA = 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

Supply Current

Shutdown Current V Quiescent Curr ent V

Standby Current

Switch On-Resistance

Switch On-Resi stanc e

DS(ON)_H VBOOT

DS(ON)_L

Current Lim it

Current Limit IOC Valley curr ent of low-side s witch 7.6 -- 11.4 A

Switching Frequency and Minimum Off Timer

Switching Frequency fSW 450 500 550 kHz Minimum Of f -Ti me T

-- 200 -- ns

OFF

Protections

OVP Trip Threshold V OVP Propagation Delay T

W ith respect to output voltage 115 120 125 %

OVP OVPDLY

-- 5 -- s

= V

= 2V, V

= 0V, V

Current = 0A

= 0V -- 2.5 5 A

ENLDO

= 2V, No Switching -- 100 130 A

ENLDO

= 2V, LDO Load

ENLDO

-- 35 45 A

– VSW = 5V -- 31 --

-- 20 --

DS7291A/B-02 September 2015www.richtek.com

m

RT7291A/B

Parameter Symbol Test Conditions Min Typ Max Unit

UVP Trip Threshold V UVP Propagation Delay T

With respect t o output v oltage 55 60 65 %

UVP UVPDLY

-- 5 -- s

Reference and Sof t -Start

RT7291A 4.95 5 5.05

Output Voltage Valley V

OUT

RT7291B 5.049 5.1 5.151

Soft-Sta r t T i me TSS F r om E N high to PGOOD high 1 1.5 2 ms

Enable and UVLO

RT7291A 1.25 1.35 1.45

EN Input High Volt age V

ENH

RT7291B 1.3 1.4 1.5

EN Hysteresis V

EN Input Current IEN

-- 200 -- mV

ENHYS

= 2V -- 1 --

A

VEN = 0V -- 0 -VCC UVLO Rising V VCC UVLO Hysteresis V

CCUVLO CCHYS

-- 4.2 -- V

-- 400 -- mV

CLK Output

RT7291A -- -- 5.05 CLK Output Voltage

High-Level V

Low-Level V

CLKH

CLKL

= 10mA

VCLK

= 10mA 0 0. 1 0.2

VCLK

RT7291B -- -- 5.151

CLK Frequency f

-- 300 -- kHz

CLK

LDO Regulator

RT7291A 4.95 5 5.05

LDO Regulator V

LDO

RT7291B 5.049 5.1 5.151 EN = GND,

LDO Load Current = 5mA

-- 1 --

LDO Load Regulation

EN = GND, LDO Load Current = 100mA

-- 5 --

Switch On-Resi stanc e RSW -- 3 5 

VCC Regulator

RT7291A 4.805 5 5.295

VCC Regulator V

VCC

RT7291B 4.905 5.1 5.395

VCC Switch Over Threshold to VBYP

VCC Switch Over Hyster esi s V

Rising

BYP

Edge

Falli ng E dge -- 200 -- mV

BYP

RT7291A 4.45 4.6 4.75

RT7291B 4.542 4.692 4.842

Switch Over On- Resi st anc e -- 3 5 

DS7291A/B-02 September 2015 www.richtek.com

RT7291A/B

Parameter Symbol Test Conditions Min Typ Max Unit

Power Good Indicat or

PGOOD Threshold Fr om Lower V PGOOD Low Hysteresis V PGOOD Low to High Delay T PGOOD Sink Current Capability V PGOOD Leakage Current I

-- 0.5 -- ms

PGDLY PGSINK

PGLEAK

Sink 4mA -- -- 0.4 V

Rising 85 90 95 %

OUT

Falling -- 10 -- %

OUT

PGOOD

= 5V -- -- 100 nA

Therma l Shutdown

Thermal Shutdown Threshol d TSD 135 150 -- °C Thermal Shutdown Hystere si s -- 25 -- ° C

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

Note 2. θ Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions.

is measured at T

= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7.

DS7291A/B-02 September 2015www.richtek.com

Typical Application Circuit

RT7291A/B

OUT

5.2V to 23V

LDO

OUT

C1 C2 100nF / 50V

10µF /25V x 2

LDO

4.7µF /10V

BYP

5.1

D2 D3

C3 C4 100nF / 50V

100nF

/ 50V

110

VIN

CLK

100nF / 50V

BOOT

100nF / 50V

(Optional)

2.2

RT7291A/B

BYP

2.2µF / 10V

LDO

VBYP

PGOOD

ENLDO

VOUT PGND

AGND

VCC

8, 9, 15, 16

7 2

PGOOD

100k

4 11

0.1µF / 50V L

1.5µH

VCC

2.2µF /

OUT

22µF /

6.3V x 4

OUT

5V/6A

10V

Figure 1. T ypical Application Circuit with Pure MLCC Solution

DS7291A/B-02 September 2015 www.richtek.com

RT7291A/B

Typical Operating Characteristics

Efficiency vs. Load Current

100

= 7.4V, EN = 2V, ENLDO = floating

Effici ency (%)

0.001 0.01 0.1 1 10

Load Current (A)

Efficiency vs . Loa d Current

100

= 19V, EN = 2V, ENLDO = floating

Effici ency (%)

0.001 0.01 0.1 1 10

Load Current (A)

Efficiency vs. Load Current

100

= 12V, EN = 2V, ENLDO = floating

Effici ency (%)

0.001 0.01 0.1 1 10

Load Current (A)

Switching Frequency vs. Loa d Current

550

= 7.4V, EN = 2V, ENLDO = floating

500 450 400 350 300 250 200 150 100

Swit ching Frequency (kHz) 1

0.001 0.01 0.1 1 10

Load Current (A)

Switching Frequency vs. Load Current

550

= 12V, EN = 2V, ENLDO = floating

500 450 400 350 300 250 200 150 100

Switching Fr equency (kHz) 1

0.001 0.01 0.1 1 10

Load Current (A)

Swit ching Frequency ( kHz) 1

Switching Frequency vs. Load Current

550

= 19V, EN = 2V, ENLDO = floating

500 450 400 350 300 250 200 150 100

0.001 0.01 0.1 1 10

Load Current (A)

DS7291A/B-02 September 2015www.richtek.com

RT7291A/B

)

Quiescent Current vs. Input Voltage

100

90 80 70 60 50 40 30

Quiescent Current (µA) 1

20 10

5 7 9 11131517192123

Inpu t Volt age (V)

Shutdown Current vs. Input Voltage

9 8 7 6 5 4 3 2

Shutdown Current (µA) 1

1 0

5 7 9 11131517192123

Inpu t Voltage ( V )

EN = ENLDO = 0V

Standby Current vs. Input Voltage

80 70 60 50 40 30 20

Standby Cur rent (µA

5 7 9 11131517192123

EN = 0V , ENLDO = 2V, I

Inpu t Voltage ( V )

Output Voltage vs. Load Current

5.25

5.20

5.15

5.10

5.05

5.00

4.95

4.90

Output Voltage (V)

4.85

4.80

4.75

0.001 0.01 0.1 1 10

= 12V, EN = 2V, ENLDO = floating

Load Current (A)

LDO

= 0AEN = 2V, ENLDO = floating, No Switching

LDO Output Voltage vs. Input Voltage

5.25

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

LDO Output Volt age (V)

4.80

4.75 4 6 8 1012141618202224

LDO

= 0mA

= 50mA

= 100mA

OUT

(5V/Div)

PGOOD

(5V/Div)

Start Up Through EN

= 12V , ENLDO = GND, No Loa d

Time (500μs/Div)

Input Voltage (V)

DS7291A/B-02 September 2015 www.richtek.com

RT7291A/B

LDO

(5V/Div)

ENLDO (5V/Div)

LDO

(5V/Div)

Start Up Through ENLDO

= 12V, EN = GND, No Load

Time (500μs/Div)

Power Off Through ENLDO

OUT

(5V/Div)

PGOOD

(5V/Div)

OUT

(30mV/Div)

Power Off Through EN

= 12V , ENLDO = GND, No Loa d

Time (500μs/Div)

Load Transient Response

(5V/Div)

ENLDO (5V/Div)

OUT

(5V/Div)

PGOOD (5V/Div)

(10V/Div)

= 12V, EN = GND, No Load

Time (500μs/Div)

UVP

= 12V , EN = ENLDO = High

(20V/Div)

(5A/Div)

OUT

(5V/Div)

PGOOD

(5V/Div)

(10V/Div)

(5A/Div)

Time (50μs/Div)

= 12V, V

= 12V , EN = ENLDO = High

OVP

= 6V, EN = ENLDO = High

OUT

Time (50μs/Div)

DS7291A/B-02 September 2015www.richtek.com

Application Information

RT7291A/B

The RT7291A/B is high-performa nce 500kHz 6A step-down regulators with internal power switches and synchronous rectifiers. It features an Advanced Constant On-Time (ACOTTM) control architecture that provides stable operation for ceramic output capacitors without complicated external compensation, a mong other benefits. The input voltage range is from 5V to 23V, and the output voltage is fixed 5V .

The proprietary ACOTTM control scheme improves conventional constant on-time architectures, achieving nearly constant switching frequency over line, loa d, and output voltage ranges. Since there is no internal clock, response to tran sients is nearly instantaneous a nd inductor current can ramp quickly to maintain output regulation without large bulk output ca pacita nce.

ACOT

Control Architecture

In order to achieve good stability with low-ESR ceramic capa citors, ACOTTM uses a virtual inductor current ra mp generated inside the IC. This internal ra mp signal repla ces the ESR ramp normally provided by the output ca pa citor's ESR. The ra mp signal a nd other internal compensation s are optimized for low-ESR cera mic output capacitors.

Making the on-time proportional to V

and inversely

OUT

proportional to VIN is not sufficient to achieve good constant-frequency behavior for several reasons. First, voltage drops across the MOSFET switches a nd inductor cause the effective input voltage to be less than the mea sured input voltage and the effective output voltage to be greater than the measured output voltage as sensing input and output voltage. When the load changes, the switch voltage drops change causing a switching frequency variation with load current. Also, at light loa ds if the inductor current goes negative, the switch deadtime between the synchronous rectifier turn-off and the high-side switch turn-on allows the switching node to rise to the input voltage. This increases the effective on-ti me and causes the switching frequency to drop noticea bly.

One way to reduce these effects is to mea sure the a ctual switching frequency and compare it to the desired ra nge. This has the a dded benefit eliminating the need to sens e

the actual output voltage, potentially saving one pin connection. The ACOTTM uses this method, measuring the actual switching frequency a nd modifying the on-time with a feedback loop to keep the average switching frequency in the desired range.

ACOTTM One-shot Operation

The RT7291A/B control algorithm is simple to understa nd. The feedback voltage, with the virtual inductor current ra mp added, is compared to the reference voltage. When the combined signal is less than the reference, the on-time one-shot is triggered, as long as the minimum off-time one-shot is clear and the measured inductor current (through the synchronous rectifier) is below the current limit. The on-time one-shot turns on the high-side switch and the inductor current ramps up linearly. After the ontime, the high-side switch is turned off a nd the synchronous rectifier is turned on and the inductor current ra mps down linearly . At the sa me time, the mini mum off-time one-shot is triggered to prevent another immedi ate on-time during the noisy switching time and allow the feedback voltage and current sense signals to settle. The minimum off-time is kept short (200ns typical) so that ra pidly-repeated ontimes ca n raise the inductor current quickly when needed.

Diode Emulation Mode

In diode emulation mode, the RT7291A/B automatically reduces switching frequency at light load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly . As the output current decrea ses from heavy load conditions, the inductor current is also reduced, and eventually comes to the point that its current valley touches zero, which is the boundary between continuous conduction and discontinuous conduction modes. To emulate the behavior of diodes, the low-side MOSFET allows only partial negative current to flow when the inductor free wheeling current becomes negative. As the load current is further decrea sed, it takes longer a nd longer time to discharge the output capacitor to the level that requires the next “ON” cycle. In reverse, when the output current increases from light load to heavy load, the switching frequency increa ses to the preset value as the

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RT7291A/B

inductor current reaches the continuous conduction. The transition load point to the light loa d operation is shown in Figure 2 and ca n be calculated as follows :

Slope = (VIN- V

OUT

) / L

PEAK

LOAD

= I

/ 2

PEAK

Figure 2. Boundary Condition of CCM/DEM

(V V )



LOAD ON

IN OUT



where tON is the on-time. The switching waveforms may appear noisy and

asynchronous when light load causes diode emulation operation. This is normal and results in high efficiency. Trade of fs in DEM noise vs. light load eff iciency is mad e by varying the inductor value. Generally , low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full load efficiency (assuming that the coil resistance remains fixed) a nd less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load tra nsient response (especially at low input voltage levels).

During discontinuous switching, the on-time is immediately increa sed to add “hysteresis” to discourage the IC from switching back to continuous switching unless the load increases substantially. The IC returns to continuous switching as soon as an on-time is generated before the inductor current reaches zero. The on-ti me is reduced back to the length needed for 500kHz switching and encouraging the circuit to remain in continuous conduction, preventing repetitive mode transition s between continuous switching and discontinuous switching.

Linear Regulators (LDO & VCC)

The RT7291A/B includes a 5V linear regulator (LDO). The LDO regulator can supply up to 100mA for external loads. Bypass LDO with a minimum 4.7μF ceramic capacitor.

When VOUT is powered on and PGOOD is pulled high, an internal 3Ω P-MOSFET switch connects V

OUT

to the LDO pin while the internal linear regulator is simulta neously turned off.

The RT7291A/B also includes a 5V linear regulator (VCC). The VCC regulator steps down input voltage to supply both internal circuitry and gate drivers. Do not connect the VCC pin to external loads. When PGOOD is pulled high and BYP pin voltage is above 4.6V, an internal 3Ω P-MOSFET switch connects VCC to the BYP pin while the VCC linear regulator is simulta neously turned off.

Current Limit

The RT7291A/B current limit is a cycle-by-cycle “valley” type, measuring the inductor current through the synchronous rectifier during the off-time while the inductor current ramps down. The current is determined by mea suring the voltage between Source and Drain of the synchronous rectifier, a dding temperature compensation for greater accuracy. If the current exceeds the current limit, the on-time one-shot is inhibited until the inductor current ramps down below the current limit. Thus, only when the inductor current is well below the current limit, another on-time is permitted. If the output current exceeds the available inductor current (controlled by the current limit mechanism), the output voltage will drop. If it drops below the output under-voltage protection level (see next section), the IC will stop switching to avoid excessive heat.

The RT7291A/B also features a negative current limit to protect the IC against sinking excessive current and possibly damage. If the voltage across the synchronous rectifier indicates the negative current is too high, the synchronous rectifier turns off.

Output Over-Voltage Protection and Under-Voltage Protection

The RT7291A/B features an output Over-V oltage Protection (OVP). If the output voltage rises above the regulation level, the IC stops switching and is latched off. The RT7291A/B also features an output Under-Voltage Protection (UVP). If the output voltage drops below the UVP trip threshold for longer tha n 2μs (typical), the UVP

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RT7291A/B

is triggered, and the IC will shut down. The IC stops switching and is latched off. To restart operation, toggle EN or power the IC of f and then on again.

Input Under-Voltage Lockout

In addition to the enable function, the RT7291A/B features an U nder-V oltage Lockout (UVLO) function that monitors the input voltage. To prevent operation without fullyenhanced internal MOSFET switche s, this function inhibits switching when input voltage drops below the UVLO-falling threshold. The IC resumes switching when input voltage exceeds the UVLO-rising threshold.

Over-Temperature Protection

The RT7291A/B features an Over-Temperature Protection (OTP) circuitry to prevent overheating due to excessive power dissipation. The OTP shuts down switching operation when the junction temperature exceeds 150°C. Once the junction temperature cools down by approxi mately 25°C the IC resumes normal operation with a complete soft-start. For continuous operation, provide adequate cooling so that the junction temperature does not exceed 150°C. Note that the VCC a nd LDO regulator remains on a s the OTP is triggered.

Enable and Disable

The enable input (EN) ha s a logic-low level of 1.15V . When VEN is below this level, the IC enters shutdown mode and supply current drops to less than 5μA (typical). When VEN exceeds its logic-high level of 1.35V, the IC is fully operational. The logics of EN and ENLDO to control the V

, CLK, LDO and VCC are stated in Table 1.

OUT

Soft-Start

The RT7291A/B provides an internal soft-start function to prevent large inrush current and output voltage overshoot when the converter starts up. The soft-start (SS) automatically begins once the chip is enabled. During softstart, it clamps the ra mp of internal reference voltage which is compared with FB signal. The typical soft-start duration is 1.5ms.

Power Off

When VEN is pulled to GND or lower than the logic-low level of 1.15V , there is a n intern al discharging resistor to discharge the residual charge inside the output ca pacitors. Besides, the value of discharging resistor is about twenty ohms.

Power Good Output (PGOOD)

The power good output is an open-drain output that requires a pull-up resistor. When the output voltage is 20% (typical) below its set voltage, PGOOD will be pulled low . It is held low until the output voltage returns to 90% of its set voltage once more. During soft-start, PGOOD is actively held low and only allowed to be pulled high after soft-start is over and the output rea ches 90% of its set voltage. There is a 2μs delay built into PGOOD circuitry to prevent false transition.

External Bootstra p Ca pacitor (C

BOOT

)

Connect a 0.22μF low ESR ceramic capacitor between the BOOT and SW pin s. This bootstrap ca pa citor provides the gate driver supply voltage for the high-side N-MOSFET switch.

T able 1. EN/ENLDO Control Logics

EN ENLDO VOUT/CLK LDO VCC

The internal power MOSFET switch gate driver is optimized to turn the switch on fa st enough for low power loss and good efficiency , a nd slow enough to reduce EMI.

1 1 ON ON ON 1 0 ON ON ON 0 1 OFF ON ON 0 0 OFF OFF OFF

Switch turn-on is when most EMI occurs since VSW rises rapidly . During switch turn-off, SW is discharged relatively slowly by the inductor current during the dead-time between high-side and low-side switch on-time s. In some cas es it is desirable to reduce EMI further , at the expense of some additional power dissipation. The switch turn-on can be slowed by placing a small (<10Ω) resistance between BOOT and the external bootstra p ca pacitor . This will slow the high-side switch turn-on and VSW's rise.

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RT7291A/B

Inductor Selection

Selecting an inductor involves specifying its inductance and also its required pea k current. The exact inductor value is generally flexible and is ultimately chosen to obtain the best mix of cost, physical size, and circuit efficiency. Lower inductor values benefit from reduced size and cost and they can improve the circuit's transient response. However, they increase the inductor ripple current and output voltage ripple and reduce the ef ficiency due to the resulting higher peak currents. Conversely , higher inductor values increa se ef f iciency, but the inductor will either be physically larger or have higher resistance since more turns of wire are required and transient response will be slower since more time is required to change current (up or down) in the inductor. A good compromise between size, efficiency, and tra n sient respon se is to use a ri pple current (ΔIL) about 20-50% of the desired full output load current. Calculate the approximate inductor value by selecting the input and output voltages, the switching frequency (fSW), the maximum output current (I

OUT(MAX)

and estimating a ΔIL as some percentage of that current.

V(VV)



OUT IN OUT



Vf I



IN SW L

Once an inductor value is chosen, the ripple current (ΔIL) is calculated to determine the required peak inductor current.

V(VV)

L L(PEAK) OUT(MAX)

Vf L 2



IN SW



OUT IN OUT

I and I I

  



To guarantee the required output current, the inductor needs a saturation current rating and a thermal rating that exceeds I

. These are minimum requirements. To

L(PEAK)

maintain control of inductor current in overload and shortcircuit conditions, some applications may desire current ratings up to the current limit value. However, the IC's output under-voltage shutdown feature make this unnecessary for most a pplication s.

For best efficiency, choose an inductor with a low DC resistance that meets the cost and size requirements. For low inductor core losses some type of ferrite core is usually best and a shielded core type, although possibly larger or more expensive, it will probably give fewer EMI and other noise problems.

Input Capacitor Selection

High quality ceramic in put decoupling capacitor, such a s X5R or X7R, with values greater than 20μF are recommended for the input ca pa citor. The X5R a nd X7R ceramic ca pa citors are usually selected for power regulator capacitors because the dielectric material has less capacitance variation and more temperature stability. V oltage rating a nd current rating are the key parameters when selecting an input ca pa citor. Generally , selecting a n input ca pa citor with voltage rating 1.5 ti mes greater tha n the maximum input voltage is a conservatively safe design. The input capacitor is used to supply the input RMS current, which can be a pproximately calculated using the following equation :

I(1)I

RMS OUT





OUT OUT



VV 12

IN IN





The next step is to select a proper capacitor for RMS current rating. One good design uses more than one ca pacitor with low Equivalent Series Resistance (ESR) in

)

parallel to form a capacitor bank. The input capacitance value determines the input ripple voltage of the regulator . The input voltage ripple can be a pproxi mately calculated using the following equation :

IV V



V(1)

 

OUT IN OUT

Cf V V



IN SW O UT IN

The typical operating circuit is recommended to use two

10μF low ESR ceramic capa citors on the input.

Output Capacitor Selection

The RT7291A/B is optimized for cera mic output ca pacitors and best performa nce will be obtained by using them. The total output capacitance value is usually determined by the desired output voltage ripple level and tra nsient response requirements for sag (undershoot on positive load steps) and soar (overshoot on negative load steps).

Output ripple at the switching frequency is caused by the inductor current ripple and its effect on the output capacitor's ESR and stored charge. These two ripple components are called ESR ripple and capacitive ripple. Since ceramic capacitors have extremely low ESR and relatively little cap a cita nce, both components are similar in amplitude and both should be considered if ripple is critical.

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RT7291A/B

VV V

RIPPLE RIPPLE(ESR) RIPPLE(C)

VIR

RIPPLE(ESR) L ESR

RIPPLE(C)



 





8C f



OUT SW

In addition to voltage ripple at the switching frequency, the output capacitor and its ESR also affect the voltage sag (undershoot) and soar (overshoot) when the load steps up and down abruptly. The ACOT transient response is very quick and output transients are usually small. However, the combination of small ceramic output capacitors (with little capacitance), low output voltages (with little stored charge in the output capacitors), and low duty cycle applications (which require high inducta nce to get rea sonable ripple currents with high input voltages) increases the size of voltage variations in response to very quick load changes. Typically, load changes occur slowly with respect to the IC's 500kHz switching frequency . However, some modern digital loads can exhibit nearly instantaneous load changes and the following section shows how to calculate the worst-case voltage swings in response to very fa st load steps.

The amplitude of the ESR step up or down is a function of the load step and the ESR of the output capa citor :

VIR 

ESR_STEP OUT ESR

The amplitude of the capacitive sag is a function of the load step, the output ca pa citor value, the inductor value, the input-to-output voltage differential, a nd the maximum duty cycle. The maximum duty cycle during a fa st tran sient is a function of the on-time and the mini mum off-time since the ACOTTM control scheme will ramp the current using on-times spaced apart with minimum off-times, which is as fast as allowed. Calculate the approximate on-time (neglecting parasitics) a nd maximum duty cycle for a given input and output voltage a s :

t and D

ON MAX

OUT ON



Vf t t



IN SW ON OFF(MIN)

The actual on-time will be slightly longer as the IC compensates for voltage drops in the circuit, but we can neglect both of these since the on-time increases compensations for the voltage losses. Calculate the output voltage sag as :

()



SAG

2C V D V

 

OUT IN(MIN) MAX OUT



()

OUT

The amplitude of the capacitive soar is a function of the load step, the output capacitor value, the inductor value and the output voltage :

SOAR

()





2C V



OUT OUT

OUT

Most applications never experience in stantaneous full loa d steps and the RT7291A/B's high switching frequency a nd fast tra nsient response can e asily control voltage regulation at all times. Therefore, sag a nd soar are seldom an issue except in very low-voltage CPU core or DDR memory supply application s, particularly for devices with high clock frequencies and quick changes into and out of sleep modes. In such application s, simply increa sing the amount of ceramic output capacitor (sag and soar are directly proportional to capacitance) or adding extra bulk capacitance can easily eliminate any excessive voltage transients.

In any application with large quick transients, it should calculate soar and sag to make sure that over-voltage protection and under-voltage protection will not be triggered.

Thermal Considerations

For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and a mbient temperature. The maximum power dissipation can be calculated by the following formula :

P where T

the ambient temperature, a nd θ

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

is the maximum junction temperature, TA is

is the junction to ambient

thermal resistance. For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to ambient thermal re sistance, θJA, is layout dependent. For UQF N-16L 3x3 (FC) pa ckage, the thermal resistance, θJA, is 70°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following f ormula :

= (125°C − 25°C) / (70°C/W) = 1.4W for

D(MAX)

UQF N-16L 3x3 (FC) pa ckage

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RT7291A/B

The maximum power dissipation depends on the operating ambient temperature for fixed T

and thermal

J(MAX)

resistance, θJA. The derating curve in Figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.

2.0

Four-Layer PCB

1.6

1.2

0.8

0.4

Maximum Power Dissipation (W) 1

0.0 0 25 50 75 100 125

Ambient Tempera ture (°C)

Figure 3. Derating Curve of Maxi mum Power Dissi pation

Layout Considerations

Layout is very important in high frequency switching converter design. The PCB can ra diate excessive noise and contribute to converter insta bility with improper layout. Certain points must be considered before starting a layout using the RT7291A/B.

 Make tra ces of the main current paths a s short and wide

as possible.

 Put the input capa citor a s close a s possible to the device

pins (VIN a nd PGND).

 SW node encounters high frequency voltage swings so

it should be kept in a small area. Keep sensitive components away from the SW node to prevent stray .

 The PGND pin should be connected to a strong ground

plane for heat sinking a nd noise protection.

 Avoid using via s in the power path connections that have

switched currents (from CIN to PGND and CIN to VIN) and the switching node (SW).

VIN

The input capacitor must be placed as close to the IC as possible.

VIN

PGND

GND

Impedance between PGND and AGND should be as small as possible for unified ground voltage.

GND

AGND

1 4

ENLDO

1 3

34567

VBYP

CLK

PGOOD

Figure 4. Layout Guide

VCC

BOOT

1 0

BOOT

The output capacitor must be placed near the IC

OUT

SW should be connected to inductor by wide and short

LDO

VOUT

LDO

trace.

OUT

Keep sensitive components away from this trace.

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Outline Dimension

RT7291A/B

Symbol

A 0.500 0.600 0.020 0.024 A1 0.000 0.050 0.000 0.002 A3 0.100 0.175 0.004 0.007

D 2.900 3.100 0.114 0.122

E 2.900 3.100 0.114 0.122

b 0.150 0.250 0.006 0.010

b1 0.100 0.200 0.004 0.008

L 0.350 0.450 0.014 0.018 L1 0.750 0.850 0.030 0.033 L2 0.550 0.650 0.022 0.026

K K1 K2 K3

Dimensions In Millimeters Dimensions In Inches

Min. Max. Min. Max.

0.400 0.016

0.975 0.038

1.335 0.053

1.675 0.066

1.935 0.076 K4 K5

0.975 0.038

1.675 0.066

U-Type 16L QFN 3x3 (FC) Package

DS7291A/B-02 September 2015 www.richtek.com

RT7291A/B

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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Richtek RT7291AGQUF, RT7291BGQUF Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual