Richtek R7735AGE, R7735AGN, R7735GGE, R7735GGN, R7735HGE Schematics

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High Performance Enhanced Quadruple Mode PWM Flyback Controller

R7735

General Description

R7735 series is the successor of R7732/3 and fully

compatible with most of SOT-23-6 / DIP-8 product so far

in the market. It has enhanced quadruple mode PWM

controller and owns excellent green power performance,

especially under light load and no load conditions. It

focuses on "easy to design" in different applications and

it will save both design effort and external components.

Besides the general features shown in the Features

section, R7735 covers wide protection options, such as

internal Over Load Protection (OLP) and Over Voltage

Protection (OVP) to eliminate the external protection

circuits. Moreover, it also features Secondary Rectifier

Short Protection (SRSP) and CS pin open protection. This

protection will make the PSU design for reliability and

safety easier.

R7735 is designed for power supply such as NB adaptor

which is a very cost effective and compact design. The

precise external OVP and Over Temperature Protection

(OTP) can be implemented by very simple circuit. The

start-up resistors can also be replaced by bleeding

resistors to save power loss and component count.

Features

z No Load Input Power Under 100mW

z Accurate Over Load Protection

z UVLO 9V/14V

z Soft Start Function

z Current Mode Control

z Built-in Slope Compensation

z Internal Leading Edge Blanking

z PWM Quadruple Mode for Green-Mode

z Excellent Green Power Performance

z Cycle-by-Cycle Current Limit

z Internal Over Voltage Protection

z Secondary Rectifier Short Protection

z Opto-Coupler Short Protection

z Feedback Open-Loop Protection

z CS Pin Open Protection

z Built-in Jittering Frequency

z Built-in PRO Pin for External Arbitrary OVP/OTP

z Soft Driving for EMI Noise

z High Noise Immunity

z RoHS Compliant and Halogen Free

Application

z Switching AC/DC Adaptor

Ordering Information

R7735

(B)* (* : See Version Table)

Package Type E : SOT-23-6 N : DIP-8 (R7735G Only)

Lead Plating System

z DVD Open Frame Power Supply

z Set-T op Box (STB)

z ATX Standby Power

z TV/Monitor Standby Power

z PC Peripherals

z NB Adaptor

G : Green (Halogen Free and Pb Free)

R7735 Version (Refer to Version Table)

Note :

Richtek products are :

` RoHS compliant and compatible with the current

requirements of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

R7735-03 September 2012 www.richtek.com

Marking Information

For marking information, contact our sales representative

directly or through a Richtek distributor located in your

area.

R7735

Pin Configurations

(TOP VIEW)

GND

COMP

GATE

VDD CS

GND

SOT-23-6

COMP

PRO

GATE

DIP-8

R7735 Version Table

Version R7735G R7735R R7735L R7735A R7735H

Frequency 65kHz 65kHz 65kHz 65kHz 100kHz

OLP Delay Time 56ms 56ms 56ms 28ms 36ms

Internal OVP(27V) Auto Recovery Auto Recovery Latch Latch Auto Recovery

OLP & SRSP Auto Recovery Auto Recovery Auto Recovery Latc h Auto Recovery

PRO Pin High Latch Auto Recovery Latc h Latch Auto Recover y

PRO Pin Low Auto Recovery Latch Latch Latch Latch

* : V

R7735XGE : V

R7735HGE(B) : V

: Secondary Rectifier Short Protection (SRSP) triggered threshold.

SRSP_TH

= 1.7V, X = G/R/L/A

SRSP_TH

= 2.6V

SRSP_TH

NCVDD

PRO

678

Typical Application Circuit

AC Mains (90V to 265V)

PRO

COMP

NTC

VDD

R7735

GND

GATE

# : See Application Information

Vo+

Vo-

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R7735-03 September 2012

Functional Pin Description

R7735

Pin No.

Pin Name Pin Function

SOT-23-6 DIP-8

1 8 GND Ground.

2 7 COMP

Voltage Feedback. By connecting an opto-coupler to close control loop and achieve the regulation.

3 5 PRO For External Arbitrary OVP or OTP.

4 4 CS Primary Current Sense.

5 2 VDD Power Supply.

6 1 GATE Gate Drive Output to Drive the External MOSFET.

-- 3, 6 NC No Internal Connection.

Function Block Diagram

L_TH

PRO

BIAS

SRSP_TH

H_TH

Secondary Rectifier Short & CS Open Protection

Brownout

Sensing

COMP Open

Sensing

OLP

Auto

Recovery

Latch

Auto

Recovery

Latch

POR

Shutdown

Logic

Counter

Oscillator

OVP

UVLO

Bias &

Bandgap

VDD

27V

9V/14V

PWM

Dmax

Quadruple Mode

Soft Driver

COMP

BURL

BURH

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Constant

Power

COMP

LEB

Slope Ramp

Comparator

R7735-03 September 2012

GATE

GND

R7735

Absolute Maximum Ratings (Note 1)

z Supply Input Voltage, VDD ----------------------------------------------------------------------------------------------- −0.3V to 30V

z GATE Pin--------------------------------------------------------------------------------------------------------------------- −0.3V to 16.5V

z PRO, COMP, CS Pin ------------------------------------------------------------------------------------------------------ −0.3V to 6.5V

z I

------------------------------------------------------------------------------------------------------------------------------ 10mA

z Power Dissipation, P

SOT-23-6 -------------------------------------------------------------------------------------------------------------------- 0.400W

DIP-8-------------------------------------------------------------------------------------------------------------------------- 0.714W

z Package Thermal Resistance (Note 2)

SOT-23-6, θJA--------------------------------------------------------------------------------------------------------------- 250°C/W

DIP-8, θJA-------------------------------------------------------------------------------------------------------------------- 140°C/W

z Junction Temperature ------------------------------------------------------------------------------------------------------ 150°C

z Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------- 260°C

z Storage Temperature Range --------------------------------------------------------------------------------------------- −65°C to 150°C

z ESD Susceptibility (Note 3)

HBM (Human Body Model)----------------------------------------------------------------------------------------------- 3kV

MM (Machine Model) ------------------------------------------------------------------------------------------------------ 250V

@ TA = 25°C

Recommended Operating Conditions (Note 4)

z Supply Input Voltage, VDD ----------------------------------------------------------------------------------------------- 12V to 25V

z Junction Temperature Range --------------------------------------------------------------------------------------------- −40°C to 125°C

z Ambient Temperature Range --------------------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics

= 15V, T

VDD Section

VDD Over Voltage Protection Level V

VDD Zener Clamp VZ 29 -- -- V

On Threshold Voltage V

Off Threshold Voltage V

VDD Holdup Mode Entry Point V

VDD Holdup Mode Ending Point V

Latch-off Voltage VLH 4.5 5.5 6.5 V

Latched Reset Voltage V

Start-up Current I

Oper ating Supply Current I

= 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

26 27 28 V

OVP

13 14 15 V

TH_ON

TH_OFF

DD_LOW

DD_HIGH

LH_RST

DD_ST

DD_OP

8.5 9 9.5 V

< 1.6V 9.5 10 10.5 V

COMP

< 1.6V 10 10.5 11 V

COMP

4 5 6 V

= −40ºC to 100ºC (Note 5)

GATE pin open

= V

TH_ON –

= 15V, V

COMP

0.2V,

= 2.5V,

1 5 10 μA

0.55 0.9 1.6 mA

Latch-off Operating Current I

TA= −40ºC to 100ºC (Note 5) 2 -- 8 μA

DD_LH

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R7735-03 September 2012

Parameter Symbol Test Conditions Min Typ Max Unit

Oscillator Section

R7735

Normal PWM Frequency f

Frequency Reduction Mode

Minimum Frequency

Maximum Duty Cycle DCY

OSC

FR_MIN

R7735H 92 100 108

R7735G/R/L/A 18 22 -R7735H -- 25 --

70 75 80 %

MAX

kHz

PWM Frequency Jitter Range Δf -- ±6 -- %

R7735G/R/L/A 60 65 70

PWM Frequency Jitter Period T

Frequency Variation Versus V

Deviation

Frequency Variation Versus Temperature Deviation

For 65kHz -- 4 -- ms

JIT

= 12V to 25V -- -- 2 %

= −30°C to 105°C

(Note 5)

-- -- 5 %

COMP In put Section

Open-Loop Voltage V

COMP_OP

COMP pin Open 5.5 5.75 6 V

R7735G/R/L 45 56 65 COMP Open-Loop Protection Delay Time

OLP

R7735A 22 28 34

R7735H 30 36 42

Short Circuit Current I

Frequency Reduction Mode Entry Voltage

Frequency Reduction Mode Ending Voltage

ZERO

2.85 3 3.15 V

FR_ET

FR_ED

= 0V 0.15 0.29 0.45 mA

COMP

R7735G/R/L/A 2.75 2.9 3.05

R7735H 2.65 2.8 2.95

Current Sense Section

Initial Peak Current Limitation Offset

Maximum Clamping Current Limit V

Leading Edge Blanking Time t

0.68 0.7 0.72 V

CS_TH

CS(MAX)

LEB

1.05 1.1 1.15 V

(Note 6) 150 250 350 ns

Internal Propagation Delay Time tPD (Note 6) -- 100 -- ns

Minimum On Time t

ON(MIN)

250 350 450 ns

GATE Section

Rising Time tR V

Falling Time tF V

GATE Output Clamping Voltage V

VDD= 25V 12.1 14 15.9 V

CLAMP

= 15V, CL= 1nF 60 125 140 ns

= 15V, CL= 1nF 25 40 65 ns

PRO Interface Section

Pull Low Threshold V

Pull High Threshold V

Internal Bias Current I

Pull High Sinking Current I

R7735-03 September 2012

0.47 0.5 0.53 V

L_TH

3.5 3.8 4.1 V

H_TH

90 100 110 μA

BIAS

(Note 7) 0.7 -- 1.4 mA

SINK

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R7735

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect

device reliability.

Note 2. θ

is measured at T

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design. Note 6. Leading edge blanking time and internal propagation delay time are guaranteed by design. Note 7. The sourcing current of PRO pin must be limited below 5mA. Otherwise it may cause permanent damage to the

device.

= 25°C on a low effective thermal conductivity single-layer test board per JEDEC 51-3.

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R7735-03 September 2012

Typical Operating Characteristics

vs. V

DD_ST

R7735

vs. Temperature

DD_ST

(µA)

DD_ST

03691215

VDD (V)

vs. V

(kHz)

OSC

R7735G/R/L/A

(µA)

DD_ST

-50 -25 0 25 50 75 100 125

Temperature (°C)

vs. Te m pe rature

(kHz)

OSC

R7735G/R/L/A

OSC

10 13 16 19 22 25

VDD (V)

vs. V

104

R7735H

102

100

(kHz)

OSC

10 13 16 19 22 25

OSC

VDD (V)

R7735-03 September 2012

-50 -25 0 25 50 75 100 125

Temperature (°C)

vs. Temperature

104

102

100

R7735H

OSC

(kHz)

OSC

-50 -25 0 25 50 75 100 125

Temperature (°C)

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R7735

vs. Temperature

TH_ON

(V)

TH_ON

-50 -25 0 25 50 75 100 125

Temperature (°C)

vs. Temperature

FR_MIN

10.0

9.5

TH_OFF

vs. Temperature

(V)

9.0

TH_OFF

8.5

8.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

1.05

0.95

= 15V,

= 2.5V,

COMP

GATE Pin Open

vs. Temperature

DD_OP

(kHz)

FR_MIN

-50 -25 0 25 50 75 100 125

Temperature (°C)

6.0

5.8

COMP_OP

vs. Temperature

(V)

5.6

COMP_OP

5.4

(mA)

0.85

DD_OP

0.75

0.65

-50-250 255075100125

Temperature (°C)

vs. Temperature

(V)

OVP

5.2

-50 -25 0 25 50 75 100 125

Temperature (°C)

www.richtek.com

-50-250 255075100125

Temperature (°C)

R7735-03 September 2012

R7735G/R/L

vs. Temperature

OLP

R7735A

vs. Temperature

OLP

R7735

(ms)

OLP

-50 -25 0 25 50 75 100 125

Temperature (°C)

vs. Temperature

R7735H

(ms)

OLP

(ms)

OLP

-50 -25 0 25 50 75 100 125

Temperature (°C)

0.80

0.75

vs. Temperature

CS_TH

(V)

0.70

CS_TH

-50 -25 0 25 50 75 100 125

Temperature (°C)

vs. Temperature

DD_LH

(µA)

DD_LH

-50 -25 0 25 50 75 100 125

Temperature (°C)

0.65

0.60

-50 -25 0 25 50 75 100 125

Temperature (°C)

vs. Temperature

110

100

(µA)

BIAS

-50 -25 0 25 50 75 100 125

BIAS

Temperature (°C)

R7735-03 September 2012

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R7735

vs. Temperature

H_TH

0.60

vs. Temperature

L_TH

(V)

H_TH

-50 -25 0 25 50 75 100 125

Temperature (°C)

TR vs. Temperature

140

130

120

(ns)

0.55

(V)

0.50

L_TH

0.45

0.40

-50-250 255075100125

Temperature (°C)

TF vs. Temperature

(ns)

110

100

-50 -25 0 25 50 75 100 125

Temperature (°C)

vs. Temperature

CLAMP

(V)

CLAMP

-50 -25 0 25 50 75 100 125

Temperature (°C)

-50 -25 0 25 50 75 100 125

Temperature (°C)

DCY

vs. Temperature

MAX

(%)

MAX

DCY

-50 -25 0 25 50 75 100 125

Temperature (°C)

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R7735-03 September 2012

Application Information

R7735

PWM Quadruple Mode

R7735 has enhanced quadruple mode PWM controller and

owns excellent green power performance, especially under

light load and no load conditions. Please refer Figure 1 for

details.

: To enhance light load efficiency, the feedback resistor

loss is reduced. Due to small feedback resistor current,

shunt regulator selection and minimum regulation current

design must be careful to make sure it's able to regulate

under low cathode current.

PWM Mode

For most of load, the circuit will run at traditional PWM

current mode.

Frequency Reduction Mode

he frequency reduction mode function provides linear

switching frequency reduction according to load

conditions, as shown in Figure 2. When the feedback

voltage of COMP pin is lower than V

, the switching

FR_ET

frequency starts to decrease. When the power supply is

at light-load and the feedback voltage of COMP pin lower

than V

, the switching frequency is clamped at f

FR_ED

FR_MIN

This frequency reduction mode function reduces power

consumption under light-load and no-load conditions, and

easily meets even the strictest regulations.

Frequency

OSC

FR_MIN

FR_ED

FR_ET

Figure 2. PWM Frequency vs. COMP Voltage

Burst Mode

During light load, switching loss will dominate the power

efficiency calculation. This mode is to cut switching loss.

As shown in Figure 1, when the output load gets light,

feedback signal drops and touches V

. PWM signal

BURL

will be blanked and system ceases to switch. After V

drops and feedback signal goes back to V

will be resumed.

BURH

COMP

OUT

, switching

VDD

Holdup Mode

DD_HIGH

DD_LOW

GATE

Load

VDD

COMP

BURH

BURL

Normal

Operation

Frequency

Reduction Mode

Burst Mode

Figure 1. PWM Quadruple Mode

R7735-03 September 2012

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R7735

V DD Holdup Mode

Under light load or load transient moment, feedback signal

will drop and touch V

. Then PWM signal will be

BURL

blanked and system ceases to switch. VDD could drop

down to turn off threshold voltage. To avoid this, when V

drops to a setting threshold, 10V, the hysteresis

comparator will bypass PWM and burst mode loop and

forces switching at a very low level to supply energy to

VDD pin. VDD holdup mode was also improved to hold up

VDD by less switching cycles. This mode is very useful in

reducing start-up resistor loss while still get start-up time

in spec. It's not likely for VDD to touch UVLO turn off

threshold during any light load condition. This will also

makes bias winding design and transient design easier.

Furthermore, VDD holdup mode is only designed to prevent

VDD from touching turn off threshold voltage under light

load or load transient moment. Relative to burst mode,

switching loss will increase on the system at VDD holdup

mode, so it is highly recommended that the system should

avoid operating at this mode during light load or no load

condition, normally.

Start-up Circuit

To minimize power loss, it's recommended that the start-

up current is from bleeding resistor. It's not only good for

power saving but also could reset latch mode protection

quickly. Figure 3 shows I

DD_Avg

vs. R

Bleeding

curve. User

can apply this curve to design the adequate bleeding

resistor.

Gate Driver

A totem pole gate driver is fine tuned to meet both EMI

and efficiency requirement in low power application. An

internal pull low circuit is activated after pretty low VDD to

prevent external MOSFET from accidentally turning on

during UVLO.

Oscillator

To guarantee precise frequency, it's trimmed to 5%

tolerance. It also generates slope compensation saw-tooth,

75% maximum duty cycle pulse and overload protection

slope. It can typically operate at built-in 65kHz center

frequency and features frequency jittering function. Its

jittering depth is 6% with about 4ms envelope frequency

at 65kHz.

DD_Avg

(μA)

DD_Avg

90Vac

85Vac

80Vac

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

Bleeding

vs. R

Bleeding

Curve

Curve (MΩ)

Figure 3. I

DD_Avg

vs. R

Bleeding

Curve

DD_Avg

www.richtek.com 12

R7735-03 September 2012

Tight Current Limit Tolerance

Since R7735 is the successor of R7732/3, its current limit

setting is completely the same as R7732/3. Generally,

the saw current limit applied to low cost Flyback controller

because of simple design. However, saw current limit is

hard to test in mass production. Therefore, it's generally

"guaranteed by design". The variation of process and

package will make its tolerance wider. It will lead to 20%

to 30% variation when doing OLP test at certain line

voltage. This will cause yield loss in power supply mass

production. Through well foundry control, design and test

/ trim mode in final test, R7735 current limit tolerance is

tight enough to make design easier.

PRO

BIAS

PRO

H_TH

L_TH

H_TH

L_TH

Auto Recovery / Latch

Normal Operating

Auto Recovery / Latch

Deglitch

30µs

Deglitch

50µs

R7735

Auto

Recovery

Latch

PRO Pin Application

R7735 features a PRO pin, as shown in Figure 4, and it

can be applied for external arbitrary OVP or OTP (ex :

Figure 5 to Figure 8).

If the voltage of PRO pin is greater than pull-low threshold

, the controller is enabled and switching will occur. If

L_TH

the voltage of PRO pin falls below pull-low threshold or

rises to pull-high threshold V

, the controller will be

H_TH

shut down and cease to switch after deglitch delay.

PRO pin is built in 1.5V internally, so leave PRO pin open

if you don't need this function. If designer needs to apply

a bypass capacitor on PRO pin, it should not be more

than 1nF. The internal bias current of PRO pin is 100μA

(typ.). R7735 has internal OVP. For arbitrary OVP or OTP

applications which behave as auto recovery or latch, it

can get these by PRO pin. For PRO pin pulling high

function applications, the voltage of PRO pin must rise

above V

(The supply current of PRO pin must be

H_TH

greater than 1.4mA and be limited below 5mA.). When IC

enters latch mode, the IC maximum operating current is

8μA (100°C), and it will be release until VDD is fallen to

TH_OFF

Figure 4. PRO Pin Diagram

VDD

PRO

(Option)

VDD OVP : VDD > VR + VZ + 3.8V

Figure 5. For VDD OVP Only

PRO

(Option)

NTC

PRO pin is guaranteed that below: If the voltage of PRO

pin reaches 4.1V or falls below 0.47V, the system will be

Figure 6. For OTP Only

protected.

R7735-03 September 2012

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R7735

VDD

PRO

(Option)

Figure 7. For VDD OVP

PRO

(Option)

Figure 8. For V

Vo+

OUT

(Option)

OVP

Soft-Start

During initial power on, especially at high line, current

spike is kind of unlimited by current limit. Therefore,

besides cycle-by-cycle current limiting, R7735 still

provides soft start function. It effectively suppresses the

stat-up current spike. The typical soft start duration is

about 40 clock cycles. This will provide more reliable

operation and possibility to use smaller current rating power

MOSFET.

Protection

R7735 provide fruitful protection functions that intend to

protect system from being damaged. All the protection

functions can be listed as below:

` Cycle-by-Cycle Current Limit

This is a basic but very useful function and it can be

implemented easily in current mode controller.

` Over Load Protection

Long time cycle-by-cycle current limit will lead to system

thermal stress. To further protect system, system will

be shut down after 56ms (R7735A: 28ms; R7735H:

36ms).

Through our proprietary prolong turn off period during

hiccup(R7735A: latch), the power loss and thermal

during OLP will be averaged to an acceptable level over

the ON/OFF cycle of the IC. This will last until fault is

removed.

` Brownout Protection

During heavy load, this will trigger 56ms(R7735A: 28ms;

R7735H: 36ms) protection and shut down the system.

If it is in light load condition, system will be shut down

after VDD is running low and triggers UVLO.

` CS Pin Open Protection

When CS pin is opened, the system will be shut down

after couples of cycle. It could pass CS pin open test

easier.

` Over Voltage Protection

Output voltage can be roughly sensed by VDD pin. If

the sensed voltage reaches 27V threshold, system will

be shut down and hiccup after 20μs deglitch delay for

R7735G/R/H or latch after 70μs deglitch delay for

R7735L/A. This will last until fault is removed.

` Feedback Open and Opto-Coupler Short

This will trigger OVP or OLP. It depends on which one

occurs first.

` Secondary Rectifier Short Protection

As shown in Figure 9. The current spike during

secondary rectifier short test is extremely high because

of the saturated main transformer. Meanwhile, the

transformer acts like a leakage inductance. During high

line, the current in power MOSFET is sometimes too

high to wait for OLP delay time. To offer better and easier

protection design, R7735 shut down the controller after

couples of cycles before fuse is blown up.

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R7735-03 September 2012

R7735

Secondary Rectifier Short

Zoom In

R7735G/R/L/H

COMP

Figure 9. Secondary Rectifier Short Protection

Negative Voltage Spike on Each Pin

Negative voltage (< -0.3V) on each pin will cause substrate

injection. It leads to controller damage or circuit false

trigger. Generally, it happens at CS pin due to negative

spike because of improper layout or inductive current

sense resistor. Therefore, it is highly recommended to

add a R-C filter to avoid CS pin damage, as shown in

Figure 10. Proper layout and careful circuit design should

be done to guarantee yield rate in mass production.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

where T

the ambient temperature, and θ

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

is the maximum junction temperature, TA is

is the junction to ambient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

ambient thermal resistance, θJA, is layout dependent. For

SOT-23-6 packages, the thermal resistance, θJA, is 250°C/

W on a standard JEDEC 51-3 single-layer thermal test

board. For DIP-8 packages, the thermal resistance, θJA,

is 140°C/W on a standard JEDEC 51-3 single-layer thermal

test board. The maximum power dissipation at TA = 25°C

can be calculated by the following formula :

= (125°C − 25°C) / (250°C/W) = 0.400W for

D(MAX)

SOT-23-6 package

AC Mains (90V to 265V)

NTC

PRO

COMP

VDD

R7735

GND

GATE

R-C Filter

Figure 10. R-C Filter on CS Pin

= (125°C − 25°C) / (140°C/W) = 0.714W for

D(MAX)

DIP-8 package

The maximum power dissipation depends on the operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance, θJA. The derating curves in Figure 11 allow

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.

R7735-03 September 2012

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R7735

)

0.8

0.7

DIP-8

0.6

0.5

0.4

SOT-23-6

0.3

0.2

0.1

Maximum Power Dissipation (W

0.0 0 25 50 75 100 125

Single-Layer PCB

Ambient Temperature (°C)

Figure 11.Derating Curve of Maximum Power Dissipation

Layout Consideration

A proper PCB layout can abate unknown noise interference

and EMI issue in the switching power supply. Please refer

to the guidelines when you want to design PCB layout for

switching power supply:

` The current path (1) from bulk capacitor, transformer,

MOSFET, Rcs return to bulk capacitor is a huge high

frequency current loop. It must be as short as possible

to decrease noise coupling and kept a space to other

low voltage traces, such as IC control circuit paths,

especially.

` The path(2) from RCD snubber circuit to MOSFET is

also a high switching loop, too. Keep it as small as

possible.

` It is good for reducing noise, output ripple and EMI issue

to separate ground traces of bulk capacitor(a),

MOSFET(b), auxiliary winding(c) and IC control circuit

(d). Finally, connect them together on bulk capacitor

ground(a). The areas of these ground traces should be

kept large.

` Placing bypass capacitor for abating noise on IC is highly

recommended. The bypass capacitor should be placed

as close to controller as possible.

` In order to minimize reflected trace inductance and EMI,

it is minimized the area of the loop connecting the

secondary winding, the output diode, and the output

filter capacitor. In addition, apply sufficient copper area

at the anode and cathode terminal of the diode for

heatsinking. Apply a larger area at the quiet cathode

terminal. A large anode area can increase high-frequency

radiated EMI.

(d)

BULK

(a)

GATE

(2)

Ground (a)

BULK

(c)

(1)

(b)

Trace Trace

IC Ground (d)

Auxiliary

Ground (c)

Trace

MOSFET

Ground (b)

AC Mains (90V to 265V)

NTC

PRO

COMP

VDD

R7735

GND

Figure 12. PCB Layout Guide

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R7735-03 September 2012

Outline Dimension

R7735

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.889 1.295 0.031 0.051

A1 0.000 0.152 0.000 0.006

B 1.397 1.803 0.055 0.071

b 0.250 0.560 0.010 0.022

C 2.591 2.997 0.102 0.118

D 2.692 3.099 0.106 0.122

e 0.838 1.041 0.033 0.041

H 0.080 0.254 0.003 0.010

L 0.300 0.610 0.012 0.024

SOT-23-6 Surface Mount Package

R7735-03 September 2012

www.richtek.com

R7735

Symbol

Dimensions In Millimeters Dimensions In Inches

Min Max Min Max

A 3.700 4.320 0.146 0.170

A1 0.381 0.710 0.015 0.028

A2 3.200 3.600 0.126 0.142

b 0.360 0.560 0.014 0.022

b1 1.143 1.778 0.045 0.070

D 9.050 9.550 0.356 0.376

E 6.200 6.600 0.244 0.260

E1 7.620 8.255 0.300 0.325

e 2.540 0.100

L 3.000 3.600 0.118 0.142

Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

8-Lead DIP Plastic Package

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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R7735-03 September 2012

Richtek R7735AGE, R7735AGN, R7735GGE, R7735GGN, R7735HGE Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual