RF Micro Devices RF3163 User Manual

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RF3163

0

Typical Applications

• 3V CDMA/AMPS Cellular Handset

• 3V CDMA2000/1XRTT Cellular Handset

Product Description

The RF3163 is a high-power, high-efficiency linear ampli­fier module specifically designed for 3V handheld sys­tems. The device is manufactured on an advanced third
generation GaAs HBT process, and was designed for use
as the final RF amplifier in 3V IS-95/CDMA 2000
1X/AMPS handheld digital cellular equipment, spread­spectrum systems, and other applications in the 8 24MHz
to 849 MHz band. The RF3163 has a digital control line
for low po w e r ap plic ation s to lower quiescent current. The
RF3163 is assembled in a 16-pin, 3mmx3mm, QFN
package.

3V 900MHZ LINEAR POWER

AMPLIFIER MODULE

• 3V CDMA2000/1X-EV-DO US-Cellular
Handset

• Spread-Spectrum System

0.10 C

0.10 C

0.10 C 0.10 C

+0.10

1.45

-0.15

0.50 TYP.

+0.10

1.45

-0.15

0.30
TYP.

0.18

0.10 C ABM

3.00

Shaded areas represen t pin 1.

-A-

-B-

3.00

Dimensions in mm.

0.50

0.30

TYP.

0.10 C

1.00

0.80

0.08 C

-C-

SCALE:
NONE

0.05

0.00

SEATING
PLANE

Optimum Technology Matching® Applied

Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS
InGaP/HBT

NC

VREG

VMODE

RF IN

9

SiGe HBT
GaN HEMT SiGe Bi-CMOS

NC

16 15 14 13

1

2

3

4

VCC1

Si CMOS

NC

NC

12Bias

RF OUT

VCC2

11

10

VCC2

VCC2

9

8765

NC

NC NC

GND

Functional Block Diagram

Package Style: QFN, 16-Pin, 3x3

Features

• Input Internally Matched@50Ω

• Output Internally Matched

• 28dBm Linear Output Power

• 41% Peak Linear Efficiency

• -51dBc ACPR @ 885 kHz

• 55% AMPS Efficiency

Ordering Information

RF3163 3V 900MHz Linear Power Amplifier Module
RF3163 PCBA Fully Assembled Evaluation Board

RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA

Tel [phone]

Fax [phone]

http://www.rfmd.com

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RF3163

Absolute Maximum Ratings

Parameter Rating Unit

Supply Voltage (RF off) +8.0 V
Supply Voltage (P

Control Voltage (V
Input RF Power +10 dBm

Mode Voltage (V
Operating Temperature -30 to +110 °C

Storage Temperature -40 to +150 °C
Moisture Sensitivity Level

(IPC/JEDEC J-STD-20)

≤31dBm) +5.2 V

OUT

)+3.9V

REG

)+3.9V

MODE

MSL 2 @ 260°C

Caution! ESD sensitive device.

RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products witho ut notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).

Parameter

Min. Typ. Max.

High Power Mode
(V

Operating Frequency Range 824 849 MHz
Linear Gain 26.0 28.5 dB
Second Harmonics -35 -30 dBc
Third Harmonics -40 -30 dBc
Maximum Linear Output 28
Linear Efficiency 36 41 %
Maximum I

ACPR @ 885kHz -51 -46 dBc
ACPR @ 1.98MHz -58 -55 dBc
Input VSWR 2:1
Stability in Band 6:1 No oscillation>-70dBc
Stability out of Band 10:1 No damage
Noise Power -133 dBm/Hz At 45MHz offset.

MODE

Low)

CC

Low Power Mode
(V

Operating Frequency Range 824 849 MHz
Linear Gain 21 24 dB
Maximum Linear Output 18
Maximum I

ACPR @885kHz -51 -46 dBc
ACPR @1.98MHz -61 -56 dBc
Input VSWR 2:1
Output VSWR Stability 6:1 No oscillation>-70dBc

MODE

High)

CC

Specification

455 515 mA

125 mA P

10:1 No damage

Unit Condition

T=25oC Ambient, VCC=3.4V, V

=0V, and P

V

MODE

parameters (unless otherw ise specified).

T=25oC Ambient, VCC=3.4V, V

=2.8V, and P

V

MODE

parameters (unless otherw ise specified).

=16dBm

OUT

OUT

=28dBm for all

OUT

REG

REG

=18dBm for all

=2.8V,

=2.8V,

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RF3163

Parameter

Min. Typ. Max.

FM Mode

Operating Frequency Range 824 849 MHz
AMPS Maximum Output Power 31 dBm
AMPS Efficiency 48 55 %
AMPS Gain 24 28
AMPS Second Harmonics -35 -30 dBc
AMPS Third Harmonics -40 -30 dBc

Specification

Unit Condition

T=25oC Ambient, VCC=3.4V, V
V
parameters (unless otherw ise specified).

Power Supply

Supply Voltage 3.2 3.4 4.2 V
High Gain Idle Current 55 80 mA V

Low Gain Idle Current 45 70 mA V

Current 4.5 5.5 mA V

V

REG

Current 250 uA

V

MODE

RF Turn On/Off Time 6 uS
DC Turn On/Off Time 40 uS
Total Current (Power Down) 0.2 5.0 uA

Low Voltage 0 0.5 V

V

REG

V

High Voltage

REG

(Recommended)

V

High Voltage

REG

(Operational)

V

V oltage 0 0.5 V High Gain Mode

MODE

2.75 2.8 2.95 V

2.7 3.0 V

2.0 2.8 V Low Gain Mode

MODE

MODE
MODE
MODE

=0V, and P

=low and V
=high and V
=high

=31dBm for all

OUT

=2.8V

REG

=2.8V

REG

REG

=2.8V,

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RF3163

Pin Function Description Interface Schematic

1NC
2VREG

3VMODE
4RF IN

5VCC1
6NC

7NC
8GND
9VCC2

10 VCC2
11 VCC2
12 RF OUT
13 NC
14 NC
15 NC
16 NC

Pkg

GND

Base

No connection. Do not connect this pin to any external circuit.
Regulated voltage supply for amplifier bias circuit. In power down

mode, both V
For nominal operation (High Power mode), V

set HIGH, devices are biased lower to improve efficiency.
RF input internally matched to 50Ω. This input is internally AC-coupled.

First stage collector supply. A 2200pF and 4.7µF decoupling capa ci to r
are required.

No connection. Do not connect this pin to any external circuit.
No connection. Do not connect this pin to any external circuit.
Ground connection.
Output stage collector supply. Please see the schematic for required

external components.
Same as pin 9.

Same as pin 9.
RF output. Internally AC-coupled.
No connection. Do not connect this pin to any external circuit.
No connection. Do not connect this pin to any external circuit.
No connection. Do not connect this pin to any external circuit.
No connection. Do not connect this pin to any external circuit.
Ground connection. The backside of the package should be soldered to

a top side ground pad which is connected to the ground plane with mul­tiple vias. The pad should have a short thermal path to the ground
plane.

REG

and V

need to be LOW (<0.5V ).

MODE

is set LOW. When

MODE

2-692

Rev A0 040730

VREG

VMODE

J1

RF IN

VCC1

C30

4.7 µF

50 Ω µstrip

Evaluation Board Schematic

16 15 14 13

C3

2200 pF

C40

4.7 µF

1

2

3

4

C3

2200 pF

C20

4.7 µF

12Bias

11

10

9

8765

L*

C1

2200 pF

50 Ω µstrip

C10

4.7 µF

RF3163

J2

RF OUT

VCC2

P1

1

GND

2

GND

P1-3 VCC1

P1-5 VCC2

3
4
5

CON5

GND

P2

1

GND

2

GND

P2-3 VREG

P2-5 VMODE

3
4
5

CON5

GND

* The current rating for the inductor needs to be 1A.

One example is Toko 0603 multilayer inductor with the
value of 1.8 nH (Toko part number LL1608-F1N8S).
The value of the inductor can be from 1.5nH to 2.2nH.
Different values of the inductor will give slight sh ift o n
the tradeoff between efficiency and ACPR.

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RF3163

Electrostatic Discharge Sensitivity

Human Body Model (HBM)

Figure 3 shows the HBM ESD sensitivity level for each pin to ground. The ESD test is in compliance with JESD22-A114.

>2000 V NC

>2000 V NC

800 V NC

16 15 14 13

750 V NC

750 V RF OUT

12>2000 V NC

750 V VCC2

11

2000 V VCC2

10

9

2000 V VCC2

2000 V VREG

2000 V VMODE

2000 V RF IN

1

2

3

4

8765

GND

2000 V NC

2000 V VCC1

>2000 V NC

Figure 3. ESD Level - Human Body Model

Machine Model (MM)

Figure 4 shows the MM ESD sensitivity level for each pin to ground. The ESD test is in compliance with JESD22-A115.

>300 V NC

250 V NC

16 15 14 13

1

>300 V NC

250 V NC

12>300 V NC

250 V RF OUT

200 V VREG

200 V VMODE

200 V RF IN

Figure 4. ESD Level - Machine Model

2-694

2

3

4

8765

GND

200 V NC

150 V VCC1

>300 V NC

275 V VCC2

11

200 V VCC2

10

9

200 V VCC2

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RF3163

PCB Design Requirements

PCB Surface Finish

The PCB surface finish used for RFMD’s qualification process is electroless nickel, immersion gold. Typical thickness is
3µinch to 8µinch gold over 180µinch nickel.

PCB Land Pattern Recommendation

PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and
tested for optimized assembly at RFMD; however, it may require some modifications to address company specific
assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances.

PCB Metal Land Pattern

A = 0.64 x 0.28 (mm) Typ.
B = 0.28 x 0.64 (mm) Typ.
C = 0.64 x 1.28 (mm)
D = 1.50 (mm) Sq.

Dimensions in mm.

1.50 Typ.

0.50 Typ.

Pin 16

BBBB

Pin 8

A

C

Pin 12Pin 1

0.75 Typ.

1.00 Typ.

0.50 Typ.

0.55 Typ.

0.55 Typ.

A
A
A
A

B B B B

D

0.75 Typ.

Figure 1. PCB Metal Land Pattern (Top View)

Rev A0 040730

2-695

RF3163

PCB Solder Mask Pattern

Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the
PCB metal land pattern with a 2 mil to 3 mil expansion to accommodate solder mask regist ration clearance around all
pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create s older mask
clearance can be provided in the master data or requested from the PCB fabrication supplier.

A = 0.74 x 0.38 (mm) Typ.
B = 0.38 x 0.74 (mm) Typ.
C = 1.60 (mm) Sq.

Dimensions in mm.

1.50 Typ.

0.50 Typ.

Pin 16

0.50 Typ.

0.55 Typ.

0.55 Typ.

A
A
A
A

Figure 2. PCB Solder Mask Pattern (Top View)

BBBB

C

BBBB

0.75

Pin 8

Pin 12Pin 1

A

0.75

A
A
A

1.50 Typ.

Thermal Pad and Via Design

The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the
device.

Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been
designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating
routing strategies.

The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size
on a 0.5 mm to 1.2mm grid patter n with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested
that the quantity of vias be increased by a 4:1 ratio to achieve similar results.

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Rev A0 040730

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