Renesas M16C, М20 User Manual
OCO
R
6C
6C/20 S
S
REJ09B0130-0090Z
M16C/26 Group
16
Usage Notes Reference Book
RENESAS 16-BIT SINGLE-CHIP MICR
M1
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FAMILY / M1
MPUTE
ERIE
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current document available.
Rev. 0.90
Revision date: December. 28, 2003
www.renesas.com
Keep safety first in your circuit designs!
•
Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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programs, algorithms, or circuit application examples contained in these materials.
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Preface
The “Usage Notes Reference Book” is a
compilation of usage notes from the
Hardware Manual as well as technical
news related to this product.
Table of contents
1. Usage Precaution.......................................................................................... 1
1.1 Precautions for Power Control ....................................................................................1
1.2 Precautions for Protect ................................................................................................2
1.3 Precautions for Interrupts............................................................................................3
1.3.1 Reading address 0000016 ................................................................................................................... 3
1.3.2 Setting the SP.......................................................................................................................................3
1.3.3 The NMI Interrupt ................................................................................................................................. 3
1.3.4 Changing the Interrupt Generate Factor............................................................................................4
1.3.5 INT Interrupt .........................................................................................................................................4
1.3.6 Rewrite the Interrupt Control Register...............................................................................................5
1.3.7 Watchdog Timer Interrupt ...................................................................................................................6
1.4 Precautions for DMAC..................................................................................................7
1.4.1 Write to DMAE Bit in DMiCON Register .............................................................................................7
1.5 Precautions for Timers.................................................................................................8
1.5.1 Timer A..................................................................................................................................................8
1.5.1.1 Timer A (Timer Mode) ...................................................................................................................8
1.5.1.2 Timer A (Event Counter Mode) ....................................................................................................9
1.5.1.3 Timer A (One-shot Timer Mode).................................................................................................10
1.5.1.4 Timer A (Pulse Width Modulation Mode) ..................................................................................11
1.5.2 Timer B................................................................................................................................................12
1.5.2.1 Timer B (Timer Mode) ................................................................................................................. 12
1.5.2.2 Timer B (Event Counter Mode) ..................................................................................................13
1.5.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) ......................................................14
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1.6 Precautions for Serial I/O (Clock-synchronous Serial I/O) ..................................... 15
1.6.1 Transmission/reception..................................................................................................................... 15
1.6.2 Transmission......................................................................................................................................16
1.6.3 Reception............................................................................................................................................17
1.7 Precautions for Serial I/O (UART Mode) ...................................................................18
1.7.1 Special Mode 2 .................................................................................................................................. 18
1.7.2 Special Mode 4 (SIM Mode)..............................................................................................................18
1.8 Precautions for A-D Converter ..................................................................................19
1.9 Precautions for Programmable I/O Ports ................................................................. 21
A-1
1.10 Precautions for Flash Memory Version ..................................................................22
1.10.1 Precautions for Functions to Inhibit Rewriting Flash Memory Rewrite......................................22
1.10.2 Precautions for Stop mode .............................................................................................................22
1.10.3 Precautions for Wait mode .............................................................................................................22
1.10.4 Precautions for Low power dissipation mode, ring oscillator low power dissipation mode ... 22
1.10.5 Writing command and data.............................................................................................................22
1.10.6 Precautions for Program Command .............................................................................................. 22
1.10.7 Operation speed...............................................................................................................................23
1.10.8 Instructions inhibited against use..................................................................................................23
1.10.9 Interrupts ..........................................................................................................................................23
1.10.10 How to access ................................................................................................................................23
1.10.11 Writing in the user ROM area ........................................................................................................23
1.10.12 DMA transfer .................................................................................................................................. 24
1.10.13 Regarding Programming/Erasure Times and Execution Time ..................................................24
1.10.14 Definition of Programming/Erasure Times..................................................................................24
1.10.15 Flash Memory Version Electrical Characteristics
10,000 E/W cycle products (D7, D9, U7, U9) .............. 24
1.10.16 Precaution of Boot Mode ..............................................................................................................24
2. Differences Made Depending on Manufactured Time...............................25
2.1 RESET Input ................................................................................................................25
A-2
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26 Group
1. Usage Precaution
1.1 Precautions for Power Control
1.1 Precautions for Power Control
____________
1. When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is
stabilized.
2. Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit of
CM1 register to “1”. When shifting to wait mode or stop mode, an instruction queue reads ahead to the
next instruction to halt a program by an WAIT instruction and an instruction to set the CM10 bit to “1” (all
clocks stopped). The next instruction may be executed before entering wait mode or stop mode, depending on a combination of instruction and an execution timing.
3. Wait until the td(M-L) elapses or main clock oscillation stabilization time, whichever is longer, before
switching the clock source for CPU clock to the main clock.
Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the
sub clock.
4. Suggestions to reduce power consumption
(a) Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A
current flows in active I/O ports. A pass current flows in input ports that high-impedance state. When
entering wait mode or stop mode, set non-used ports to input and stabilize the potential.
(b) A-D converter
When A-D conversion is not performed, set the VCUT bit of ADiCON1 register to “0” (no VREF connection). When A-D conversion is performed, start the A-D conversion at least 1 µs or longer after setting
the VCUT bit to “1” (VREF connection).
(c) Stopping peripheral functions
Use the CM0 register CM02 bit to stop the unnecessary peripheral functions during wait mode.
However, because the peripheral function clock (fC32) generated from the sub-clock does not stop,
this measure is not conducive to reducing the power consumption of the chip. If low speed mode or
low power dissipation mode is to be changed to wait mode, set the CM02 bit to “0” (do not peripheral
function clock stopped when in wait mode), before changing wait mode.
(d) Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
(e) External clock
When using an external clock input for the CPU clock, set the CM0 register CM05 bit to “1” (stop).
Setting the CM05 bit to “1” disables the XOUT pin from functioning, which helps to reduce the amount
of current drawn in the chip. (When using an external clock input, note that the clock remains fed into
the chip regardless of how the CM05 bit is set.)
Rev.0.90 2003.12.28 page 1 of 28
Under development
M16C/26 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.2 Precautions for Protect
1.2 Precautions for Protect
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction.
Rev.0.90 2003.12.28 page 2 of 28
Under development
M16C/26 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.3 Precautions for Interrupts
1.3 Precautions for Interrupts
1.3.1 Reading address 0000016
Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU
reads interrupt information (interrupt number and interrupt request priority level) from the address
0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or an
unexpected interrupt request is generated.
1.3.2 Setting the SP
Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to ‘000016’
after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the program may go out of control.
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first
and only the first instruction after reset, all interrupts including NMI interrupt are disabled.
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_______
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1.3.3 The NMI Interrupt
_______ _______
1. The NMI interrupt is invalid after reset. The NMI interrupt becomes effective by setting to “1” the PM24
bit of the PM2 register. Once enabled, it stays enabled until a reset is applied.
2. The input level of the NMI pin can be read by accessing the P8 register’s P8_5 bit. Note that the P8_5
bit can only be read when determining the pin level in NMI interrupt routine.
3. When selecting NMI function, stop mode cannot be entered into while input on the NMI pin is low. This
is because while input on the NMI pin is low the CM1 register’s CM10 bit is fixed to “0”.
4. When selecting NMI function, do not go to wait mode while input on the NMI pin is low. This is because
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_______ _______
_______
_______ _______
_______
when input on the NMI pin goes low, the CPU stops but CPU clock remains active; therefore, the current
consumption in the chip does not drop. In this case, normal condition is restored by an interrupt generated thereafter.
_______ _______
5. When selecting NMI function, the low and high level durations of the input signal to the NMI pin must
each be 2 CPU clock cycles + 300 ns or more.
Rev.0.90 2003.12.28 page 3 of 28
Under development
M16C/26 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.3 Precautions for Interrupts
1.3.4 Changing the Interrupt Generate Factor
If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor
for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0” (interrupt not
requested).
“Changing the interrupt generate factor” referred to here means any act of changing the source, polarity
or timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any
peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to
clear the IR bit for that interrupt to “0” (interrupt not requested) after making such changes. Refer to the
description of each peripheral function for details about the interrupts from peripheral functions.
Figure 1.3.1 shows the procedure for changing the interrupt generate factor.
Changing the interrupt source
Disable interrupts (Note 2, Note 3)
Change the interrupt generate factor (including a mode change of peripheral function)
Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (Note 3)
Enable interrupts (Note 2, Note 3)
End of change
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to
be changed
Note 1: The above settings must be executed individually. Do not execute two or more settings
simultaneously (using one instruction).
Note 2: Use the I flag for the INTi interrupt (i = 0 to 1, 3 to 5).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the
peripheral function that is the source of the interrupt in order not to generate an interrupt
request before changing the interrupt generate factor. In this case, if the maskable interrupts
can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding
ILVL2 to ILVL0 bit for the interrupt whose interrupt generate factor is to be changed.
Note 3: Refer to Section 1.1.6, “Rewrite the Interrupt Control Register” for details about the
instructions to use and the notes to be taken for instruction execution.
Figure 1.3.1. Procedure for Changing the Interrupt Generate Factor
______
1.3.5 INT Interrupt
1. Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the signal
input to pins INT0 through INT1, and INT3 through INT5 regardless of the CPU operation clock.
2. If the POL bit in the INT0IC to INT1IC and INT3IC to INT5IC registers or the IFSR7 to IFSR0 bits in the
IFSR register are changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear
the IR bit to 0 (interrupt not requested) after changing any of those register bits.
Rev.0.90 2003.12.28 page 4 of 28
_______ _______ _______ _______
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26 Group
1.3.6 Rewrite the Interrupt Control Register
(1) The interrupt control register for any interrupt should be modified in places where no requests for that
interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
(2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the
instruction to be used.
Changing any bit other than the IR bit
If while executing an instruction, a request for an interrupt controlled by the register being modified
occurs, the IR bit in the register may not be set to “1” (interrupt requested), with the result that the
interrupt request is ignored. If such a situation presents a problem, use the instructions shown below
to modify the register.
Usable instructions: AND, OR, BCLR, BSET
Changing the IR bit
Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not requested). Therefore, be sure to use the MOV instruction to clear the IR bit.
1.3 Precautions for Interrupts
(3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as
you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the sample
program fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the
interrupt control register is rewrited, owing to the effects of the internal bus and the instruction queue
buffer.
Example 1:Using the NOP instruction to keep the program waiting until
the interrupt control register is modified
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “0016”.
NOP ;
NOP
FSET I ; Enable interrupts.
The number of NOP instruction is 2.
Example 2:Using the dummy read to keep the FSET instruction waiting
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “0016”.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3:Using the POPC instruction to changing the I flag
INT_SWITCH3:
PUSHC FLG
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “00
POPC FLG ; Enable interrupts.
Rev.0.90 2003.12.28 page 5 of 28
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