Renesas V850ES/JG3-L User’s Manual: Hardware

User’s Manual

V850ES/JG3-L (on-chip USB controller)

User’s Manual: Hardware

RENESAS MCU V850ES/Jx3-L Microcontrollers

μ PD70F3794 μPD70F3795 μPD70F3796 μPD70F3843 μPD70F3844

All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com).

www.renesas.com

Rev.3.00 Aug 2012

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

crime systems; and safety equipment etc.

Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.

6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you.

8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations.

10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products.

11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-

owned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

(2012.4)

NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V

(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

(MAX) and VIH (MIN) due to noise, etc., the device may

(MAX) and

or GND

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

How to Use This Manual

Readers This manual is intended for users who wish to understand the functions of the

V850ES/JG3-L and design application systems using these products.

Purpose This manual is intended to give users an understanding of the hardware functions of the

V850ES/JG3-L shown in the Organization below.

Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES

Architecture User’s Manual).

Hardware Architecture

• Pin functions • Data types

• CPU function • Register set

• On-chip peripheral functions • Instruction format and instruction set

• Flash memory programming • Interrupts and exceptions

• Electrical specifications • Pipeline operation

How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of

electrical engineering, logic circuits, and microcontrollers.

To understand the overall functions of the V850ES/JG3-L → Read this manual according to the CONTENTS.

To find the details of a register where the name is known → Use APPENDIX C REGISTER INDEX.

format of each register is defined as a reserved word in the device file.

To understand the details of an instruction function → Refer to the V850ES Architecture User’s Manual available separately.

To know the electrical specifications of the V850ES/JG3-L

→ See CHAPTER 33 ELECTRICAL SPECIFICATIONS (

70F3796)

CHAPTER 34 ELECTRICAL SPECIFICATIONS (

The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note with

caution that if “xxx.yyy” is described as is in a program, however, the compiler/assembler

cannot recognize it correctly.

PD70F3843, 70F3844)

PD70F3794, 70F3795,

The mark <R> shows major revised points. The revised points can be easily searched

by copying an “<R>” in the PDF file and specifying it in the “Find what: ” field.

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representation: xxx (overscore over pin or signal name)

Memory map address: Higher addresses on the top and lower addresses on the

bottom

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numeric representation: Binary ... xxxx or xxxxB

Decimal ... xxxx

Hexadecimal ... xxxxH

Prefix indicating power of 2 (address space, memory capacity):

K (kilo): 2

M (mega): 2

G (giga): 2

= 1,024

= 1,0242

= 1,024

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents related to V850ES/JG3-L

Document Name Document No.

V850ES Architecture User’s Manual U15943E

V850ES/JG3-L (on-chip USB controller) Hardware User’s Manual This manual

Documents related to development tools

Document Name Document No.

QB-V850ESJX3L In-Circuit Emulator To be prepared

QB-V850MINI, QB-V850MINIL On-Chip Debug Emulator U17638E

QB-MINI2 On-Chip Debug Emulator with Programming Function U18371E

CA850 Ver. 3.20 C Compiler Package

PM+ Ver. 6.30 Project Manager U18416E

ID850QB Ver. 3.40 Integrated Debugger Operation U18604E

SM850 Ver. 2.50 System Simulator Operation U16218E

SM850 Ver. 2.00 or Later System Simulator External Part User Open

RX850 Ver. 3.20 Real-Time OS

RX850 Pro Ver. 3.21 Real-Time OS

AZ850 Ver. 3.30 System Performance Analyzer U17423E

PG-FP5 Flash Memory Programmer U18865E

Operation U18512E

C Language U18513E

Assembly Language U18514E

Link Directives U18415E

U14873E

Interface Specification

Operation U18601E SM+ System Simulator

User Open Interface U18212E

Basics U13430E

Installation U17419E

Technical U13431E

Task Debugger U17420E

Basics U18165E

Installation U17421E

Task Debugger U17422E

Other Documents

Document Name Document No.

RENESAS MICROCOMPUTER GENERAL CATALOG R01CS0001E

Semiconductor Package Mount Manual

Quality Grades on Renesas Semiconductor Devices

Renesas Semiconductor Device Reliability/Quality Control System

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

Note

C11531E

C10983E

C11892E

Note See the “Semiconductor Package Mount Manual” website

(http://www.renesas.com/products/package/manual/index.jsp).

Caution The related documents listed above are subject to change without notice.

Be sure to use the latest version of each document when designing.

Caution: This product uses SuperFlash

technology licensed from Silicon Storage Technology, Inc.

IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany.

MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in

the United States of America.

EEPROM is a trademark of Renesas Electronics Corporation

Applilet is a registered trademark of Renesas Electronics in Japan, Germany, Hong Kong, China, the Republic of

Korea, the United Kingdom, and the United States of America.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United

States and/or other countries.

SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United

States and Japan.

PC/AT is a trademark of International Business Machines Corporation.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

TRON is an abbreviation of The Realtime Operating System Nucleus.

ITRON is an abbreviation of Industrial TRON.

CHAPTER 1 INTRODUCTION................................................................................................................. 21

1.1 General...................................................................................................................................... 21

1.2 Features .................................................................................................................................... 23

1.3 Application Fields .................................................................................................................... 25

1.4 Ordering Information ............................................................................................................... 25

1.5 Pin Configuration (Top View).................................................................................................. 26

1.6 Function Block Configuration................................................................................................. 30

1.6.1 Internal block diagram.....................................................................................................................30

1.6.2 Internal units ...................................................................................................................................31

CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 34

2.1 List of Pin Functions................................................................................................................ 34

2.2 Pin States.................................................................................................................................. 44

2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins......... 45

2.4 Cautions.................................................................................................................................... 49

CHAPTER 3 CPU FUNCTION ................................................................................................................ 50

3.1 Features .................................................................................................................................... 50

3.2 CPU Register Set...................................................................................................................... 51

3.2.1 Program register set .......................................................................................................................52

3.2.2 System register set .........................................................................................................................53

3.3 Operation Modes...................................................................................................................... 59

3.4 Address Space ......................................................................................................................... 60

3.4.1 CPU address space........................................................................................................................60

3.4.2 Memory map...................................................................................................................................61

3.4.3 Areas ..............................................................................................................................................63

3.4.4 Wraparound of data space..............................................................................................................70

3.4.5 Recommended use of address space.............................................................................................70

3.4.6 Peripheral I/O registers...................................................................................................................74

3.4.7 Special registers .............................................................................................................................85

3.4.8 Registers to be set first ...................................................................................................................89

3.4.9 Cautions..........................................................................................................................................90

CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 92

4.1 Features .................................................................................................................................... 92

4.2 Basic Port Configuration......................................................................................................... 92

4.3 Port Configuration ................................................................................................................... 93

4.3.1 Port 0 ..............................................................................................................................................99

4.3.2 Port 1 ............................................................................................................................................103

4.3.3 Port 3 ............................................................................................................................................105

4.3.4 Port 4 ............................................................................................................................................111

4.3.5 Port 5 ............................................................................................................................................113

4.3.6 Port 7 ............................................................................................................................................118

4.3.7 Port 9 ............................................................................................................................................120

4.3.8 Port CM.........................................................................................................................................128

4.3.9 Port CT .........................................................................................................................................130

4.3.10 Port DH .........................................................................................................................................132

4.3.11 Port DL..........................................................................................................................................134

4.4 Block Diagrams ...................................................................................................................... 137

4.5 Port Register Settings When Alternate Function Is Used.................................................. 169

4.6 Cautions.................................................................................................................................. 177

4.6.1 Cautions on setting port pins.........................................................................................................177

4.6.2 Cautions on bit manipulation instruction for port n register (Pn)....................................................180

4.6.3 Cautions on on-chip debug pins....................................................................................................181

4.6.4 Cautions on P05/INTP2/DRST pin................................................................................................181

4.6.5 Cautions on P10, P11, and P53 pins when power is turned on ....................................................181

4.6.6 Hysteresis characteristics .............................................................................................................181

CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 182

5.1 Features .................................................................................................................................. 182

5.2 Bus Control Pins .................................................................................................................... 183

5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed....................183

5.2.2 Pin status in each operation mode................................................................................................183

5.3 Memory Block Function ........................................................................................................ 184

5.4 Bus Access............................................................................................................................. 185

5.4.1 Number of clock cycles required for access..................................................................................185

5.4.2 Bus size setting function ...............................................................................................................186

5.4.3 Access according to bus size........................................................................................................187

5.5 Wait Function.......................................................................................................................... 194

5.5.1 Programmable wait function..........................................................................................................194

5.5.2 External wait function....................................................................................................................195

5.5.3 Relationship between programmable wait and external wait.........................................................196

5.5.4 Programmable address wait function............................................................................................197

5.6 Idle State Insertion Function................................................................................................. 198

5.7 Bus Hold Function ................................................................................................................. 199

5.7.1 Functional outline..........................................................................................................................199

5.7.2 Bus hold procedure.......................................................................................................................200

5.7.3 Operation in power save mode .....................................................................................................200

5.8 Bus Priority............................................................................................................................. 201

5.9 Bus Timing.............................................................................................................................. 202

CHAPTER 6 CLOCK GENERATOR .................................................................................................... 206

6.1 Overview ................................................................................................................................. 206

6.2 Configuration.......................................................................................................................... 207

6.3 Registers................................................................................................................................. 210

6.4 Operations .............................................................................................................................. 216

6.4.1 Operation of each clock ................................................................................................................216

6.4.2 Clock output function ....................................................................................................................217

6.4.3 External clock signal input.............................................................................................................217

6.5 PLL Function .......................................................................................................................... 217

6.5.1 Overview.......................................................................................................................................217

6.5.2 Registers.......................................................................................................................................218

6.5.3 Usage ...........................................................................................................................................222

6.6 How to Connect a Resonator................................................................................................ 223

6.6.1 Main clock oscillator......................................................................................................................223

6.6.2 Subclock oscillator ........................................................................................................................223

CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) ................................................................ 226

7.1 Overview ................................................................................................................................. 226

7.2 Configuration.......................................................................................................................... 227

7.2.1 Pins used by TMPn.......................................................................................................................229

7.2.2 Interrupts.......................................................................................................................................230

7.3 Registers................................................................................................................................. 231

7.4 Operations .............................................................................................................................. 243

7.4.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) ..................................................................250

7.4.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) ......................................................261

7.4.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) ..........................................270

7.4.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011)....................................................282

7.4.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) ...................................................................290

7.4.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) .........................................................299

7.4.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110)..............................................315

7.4.8 Timer output operations ................................................................................................................319

7.5 Selector ................................................................................................................................... 320

7.6 Cautions.................................................................................................................................. 321

CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)................................................................ 322

8.1 Functions ................................................................................................................................ 322

8.2 Configuration.......................................................................................................................... 323

8.2.1 Pins used by TMQ0 ......................................................................................................................325

8.2.2 Interrupts.......................................................................................................................................325

8.3 Registers................................................................................................................................. 326

8.4 Operations .............................................................................................................................. 341

8.4.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) .................................................................348

8.4.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) .....................................................360

8.4.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) .........................................370

8.4.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011)...................................................385

8.4.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) ..................................................................395

8.4.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101).........................................................406

8.4.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110).............................................426

8.4.8 Timer output operations ................................................................................................................431

8.5 Cautions.................................................................................................................................. 432

CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) ............................................................................ 433

9.1 Features .................................................................................................................................. 433

9.2 Configuration.......................................................................................................................... 434

9.3 Registers................................................................................................................................. 435

9.4 Operation ................................................................................................................................ 437

9.4.1 Interval timer mode .......................................................................................................................437

9.4.2 Cautions........................................................................................................................................441

CHAPTER 10 WATCH TIMER.............................................................................................................. 442

10.1 Functions ................................................................................................................................ 442

10.2 Configuration.......................................................................................................................... 443

10.3 Control Registers ................................................................................................................... 445

10.4 Operation ................................................................................................................................ 449

10.4.1 Watch timer operations .................................................................................................................449

10.4.2 Interval timer operations................................................................................................................450

10.5 Cautions .................................................................................................................................. 452

CHAPTER 11 REAL-TIME COUNTER................................................................................................. 453

11.1 Functions ................................................................................................................................ 453

11.2 Configuration.......................................................................................................................... 454

11.2.1 Pin configuration ...........................................................................................................................456

11.2.2 Interrupt functions .........................................................................................................................456

11.3 Registers ................................................................................................................................. 457

11.4 Operation ................................................................................................................................ 472

11.4.1 Initial settings ................................................................................................................................472

11.4.2 Rewriting each counter during real-time counter operation ...........................................................473

11.4.3 Reading each counter during real-time counter operation ............................................................474

11.4.4 Changing INTRTC0 interrupt setting during real-time counter operation ......................................475

11.4.5 Changing INTRTC1 interrupt setting during real-time counter operation ......................................476

11.4.6 Initial INTRTC2 interrupt settings ..................................................................................................477

11.4.7 Changing INTRTC2 interrupt setting during real-time counter operation ......................................478

11.4.8 Initializing real-time counter ..........................................................................................................479

11.4.9 Watch error correction example of real-time counter ....................................................................480

CHAPTER 12 WATCHDOG TIMER 2 ................................................................................................. 484

12.1 Functions ................................................................................................................................ 484

12.2 Configuration.......................................................................................................................... 485

12.3 Registers ................................................................................................................................. 486

12.4 Operation ................................................................................................................................ 488

CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO)................................................................... 489

13.1 Function .................................................................................................................................. 489

13.2 Configuration.......................................................................................................................... 490

13.3 Registers ................................................................................................................................. 492

13.4 Operation ................................................................................................................................ 494

13.5 Usage....................................................................................................................................... 495

13.6 Cautions .................................................................................................................................. 495

CHAPTER 14 A/D CONVERTER ......................................................................................................... 496

14.1 Overview ................................................................................................................................. 496

14.2 Functions ................................................................................................................................ 496

14.3 Configuration.......................................................................................................................... 497

14.4 Registers ................................................................................................................................. 500

14.5 Operation ................................................................................................................................ 511

14.5.1 Basic operation .............................................................................................................................511

14.5.2 Conversion timing .........................................................................................................................512

14.5.3 Trigger modes ...............................................................................................................................513

14.5.4 Operation mode ............................................................................................................................515

14.5.5 Power-fail compare mode .............................................................................................................521

14.6 Cautions .................................................................................................................................. 528

14.7 How to Read A/D Converter Characteristics Table ............................................................ 533

CHAPTER 15 D/A CONVERTER ......................................................................................................... 537

15.1 Functions ................................................................................................................................ 537

15.2 Configuration.......................................................................................................................... 538

15.3 Registers ................................................................................................................................. 539

15.4 Operation ................................................................................................................................ 541

15.4.1 Operation in normal mode.............................................................................................................541

15.4.2 Operation in real-time output mode...............................................................................................541

15.4.3 Cautions........................................................................................................................................542

CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ............................................. 543

16.1 Features .................................................................................................................................. 543

16.2 Configuration.......................................................................................................................... 544

16.2.1 Pin functions of each channel .......................................................................................................546

16.3 Mode Switching of UARTA and Other Serial Interfaces..................................................... 547

16.3.1 UARTA0 and CSIB4 mode switching ............................................................................................547

16.3.2 UARTA1 and I2C02 mode switching..............................................................................................548

16.3.3 UARTA2 and I2C00 mode switching..............................................................................................549

16.4 Registers ................................................................................................................................. 550

16.5 Interrupt Request Signals ..................................................................................................... 557

16.6 Operation ................................................................................................................................ 558

16.6.1 Data format ...................................................................................................................................558

16.6.2 UART transmission .......................................................................................................................560

16.6.3 Continuous transmission procedure..............................................................................................561

16.6.4 UART reception ............................................................................................................................563

16.6.5 Reception errors ...........................................................................................................................565

16.6.6 Parity types and operations...........................................................................................................567

16.6.7 LIN transmission/reception format ................................................................................................568

16.6.8 SBF transmission ..........................................................................................................................570

16.6.9 SBF reception ...............................................................................................................................571

16.6.10 Receive data noise filter..............................................................................................................572

16.7 Dedicated Baud Rate Generator ........................................................................................... 573

16.8 Cautions .................................................................................................................................. 581

CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) ............................................. 582

17.1 Features .................................................................................................................................. 582

17.2 Configuration.......................................................................................................................... 583

17.2.1 Pin functions of each channel .......................................................................................................585

17.3 Mode Switching of UARTC and Other Serial Interfaces..................................................... 586

17.3.1 UARTC0 and CSIB1 mode switching............................................................................................586

17.4 Registers ................................................................................................................................. 587

17.5 Interrupt Request Signals ..................................................................................................... 596

17.6 Operation ................................................................................................................................ 597

17.6.1 Data format ...................................................................................................................................597

17.6.2 UART transmission .......................................................................................................................599

17.6.3 Continuous transmission procedure..............................................................................................600

17.6.4 UART reception ............................................................................................................................602

17.6.5 Reception errors ...........................................................................................................................604

17.6.6 Parity types and operations...........................................................................................................606

17.6.7 LIN transmission/reception format ................................................................................................607

17.6.8 SBF transmission ..........................................................................................................................609

17.6.9 SBF reception ...............................................................................................................................610

17.6.10 Receive data noise filter..............................................................................................................611

17.7 Dedicated Baud Rate Generator ........................................................................................... 612

17.8 Cautions .................................................................................................................................. 620

CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)............................................................... 621

18.1 Features .................................................................................................................................. 621

18.2 Configuration.......................................................................................................................... 622

18.2.1 Pin functions of each channel .......................................................................................................623

18.3 Mode Switching of CSIB and Other Serial Interfaces......................................................... 624

18.3.1 CSIB0 and I2C01 mode switching .................................................................................................624

18.3.2 CSIB4 and UARTA0 mode switching ............................................................................................625

18.4 Registers ................................................................................................................................. 626

18.5 Interrupt Request Signals ..................................................................................................... 635

18.6 Operation ................................................................................................................................ 636

18.6.1 Single transfer mode (master mode, transmission mode).............................................................636

18.6.2 Single transfer mode (master mode, reception mode) ..................................................................638

18.6.3 Single transfer mode (master mode, transmission/reception mode) .............................................640

18.6.4 Single transfer mode (slave mode, transmission mode) ...............................................................642

18.6.5 Single transfer mode (slave mode, reception mode).....................................................................644

18.6.6 Single transfer mode (slave mode, transmission/reception mode)................................................647

18.6.7 Continuous transfer mode (master mode, transmission mode).....................................................649

18.6.8 Continuous transfer mode (master mode, reception mode) ..........................................................651

18.6.9 Continuous transfer mode (master mode, transmission/reception mode) .....................................654

18.6.10 Continuous transfer mode (slave mode, transmission mode) .....................................................658

18.6.11 Continuous transfer mode (slave mode, reception mode) ..........................................................660

18.6.12 Continuous transfer mode (slave mode, transmission/reception mode) .....................................663

18.6.13 Reception errors .........................................................................................................................666

18.6.14 Clock timing ................................................................................................................................667

18.7 Output Pins ............................................................................................................................. 669

18.8 Baud Rate Generator ............................................................................................................. 670

18.8.1 Baud rate generation ....................................................................................................................671

18.9 Cautions .................................................................................................................................. 672

CHAPTER 19 I2C BUS .......................................................................................................................... 673

19.1 Mode Switching of I2C Bus and Other Serial Interfaces..................................................... 673

19.1.1 UARTA2 and I2C00 mode switching..............................................................................................673

19.1.2 CSIB0 and I2C01 mode switching .................................................................................................674

19.1.3 UARTA1 and I2C02 mode switching..............................................................................................675

19.2 Features .................................................................................................................................. 676

19.3 Configuration.......................................................................................................................... 677

19.4 Registers ................................................................................................................................. 681

19.5 I2C Bus Mode Functions ........................................................................................................ 697

19.5.1 Pin configuration ...........................................................................................................................697

19.6 I2C Bus Definitions and Control Methods ............................................................................ 698

19.6.1 Start condition ...............................................................................................................................698

19.6.2 Addresses .....................................................................................................................................699

19.6.3 Transfer direction specification .....................................................................................................700

19.6.4 ACK ..............................................................................................................................................701

19.6.5 Stop condition ...............................................................................................................................702

19.6.6 Wait state ......................................................................................................................................703

19.6.7 Wait state cancellation method .....................................................................................................705

19.7 I2C Interrupt Request Signals (INTIICn)................................................................................ 706

19.7.1 Master device operation................................................................................................................706

19.7.2 Slave device operation (when receiving slave address data (address match)) .............................709

19.7.3 Slave device operation (when receiving extension code)..............................................................713

19.7.4 Operation without communication .................................................................................................717

19.7.5 Operation when arbitration loss occurs (operation as slave after arbitration loss) ........................717

19.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) ........................719

19.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control ........................ 726

19.9 Address Match Detection Method ........................................................................................ 728

19.10 Error Detection ....................................................................................................................... 728

19.11 Extension Code ...................................................................................................................... 728

19.12 Arbitration............................................................................................................................... 729

19.13 Wakeup Function ................................................................................................................... 730

19.14 Communication Reservation ................................................................................................ 731

19.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) ..........................731

19.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1)..........................735

19.15 Cautions.................................................................................................................................. 736

19.16 Communication Operations.................................................................................................. 737

19.16.1 Master operation in single master system...................................................................................738

19.16.2 Master operation in multimaster system .....................................................................................739

19.16.3 Slave operation...........................................................................................................................742

19.17 Timing of Data Communication............................................................................................ 745

CHAPTER 20 USB FUNCTION CONTROLLER (USBF) .................................................................. 752

20.1 Overview ................................................................................................................................. 752

20.2 Configuration.......................................................................................................................... 753

20.2.1 Block diagram ...............................................................................................................................753

20.2.2 USB memory map.........................................................................................................................754

20.3 External Circuit Configuration .............................................................................................. 755

20.3.1 Outline ..........................................................................................................................................755

20.3.2 Connection configuration ..............................................................................................................756

20.4 Cautions .................................................................................................................................. 758

20.5 Requests ................................................................................................................................. 759

20.5.1 Automatic requests .......................................................................................................................759

20.5.2 Other requests ..............................................................................................................................766

20.6 Register Configuration .......................................................................................................... 767

20.6.1 USB control registers ....................................................................................................................767

20.6.2 USB function controller register list ...............................................................................................768

20.6.3 EPC control registers ....................................................................................................................784

20.6.4 Data hold registers ........................................................................................................................836

20.6.5 EPC request data registers ...........................................................................................................859

20.6.6 Bridge register...............................................................................................................................874

20.6.7 DMA register .................................................................................................................................878

20.6.8 Bulk-in register ..............................................................................................................................882

20.6.9 Bulk-out register ............................................................................................................................883

20.6.10 Peripheral control registers .........................................................................................................885

20.7 STALL Handshake or No Handshake................................................................................... 889

20.8 Register Values in Specific Status ....................................................................................... 890

20.9 FW Processing ....................................................................................................................... 892

20.9.1 Initialization processing .................................................................................................................894

20.9.2 Interrupt servicing .........................................................................................................................897

20.9.3 USB main processing ...................................................................................................................898

20.9.4 Suspend/Resume processing .......................................................................................................924

20.9.5 Processing after power application ...............................................................................................927

20.9.6 Receiving data for bulk transfer (OUT) in DMA mode ...................................................................930

20.9.7 Transmitting data for bulk transfer (IN) in DMA mode ...................................................................935

CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) ................................................................... 940

21.1 Features .................................................................................................................................. 940

21.2 Configuration.......................................................................................................................... 941

21.3 Registers ................................................................................................................................. 943

21.4 Transfer Sources and Destinations ..................................................................................... 951

21.5 Transfer Modes ...................................................................................................................... 951

21.6 Transfer Types ....................................................................................................................... 952

21.7 DMA Channel Priorities ......................................................................................................... 953

21.8 Time Related to DMA Transfer.............................................................................................. 954

21.9 DMA Transfer Start Factors .................................................................................................. 955

21.10 DMA Abort Factors ................................................................................................................ 956

21.11 End of DMA Transfer ............................................................................................................. 956

21.12 Operation Timing.................................................................................................................... 956

21.13 Cautions.................................................................................................................................. 961

CHAPTER 22 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION......................... 966

22.1 Features .................................................................................................................................. 966

22.2 Non-Maskable Interrupts ....................................................................................................... 970

22.2.1 Operation ......................................................................................................................................972

22.2.2 Restoration....................................................................................................................................973

22.2.3 NP flag ..........................................................................................................................................974

22.3 Maskable Interrupts ............................................................................................................... 975

22.3.1 Operation ......................................................................................................................................975

22.3.2 Restoration....................................................................................................................................977

22.3.3 Priorities of maskable interrupts ....................................................................................................978

22.3.4 Interrupt control register (xxICn) ...................................................................................................982

22.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) .............................................................................984

22.3.6 In-service priority register (ISPR) ..................................................................................................986

22.3.7 ID flag ...........................................................................................................................................987

22.3.8 Watchdog timer mode register 2 (WDTM2)...................................................................................987

22.4 Software Exception................................................................................................................ 988

22.4.1 Operation ......................................................................................................................................988

22.4.2 Restoration....................................................................................................................................989

22.4.3 EP flag ..........................................................................................................................................990

22.5 Exception Trap ....................................................................................................................... 991

22.5.1 Illegal opcode ................................................................................................................................991

22.5.2 Debug trap ....................................................................................................................................993

22.6 Multiple Interrupt Servicing Control..................................................................................... 995

22.7 External Interrupt Request Input Pins (NMI, INTP0 to INTP7) ........................................... 996

22.7.1 Noise elimination...........................................................................................................................996

22.7.2 Edge detection ..............................................................................................................................996

22.8 Interrupt Response Time of CPU........................................................................................ 1002

22.9 Periods in Which Interrupts Are Not Acknowledged by CPU ......................................... 1003

22.10 Cautions................................................................................................................................ 1003

22.10.1 Restored PC .............................................................................................................................1003

CHAPTER 23 KEY INTERRUPT FUNCTION ................................................................................... 1004

23.1 Function ................................................................................................................................ 1004

23.2 Pin Functions........................................................................................................................ 1005

23.3 Registers ............................................................................................................................... 1005

23.4 Cautions ................................................................................................................................ 1006

CHAPTER 24 STANDBY FUNCTION ................................................................................................ 1007

24.1 Overview ............................................................................................................................... 1007

24.2 Registers ............................................................................................................................... 1009

24.3 HALT Mode ........................................................................................................................... 1014

24.3.1 Setting and operation status .......................................................................................................1014

24.3.2 Releasing HALT mode ................................................................................................................1014

24.4 IDLE1 Mode........................................................................................................................... 1016

24.4.1 Setting and operation status .......................................................................................................1016

24.4.2 Releasing IDLE1 mode ...............................................................................................................1017

24.5 IDLE2 Mode........................................................................................................................... 1019

24.5.1 Setting and operation status .......................................................................................................1019

24.5.2 Releasing IDLE2 mode ...............................................................................................................1020

24.5.3 Securing setup time when releasing IDLE2 mode.......................................................................1022

24.6 STOP Mode/Low-Voltage STOP Mode ............................................................................... 1023

24.6.1 Setting and operation status .......................................................................................................1023

24.6.2 Releasing STOP mode/low-voltage STOP mode........................................................................1027

24.6.3 Re-setting after release of low-voltage STOP mode ...................................................................1028

24.6.4 Securing oscillation stabilization time when releasing STOP mode ............................................1029

24.7 Subclock Operation Mode/Low-Voltage Subclock Operation Mode .............................. 1030

24.7.1 Setting and operation status .......................................................................................................1030

24.7.2 Releasing subclock operation mode ...........................................................................................1034

24.7.3 Releasing low-voltage subclock operation mode ........................................................................1034

24.8 Sub-IDLE Mode/Low-Voltage Sub-IDLE Mode .................................................................. 1035

24.8.1 Setting and operation status .......................................................................................................1035

24.8.2 Releasing sub-IDLE mode/low-voltage sub-IDLE mode .............................................................1038

24.9 RTC backup Mode ................................................................................................................ 1039

24.9.1 Registers ....................................................................................................................................1039

24.9.2 RTC backup mode setting conditions..........................................................................................1041

24.9.3 RTC backup mode setting procedure..........................................................................................1042

CHAPTER 25 RESET FUNCTION...................................................................................................... 1049

25.1 Overview ............................................................................................................................... 1049

25.2 Configuration........................................................................................................................ 1050

25.3 Register to Check Reset Source ........................................................................................ 1051

25.4 Operation .............................................................................................................................. 1052

25.4.1 Reset operation via RESET pin ..................................................................................................1052

25.4.2 Reset operation by watchdog timer 2..........................................................................................1055

25.4.3 Reset operation by low-voltage detector .....................................................................................1057

25.4.4 Operation immediately after reset ends ......................................................................................1058

25.4.5 Reset function operation .............................................................................................................1060

25.5 Cautions ................................................................................................................................ 1061

CHAPTER 26 CLOCK MONITOR ...................................................................................................... 1062

26.1 Functions .............................................................................................................................. 1062

26.2 Configuration........................................................................................................................ 1062

26.3 Registers ............................................................................................................................... 1063

26.4 Operation .............................................................................................................................. 1064

CHAPTER 27 LOW-VOLTAGE DETECTOR (LVI) ........................................................................... 1067

27.1 Functions .............................................................................................................................. 1067

27.2 Configuration........................................................................................................................ 1067

27.3 Registers ............................................................................................................................... 1068

27.4 Operation .............................................................................................................................. 1070

27.4.1 To use for internal reset signal....................................................................................................1070

27.4.2 To use for interrupt......................................................................................................................1071

CHAPTER 28 CRC FUNCTION.......................................................................................................... 1072

28.1 Functions .............................................................................................................................. 1072

28.2 Configuration........................................................................................................................ 1072

28.3 Registers ............................................................................................................................... 1073

28.4 Operation .............................................................................................................................. 1074

28.5 Usage..................................................................................................................................... 1075

CHAPTER 29 REGULATOR ............................................................................................................... 1077

29.1 Outline ................................................................................................................................... 1077

29.2 Operation .............................................................................................................................. 1078

CHAPTER 30 OPTION BYTE............................................................................................................. 1079

30.1 Program Example................................................................................................................. 1081

CHAPTER 31 FLASH MEMORY........................................................................................................ 1082

31.1 Features ................................................................................................................................ 1082

31.2 Memory Configuration......................................................................................................... 1083

31.3 Functional Outline................................................................................................................ 1085

31.4 Rewriting by Dedicated Flash Memory Programmer ....................................................... 1088

31.4.1 Programming environment ..........................................................................................................1088

31.4.2 Communication mode .................................................................................................................1089

31.4.3 Interface ......................................................................................................................................1091

31.4.4 Flash memory control .................................................................................................................1096

31.4.5 Selection of communication mode ..............................................................................................1097

31.4.6 Communication commands.........................................................................................................1098

31.4.7 Pin connection in on-board programming ...................................................................................1099

31.5 Rewriting by Self Programming.......................................................................................... 1103

31.5.1 Overview .....................................................................................................................................1103

31.5.2 Features......................................................................................................................................1104

31.5.3 Standard self programming flow .................................................................................................1105

31.5.4 Flash functions............................................................................................................................1106

31.5.5 Pin processing ............................................................................................................................1106

31.5.6 Internal resources used...............................................................................................................1107

CHAPTER 32 ON-CHIP DEBUG FUNCTION ................................................................................... 1108

32.1 Debugging with DCU ........................................................................................................... 1110

32.1.1 Connection circuit example .........................................................................................................1110

32.1.2 Interface signals ..........................................................................................................................1111

32.1.3 Mask function..............................................................................................................................1112

32.1.4 Registers.....................................................................................................................................1113

32.1.5 Operation ....................................................................................................................................1114

32.1.6 Cautions......................................................................................................................................1115

32.2 Debugging Without Using DCU .......................................................................................... 1116

32.2.1 Circuit connection examples .......................................................................................................1116

32.2.2 Mask function..............................................................................................................................1118

32.2.3 Allocation of user resources........................................................................................................1119

32.2.4 Cautions......................................................................................................................................1126

32.3 ROM Security Function ....................................................................................................... 1127

32.3.1 Security ID ..................................................................................................................................1127

32.3.2 Setting.........................................................................................................................................1128

CHAPTER 33 ELECTRICAL SPECIFICATIONS (μ PD70F3794, 70F3795, 70F3796) .................... 1129

33.1 Absolute Maximum Ratings ................................................................................................ 1129

33.2 Capacitance .......................................................................................................................... 1130

33.3 Operating Conditions .......................................................................................................... 1131

33.4 Oscillator Characteristics.................................................................................................... 1132

33.4.1 Main clock oscillator characteristics ............................................................................................1132

33.4.2 Subclock oscillator characteristics ..............................................................................................1136

33.4.3 PLL characteristics......................................................................................................................1138

33.4.4 Internal oscillator characteristics .................................................................................................1138

33.5 Regulator Characteristics ................................................................................................... 1139

33.6 DC Characteristics ............................................................................................................... 1140

33.6.1 Pin characteristics .......................................................................................................................1140

33.6.2 Supply current characteristics .....................................................................................................1142

33.6.3 Data retention characteristics (in STOP mode) ...........................................................................1143

33.7 AC Characteristics ............................................................................................................... 1144

33.7.1 Measurement conditions .............................................................................................................1144

33.7.2 CLKOUT output timing ................................................................................................................1145

33.7.3 Bus timing ...................................................................................................................................1146

33.7.4 Power on/power off/reset timing..................................................................................................1153

33.8 Peripheral Function Characteristics .................................................................................. 1154

33.8.1 Interrupt timing ............................................................................................................................1154

33.8.2 Key return timing.........................................................................................................................1154

33.8.3 Timer timing ................................................................................................................................1154

33.8.4 UART timing................................................................................................................................1155

33.8.5 CSIB timing .................................................................................................................................1155

33.8.6 I2C bus mode...............................................................................................................................1157

33.8.7 A/D converter ..............................................................................................................................1158

33.8.8 D/A converter ..............................................................................................................................1159

33.8.9 LVI circuit characteristics ............................................................................................................1159

33.8.10 RTC back-up mode characteristics ...........................................................................................1160

33.9 Flash Memory Programming Characteristics ................................................................... 1161

CHAPTER 34 ELECTRICAL SPECIFICATIONS (

PD70F3843, 70F3844)..................................... 1163

34.1 Absolute Maximum Ratings ................................................................................................ 1163

34.2 Capacitance .......................................................................................................................... 1164

34.3 Operating Conditions .......................................................................................................... 1165

34.4 Oscillator Characteristics.................................................................................................... 1166

34.4.1 Main clock oscillator characteristics ............................................................................................1166

34.4.2 Subclock oscillator characteristics ..............................................................................................1170

34.4.3 PLL characteristics......................................................................................................................1172

34.4.4 Internal oscillator characteristics .................................................................................................1172

34.5 Regulator Characteristics ................................................................................................... 1173

34.6 DC Characteristics ............................................................................................................... 1174

34.6.1 Pin characteristics .......................................................................................................................1174

34.6.2 Supply current characteristics .....................................................................................................1176

34.6.3 Data retention characteristics (in STOP mode) ...........................................................................1177

34.7 AC Characteristics ............................................................................................................... 1178

34.7.1 Measurement conditions .............................................................................................................1178

34.7.2 CLKOUT output timing ................................................................................................................1179

34.7.3 Bus timing ...................................................................................................................................1180

34.7.4 Power on/power off/reset timing..................................................................................................1187

34.8 Peripheral Function Characteristics .................................................................................. 1188

34.8.1 Interrupt timing ............................................................................................................................1188

34.8.2 Key return timing.........................................................................................................................1188

34.8.3 Timer timing ................................................................................................................................1188

34.8.4 UART timing................................................................................................................................1189

34.8.5 CSIB timing .................................................................................................................................1189

34.8.6 I2C bus mode...............................................................................................................................1191

34.8.7 A/D converter ..............................................................................................................................1192

34.8.8 D/A converter ..............................................................................................................................1193

34.8.9 LVI circuit characteristics ............................................................................................................1193

34.8.10 RTC back-up mode characteristics ...........................................................................................1194

34.9 Flash Memory Programming Characteristics ................................................................... 1195

CHAPTER 35 PACKAGE DRAWINGS .............................................................................................. 1197

CHAPTER 36 RECOMMENDED SOLDERING CONDITIONS......................................................... 1199

APPENDIX A DEVELOPMENT TOOLS............................................................................................. 1201

A.1 Software Package ................................................................................................................ 1203

A.2 Language Processing Software ......................................................................................... 1203

A.3 Control Software .................................................................................................................. 1203

A.4 Debugging Tools (Hardware) .............................................................................................. 1204

A.4.1 When using IECUBE QB-V850ESJX3L ......................................................................................1204

A.4.2 When using MINICUBE QB-V850MINI .......................................................................................1207

A.4.3 When using MINICUBE2 QB-MINI2............................................................................................1208

A.5 Debugging Tools (Software) ............................................................................................... 1209

A.6 Embedded Software............................................................................................................. 1210

A.7 Flash Memory Writing Tools ............................................................................................... 1211

APPENDIX B MAJOR DIFFERENCES BETWEEN PRODUCTS..................................................... 1212

APPENDIX C REGISTER INDEX ....................................................................................................... 1215

APPENDIX D INSTRUCTION SET LIST ........................................................................................... 1234

D.1 Conventions.......................................................................................................................... 1234

D.2 Instruction Set (in Alphabetical Order) .............................................................................. 1237

V850ES/JG3-L (on-chip USB controller) RENESAS MCU

R01UH0001EJ0300

Rev.3.00

Aug 3, 2012

CHAPTER 1 INTRODUCTION

The V850ES/JG3-L is one of the products in the Renesas Electronics V850 single-chip microcontroller series designed

for low-power operation for real-time control applications.

1.1 General

The V850ES/JG3-L is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions

such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a D/A converter, USB function controller.

In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/JG3-L features

multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware multiplier,

as optimum instructions for digital servo control applications. Moreover, as a real-time control system, the V850ES/JG3-L

enables an extremely high cost-performance for applications that require USB function controller, such as PC peripheral

device, ECR peripheral device, and industrial instrument.

R01UH0001EJ0300 Rev.3.00 Page 21 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

Table 1-1. V850ES/JG3-L Product List

Generic Name Part Number

Internal memory

PD70F3794

Flash memory

256 KB 384 KB 512 KB 768 KB 1 MB

RAM 40 KB

PD70F3795

Logical space 64 MB Memory

<R>

space

External bus interface Address bus: 6

External memory area 13 MB

Address data bus: 16 Multiplexed bus mode

General-purpose register

Clock

Main clock (oscillation frequency)

32 bits × 32 registers

Ceramic/crystal (in PLL mode: f

X = 2.5 to 6 MHz (multiplied by 4/8), in clock through mode: fX = 2.5 to 10 MHz)

External clock

X = 2.5 to 6 MHz (multiplied by 4/8), in clock through mode: fX = 2.5 to 6 MHz

Subclock

(in PLL mode: f

Crystal (fXT = 32.768 kHz)

(oscillation frequency)

Internal oscillator fR = 220 kHz (TYP.)

Minimum instruction execution time

50 ns (main clock (f

62.5 ns (main clock (f

XX) = 20 MHz: When USB is not used)

XX) = 16 MHz: When USB is used)

I/O port I/O: 80 (5 V tolerant/N-ch open-drain output selectable: 28)

Timer

16-bit TMP 6 channels

16-bit TMQ 1 channel

16-bit TMM 1 channel

Watch timer 1 channel

RTC 1 channel

WDT 1 channel

Real-time output port

4 bits × 1 channel, 2 bits × 1 channel, or 6 bits × 1 channel

10-bit A/D converter 12 channels

8-bit D/A converter 2 channels

Serial interface

CSIB 3 channels

UARTA/CSIB 1 channel

CSIB/I2C bus 1 channel

UARTA/I2C bus 2 channels

UARTA 3 channels

UARTC 1 channel

USB function 1 channel

DMA controller 4 channels (transfer target: on-chip peripheral I/O,

internal RAM, external memory)

Interrupt source

External

Internal 55

Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE/

low-voltage STOP/low-voltage subclock/low-voltage sub-IDLE mode/RTC backup mode

Reset source RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)

CRC function 16-bit error detection code generated for 8-bit unit data

On-chip debug

MINICUBE

, MINICUBE2 supported

Operating power supply voltage 2.0 V@2.5 MHz, 2.2 V@5 MHz, 2.7 V@20 MHz, 3.0 V to 3.6 V (USB operating)

Operating ambient temperature

Package

−40 to +85°C 100-pin LQFP (14 × 14 mm)

121-pin FBGA (8 × 8 mm)

Notes1. Including 24 KB of expanded internal RAM area.

2. The figure in parentheses indicates the number of external interrupts that can release the STOP mode.

V850ES/JG3-L

PD70F3796

9 (9)

Note

PD70F3843

80 KB

4 channels (transfer target: on-chip

peripheral I/O, internal RAM, expanded

internal RAM external memory)

PD70F3844

Note1

R01UH0001EJ0300 Rev.3.00 Page 22 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

1.2 Features

<R>

{ Minimum instruction execution time: 50 ns (operating on main clock (f (In PLL mode: ×4 : 5 MHz)

62.5 ns (operating on main clock (f

(In PLL mode: ×8, 1/3 : 6 MHz)

200 ns (operating on main clock (f

(In clock-through mode)

400 ns (operating on main clock (f

(In clock-through mode)

30.5

s (operating on subclock (fXT) of 32.768 kHz: VDD = 2.0 to 3.6 V)

{ General-purpose registers: 32 bits × 32 registers { CPU features: Signed multiplication (16 × 16 → 32): 1 to 2 clocks

Signed multiplication (32 × 32 → 64): 1 to 5 clocks

Saturated operations (overflow and underflow detection functions included)

Most instructions can be executed in 1 clock cycle by using 32-bit RISC-based 5-stage

pipeline architecture

Instruction fetching from internal ROM and accessing internal RAM for data can be

executed separately, by using Harvard architecture

High code efficiency achieved by using variable length instructions

32-bit shift instruction: 1 clock cycle

Bit manipulation instructions

Load/store instructions with long/short format

{ Memory space: 64 MB of linear address space (for programs and data)

External expansion: Up to 16 MB (including 1 MB used as internal ROM/RAM)

• Internal memory: RAM: 40 K/80 KB (see Table 1-1)

Flash memory: 256 K/384 K/512 K/768 K/1 MB (see Table 1-1)

• External bus interface: Multiplexed bus mode

8/16 bit data bus sizing function

Wait function

• Programmable wait function

• External wait function

Idle state function

Bus hold function

{ Interrupts and exceptions:

Internal external:

maskable Non-

maskable

PD70F3794 1 54 55 1 8 9

PD70F3795 1 54 55 1 8 9

PD70F3796 1 54 55 1 8 9

PD70F3843 1 54 55 1 8 9

PD70F3844 1 54 55 1 8 9

total maskable Non-

XX) of 20 MHz: VDD = 2.7 to 3.6 V)

XX) of 16 MHz: VDD = 3.0 to 3.6 V)

XX) of 5 MHz: VDD = 2.2 to 3.6 V)

XX) of 2.5 MHz: VDD = 2.0 to 3.6 V)

total

maskable

Software exceptions: 32 sources

Exception trap: 2 sources

{ Ports: I/O ports: 80

{ Timer function: 16-bit interval timer M (TMM): 1 channel

16-bit timer/event counter P (TMP): 6 channels

R01UH0001EJ0300 Rev.3.00 Page 23 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

16-bit timer/event counter Q (TMQ): 1 channel

Watch timer: 1 channel

Watchdog timer: 1 channel

{ Real-time counter: 1 channel { Real-time output port: 6 bits × 1 channel

{ Serial interface: Asynchronous serial interface A (UARTA)

3-wire variable-length serial interface B (CSIB)

C bus interface (I2C)

UARTA/CSIB: 1 channel

UARTA/I

CSIB/I2C: 1 channel

CSIB: 3 channels

UARTA: 3 channels

UARTC: 1 channel

USB function: 1 channel

{ A/D converter: 10-bit resolution: 12 channels

{ D/A converter: 8-bit resolution: 2 channels

{ DMA controller: 4 channels

{ DCU (debug control unit): JTAG interface

{ Clock generator: During main clock or subclock operation

7-level CPU clock (f

Clock-through mode/PLL mode selectable

{ Internal oscillator clock: 220 kHz (TYP.)

{ Power-save functions: HALT/IDLE1/IDLE2/STOP/low-voltage STOP/subclock/sub-IDLE/

low-voltage subclock/low-voltage sub-IDLE mode/RTC backup mode

{ Package: 100-pin plastic LQFP (fine pitch) (14 × 14) 121-pin plastic FBGA (8 × 8)

{ Power supply voltage: V

DD = 2.0 V to 3.6 V (2.5 MHz)

VDD = 2.2 V to 3.6 V (5 MHz)

DD = 2.7 V to 3.6 V (20 MHz)

DD = 3.0 V to 3.6 V (USB operating)

C: 2 channels

XX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)

R01UH0001EJ0300 Rev.3.00 Page 24 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

1.3 Application Fields

Equipment requiring a USB interfaces such as PC peripheral device, ECR peripheral device (bar code scanner, IC card reader/writer, printer, etc), industrial instrument, etc

1.4 Ordering Information

Part Number Package Internal Flash Memory

PD70F3794GC-UEU-AX

PD70F3795GC-UEU-AX

PD70F3796GC-UEU-AX

PD70F3843GC-UEU-AX

PD70F3844GC-UEU-AX

PD70F3794F1-CAH-A

PD70F3795F1-CAH-A

PD70F3796F1-CAH-A

PD70F3843F1-CAH-A

PD70F3844F1-CAH-A

Remark The V850ES/JG3-L is a lead-free product.

100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic LQFP (fine pitch) (14 × 14) 121-pin plastic FBGA (8 × 8 ) 121-pin plastic FBGA (8 × 8 ) 121-pin plastic FBGA (8 × 8 ) 121-pin plastic FBGA (8 × 8 ) 121-pin plastic FBGA (8 × 8 )

256 KB

384 KB

512 KB

768 KB

1 MB

256 KB

384 KB

512 KB

768 KB

1 MB

R01UH0001EJ0300 Rev.3.00 Page 25 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

1.5 Pin Configuration (Top View)

100-pin plastic LQFP (fine pitch) (14 × 14)

PD70F3794GC-UEU-AX

PD70F3843GC-UEU-AX

<R>

PD70F3795GC-UEU-AX

PD70F3844GC-UEU-AX

P70/ANI0

P71/ANI1

P72/ANI2

P73/ANI3

P74/ANI4

P75/ANI5

P76/ANI6

P77/ANI7

P78/ANI8

P79/ANI9

P710/ANI10

PD70F3796GC-UEU-AX

P711/ANI11

PDH1/A17

PDH0/A16

PDL15/AD15

PDL14/AD14

PDL13/AD13

PDL12/AD12

PDL11/AD11

PDL10/AD10

PDL9/AD9

PDL8/AD8

PDL7/AD7

PDL6/AD6

PDL5/AD5/FLMD1

REF0

AV P10/ANO0 P11/ANO1

REF1

PDH4/A20

P02/NMI/A21

Note 1

FLMD0

Note 2

REGC

X1 X2

RESET

XT1 XT2

P03/INTP0/ADTRG/UCLK/RTC1HZ

P04/INTP1/RTCDIV/RTCCL

P05/INTP2/DRST

P40/SIB0/SDA01

P41/SOB0/SCL01

P30/TXDA0/SOB4

P06/INTP3

P42/SCKB0

9998979695949392919089888786858483828180797877

100

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26272829303132333435363738394041424344454647484950

UDPF

UDMF

P36/TXDA3

P37/RXDA3

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

PDL4/AD4 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 EV

PCT6/ASTB PCT4/RD PCT1/WR1 PCT0/WR0 PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PDH3/A19 PDH2/A18 P915/INTP6/TIP50/TOP50 P914/INTP5/TIP51/TOP51 P913/INTP4 P912/SCKB3 P911/SOB3 P910/SIB3 P99/SCKB1 P98/SOB1

P38/TXDA2/SDA00

P39/RXDA2/SCL00

P31/RXDA0/INTP7/SIB4

P50/TIQ01/KR0/TOQ01/RTP00

P32/ASCKA0/SCKB4/TIP00/TOP00

P51/TIQ02/KR1/TOQ02/RTP01

P52/TIQ03/KR2/TOQ03/RTP02/DDI

P90/KR6/TXDA1/SDA02

P91/KR7/RXDA1/SCL02

P93/TIP40/TOP40RXDA4

P92/TIP41/TOP41/TXDA4

P94/TIP31/TOP31/TXDA5

P96/TXDC0/TIP21/TOP21

P54/SOB2/KR4/RTP04/DCK

P55/SCKB2/KR5/RTP05/DMS

P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO

P95/TIP30/TOP30/RXDA5

P97/SIB1/RXDC0/TIP20/TOP20

Notes 1. The FLMD0 pin is used in flash programming. Connect this pin to VSS in the normal operation mode.

2. Connect the REGC pin to V

SS via a 4.7

F (recommended value) capacitor.

R01UH0001EJ0300 Rev.3.00 Page 26 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

121-pin plastic FBGA (8 × 8)

PF70F3794F1-CAH-A

PF70F3843F1-CAH-A

PF70F3795F1-CAH-A

PF70F3844F1-CAH-A

Top View Bottom View

11 10

PF70F3796F1-CAH-A

9 8 7 6 5 4 3 2 1

Index mark

HGFE

KLL

DEFG

Index mark

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

A1 AVREF0 C1 AVSS E1 REGC

A2 AVREF0 C2 AVSS E2 REGC

A3 P70/ANI0 C3 P72/ANI2 E3 P10/ANO0

A4 P74/ANI4 C4 P76/ANI6 E4 P11/ANO1

A5 P78/ANI8 C5 P710/ANI10 E5 EVSS

A6 EVSS C6 PDH0/A16 E6 EVSS

A7 PDL11/AD11 C7 PDL13/AD13 E7 EVSS

A8 PDL8/AD8 C8 PDL10/AD10 E8 PCT0/WR0

A9 PDL6/AD6 C9 PDL2/AD2 E9 PCM3/HLDRQ

A10 PDL5/AD5/FLMD1 C10 PDL1/AD1 E10 PCM2/HLDAK

A11 EVDD C11 PDL0/AD0 E11 EVSS

B1 AVREF0 D1 VDD F1 X1

B2 AVREF1 D2 RVDD F2 X2

B3 P71/ANI1 D3 P73/ANI3 F3 FLMD0

B4 P75/ANI5 D4 P77/ANI7 F4 PDH4/A20

B5 P79/ANI9 D5 P711/ANI11 F5 EVSS

B6 PDL15/AD15 D6 PDH1/A17 F6 EVSS

B7 PDL12/AD12 D7 PDL14/AD14 F7 EVSS

B8 PDL9/AD9 D8 PCT6/ASTB F8 PDH3/A19

B9 PDL7/AD7 D9 PCT4/RD F9 PDH2/A18

B10 PDL4/AD4 D10 PCT1/WR1 F10 PCM1/CLKOUT

B11 PDL3/AD3 D11 EVDD F11 PCM0/WAIT

Note 1

Note 2

(1/2)

Notes 1. Connect the E1 and E2 pins by using the shortest possible pattern and connect them to VSS via a 4.7 μF

(recommended value) capacitor.

2. The FLMD0 pin is used in flash programming. Connect this pin to V

SS in the normal operation mode.

R01UH0001EJ0300 Rev.3.00 Page 27 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

<R>

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

G1 VSS H9 P911/SOB3 K6 UVDD

G2 VSS H10 P910/SIB3 K7

G3 P03/INTP0/ADTRG/UCLK/

RTC1HZ

G4 PDH5/NMI/A21 J1 VSS K9 P92/TIP41/TOP41/TXDA4

G5 EVSS J2 IC

G6 EVSS J3 P05/INTP2/DRST K11 P96/TXDC0/TIP21/TOP21

G7 EVSS J4 P06/INTP3 L1 EVSS

G8 P915/INTP6/TIP50/TOP50 J5 EVSS L2 P42/SCKB0

G9 P914/INTP5/TIP51/TOP51 J6 P37/RXDA3 L3 P30/TXDA0/SOB4

G10 P913/INTP4 J7 P52/TIQ03/KR2/TOQ03

G11 P912/SCKB3 J8 P55/SCKB2/KR5/RTP05/DMS L5 EVSS

H1 XT1 J9 P93/TIP40/TOP40/RXDA4 L6 EVDD

H2 XT2 J10 P98/SOB1 L7

H3 RESET J11 P97/SIB1/RXDC0/TIP20/

H4 P04/INTP1/RTCDIV/RTCCL K1 P40/SIB0/SDA01 L9 P91/KR7/RXDA1/SCL02

H5 P36/TXDA3 K2 P41/SOB0/SCL01 L10 P94/TIP31/TOP31/TXDA5

H6 P38/TXDA2/SDA00 K3 P31/RXDA0/INTP7/SIB4 L11 EVDD

H7 P39/RXDA2/SCL00 K4 UDMF − −

H8 P90/KR6/TXDA1/SDA02 K5 UDPF − −

H11 P99/SCKB1 K8 P54/SOB2/KR4/RTP04/DCK

Note

K10 P95/TIP30/TOP30/RXDA5

L4 P32/ASCKA0/SCKB4/TIP00

/RTP02/DDI

L8 P53/SIB2/KR3/TIQ00/TOQ00

TOP20

P51/TIQ02/KR1/

/TOP00

P50/TIQ01/KR0/TOQ01/RTP00

/RTP03/DDO

TOQ02

(2/2)

/RTP01

Note Be sure to open.

R01UH0001EJ0300 Rev.3.00 Page 28 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

Pin functions

<R>

A16 to A21:

AD0 to AD15:

ADTRG:

ANI0 to ANI11:

ANO0, ANO1:

ASCKA0:

ASTB:

REF0, AVREF1:

AVSS:

CLKOUT:

DCK:

DDI:

DDO:

DMS:

DRST:

DD:

SS:

FLMD0, FLMD1:

HLDAK:

HLDRQ:

IC:

INTP0 to INTP7:

KR0 to KR7:

NMI:

P02 to P06:

P10, P11:

P30 to P32:

P36 to P39

P40 to P42:

P50 to P55:

P70 to P711:

P90 to P915:

PCM0 to PCM3:

PCT0, PCT1,

PCT4, PCT6:

PDH0 to PDH4

PDL0 to PDL15:

RD:

REGC:

RESET:

Address bus

Address/data bus

A/D trigger input

Analog input

Analog output

Asynchronous serial clock

Address strobe

Analog reference voltage

Analog V

Clock output

Debug clock

Debug data input

Debug data output

Debug mode select

Debug reset

Power supply for external pin

Ground for external pin

Flash programming mode

Hold acknowledge

Hold request

Internal Connected

External interrupt input

Key return

Non-maskable interrupt request

Port 0

Port 1

Port 3

Port 4

Port 5

Port 7

Port 9

Port CM

Port CT

Port DH

Port DL

Read strobe

Regulator control

Reset

RTC1HZ,

RTCCL, RTCDIV

RTP00 to RTP05:

RXDA0 to RXDA5:

RXDC0:

SCKB0 to SCKB4:

SCL00 to SCL02:

SDA00 to SDA02:

SIB0 to SIB4:

SOB0 to SOB4:

TIP00,

TIP20, TIP21,

TIP30, TIP31,

TIP40, TIP41,

TIP50, TIP51,

TIQ00 to TIQ03:

TOP00,

TOP20, TOP21,

TOP30, TOP31,

TOP40, TOP41,

TOP50, TOP51,

TOQ00 to TOQ03:

TXDA0 to TXDA5:

TXDC0:

UCLK:

UDMF:

UDPF:

DD:

VDD:

SS:

WAIT:

WR0:

WR1:

X1, X2:

XT1, XT2:

Real-time Counter Clock Output

Real-time output port

Power Supply for RTC

Receive data

Serial clock

Serial data

Serial input

Serial output

Timer input

Timer output

Transmit data

USB clock USB data I/O (−) function

USB data I/O (+) function

Power supply for external USB

Power supply

Ground

Wait

Lower byte write strobe

Upper byte write strobe

Crystal for main clock

Crystal for subclock

R01UH0001EJ0300 Rev.3.00 Page 29 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

1.6 Function Block Configuration

1.6.1 Internal block diagram

<R>

Timer/counter function

TIP00, TIP20 to TIP50,

TIP21 to TIP51

TOP00, TOP20 to TOP50,

TOP21 to TOP51

TIQ00 to TIQ03

TOQ00 to TOQ03

16-bit timer/

event counter P:

5 ch

16-bit timer/

event counter Q:

1 ch

16-bit interval

timer M:

1 ch

Watchdog

timer 2: 1ch

Watch timer:

1ch

ROM RAM

Note 1

CPU

Multiplier

16 × 16 → 32

ALU

32-bit barrel

registers 32 bits × 32

Note 2

shifter

System

registers

General-purpose

DMA

BCU

HLDRQ

HLDAK ASTB

WAIT

WR0, WR1 A16 to A21 AD0 to AD15

Expanded

internal RAM

Note 3

(24KB)

RTC1HZ RTCCL RTCDIV

RTP00 to RTP05 RTO : 1 ch

Serial interface function

SOB0 to SOB4

SIB0 to SIB4

SCKB0 to SCKB4

SDA00 to SDA02

SCL00 to SCL02

TXDA0 to TXDA5

RXDA0 to RXDA5

ASCKA0

TXDC0

RXDC0

UDMF UDPF

Real-time

counter:

1 ch

CSIB: 5 ch

C: 3 ch

UARTA:

6 ch

UARTC:

1 ch

USB function

CRC

Ports

P50 to P55

P40 to P42

P90 to P915

P70 to P711

PDH0 to PDH4

PCM0 to PCM3

PDL0 to PDL15

PCT0, PCT1, PCT4, PCT6

Interrupt function

INTC

Key interrupt

function

Debug function

DCU

P30 to P32, P36 to P39

NMI

INTP0 to INTP7

KR0 to KR7

DRST

DMS

DDI

DCK

DDO

converter

P10, P11

P02 to P06

REF1

A/D

converter

ADTRG

D/A

ANO0, ANO1

REF0

ANI0 to ANI11

Regulator

Flash

controller

UV EV EV

PLL

Internal

oscillator

CLM

LVI

Regulator

CLKOUT X1 X2 XT1 XT2 RESET

FLMD0 FLMD1

REGC

Notes1.

PD70F3794: 256 KB

PD70F3795: 384 KB

μPD70F3796: 512 KB

PD70F3843: 768 KB

PD70F3844: 1 MB

PD70F3794, 70F3795, 70F3796: 40 KB

PD70F3843, 70F3844: 56 KB

PD70F3843, 70F3844 only

R01UH0001EJ0300 Rev.3.00 Page 30 of 1248 Aug 3, 2012

+ 1218 hidden pages

Renesas V850ES/JG3-L User’s Manual: Hardware

Specifications and Main Features

Frequently Asked Questions

User Manual

Notice

NOTES FOR CMOS DEVICES

How to Use This Manual

Table of Contents

CHAPTER 1 INTRODUCTION

1.1 General

1.2 Features

1.3 Application Fields

1.4 Ordering Information

1.5 Pin Configuration (Top View)

1.6 Function Block Configuration

1.6.1 Internal block diagram