Renesas V850ES/JG3-L User’s Manual: Hardware

User’s Manual

V850ES/JG3-L (on-chip USB controller)

User’s Manual: Hardware

RENESAS MCU V850ES/Jx3-L Microcontrollers

μ PD70F3794 μPD70F3795 μPD70F3796 μPD70F3843 μPD70F3844

All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com).

www.renesas.com

Rev.3.00 Aug 2012

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

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“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

crime systems; and safety equipment etc.

Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.

6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you.

8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-

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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

(2012.4)

NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V

(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

(MAX) and VIH (MIN) due to noise, etc., the device may

(MAX) and

or GND

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

How to Use This Manual

Readers This manual is intended for users who wish to understand the functions of the

V850ES/JG3-L and design application systems using these products.

Purpose This manual is intended to give users an understanding of the hardware functions of the

V850ES/JG3-L shown in the Organization below.

Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES

Architecture User’s Manual).

Hardware Architecture

• Pin functions • Data types

• CPU function • Register set

• On-chip peripheral functions • Instruction format and instruction set

• Flash memory programming • Interrupts and exceptions

• Electrical specifications • Pipeline operation

How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of

electrical engineering, logic circuits, and microcontrollers.

To understand the overall functions of the V850ES/JG3-L → Read this manual according to the CONTENTS.

To find the details of a register where the name is known → Use APPENDIX C REGISTER INDEX.

format of each register is defined as a reserved word in the device file.

To understand the details of an instruction function → Refer to the V850ES Architecture User’s Manual available separately.

To know the electrical specifications of the V850ES/JG3-L

→ See CHAPTER 33 ELECTRICAL SPECIFICATIONS (

70F3796)

CHAPTER 34 ELECTRICAL SPECIFICATIONS (

The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note with

caution that if “xxx.yyy” is described as is in a program, however, the compiler/assembler

cannot recognize it correctly.

PD70F3843, 70F3844)

PD70F3794, 70F3795,

The mark <R> shows major revised points. The revised points can be easily searched

by copying an “<R>” in the PDF file and specifying it in the “Find what: ” field.

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representation: xxx (overscore over pin or signal name)

Memory map address: Higher addresses on the top and lower addresses on the

bottom

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numeric representation: Binary ... xxxx or xxxxB

Decimal ... xxxx

Hexadecimal ... xxxxH

Prefix indicating power of 2 (address space, memory capacity):

K (kilo): 2

M (mega): 2

G (giga): 2

= 1,024

= 1,0242

= 1,024

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents related to V850ES/JG3-L

Document Name Document No.

V850ES Architecture User’s Manual U15943E

V850ES/JG3-L (on-chip USB controller) Hardware User’s Manual This manual

Documents related to development tools

Document Name Document No.

QB-V850ESJX3L In-Circuit Emulator To be prepared

QB-V850MINI, QB-V850MINIL On-Chip Debug Emulator U17638E

QB-MINI2 On-Chip Debug Emulator with Programming Function U18371E

CA850 Ver. 3.20 C Compiler Package

PM+ Ver. 6.30 Project Manager U18416E

ID850QB Ver. 3.40 Integrated Debugger Operation U18604E

SM850 Ver. 2.50 System Simulator Operation U16218E

SM850 Ver. 2.00 or Later System Simulator External Part User Open

RX850 Ver. 3.20 Real-Time OS

RX850 Pro Ver. 3.21 Real-Time OS

AZ850 Ver. 3.30 System Performance Analyzer U17423E

PG-FP5 Flash Memory Programmer U18865E

Operation U18512E

C Language U18513E

Assembly Language U18514E

Link Directives U18415E

U14873E

Interface Specification

Operation U18601E SM+ System Simulator

User Open Interface U18212E

Basics U13430E

Installation U17419E

Technical U13431E

Task Debugger U17420E

Basics U18165E

Installation U17421E

Task Debugger U17422E

Other Documents

Document Name Document No.

RENESAS MICROCOMPUTER GENERAL CATALOG R01CS0001E

Semiconductor Package Mount Manual

Quality Grades on Renesas Semiconductor Devices

Renesas Semiconductor Device Reliability/Quality Control System

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

Note

C11531E

C10983E

C11892E

Note See the “Semiconductor Package Mount Manual” website

(http://www.renesas.com/products/package/manual/index.jsp).

Caution The related documents listed above are subject to change without notice.

Be sure to use the latest version of each document when designing.

Caution: This product uses SuperFlash

technology licensed from Silicon Storage Technology, Inc.

IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany.

MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in

the United States of America.

EEPROM is a trademark of Renesas Electronics Corporation

Applilet is a registered trademark of Renesas Electronics in Japan, Germany, Hong Kong, China, the Republic of

Korea, the United Kingdom, and the United States of America.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United

States and/or other countries.

SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United

States and Japan.

PC/AT is a trademark of International Business Machines Corporation.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

TRON is an abbreviation of The Realtime Operating System Nucleus.

ITRON is an abbreviation of Industrial TRON.

CHAPTER 1 INTRODUCTION................................................................................................................. 21

1.1 General...................................................................................................................................... 21

1.2 Features .................................................................................................................................... 23

1.3 Application Fields .................................................................................................................... 25

1.4 Ordering Information ............................................................................................................... 25

1.5 Pin Configuration (Top View).................................................................................................. 26

1.6 Function Block Configuration................................................................................................. 30

1.6.1 Internal block diagram.....................................................................................................................30

1.6.2 Internal units ...................................................................................................................................31

CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 34

2.1 List of Pin Functions................................................................................................................ 34

2.2 Pin States.................................................................................................................................. 44

2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins......... 45

2.4 Cautions.................................................................................................................................... 49

CHAPTER 3 CPU FUNCTION ................................................................................................................ 50

3.1 Features .................................................................................................................................... 50

3.2 CPU Register Set...................................................................................................................... 51

3.2.1 Program register set .......................................................................................................................52

3.2.2 System register set .........................................................................................................................53

3.3 Operation Modes...................................................................................................................... 59

3.4 Address Space ......................................................................................................................... 60

3.4.1 CPU address space........................................................................................................................60

3.4.2 Memory map...................................................................................................................................61

3.4.3 Areas ..............................................................................................................................................63

3.4.4 Wraparound of data space..............................................................................................................70

3.4.5 Recommended use of address space.............................................................................................70

3.4.6 Peripheral I/O registers...................................................................................................................74

3.4.7 Special registers .............................................................................................................................85

3.4.8 Registers to be set first ...................................................................................................................89

3.4.9 Cautions..........................................................................................................................................90

CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 92

4.1 Features .................................................................................................................................... 92

4.2 Basic Port Configuration......................................................................................................... 92

4.3 Port Configuration ................................................................................................................... 93

4.3.1 Port 0 ..............................................................................................................................................99

4.3.2 Port 1 ............................................................................................................................................103

4.3.3 Port 3 ............................................................................................................................................105

4.3.4 Port 4 ............................................................................................................................................111

4.3.5 Port 5 ............................................................................................................................................113

4.3.6 Port 7 ............................................................................................................................................118

4.3.7 Port 9 ............................................................................................................................................120

4.3.8 Port CM.........................................................................................................................................128

4.3.9 Port CT .........................................................................................................................................130

4.3.10 Port DH .........................................................................................................................................132

4.3.11 Port DL..........................................................................................................................................134

4.4 Block Diagrams ...................................................................................................................... 137

4.5 Port Register Settings When Alternate Function Is Used.................................................. 169

4.6 Cautions.................................................................................................................................. 177

4.6.1 Cautions on setting port pins.........................................................................................................177

4.6.2 Cautions on bit manipulation instruction for port n register (Pn)....................................................180

4.6.3 Cautions on on-chip debug pins....................................................................................................181

4.6.4 Cautions on P05/INTP2/DRST pin................................................................................................181

4.6.5 Cautions on P10, P11, and P53 pins when power is turned on ....................................................181

4.6.6 Hysteresis characteristics .............................................................................................................181

CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 182

5.1 Features .................................................................................................................................. 182

5.2 Bus Control Pins .................................................................................................................... 183

5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed....................183

5.2.2 Pin status in each operation mode................................................................................................183

5.3 Memory Block Function ........................................................................................................ 184

5.4 Bus Access............................................................................................................................. 185

5.4.1 Number of clock cycles required for access..................................................................................185

5.4.2 Bus size setting function ...............................................................................................................186

5.4.3 Access according to bus size........................................................................................................187

5.5 Wait Function.......................................................................................................................... 194

5.5.1 Programmable wait function..........................................................................................................194

5.5.2 External wait function....................................................................................................................195

5.5.3 Relationship between programmable wait and external wait.........................................................196

5.5.4 Programmable address wait function............................................................................................197

5.6 Idle State Insertion Function................................................................................................. 198

5.7 Bus Hold Function ................................................................................................................. 199

5.7.1 Functional outline..........................................................................................................................199

5.7.2 Bus hold procedure.......................................................................................................................200

5.7.3 Operation in power save mode .....................................................................................................200

5.8 Bus Priority............................................................................................................................. 201

5.9 Bus Timing.............................................................................................................................. 202

CHAPTER 6 CLOCK GENERATOR .................................................................................................... 206

6.1 Overview ................................................................................................................................. 206

6.2 Configuration.......................................................................................................................... 207

6.3 Registers................................................................................................................................. 210

6.4 Operations .............................................................................................................................. 216

6.4.1 Operation of each clock ................................................................................................................216

6.4.2 Clock output function ....................................................................................................................217

6.4.3 External clock signal input.............................................................................................................217

6.5 PLL Function .......................................................................................................................... 217

6.5.1 Overview.......................................................................................................................................217

6.5.2 Registers.......................................................................................................................................218

6.5.3 Usage ...........................................................................................................................................222

6.6 How to Connect a Resonator................................................................................................ 223

6.6.1 Main clock oscillator......................................................................................................................223

6.6.2 Subclock oscillator ........................................................................................................................223

CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) ................................................................ 226

7.1 Overview ................................................................................................................................. 226

7.2 Configuration.......................................................................................................................... 227

7.2.1 Pins used by TMPn.......................................................................................................................229

7.2.2 Interrupts.......................................................................................................................................230

7.3 Registers................................................................................................................................. 231

7.4 Operations .............................................................................................................................. 243

7.4.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) ..................................................................250

7.4.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) ......................................................261

7.4.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) ..........................................270

7.4.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011)....................................................282

7.4.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) ...................................................................290

7.4.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) .........................................................299

7.4.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110)..............................................315

7.4.8 Timer output operations ................................................................................................................319

7.5 Selector ................................................................................................................................... 320

7.6 Cautions.................................................................................................................................. 321

CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)................................................................ 322

8.1 Functions ................................................................................................................................ 322

8.2 Configuration.......................................................................................................................... 323

8.2.1 Pins used by TMQ0 ......................................................................................................................325

8.2.2 Interrupts.......................................................................................................................................325

8.3 Registers................................................................................................................................. 326

8.4 Operations .............................................................................................................................. 341

8.4.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) .................................................................348

8.4.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) .....................................................360

8.4.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) .........................................370

8.4.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011)...................................................385

8.4.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) ..................................................................395

8.4.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101).........................................................406

8.4.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110).............................................426

8.4.8 Timer output operations ................................................................................................................431

8.5 Cautions.................................................................................................................................. 432

CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) ............................................................................ 433

9.1 Features .................................................................................................................................. 433

9.2 Configuration.......................................................................................................................... 434

9.3 Registers................................................................................................................................. 435

9.4 Operation ................................................................................................................................ 437

9.4.1 Interval timer mode .......................................................................................................................437

9.4.2 Cautions........................................................................................................................................441

CHAPTER 10 WATCH TIMER.............................................................................................................. 442

10.1 Functions ................................................................................................................................ 442

10.2 Configuration.......................................................................................................................... 443

10.3 Control Registers ................................................................................................................... 445

10.4 Operation ................................................................................................................................ 449

10.4.1 Watch timer operations .................................................................................................................449

10.4.2 Interval timer operations................................................................................................................450

10.5 Cautions .................................................................................................................................. 452

CHAPTER 11 REAL-TIME COUNTER................................................................................................. 453

11.1 Functions ................................................................................................................................ 453

11.2 Configuration.......................................................................................................................... 454

11.2.1 Pin configuration ...........................................................................................................................456

11.2.2 Interrupt functions .........................................................................................................................456

11.3 Registers ................................................................................................................................. 457

11.4 Operation ................................................................................................................................ 472

11.4.1 Initial settings ................................................................................................................................472

11.4.2 Rewriting each counter during real-time counter operation ...........................................................473

11.4.3 Reading each counter during real-time counter operation ............................................................474

11.4.4 Changing INTRTC0 interrupt setting during real-time counter operation ......................................475

11.4.5 Changing INTRTC1 interrupt setting during real-time counter operation ......................................476

11.4.6 Initial INTRTC2 interrupt settings ..................................................................................................477

11.4.7 Changing INTRTC2 interrupt setting during real-time counter operation ......................................478

11.4.8 Initializing real-time counter ..........................................................................................................479

11.4.9 Watch error correction example of real-time counter ....................................................................480

CHAPTER 12 WATCHDOG TIMER 2 ................................................................................................. 484

12.1 Functions ................................................................................................................................ 484

12.2 Configuration.......................................................................................................................... 485

12.3 Registers ................................................................................................................................. 486

12.4 Operation ................................................................................................................................ 488

CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO)................................................................... 489

13.1 Function .................................................................................................................................. 489

13.2 Configuration.......................................................................................................................... 490

13.3 Registers ................................................................................................................................. 492

13.4 Operation ................................................................................................................................ 494

13.5 Usage....................................................................................................................................... 495

13.6 Cautions .................................................................................................................................. 495

CHAPTER 14 A/D CONVERTER ......................................................................................................... 496

14.1 Overview ................................................................................................................................. 496

14.2 Functions ................................................................................................................................ 496

14.3 Configuration.......................................................................................................................... 497

14.4 Registers ................................................................................................................................. 500

14.5 Operation ................................................................................................................................ 511

14.5.1 Basic operation .............................................................................................................................511

14.5.2 Conversion timing .........................................................................................................................512

14.5.3 Trigger modes ...............................................................................................................................513

14.5.4 Operation mode ............................................................................................................................515

14.5.5 Power-fail compare mode .............................................................................................................521

14.6 Cautions .................................................................................................................................. 528

14.7 How to Read A/D Converter Characteristics Table ............................................................ 533

CHAPTER 15 D/A CONVERTER ......................................................................................................... 537

15.1 Functions ................................................................................................................................ 537

15.2 Configuration.......................................................................................................................... 538

15.3 Registers ................................................................................................................................. 539

15.4 Operation ................................................................................................................................ 541

15.4.1 Operation in normal mode.............................................................................................................541

15.4.2 Operation in real-time output mode...............................................................................................541

15.4.3 Cautions........................................................................................................................................542

CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ............................................. 543

16.1 Features .................................................................................................................................. 543

16.2 Configuration.......................................................................................................................... 544

16.2.1 Pin functions of each channel .......................................................................................................546

16.3 Mode Switching of UARTA and Other Serial Interfaces..................................................... 547

16.3.1 UARTA0 and CSIB4 mode switching ............................................................................................547

16.3.2 UARTA1 and I2C02 mode switching..............................................................................................548

16.3.3 UARTA2 and I2C00 mode switching..............................................................................................549

16.4 Registers ................................................................................................................................. 550

16.5 Interrupt Request Signals ..................................................................................................... 557

16.6 Operation ................................................................................................................................ 558

16.6.1 Data format ...................................................................................................................................558

16.6.2 UART transmission .......................................................................................................................560

16.6.3 Continuous transmission procedure..............................................................................................561

16.6.4 UART reception ............................................................................................................................563

16.6.5 Reception errors ...........................................................................................................................565

16.6.6 Parity types and operations...........................................................................................................567

16.6.7 LIN transmission/reception format ................................................................................................568

16.6.8 SBF transmission ..........................................................................................................................570

16.6.9 SBF reception ...............................................................................................................................571

16.6.10 Receive data noise filter..............................................................................................................572

16.7 Dedicated Baud Rate Generator ........................................................................................... 573

16.8 Cautions .................................................................................................................................. 581

CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) ............................................. 582

17.1 Features .................................................................................................................................. 582

17.2 Configuration.......................................................................................................................... 583

17.2.1 Pin functions of each channel .......................................................................................................585

17.3 Mode Switching of UARTC and Other Serial Interfaces..................................................... 586

17.3.1 UARTC0 and CSIB1 mode switching............................................................................................586

17.4 Registers ................................................................................................................................. 587

17.5 Interrupt Request Signals ..................................................................................................... 596

17.6 Operation ................................................................................................................................ 597

17.6.1 Data format ...................................................................................................................................597

17.6.2 UART transmission .......................................................................................................................599

17.6.3 Continuous transmission procedure..............................................................................................600

17.6.4 UART reception ............................................................................................................................602

17.6.5 Reception errors ...........................................................................................................................604

17.6.6 Parity types and operations...........................................................................................................606

17.6.7 LIN transmission/reception format ................................................................................................607

17.6.8 SBF transmission ..........................................................................................................................609

17.6.9 SBF reception ...............................................................................................................................610

17.6.10 Receive data noise filter..............................................................................................................611

17.7 Dedicated Baud Rate Generator ........................................................................................... 612

17.8 Cautions .................................................................................................................................. 620

CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)............................................................... 621

18.1 Features .................................................................................................................................. 621

18.2 Configuration.......................................................................................................................... 622

18.2.1 Pin functions of each channel .......................................................................................................623

18.3 Mode Switching of CSIB and Other Serial Interfaces......................................................... 624

18.3.1 CSIB0 and I2C01 mode switching .................................................................................................624

18.3.2 CSIB4 and UARTA0 mode switching ............................................................................................625

18.4 Registers ................................................................................................................................. 626

18.5 Interrupt Request Signals ..................................................................................................... 635

18.6 Operation ................................................................................................................................ 636

18.6.1 Single transfer mode (master mode, transmission mode).............................................................636

18.6.2 Single transfer mode (master mode, reception mode) ..................................................................638

18.6.3 Single transfer mode (master mode, transmission/reception mode) .............................................640

18.6.4 Single transfer mode (slave mode, transmission mode) ...............................................................642

18.6.5 Single transfer mode (slave mode, reception mode).....................................................................644

18.6.6 Single transfer mode (slave mode, transmission/reception mode)................................................647

18.6.7 Continuous transfer mode (master mode, transmission mode).....................................................649

18.6.8 Continuous transfer mode (master mode, reception mode) ..........................................................651

18.6.9 Continuous transfer mode (master mode, transmission/reception mode) .....................................654

18.6.10 Continuous transfer mode (slave mode, transmission mode) .....................................................658

18.6.11 Continuous transfer mode (slave mode, reception mode) ..........................................................660

18.6.12 Continuous transfer mode (slave mode, transmission/reception mode) .....................................663

18.6.13 Reception errors .........................................................................................................................666

18.6.14 Clock timing ................................................................................................................................667

18.7 Output Pins ............................................................................................................................. 669

18.8 Baud Rate Generator ............................................................................................................. 670

18.8.1 Baud rate generation ....................................................................................................................671

18.9 Cautions .................................................................................................................................. 672

CHAPTER 19 I2C BUS .......................................................................................................................... 673

19.1 Mode Switching of I2C Bus and Other Serial Interfaces..................................................... 673

19.1.1 UARTA2 and I2C00 mode switching..............................................................................................673

19.1.2 CSIB0 and I2C01 mode switching .................................................................................................674

19.1.3 UARTA1 and I2C02 mode switching..............................................................................................675

19.2 Features .................................................................................................................................. 676

19.3 Configuration.......................................................................................................................... 677

19.4 Registers ................................................................................................................................. 681

19.5 I2C Bus Mode Functions ........................................................................................................ 697

19.5.1 Pin configuration ...........................................................................................................................697

19.6 I2C Bus Definitions and Control Methods ............................................................................ 698

19.6.1 Start condition ...............................................................................................................................698

19.6.2 Addresses .....................................................................................................................................699

19.6.3 Transfer direction specification .....................................................................................................700

19.6.4 ACK ..............................................................................................................................................701

19.6.5 Stop condition ...............................................................................................................................702

19.6.6 Wait state ......................................................................................................................................703

19.6.7 Wait state cancellation method .....................................................................................................705

19.7 I2C Interrupt Request Signals (INTIICn)................................................................................ 706

19.7.1 Master device operation................................................................................................................706

19.7.2 Slave device operation (when receiving slave address data (address match)) .............................709

19.7.3 Slave device operation (when receiving extension code)..............................................................713

19.7.4 Operation without communication .................................................................................................717

19.7.5 Operation when arbitration loss occurs (operation as slave after arbitration loss) ........................717

19.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) ........................719

19.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control ........................ 726

19.9 Address Match Detection Method ........................................................................................ 728

19.10 Error Detection ....................................................................................................................... 728

19.11 Extension Code ...................................................................................................................... 728

19.12 Arbitration............................................................................................................................... 729

19.13 Wakeup Function ................................................................................................................... 730

19.14 Communication Reservation ................................................................................................ 731

19.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) ..........................731

19.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1)..........................735

19.15 Cautions.................................................................................................................................. 736

19.16 Communication Operations.................................................................................................. 737

19.16.1 Master operation in single master system...................................................................................738

19.16.2 Master operation in multimaster system .....................................................................................739

19.16.3 Slave operation...........................................................................................................................742

19.17 Timing of Data Communication............................................................................................ 745

CHAPTER 20 USB FUNCTION CONTROLLER (USBF) .................................................................. 752

20.1 Overview ................................................................................................................................. 752

20.2 Configuration.......................................................................................................................... 753

20.2.1 Block diagram ...............................................................................................................................753

20.2.2 USB memory map.........................................................................................................................754

20.3 External Circuit Configuration .............................................................................................. 755

20.3.1 Outline ..........................................................................................................................................755

20.3.2 Connection configuration ..............................................................................................................756

20.4 Cautions .................................................................................................................................. 758

20.5 Requests ................................................................................................................................. 759

20.5.1 Automatic requests .......................................................................................................................759

20.5.2 Other requests ..............................................................................................................................766

20.6 Register Configuration .......................................................................................................... 767

20.6.1 USB control registers ....................................................................................................................767

20.6.2 USB function controller register list ...............................................................................................768

20.6.3 EPC control registers ....................................................................................................................784

20.6.4 Data hold registers ........................................................................................................................836

20.6.5 EPC request data registers ...........................................................................................................859

20.6.6 Bridge register...............................................................................................................................874

20.6.7 DMA register .................................................................................................................................878

20.6.8 Bulk-in register ..............................................................................................................................882

20.6.9 Bulk-out register ............................................................................................................................883

20.6.10 Peripheral control registers .........................................................................................................885

20.7 STALL Handshake or No Handshake................................................................................... 889

20.8 Register Values in Specific Status ....................................................................................... 890

20.9 FW Processing ....................................................................................................................... 892

20.9.1 Initialization processing .................................................................................................................894

20.9.2 Interrupt servicing .........................................................................................................................897

20.9.3 USB main processing ...................................................................................................................898

20.9.4 Suspend/Resume processing .......................................................................................................924

20.9.5 Processing after power application ...............................................................................................927

20.9.6 Receiving data for bulk transfer (OUT) in DMA mode ...................................................................930

20.9.7 Transmitting data for bulk transfer (IN) in DMA mode ...................................................................935

CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) ................................................................... 940

21.1 Features .................................................................................................................................. 940

21.2 Configuration.......................................................................................................................... 941

21.3 Registers ................................................................................................................................. 943

21.4 Transfer Sources and Destinations ..................................................................................... 951

21.5 Transfer Modes ...................................................................................................................... 951

21.6 Transfer Types ....................................................................................................................... 952

21.7 DMA Channel Priorities ......................................................................................................... 953

21.8 Time Related to DMA Transfer.............................................................................................. 954

21.9 DMA Transfer Start Factors .................................................................................................. 955

21.10 DMA Abort Factors ................................................................................................................ 956

21.11 End of DMA Transfer ............................................................................................................. 956

21.12 Operation Timing.................................................................................................................... 956

21.13 Cautions.................................................................................................................................. 961

CHAPTER 22 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION......................... 966

22.1 Features .................................................................................................................................. 966

22.2 Non-Maskable Interrupts ....................................................................................................... 970

22.2.1 Operation ......................................................................................................................................972

22.2.2 Restoration....................................................................................................................................973

22.2.3 NP flag ..........................................................................................................................................974

22.3 Maskable Interrupts ............................................................................................................... 975

22.3.1 Operation ......................................................................................................................................975

22.3.2 Restoration....................................................................................................................................977

22.3.3 Priorities of maskable interrupts ....................................................................................................978

22.3.4 Interrupt control register (xxICn) ...................................................................................................982

22.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) .............................................................................984

22.3.6 In-service priority register (ISPR) ..................................................................................................986

22.3.7 ID flag ...........................................................................................................................................987

22.3.8 Watchdog timer mode register 2 (WDTM2)...................................................................................987

22.4 Software Exception................................................................................................................ 988

22.4.1 Operation ......................................................................................................................................988

22.4.2 Restoration....................................................................................................................................989

22.4.3 EP flag ..........................................................................................................................................990

22.5 Exception Trap ....................................................................................................................... 991

22.5.1 Illegal opcode ................................................................................................................................991

22.5.2 Debug trap ....................................................................................................................................993

22.6 Multiple Interrupt Servicing Control..................................................................................... 995

22.7 External Interrupt Request Input Pins (NMI, INTP0 to INTP7) ........................................... 996

22.7.1 Noise elimination...........................................................................................................................996

22.7.2 Edge detection ..............................................................................................................................996

22.8 Interrupt Response Time of CPU........................................................................................ 1002

22.9 Periods in Which Interrupts Are Not Acknowledged by CPU ......................................... 1003

22.10 Cautions................................................................................................................................ 1003

22.10.1 Restored PC .............................................................................................................................1003

CHAPTER 23 KEY INTERRUPT FUNCTION ................................................................................... 1004

23.1 Function ................................................................................................................................ 1004

23.2 Pin Functions........................................................................................................................ 1005

23.3 Registers ............................................................................................................................... 1005

23.4 Cautions ................................................................................................................................ 1006

CHAPTER 24 STANDBY FUNCTION ................................................................................................ 1007

24.1 Overview ............................................................................................................................... 1007

24.2 Registers ............................................................................................................................... 1009

24.3 HALT Mode ........................................................................................................................... 1014

24.3.1 Setting and operation status .......................................................................................................1014

24.3.2 Releasing HALT mode ................................................................................................................1014

24.4 IDLE1 Mode........................................................................................................................... 1016

24.4.1 Setting and operation status .......................................................................................................1016

24.4.2 Releasing IDLE1 mode ...............................................................................................................1017

24.5 IDLE2 Mode........................................................................................................................... 1019

24.5.1 Setting and operation status .......................................................................................................1019

24.5.2 Releasing IDLE2 mode ...............................................................................................................1020

24.5.3 Securing setup time when releasing IDLE2 mode.......................................................................1022

24.6 STOP Mode/Low-Voltage STOP Mode ............................................................................... 1023

24.6.1 Setting and operation status .......................................................................................................1023

24.6.2 Releasing STOP mode/low-voltage STOP mode........................................................................1027

24.6.3 Re-setting after release of low-voltage STOP mode ...................................................................1028

24.6.4 Securing oscillation stabilization time when releasing STOP mode ............................................1029

24.7 Subclock Operation Mode/Low-Voltage Subclock Operation Mode .............................. 1030

24.7.1 Setting and operation status .......................................................................................................1030

24.7.2 Releasing subclock operation mode ...........................................................................................1034

24.7.3 Releasing low-voltage subclock operation mode ........................................................................1034

24.8 Sub-IDLE Mode/Low-Voltage Sub-IDLE Mode .................................................................. 1035

24.8.1 Setting and operation status .......................................................................................................1035

24.8.2 Releasing sub-IDLE mode/low-voltage sub-IDLE mode .............................................................1038

24.9 RTC backup Mode ................................................................................................................ 1039

24.9.1 Registers ....................................................................................................................................1039

24.9.2 RTC backup mode setting conditions..........................................................................................1041

24.9.3 RTC backup mode setting procedure..........................................................................................1042

CHAPTER 25 RESET FUNCTION...................................................................................................... 1049

25.1 Overview ............................................................................................................................... 1049

25.2 Configuration........................................................................................................................ 1050

25.3 Register to Check Reset Source ........................................................................................ 1051

25.4 Operation .............................................................................................................................. 1052

25.4.1 Reset operation via RESET pin ..................................................................................................1052

25.4.2 Reset operation by watchdog timer 2..........................................................................................1055

25.4.3 Reset operation by low-voltage detector .....................................................................................1057

25.4.4 Operation immediately after reset ends ......................................................................................1058

25.4.5 Reset function operation .............................................................................................................1060

25.5 Cautions ................................................................................................................................ 1061

CHAPTER 26 CLOCK MONITOR ...................................................................................................... 1062

26.1 Functions .............................................................................................................................. 1062

26.2 Configuration........................................................................................................................ 1062

26.3 Registers ............................................................................................................................... 1063

26.4 Operation .............................................................................................................................. 1064

CHAPTER 27 LOW-VOLTAGE DETECTOR (LVI) ........................................................................... 1067

27.1 Functions .............................................................................................................................. 1067

27.2 Configuration........................................................................................................................ 1067

27.3 Registers ............................................................................................................................... 1068

27.4 Operation .............................................................................................................................. 1070

27.4.1 To use for internal reset signal....................................................................................................1070

27.4.2 To use for interrupt......................................................................................................................1071

CHAPTER 28 CRC FUNCTION.......................................................................................................... 1072

28.1 Functions .............................................................................................................................. 1072

28.2 Configuration........................................................................................................................ 1072

28.3 Registers ............................................................................................................................... 1073

28.4 Operation .............................................................................................................................. 1074

28.5 Usage..................................................................................................................................... 1075

CHAPTER 29 REGULATOR ............................................................................................................... 1077

29.1 Outline ................................................................................................................................... 1077

29.2 Operation .............................................................................................................................. 1078

CHAPTER 30 OPTION BYTE............................................................................................................. 1079

30.1 Program Example................................................................................................................. 1081

CHAPTER 31 FLASH MEMORY........................................................................................................ 1082

31.1 Features ................................................................................................................................ 1082

31.2 Memory Configuration......................................................................................................... 1083

31.3 Functional Outline................................................................................................................ 1085

31.4 Rewriting by Dedicated Flash Memory Programmer ....................................................... 1088

31.4.1 Programming environment ..........................................................................................................1088

31.4.2 Communication mode .................................................................................................................1089

31.4.3 Interface ......................................................................................................................................1091

31.4.4 Flash memory control .................................................................................................................1096

31.4.5 Selection of communication mode ..............................................................................................1097

31.4.6 Communication commands.........................................................................................................1098

31.4.7 Pin connection in on-board programming ...................................................................................1099

31.5 Rewriting by Self Programming.......................................................................................... 1103

31.5.1 Overview .....................................................................................................................................1103

31.5.2 Features......................................................................................................................................1104

31.5.3 Standard self programming flow .................................................................................................1105

31.5.4 Flash functions............................................................................................................................1106

31.5.5 Pin processing ............................................................................................................................1106

31.5.6 Internal resources used...............................................................................................................1107

CHAPTER 32 ON-CHIP DEBUG FUNCTION ................................................................................... 1108

32.1 Debugging with DCU ........................................................................................................... 1110

32.1.1 Connection circuit example .........................................................................................................1110

32.1.2 Interface signals ..........................................................................................................................1111

32.1.3 Mask function..............................................................................................................................1112

32.1.4 Registers.....................................................................................................................................1113

32.1.5 Operation ....................................................................................................................................1114

32.1.6 Cautions......................................................................................................................................1115

32.2 Debugging Without Using DCU .......................................................................................... 1116

32.2.1 Circuit connection examples .......................................................................................................1116

32.2.2 Mask function..............................................................................................................................1118

32.2.3 Allocation of user resources........................................................................................................1119

32.2.4 Cautions......................................................................................................................................1126

32.3 ROM Security Function ....................................................................................................... 1127

32.3.1 Security ID ..................................................................................................................................1127

32.3.2 Setting.........................................................................................................................................1128

CHAPTER 33 ELECTRICAL SPECIFICATIONS (μ PD70F3794, 70F3795, 70F3796) .................... 1129

33.1 Absolute Maximum Ratings ................................................................................................ 1129

33.2 Capacitance .......................................................................................................................... 1130

33.3 Operating Conditions .......................................................................................................... 1131

33.4 Oscillator Characteristics.................................................................................................... 1132

33.4.1 Main clock oscillator characteristics ............................................................................................1132

33.4.2 Subclock oscillator characteristics ..............................................................................................1136

33.4.3 PLL characteristics......................................................................................................................1138

33.4.4 Internal oscillator characteristics .................................................................................................1138

33.5 Regulator Characteristics ................................................................................................... 1139

33.6 DC Characteristics ............................................................................................................... 1140

33.6.1 Pin characteristics .......................................................................................................................1140

33.6.2 Supply current characteristics .....................................................................................................1142

33.6.3 Data retention characteristics (in STOP mode) ...........................................................................1143

33.7 AC Characteristics ............................................................................................................... 1144

33.7.1 Measurement conditions .............................................................................................................1144

33.7.2 CLKOUT output timing ................................................................................................................1145

33.7.3 Bus timing ...................................................................................................................................1146

33.7.4 Power on/power off/reset timing..................................................................................................1153

33.8 Peripheral Function Characteristics .................................................................................. 1154

33.8.1 Interrupt timing ............................................................................................................................1154

33.8.2 Key return timing.........................................................................................................................1154

33.8.3 Timer timing ................................................................................................................................1154

33.8.4 UART timing................................................................................................................................1155

33.8.5 CSIB timing .................................................................................................................................1155

33.8.6 I2C bus mode...............................................................................................................................1157

33.8.7 A/D converter ..............................................................................................................................1158

33.8.8 D/A converter ..............................................................................................................................1159

33.8.9 LVI circuit characteristics ............................................................................................................1159

33.8.10 RTC back-up mode characteristics ...........................................................................................1160

33.9 Flash Memory Programming Characteristics ................................................................... 1161

CHAPTER 34 ELECTRICAL SPECIFICATIONS (

PD70F3843, 70F3844)..................................... 1163

34.1 Absolute Maximum Ratings ................................................................................................ 1163

34.2 Capacitance .......................................................................................................................... 1164

34.3 Operating Conditions .......................................................................................................... 1165

34.4 Oscillator Characteristics.................................................................................................... 1166

34.4.1 Main clock oscillator characteristics ............................................................................................1166

34.4.2 Subclock oscillator characteristics ..............................................................................................1170

34.4.3 PLL characteristics......................................................................................................................1172

34.4.4 Internal oscillator characteristics .................................................................................................1172

34.5 Regulator Characteristics ................................................................................................... 1173

34.6 DC Characteristics ............................................................................................................... 1174

34.6.1 Pin characteristics .......................................................................................................................1174

34.6.2 Supply current characteristics .....................................................................................................1176

34.6.3 Data retention characteristics (in STOP mode) ...........................................................................1177

34.7 AC Characteristics ............................................................................................................... 1178

34.7.1 Measurement conditions .............................................................................................................1178

34.7.2 CLKOUT output timing ................................................................................................................1179

34.7.3 Bus timing ...................................................................................................................................1180

34.7.4 Power on/power off/reset timing..................................................................................................1187

34.8 Peripheral Function Characteristics .................................................................................. 1188

34.8.1 Interrupt timing ............................................................................................................................1188

34.8.2 Key return timing.........................................................................................................................1188

34.8.3 Timer timing ................................................................................................................................1188

34.8.4 UART timing................................................................................................................................1189

34.8.5 CSIB timing .................................................................................................................................1189

34.8.6 I2C bus mode...............................................................................................................................1191

34.8.7 A/D converter ..............................................................................................................................1192

34.8.8 D/A converter ..............................................................................................................................1193

34.8.9 LVI circuit characteristics ............................................................................................................1193

34.8.10 RTC back-up mode characteristics ...........................................................................................1194

34.9 Flash Memory Programming Characteristics ................................................................... 1195

CHAPTER 35 PACKAGE DRAWINGS .............................................................................................. 1197

CHAPTER 36 RECOMMENDED SOLDERING CONDITIONS......................................................... 1199

APPENDIX A DEVELOPMENT TOOLS............................................................................................. 1201

A.1 Software Package ................................................................................................................ 1203

A.2 Language Processing Software ......................................................................................... 1203

A.3 Control Software .................................................................................................................. 1203

A.4 Debugging Tools (Hardware) .............................................................................................. 1204

A.4.1 When using IECUBE QB-V850ESJX3L ......................................................................................1204

A.4.2 When using MINICUBE QB-V850MINI .......................................................................................1207

A.4.3 When using MINICUBE2 QB-MINI2............................................................................................1208

A.5 Debugging Tools (Software) ............................................................................................... 1209

A.6 Embedded Software............................................................................................................. 1210

A.7 Flash Memory Writing Tools ............................................................................................... 1211

APPENDIX B MAJOR DIFFERENCES BETWEEN PRODUCTS..................................................... 1212

APPENDIX C REGISTER INDEX ....................................................................................................... 1215

APPENDIX D INSTRUCTION SET LIST ........................................................................................... 1234

D.1 Conventions.......................................................................................................................... 1234

D.2 Instruction Set (in Alphabetical Order) .............................................................................. 1237

V850ES/JG3-L (on-chip USB controller) RENESAS MCU

R01UH0001EJ0300

Rev.3.00

Aug 3, 2012

CHAPTER 1 INTRODUCTION

The V850ES/JG3-L is one of the products in the Renesas Electronics V850 single-chip microcontroller series designed

for low-power operation for real-time control applications.

1.1 General

The V850ES/JG3-L is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions

such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a D/A converter, USB function controller.

In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/JG3-L features

multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware multiplier,

as optimum instructions for digital servo control applications. Moreover, as a real-time control system, the V850ES/JG3-L

enables an extremely high cost-performance for applications that require USB function controller, such as PC peripheral

device, ECR peripheral device, and industrial instrument.

R01UH0001EJ0300 Rev.3.00 Page 21 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

Table 1-1. V850ES/JG3-L Product List

Generic Name Part Number

Internal memory

PD70F3794

Flash memory

256 KB 384 KB 512 KB 768 KB 1 MB

RAM 40 KB

PD70F3795

Logical space 64 MB Memory

<R>

space

External bus interface Address bus: 6

External memory area 13 MB

Address data bus: 16 Multiplexed bus mode

General-purpose register

Clock

Main clock (oscillation frequency)

32 bits × 32 registers

Ceramic/crystal (in PLL mode: f

X = 2.5 to 6 MHz (multiplied by 4/8), in clock through mode: fX = 2.5 to 10 MHz)

External clock

X = 2.5 to 6 MHz (multiplied by 4/8), in clock through mode: fX = 2.5 to 6 MHz

Subclock

(in PLL mode: f

Crystal (fXT = 32.768 kHz)

(oscillation frequency)

Internal oscillator fR = 220 kHz (TYP.)

Minimum instruction execution time

50 ns (main clock (f

62.5 ns (main clock (f

XX) = 20 MHz: When USB is not used)

XX) = 16 MHz: When USB is used)

I/O port I/O: 80 (5 V tolerant/N-ch open-drain output selectable: 28)

Timer

16-bit TMP 6 channels

16-bit TMQ 1 channel

16-bit TMM 1 channel

Watch timer 1 channel

RTC 1 channel

WDT 1 channel

Real-time output port

4 bits × 1 channel, 2 bits × 1 channel, or 6 bits × 1 channel

10-bit A/D converter 12 channels

8-bit D/A converter 2 channels

Serial interface

CSIB 3 channels

UARTA/CSIB 1 channel

CSIB/I2C bus 1 channel

UARTA/I2C bus 2 channels

UARTA 3 channels

UARTC 1 channel

USB function 1 channel

DMA controller 4 channels (transfer target: on-chip peripheral I/O,

internal RAM, external memory)

Interrupt source

External

Internal 55

Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE/

low-voltage STOP/low-voltage subclock/low-voltage sub-IDLE mode/RTC backup mode

Reset source RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)

CRC function 16-bit error detection code generated for 8-bit unit data

On-chip debug

MINICUBE

, MINICUBE2 supported

Operating power supply voltage 2.0 V@2.5 MHz, 2.2 V@5 MHz, 2.7 V@20 MHz, 3.0 V to 3.6 V (USB operating)

Operating ambient temperature

Package

−40 to +85°C 100-pin LQFP (14 × 14 mm)

121-pin FBGA (8 × 8 mm)

Notes1. Including 24 KB of expanded internal RAM area.

2. The figure in parentheses indicates the number of external interrupts that can release the STOP mode.

V850ES/JG3-L

PD70F3796

9 (9)

Note

PD70F3843

80 KB

4 channels (transfer target: on-chip

peripheral I/O, internal RAM, expanded

internal RAM external memory)

PD70F3844

Note1

R01UH0001EJ0300 Rev.3.00 Page 22 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

1.2 Features

<R>

{ Minimum instruction execution time: 50 ns (operating on main clock (f (In PLL mode: ×4 : 5 MHz)

62.5 ns (operating on main clock (f

(In PLL mode: ×8, 1/3 : 6 MHz)

200 ns (operating on main clock (f

(In clock-through mode)

400 ns (operating on main clock (f

(In clock-through mode)

30.5

s (operating on subclock (fXT) of 32.768 kHz: VDD = 2.0 to 3.6 V)

{ General-purpose registers: 32 bits × 32 registers { CPU features: Signed multiplication (16 × 16 → 32): 1 to 2 clocks

Signed multiplication (32 × 32 → 64): 1 to 5 clocks

Saturated operations (overflow and underflow detection functions included)

Most instructions can be executed in 1 clock cycle by using 32-bit RISC-based 5-stage

pipeline architecture

Instruction fetching from internal ROM and accessing internal RAM for data can be

executed separately, by using Harvard architecture

High code efficiency achieved by using variable length instructions

32-bit shift instruction: 1 clock cycle

Bit manipulation instructions

Load/store instructions with long/short format

{ Memory space: 64 MB of linear address space (for programs and data)

External expansion: Up to 16 MB (including 1 MB used as internal ROM/RAM)

• Internal memory: RAM: 40 K/80 KB (see Table 1-1)

Flash memory: 256 K/384 K/512 K/768 K/1 MB (see Table 1-1)

• External bus interface: Multiplexed bus mode

8/16 bit data bus sizing function

Wait function

• Programmable wait function

• External wait function

Idle state function

Bus hold function

{ Interrupts and exceptions:

Internal external:

maskable Non-

maskable

PD70F3794 1 54 55 1 8 9

PD70F3795 1 54 55 1 8 9

PD70F3796 1 54 55 1 8 9

PD70F3843 1 54 55 1 8 9

PD70F3844 1 54 55 1 8 9

total maskable Non-

XX) of 20 MHz: VDD = 2.7 to 3.6 V)

XX) of 16 MHz: VDD = 3.0 to 3.6 V)

XX) of 5 MHz: VDD = 2.2 to 3.6 V)

XX) of 2.5 MHz: VDD = 2.0 to 3.6 V)

total

maskable

Software exceptions: 32 sources

Exception trap: 2 sources

{ Ports: I/O ports: 80

{ Timer function: 16-bit interval timer M (TMM): 1 channel

16-bit timer/event counter P (TMP): 6 channels

R01UH0001EJ0300 Rev.3.00 Page 23 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

16-bit timer/event counter Q (TMQ): 1 channel

Watch timer: 1 channel

Watchdog timer: 1 channel

{ Real-time counter: 1 channel { Real-time output port: 6 bits × 1 channel

{ Serial interface: Asynchronous serial interface A (UARTA)

3-wire variable-length serial interface B (CSIB)

C bus interface (I2C)

UARTA/CSIB: 1 channel

UARTA/I

CSIB/I2C: 1 channel

CSIB: 3 channels

UARTA: 3 channels

UARTC: 1 channel

USB function: 1 channel

{ A/D converter: 10-bit resolution: 12 channels

{ D/A converter: 8-bit resolution: 2 channels

{ DMA controller: 4 channels

{ DCU (debug control unit): JTAG interface

{ Clock generator: During main clock or subclock operation

7-level CPU clock (f

Clock-through mode/PLL mode selectable

{ Internal oscillator clock: 220 kHz (TYP.)

{ Power-save functions: HALT/IDLE1/IDLE2/STOP/low-voltage STOP/subclock/sub-IDLE/

low-voltage subclock/low-voltage sub-IDLE mode/RTC backup mode

{ Package: 100-pin plastic LQFP (fine pitch) (14 × 14) 121-pin plastic FBGA (8 × 8)

{ Power supply voltage: V

DD = 2.0 V to 3.6 V (2.5 MHz)

VDD = 2.2 V to 3.6 V (5 MHz)

DD = 2.7 V to 3.6 V (20 MHz)

DD = 3.0 V to 3.6 V (USB operating)

C: 2 channels

XX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)

R01UH0001EJ0300 Rev.3.00 Page 24 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

1.3 Application Fields

Equipment requiring a USB interfaces such as PC peripheral device, ECR peripheral device (bar code scanner, IC card reader/writer, printer, etc), industrial instrument, etc

1.4 Ordering Information

Part Number Package Internal Flash Memory

PD70F3794GC-UEU-AX

PD70F3795GC-UEU-AX

PD70F3796GC-UEU-AX

PD70F3843GC-UEU-AX

PD70F3844GC-UEU-AX

PD70F3794F1-CAH-A

PD70F3795F1-CAH-A

PD70F3796F1-CAH-A

PD70F3843F1-CAH-A

PD70F3844F1-CAH-A

Remark The V850ES/JG3-L is a lead-free product.

100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic LQFP (fine pitch) (14 × 14) 121-pin plastic FBGA (8 × 8 ) 121-pin plastic FBGA (8 × 8 ) 121-pin plastic FBGA (8 × 8 ) 121-pin plastic FBGA (8 × 8 ) 121-pin plastic FBGA (8 × 8 )

256 KB

384 KB

512 KB

768 KB

1 MB

256 KB

384 KB

512 KB

768 KB

1 MB

R01UH0001EJ0300 Rev.3.00 Page 25 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

1.5 Pin Configuration (Top View)

100-pin plastic LQFP (fine pitch) (14 × 14)

PD70F3794GC-UEU-AX

PD70F3843GC-UEU-AX

<R>

PD70F3795GC-UEU-AX

PD70F3844GC-UEU-AX

P70/ANI0

P71/ANI1

P72/ANI2

P73/ANI3

P74/ANI4

P75/ANI5

P76/ANI6

P77/ANI7

P78/ANI8

P79/ANI9

P710/ANI10

PD70F3796GC-UEU-AX

P711/ANI11

PDH1/A17

PDH0/A16

PDL15/AD15

PDL14/AD14

PDL13/AD13

PDL12/AD12

PDL11/AD11

PDL10/AD10

PDL9/AD9

PDL8/AD8

PDL7/AD7

PDL6/AD6

PDL5/AD5/FLMD1

REF0

AV P10/ANO0 P11/ANO1

REF1

PDH4/A20

P02/NMI/A21

Note 1

FLMD0

Note 2

REGC

X1 X2

RESET

XT1 XT2

P03/INTP0/ADTRG/UCLK/RTC1HZ

P04/INTP1/RTCDIV/RTCCL

P05/INTP2/DRST

P40/SIB0/SDA01

P41/SOB0/SCL01

P30/TXDA0/SOB4

P06/INTP3

P42/SCKB0

9998979695949392919089888786858483828180797877

100

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26272829303132333435363738394041424344454647484950

UDPF

UDMF

P36/TXDA3

P37/RXDA3

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

PDL4/AD4 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 EV

PCT6/ASTB PCT4/RD PCT1/WR1 PCT0/WR0 PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PDH3/A19 PDH2/A18 P915/INTP6/TIP50/TOP50 P914/INTP5/TIP51/TOP51 P913/INTP4 P912/SCKB3 P911/SOB3 P910/SIB3 P99/SCKB1 P98/SOB1

P38/TXDA2/SDA00

P39/RXDA2/SCL00

P31/RXDA0/INTP7/SIB4

P50/TIQ01/KR0/TOQ01/RTP00

P32/ASCKA0/SCKB4/TIP00/TOP00

P51/TIQ02/KR1/TOQ02/RTP01

P52/TIQ03/KR2/TOQ03/RTP02/DDI

P90/KR6/TXDA1/SDA02

P91/KR7/RXDA1/SCL02

P93/TIP40/TOP40RXDA4

P92/TIP41/TOP41/TXDA4

P94/TIP31/TOP31/TXDA5

P96/TXDC0/TIP21/TOP21

P54/SOB2/KR4/RTP04/DCK

P55/SCKB2/KR5/RTP05/DMS

P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO

P95/TIP30/TOP30/RXDA5

P97/SIB1/RXDC0/TIP20/TOP20

Notes 1. The FLMD0 pin is used in flash programming. Connect this pin to VSS in the normal operation mode.

2. Connect the REGC pin to V

SS via a 4.7

F (recommended value) capacitor.

R01UH0001EJ0300 Rev.3.00 Page 26 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

121-pin plastic FBGA (8 × 8)

PF70F3794F1-CAH-A

PF70F3843F1-CAH-A

PF70F3795F1-CAH-A

PF70F3844F1-CAH-A

Top View Bottom View

11 10

PF70F3796F1-CAH-A

9 8 7 6 5 4 3 2 1

Index mark

HGFE

KLL

DEFG

Index mark

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

A1 AVREF0 C1 AVSS E1 REGC

A2 AVREF0 C2 AVSS E2 REGC

A3 P70/ANI0 C3 P72/ANI2 E3 P10/ANO0

A4 P74/ANI4 C4 P76/ANI6 E4 P11/ANO1

A5 P78/ANI8 C5 P710/ANI10 E5 EVSS

A6 EVSS C6 PDH0/A16 E6 EVSS

A7 PDL11/AD11 C7 PDL13/AD13 E7 EVSS

A8 PDL8/AD8 C8 PDL10/AD10 E8 PCT0/WR0

A9 PDL6/AD6 C9 PDL2/AD2 E9 PCM3/HLDRQ

A10 PDL5/AD5/FLMD1 C10 PDL1/AD1 E10 PCM2/HLDAK

A11 EVDD C11 PDL0/AD0 E11 EVSS

B1 AVREF0 D1 VDD F1 X1

B2 AVREF1 D2 RVDD F2 X2

B3 P71/ANI1 D3 P73/ANI3 F3 FLMD0

B4 P75/ANI5 D4 P77/ANI7 F4 PDH4/A20

B5 P79/ANI9 D5 P711/ANI11 F5 EVSS

B6 PDL15/AD15 D6 PDH1/A17 F6 EVSS

B7 PDL12/AD12 D7 PDL14/AD14 F7 EVSS

B8 PDL9/AD9 D8 PCT6/ASTB F8 PDH3/A19

B9 PDL7/AD7 D9 PCT4/RD F9 PDH2/A18

B10 PDL4/AD4 D10 PCT1/WR1 F10 PCM1/CLKOUT

B11 PDL3/AD3 D11 EVDD F11 PCM0/WAIT

Note 1

Note 2

(1/2)

Notes 1. Connect the E1 and E2 pins by using the shortest possible pattern and connect them to VSS via a 4.7 μF

(recommended value) capacitor.

2. The FLMD0 pin is used in flash programming. Connect this pin to V

SS in the normal operation mode.

R01UH0001EJ0300 Rev.3.00 Page 27 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

<R>

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

G1 VSS H9 P911/SOB3 K6 UVDD

G2 VSS H10 P910/SIB3 K7

G3 P03/INTP0/ADTRG/UCLK/

RTC1HZ

G4 PDH5/NMI/A21 J1 VSS K9 P92/TIP41/TOP41/TXDA4

G5 EVSS J2 IC

G6 EVSS J3 P05/INTP2/DRST K11 P96/TXDC0/TIP21/TOP21

G7 EVSS J4 P06/INTP3 L1 EVSS

G8 P915/INTP6/TIP50/TOP50 J5 EVSS L2 P42/SCKB0

G9 P914/INTP5/TIP51/TOP51 J6 P37/RXDA3 L3 P30/TXDA0/SOB4

G10 P913/INTP4 J7 P52/TIQ03/KR2/TOQ03

G11 P912/SCKB3 J8 P55/SCKB2/KR5/RTP05/DMS L5 EVSS

H1 XT1 J9 P93/TIP40/TOP40/RXDA4 L6 EVDD

H2 XT2 J10 P98/SOB1 L7

H3 RESET J11 P97/SIB1/RXDC0/TIP20/

H4 P04/INTP1/RTCDIV/RTCCL K1 P40/SIB0/SDA01 L9 P91/KR7/RXDA1/SCL02

H5 P36/TXDA3 K2 P41/SOB0/SCL01 L10 P94/TIP31/TOP31/TXDA5

H6 P38/TXDA2/SDA00 K3 P31/RXDA0/INTP7/SIB4 L11 EVDD

H7 P39/RXDA2/SCL00 K4 UDMF − −

H8 P90/KR6/TXDA1/SDA02 K5 UDPF − −

H11 P99/SCKB1 K8 P54/SOB2/KR4/RTP04/DCK

Note

K10 P95/TIP30/TOP30/RXDA5

L4 P32/ASCKA0/SCKB4/TIP00

/RTP02/DDI

L8 P53/SIB2/KR3/TIQ00/TOQ00

TOP20

P51/TIQ02/KR1/

/TOP00

P50/TIQ01/KR0/TOQ01/RTP00

/RTP03/DDO

TOQ02

(2/2)

/RTP01

Note Be sure to open.

R01UH0001EJ0300 Rev.3.00 Page 28 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

Pin functions

<R>

A16 to A21:

AD0 to AD15:

ADTRG:

ANI0 to ANI11:

ANO0, ANO1:

ASCKA0:

ASTB:

REF0, AVREF1:

AVSS:

CLKOUT:

DCK:

DDI:

DDO:

DMS:

DRST:

DD:

SS:

FLMD0, FLMD1:

HLDAK:

HLDRQ:

IC:

INTP0 to INTP7:

KR0 to KR7:

NMI:

P02 to P06:

P10, P11:

P30 to P32:

P36 to P39

P40 to P42:

P50 to P55:

P70 to P711:

P90 to P915:

PCM0 to PCM3:

PCT0, PCT1,

PCT4, PCT6:

PDH0 to PDH4

PDL0 to PDL15:

RD:

REGC:

RESET:

Address bus

Address/data bus

A/D trigger input

Analog input

Analog output

Asynchronous serial clock

Address strobe

Analog reference voltage

Analog V

Clock output

Debug clock

Debug data input

Debug data output

Debug mode select

Debug reset

Power supply for external pin

Ground for external pin

Flash programming mode

Hold acknowledge

Hold request

Internal Connected

External interrupt input

Key return

Non-maskable interrupt request

Port 0

Port 1

Port 3

Port 4

Port 5

Port 7

Port 9

Port CM

Port CT

Port DH

Port DL

Read strobe

Regulator control

Reset

RTC1HZ,

RTCCL, RTCDIV

RTP00 to RTP05:

RXDA0 to RXDA5:

RXDC0:

SCKB0 to SCKB4:

SCL00 to SCL02:

SDA00 to SDA02:

SIB0 to SIB4:

SOB0 to SOB4:

TIP00,

TIP20, TIP21,

TIP30, TIP31,

TIP40, TIP41,

TIP50, TIP51,

TIQ00 to TIQ03:

TOP00,

TOP20, TOP21,

TOP30, TOP31,

TOP40, TOP41,

TOP50, TOP51,

TOQ00 to TOQ03:

TXDA0 to TXDA5:

TXDC0:

UCLK:

UDMF:

UDPF:

DD:

VDD:

SS:

WAIT:

WR0:

WR1:

X1, X2:

XT1, XT2:

Real-time Counter Clock Output

Real-time output port

Power Supply for RTC

Receive data

Serial clock

Serial data

Serial input

Serial output

Timer input

Timer output

Transmit data

USB clock USB data I/O (−) function

USB data I/O (+) function

Power supply for external USB

Power supply

Ground

Wait

Lower byte write strobe

Upper byte write strobe

Crystal for main clock

Crystal for subclock

R01UH0001EJ0300 Rev.3.00 Page 29 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

1.6 Function Block Configuration

1.6.1 Internal block diagram

<R>

Timer/counter function

TIP00, TIP20 to TIP50,

TIP21 to TIP51

TOP00, TOP20 to TOP50,

TOP21 to TOP51

TIQ00 to TIQ03

TOQ00 to TOQ03

16-bit timer/

event counter P:

5 ch

16-bit timer/

event counter Q:

1 ch

16-bit interval

timer M:

1 ch

Watchdog

timer 2: 1ch

Watch timer:

1ch

ROM RAM

Note 1

CPU

Multiplier

16 × 16 → 32

ALU

32-bit barrel

registers 32 bits × 32

Note 2

shifter

System

registers

General-purpose

DMA

BCU

HLDRQ

HLDAK ASTB

WAIT

WR0, WR1 A16 to A21 AD0 to AD15

Expanded

internal RAM

Note 3

(24KB)

RTC1HZ RTCCL RTCDIV

RTP00 to RTP05 RTO : 1 ch

Serial interface function

SOB0 to SOB4

SIB0 to SIB4

SCKB0 to SCKB4

SDA00 to SDA02

SCL00 to SCL02

TXDA0 to TXDA5

RXDA0 to RXDA5

ASCKA0

TXDC0

RXDC0

UDMF UDPF

Real-time

counter:

1 ch

CSIB: 5 ch

C: 3 ch

UARTA:

6 ch

UARTC:

1 ch

USB function

CRC

Ports

P50 to P55

P40 to P42

P90 to P915

P70 to P711

PDH0 to PDH4

PCM0 to PCM3

PDL0 to PDL15

PCT0, PCT1, PCT4, PCT6

Interrupt function

INTC

Key interrupt

function

Debug function

DCU

P30 to P32, P36 to P39

NMI

INTP0 to INTP7

KR0 to KR7

DRST

DMS

DDI

DCK

DDO

converter

P10, P11

P02 to P06

REF1

A/D

converter

ADTRG

D/A

ANO0, ANO1

REF0

ANI0 to ANI11

Regulator

Flash

controller

UV EV EV

PLL

Internal

oscillator

CLM

LVI

Regulator

CLKOUT X1 X2 XT1 XT2 RESET

FLMD0 FLMD1

REGC

Notes1.

PD70F3794: 256 KB

PD70F3795: 384 KB

μPD70F3796: 512 KB

PD70F3843: 768 KB

PD70F3844: 1 MB

PD70F3794, 70F3795, 70F3796: 40 KB

PD70F3843, 70F3844: 56 KB

PD70F3843, 70F3844 only

R01UH0001EJ0300 Rev.3.00 Page 30 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

1.6.2 Internal units

(1) CPU

The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic

operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits)

contribute to faster complex processing.

(2) Bus control unit (BCU)

The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an

instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU

generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an

instruction queue.

(3) Flash memory (ROM)

This is a 1 M/768 K/512 K/384 K/256 KB flash memory mapped to addresses 0000000H to 00FFFFFH/0000000H

to 00BFFFFH/0000000H to 007FFFFH/0000000H to 005FFFFH/0000000H to 003FFFFH.

It can be accessed from the CPU in one clock during instruction fetch.

(4) RAM

This is a 80

/3FF5000H to 3FFEFFFH. It can be accessed from the CPU in one clock during data access.

Note Including 24 KB of expanded internal RAM area.

(5) Interrupt controller (INTC)

This controller handles hardware interrupt requests (NMI, INTP0 to INTP7) from on-chip peripheral hardware and

external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed

interrupt servicing control can be performed.

(6) Clock generator (CG)

A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (f

and subclock frequency (f

clock frequency (f

The CPU clock frequency (fCPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT.

(7) Internal oscillator

An internal oscillator is provided on chip. The oscillation frequency is 220 kHz (TYP). The internal oscillator

supplies the clock for watchdog timer 2 and timer M.

(8) Timer/counter

Six-channel 16-bit timer/event counter P (TMP), one-channel 16-bit timer/event counter Q (TMQ), and one-channel

16-bit interval timer M (TMM), are provided on chip.

(9) Watch timer

This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz subclock or the 32.768

kHz f

BRG clock from the prescaler). The watch timer can also be used as an interval timer based on the main clock.

Note

/40 KB RAM mapped to addresses 3FF1000H to 03FFEFFFH + 03FA000H to 03FFFFFH

XT), respectively. There are two modes: In the clock-through mode, fX is used as the main

XX) as is. In the PLL mode, fX is used multiplied by 4.

R01UH0001EJ0300 Rev.3.00 Page 31 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

(10) Real-time counter (for watch)

The real-time counter counts the reference time (one second) for watch counting based on the subclock (32.768

kHz) or main clock. This can simultaneously be used as the interval timer based on the main clock. Hardware

counters dedicated to year, month, day of week, day, hour, minute, and second are provided, and can count up to

99 years.

(11) Watchdog timer 2

A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc.

The internal oscillator clock, the main clock, or the subclock can be selected as the source clock.

Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal

(WDT2RES) after an overflow occurs.

(12) Serial interface

The V850ES/JG3-L includes three kinds of serial interfaces: asynchronous serial interface A (UARTA), 3-wire

variable-length serial interface B (CSIB), and an I

In the case of UARTA, data is transferred via the TXDA0 to TXDA2 pins and RXDA0 to RXDA2 pins.

In the case of CSIB, data is transferred via the SOB0 to SOB4 pins, SIB0 to SIB4 pins, and SCKB0 to SCKB4

pins.

In the case of I

C, data is transferred via the SDA00 to SDA02 and SCL00 to SCL02 pins.

In the case of USBF, data is transferred via the UDMF and UDPF pins.

(13) A/D converter

This 10-bit A/D converter includes 12 analog input pins. Conversion is performed using the successive

approximation method.

(14) D/A converter

A two-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip.

(15) DMA controller

A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and on-

chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.

(16) Key interrupts function

A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8

channels).

(17) Real-time output function

The real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer compare

(18) CRC function

A CRC operation circuit that generates a 16-bit CRC (Cyclic Redundancy Check) code upon the setting of 8-bit

data is provided on-chip.

C bus interface (I2C), USB function controller (USBF).

R01UH0001EJ0300 Rev.3.00 Page 32 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 1 INTRODUCTION

(19) DCU (debug control unit)

An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is provided.

Switching between the normal port function and on-chip debugging function is done with the control pin input

level and the OCDM register.

(20) Ports

The following general-purpose port functions and control pin functions are available.

Table 1-2. Port Functions

Port I/O Alternate Function

P0 5-bit I/O NMI, external interrupt, A/D converter trigger, debug reset, real-time counter output

P1 2-bit I/O D/A converter analog output

P3 7-bit I/O External interrupt, serial interface, timer I/O

P4 3-bit I/O Serial interface

P5 6-bit I/O Timer I/O, real-time output, key interrupt input, serial interface, debug I/O

P7 12-bit I/O A/D converter analog input

<R>

P9 16-bit I/O Serial interface, key interrupt input, timer I/O, external interrupt

PCM 4-bit I/O External control signal

PCT 4-bit I/O External control signal

PDH 5-bit I/O External address bus

PDL 16-bit I/O External address/data bus

R01UH0001EJ0300 Rev.3.00 Page 33 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

CHAPTER 2 PIN FUNCTIONS

2.1 List of Pin Functions

The functions of the pins in the V850ES/JG3-L are described below.

There are four types of pin I/O buffer power supplies: AV

power supplies and the pins is described below.

Table 2-1. Pin I/O Buffer Power Supplies

Power Supply Corresponding Pins

AVREF0 Port 7

AVREF1 Port 1

EVDD RESET, ports 0, 3 to 5, 9, CM, CT, DH, DL, FLMD0

UVDD UDMF, UDPF

REF0, AVREF1, EVDD, and UVDD. The relationship between these

R01UH0001EJ0300 Rev.3.00 Page 34 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

(1) Port functions

(1/3)

Pin No. Function

GC F1

P02 7 G4 NMI/A21

P03 18 G3 INTP0/ADTRG/UCLK/RTC1HZ

P04 19 H4 INTP1/RTCDIV/RTCCL

Note

P05

20 J3 INTP2/DRST

P06 21 J4

P10 3 E3 ANO0

P11 4 E4

P30 25 L3

P31 26 K3

P32 27 L4

P36 31 H5 TXDA3

P37 32 J6 RXDA3

P38 35 H6

P39 36 H7

P40 22 K1

P41 23 K2

P42 24 L2

P50 37 L7

P51 38 K7

P52 39 J7

P53 40 L8

P54 41 K8

P55 42 J8

Note Incorporates a pull-down resistor. It can be disconnected by clearing the OCDM.OCDM0 bit to 0.

Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14)

F1: 121-pin plastic FBGA (8 × 8)

I/O Description Alternate Function

Port 0 (refer to 4.3.1)

I/O

5-bit I/O port Input/output can be specified in 1-bit units. N-ch open-drain output can be specified in 1-bit units. 5 V tolerant.

INTP3

Port 1 (refer to 4.3.2)

I/O

2-bit I/O port Input/output can be specified in 1-bit units.

Port 3 (refer to 4.3.3)

I/O

7-bit I/O port Input/output can be specified in 1-bit units. N-ch open-drain output can be specified in 1-bit units. 5 V tolerant.

Port 4 (refer to 4.3.4)

I/O

3-bit I/O port Input/output can be specified in 1-bit units. N-ch open-drain output can be specified in 1-bit units. 5 V tolerant.

Port 5 (refer to 4.3.5)

I/O

6-bit I/O port Input/output can be specified in 1-bit units. N-ch open-drain output can be specified in 1-bit units. 5 V tolerant.

ANO1

TXDA0/SOB4

RXDA0/INTP7/SIB4

ASCKA0/SCKB4/TIP00/TOP00

TXDA2/SDA00

RXDA2/SCL00

SIB0/SDA01

SOB0/SCL01

SCKB0

TIQ01/KR0/TOQ01/RTP00

TIQ02/KR1/TOQ02/RTP01

TIQ03/KR2/TOQ03/RTP02/DDI

SIB2/KR3/TIQ00/TOQ00/RTP03/DDO

SOB2/KR4/RTP04/DCK

SCKB2/KR5/RTP05/DMS

R01UH0001EJ0300 Rev.3.00 Page 35 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

Pin No. Function

GC F1

P70

P71 99 B3 ANI1

P72 98 C3 ANI2

P73 97 D3 ANI3

P74 96 A4 ANI4

P75 95 B4 ANI5

P76 94 C4 ANI6

P77 93 D4 ANI7

P78 92 A5 ANI8

P79 91 B5 ANI9

P710 90 C5 ANI10

P711 89 D5

<R>

P90 43 H8 KR6/TXDA1/SDA02

P91 44 L9 KR7/RXDA1/SCL02

P92 45 K9 TIP41/TOP41/TXDA4

P93 46 J9 TIP40/TOP40/RXDA4

P94 47 L10 TIP31/TOP31/TXDA5

P95 48 K10 TIP30/TOP30/RXDA5

P96 49 K11 TXDC0/TIP21/TOP21

P97 50 J11 SIB1/RXDC0 /TIP20/TOP20

P98 51 J10 SOB1

P99 52 H11 SCKB1

P910 53 H10 SIB3

P911 54 H9 SOB3

P912 55 G11 SCKB3

P913 56 G10 INTP4

P914 57 G9 INTP5/TIP51/TOP51

P915 58 G8

100 A3

Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14) F1: 121-pin plastic FBGA (8 × 8)

I/O Description Alternate Function

Port 7 (refer to 4.3.6)

I/O

12-bit I/O port Input/output can be specified in 1-bit units.

Port 9 (refer to 4.3.7)

I/O

16-bit I/O port Input/output can be specified in 1-bit units. N-ch open-drain output can be specified in 1-bit units. 5 V tolerant.(P90 to P96)

ANI0

ANI11

INTP6/TIP50/TOP50

(2/3)

R01UH0001EJ0300 Rev.3.00 Page 36 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

(3/3)

Function

PCM0 61 F11 WAIT

PCM1 62 F10 CLKOUT

PCM2 63 E10 HLDAK

PCM3 64 E9

PCT0 65 E8 WR0

PCT1 66 D10 WR1

PCT4 67 D9 RD

PCT6 68 D8

PDH0 87 C6 A16

PDH1 88 D6 A17

PDH2 59 F9 A18

PDH3 60 F8 A19

PDH4 6 F4

PDL0 71 C11 AD0

PDL1 72 C10 AD1

PDL2 73 C9 AD2

PDL3 74 B11 AD3

PDL4 75 B10 AD4

PDL5 76 A10 AD5/FLMD1

PDL6 77 A9 AD6

PDL7 78 B9 AD7

PDL8 79 A8 AD8

PDL9 80 B8 AD9

PDL10 81 C8 AD10

PDL11 82 A7 AD11

PDL12 83 B7 AD12

PDL13 84 C7 AD13

PDL14 85 D7 AD14

PDL15 86 B6

Pin No.

GC F1

I/O

Port CM (refer to 4.3.8)

I/O

4-bit I/O port Input/output can be specified in 1-bit units.

Port CT (refer to 4.3.9)

I/O

4-bit I/O port Input/output can be specified in 1-bit units.

Port DH (refer to 4.3.10)

I/O

5-bit I/O port Input/output can be specified in 1-bit units.

Port DL (refer to 4.3.11)

I/O

16-bit I/O port Input/output can be specified in 1-bit units.

Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14) F1: 121-pin plastic FBGA (8 × 8)

Description

HLDRQ

ASTB

A20

AD15

Alternate Function

R01UH0001EJ0300 Rev.3.00 Page 37 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

<R>

(2) Non-port functions

Function

A16 87 C6 PDH0

A17 88 D6 PDH1

A18 59 F9 PDH2

A19 60 F8 PDH3

A20 6 F4 PDH4

A21 7

AD0 71 C11 PDL0

AD1 72 C10 PDL1

AD2 73 C9 PDL2

AD3 74 B11 PDL3

AD4 75 B10 PDL4

AD5 76 A10 PDL5/FLMD1

AD6 77 A9 PDL6

AD7 78 B9 PDL7

AD8 79 A8 PDL8

AD9 80 B8 PDL9

AD10 81 C8 PDL10

AD11 82 A7 PDL11

AD12 83 B7 PDL12

AD13 84 C7 PDL13

AD14 85 D7 PDL14

AD15 86 B6

Pin No.

GC F1

I/O

Output Address bus for external memory

I/O Address bus/data bus for external memory

Description

P02/NMI

PDL15

Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14) F1: 121-pin plastic FBGA (8 × 8)

(1/6)

Alternate Function

R01UH0001EJ0300 Rev.3.00 Page 38 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

(2/6)

Function

ADTRG 18 G3 Input A/D converter external trigger input. 5 V tolerant. P03/INTP0/UCLK/RTC1HZ

ANI0 100 A3 P70

ANI1 99 B3 P71

ANI2 98 C3 P72

ANI3 97 D3 P73

ANI4 96 A4 P74

ANI5 95 B4 P75

ANI6 94 C4 P76

ANI7 93 D4 P77

ANI8 92 A5 P78

ANI9 91 B5 P79

ANI10 90 C5 P710

ANI11 89 D5

ANO0 3 E3 P10

ANO1 4 E4

ASCKA0 27 L4 Input UARTA0 baud rate clock input. 5 V tolerant. P32/SCKB4/TIP00/TOP00

ASTB 68 D8 Output Address strobe signal output for external memory PCT6

AVREF0 1 A1,

AVREF1 5 B2

AVSS 2 C1,

CLKOUT 62 F10 Output Internal system clock output PCM1

DCK 41 K8 Input Debug clock input. 5 V tolerant. P54/SOB2/KR4/RTP04

DDI 39 J7 Input Debug data input. 5 V tolerant. P52/TIQ03/KR2/TOQ03/RTP02

Note 1

DDO

DMS 42 J8 Input Debug mode select input. 5 V tolerant. P55/SCKB2/KR5/RTP05

DRST

EVDD 34, 70

EVSS 33, 69

FLMD0 8 F3

FLMD1 76 A10

HLDAK 63 E10 Output Bus hold acknowledge output PCM2

HLDRQ 64 E9 Input Bus hold request input PCM3

Pin No.

GC F1

A2,

40 L8 Output Debug data output.

Note 2

Note 3

I/O

Input Analog voltage input for A/D converter

Output Analog voltage output for D/A converter

Reference voltage input for A/D converter/positive power

−

supply for port 7

Reference voltage input for D/A converter/positive power supply for port 1

Ground potential for A/D and D/A converters (same

−

potential as V

N-ch open-drain output selectable. 5 V tolerant.

J3 Input Debug reset input. 5 V tolerant.

Positive power supply for external (same potential as V

−

Ground potential for external (same potential as V

−

Input Flash memory programming mode setting pin

SS)

Notes 1. In the on-chip debug mode, high-level output is forcibly set.

2. A11, D11, K6, L6, L11

3. A6, E5 to E7, E11, F5 to F7, G5 to G7, L1, L5

Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14)

F1: 121-pin plastic FBGA (8 × 8)

Description

P711

P11

P53/SIB2/KR3/TIQ00/TOQ00/ RTP03

P05/INTP2

DD)

SS)

PDL5/AD5

Alternate Function

−

R01UH0001EJ0300 Rev.3.00 Page 39 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

(3/6)

Function

Pin No.

I/O

GC F1

−

INTP0 18 G3 P03/ADTRG/UCLK/RTC1HZ

INTP1 19 H4 P04/RTCDIV/RTCCL

INTP2 20 J3 P05/DRST

INTP3 21 J4 P06

Internal connected

−

Input External interrupt request input

(maskable, analog noise elimination). Analog noise elimination or digital noise elimination selectable for INTP3 pin. 5 V tolerant.

INTP4 56 G10 P913

INTP5 57 G9 P914/TIP51/TOP51

INTP6 58 G8 P915/TIP50/TOP50

INTP7 26 K3

Note 1

KR0

37 L7 P50/TIQ01/TOQ01/RTP00

Note 1

KR1

38 K7 P51/TIQ02/TOQ02/RTP01

Note 1

KR2

39 J7 P52/TIQ03/TOQ03/RTP02/DDI

Note 1

KR3

40 L8 P53/SIB2/TIQ00/TOQ00/

Note 1

KR4

41 K8 P54/SOB2/RTP04/DCK

Note 1

KR5

42 J8 P55/SCKB2/RTP05/DMS

Note 1

KR6

43 H8 P90/TXDA1/SDA02

Note 1

KR7

44 L9

Note 2

NMI

17 G4 Input External interrupt input (non-maskable, analog

Input Key interrupt input (on-chip analog noise

eliminator). 5 V tolerant.

noise elimination). 5 V tolerant.

RD 67 D9 Output Read strobe signal output for external memory PCT4

REGC 10 E1,E2 − Connection of regulator output stabilization

capacitance (4.7

RESET 14 H3 Input System reset input

RTC1HZ 18 G3 Output Real-time counter correction clock (1 Hz) output P03/INTP0/ADTRG/UCLK

RTCCL 19 H4 Output Real-time counter clock (32 kHz primary oscillation)

output

RTCDIV 19 H4 Output Real-time counter clock (32 kHz division) output P04/INTP1/RTCCL

RTP00 37 L7 P50/TIQ01/KR0/TOQ01

RTP01 38 K7 P51/TIQ02/KR1/TOQ02

RTP02 39 J7 P52/TIQ03/KR2/TOQ03/DDI

Output Real-time output port.

N-ch open-drain output selectable. 5 V tolerant.

RTP03 40 L8 P53/SIB2/KR3/TIQ00/TOQ00/DDO

RTP04 41 K8 P54/SOB2/KR4/DCK

RTP05 42 J8

Notes1. Connect a pull-up resistor externally.

2. The NMI pin alternately functions as the P02 pin. It functions as the P02 pin after reset. To enable the NMI

function, set the PMC0.PMC02 bit to 1. The initial setting of the NMI pin is “No edge detected”. Select the NMI pin valid edge using the INTF0 and INTR0 registers.

Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14) F1: 121-pin plastic FBGA (8 × 8)

Description

F (recommended value))

Alternate Function

−

P31/RXDA0/SIB4

RTP03/DDO

P91/RXDA1/SCL02

P02/A21

−

P04/INTP1/RTCDIV

P55/SCKB2/KR5/DMS

R01UH0001EJ0300 Rev.3.00 Page 40 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

(4/6)

Function

RXDA0 26 K3 P31/INTP7/SIB4

RXDA1 44 L9 P91/KR7/SCL02

RXDA2 36 H7 P39/SCL00

RXDA3 32 J6 P37

RXDA4 46 J9 P93/TIP40/TOP40

RXDA5 48 K10

RXDC0 50 J11

RVDD 17 D2 − Positive power supply for RTC

SCKB0 24 L2 P42

SCKB1 52 H11 P99

SCKB2 42 J8 P55/KR5/RTP05/DMS

SCKB3 55 G11 P912

SCKB4 27 L4

SCL00 36 H7 P39/RXDA2

SCL01 23 K2 P41/SOB0

SCL02 44 L9

SDA00 35 H6 P38/TXDA2

SDA01 22 K1 P40/SIB0

SDA02 43 H8

SIB0 22 K1 P40/SDA01

SIB1 50 J11 P97/RXDC0 /TIP20/TOP20

SIB2 40 L8 P53/KR3/TIQ00/TOQ00/RTP03/DDO

SIB3 53 H10 P910

SIB4 26 K3

SOB0 23 K2 P41/SCL01

SOB1 51 J10 P98

SOB2 41 K8 P54/KR4/RTP04/DCK

SOB3 54 H9 P911

SOB4 25 L3

Pin No.

GC F1

I/O

Serial receive data input (UARTA0 to UARTA2)

Input

5 V tolerant.

Serial receive data input (UARTC0) P97/SIB1/TIP20/TOP20

Serial clock I/O (CSIB0 to CSIB4)

I/O

N-ch open-drain output selectable. 5 V tolerant.

Serial clock I/O (I

I/O

N-ch open-drain output selectable. 5 V tolerant.

Serial transmit/receive data I/O (I

I/O

N-ch open-drain output selectable. 5 V tolerant.

Serial receive data input (CSIB0 to CSIB4)

Input

5 V tolerant.

Serial transmit data output (CSIB0 to CSIB4)

Output

N-ch open-drain output selectable. 5 V tolerant.

Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14) F1: 121-pin plastic FBGA (8 × 8)

Description

C00 to I2C02)

Alternate Function

P95/TIP30/TOP30

−

P32/ASCKA0/TIP00/TOP00

P91/KR7/RXDA1

P90/KR6/TXDA1

P31/RXDA0/INTP7

P30/TXDA0

R01UH0001EJ0300 Rev.3.00 Page 41 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

(5/6)

Function

TIP00 27 L4

TIP20 50

TIP21 49

TIP30 48

TIP31 47

TIP40 46

TIP41 45

TIP50 58

TIP51 57

TIQ00 40 L8

TIQ01 37 L7 P50/KR0/TOQ01/RTP00

TIQ02 38 K7 P51/KR1/TOQ02/RTP01

TIQ03 39 J7

TOP00 27 L4

TOP20 50 J11 P97/SIB1/TIP20

TOP21 49 K11

TOP30 48 K10 P95/TIP30

TOP31 47 L10

TOP40 46 J9 P93/TIP40

TOP41 45 K9

TOP50 58 G8 P915/INTP6/TIP50

TOP51 57 G9

Pin No.

GC F1

J11

K11

K10

L10

I/O

External event count input/capture trigger input/external

Input

trigger input (TMP0). 5 V tolerant.

External event count input/capture trigger input/external trigger input (TMP2). 5 V tolerant.

Capture trigger input (TMP2). 5 V tolerant.

External event count input/capture trigger input/external trigger input (TMP3). 5 V tolerant.

Capture trigger input (TMP3). 5 V tolerant.

External event count input/capture trigger input/external trigger input (TMP4). 5 V tolerant.

Capture trigger input (TMP4). 5 V tolerant.

External event count input/capture trigger input/external trigger input (TMP5). 5 V tolerant.

Capture trigger input (TMP5). 5 V tolerant.

External event count input/capture trigger input/external

Input

trigger input (TMQ0). 5 V tolerant.

Capture trigger input (TMQ0). 5 V tolerant.

Timer output (TMP0)

Output

N-ch open-drain output selectable. 5 V tolerant.

Timer output (TMP2) N-ch open-drain output selectable. 5 V tolerant.

Timer output (TMP3) N-ch open-drain output selectable. 5 V tolerant.

Timer output (TMP4) N-ch open-drain output selectable. 5 V tolerant.

Timer output (TMP5) N-ch open-drain output selectable. 5 V tolerant.

Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14) F1: 121-pin plastic FBGA (8 × 8)

Description

P32/ASCKA0/SCKB4/TOP00

P97/SIB1/TOP20

P96/TOP21

P95/TOP30

P94/TOP31

P93/TOP40

P92/TOP41

P915/INTP6/TOP50

P914/INTP5/TOP51

P53/SIB2/KR3/TOQ00/RTP03 /DDO

P52/KR2/TOQ03/RTP02/DDI

P32/ASCKA0/SCKB4/TIP00

P96/TIP21

P94/TIP31

P92/TIP41

P914/INTP5/TIP51

Alternate Function

R01UH0001EJ0300 Rev.3.00 Page 42 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

(6/6)

Function

TOQ00 40 L8 P53/SIB2/KR3/TIQ00/RTP03/DDO

TOQ01 37 L7 P50/TIQ01/KR0/RTP00

TOQ02 38 K7 P51/TIQ02/KR1/RTP01

TOQ03 39 J7

TXDA0 25 L3 P30/SOB4

TXDA1 43 H8 P90/KR6/SDA02

TXDA2 35 H6 P38/SDA00

TXDA3 31 H5 P36

TXDA4 45 K9 P92/TIP41/TOP41

TXDA5 47 L10

TXDC0 49 K11

UCLK 18 G3 Input USB clock signal input P03/INTP0/ADTRG/UCLK/RTC1HZ

UDMF 28 K4 I/O USB data I/O (−) function

UDPF 29 K5 I/O USB data I/O (+) function

UVDD 30 K6 − Power supply for USB

VDD 9 D1 − Positive power supply pin for internal circuits

VSS 11

WAIT 61 F11 Input External wait input PCM0

WR0 65 E8 Write strobe for external memory (lower 8 bits) PCT0

WR1 66 D10

X1 12 F1 Input

X2 13 F2

XT1 15 H1 Input

XT2 16 H2

Pin No.

GC F1

G1, G2,

I/O

Output

−

Output

−

Timer output (TMQ0) N-ch open-drain output selectable. 5 V tolerant.

Serial transmit data output (UARTA0 to UARTA5) N-ch open-drain output selectable. 5 V tolerant.

Serial transmit data output (UARTAC) N-ch open-drain output selectable. 5 V tolerant.

Ground potential for internal circuits

Write strove for external memory (higher 8 bits) PCT1

Connection of resonator for main clock

Connection of resonator for subclock

Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14) F1: 121-pin plastic FBGA (8 × 8)

Description

P52/TIQ03/KR2/RTP02/DDI

P94/TIP31/TOP31

P96/TIP21/TOP21

Alternate Function

−

R01UH0001EJ0300 Rev.3.00 Page 43 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

2.2 Pin States

The operation states of pins in the various modes are described below.

<R>

Pin Name

P05/DRST Pulled down

P10/ANO0, P11/ANO1

P53/DDO

AD0 to AD15 Notes 7, 8

A16 to A21 Undefined

WAIT

CLKOUT Operating L L Operating Operating

WR0, WR1

ASTB

HLDAK

HLDRQ

Other port pins Hi-Z Hi-Z Held Held Held Held Held

When Power

Is Turned

Note 1

Undefined

Note 6

Hi-Z

Notes 1. Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower limit)

when the power is turned on.

2. Operates while an alternate function is operating.

3. The state of the pins in the idle state inserted after the T3 state is shown (only after a read operation).

4. Pulled down during external reset. During internal reset by the watchdog timer, clock monitor, etc., the state of

this pin differs according to the OCDM.OCDM0 bit setting.

5. DDO output is specified in the on-chip debug mode.

6. The bus control pins function alternately as port pins, so they are initialized to the input mode (port mode).

7. Operates even in the HALT mode, during DMA operation.

8. In separate bus mode: Hi-Z

In multiplexed bus mode: Undefined

9. Because the V

DD and EVDD voltages are less than the minimum operating voltage, the pin status is undefined.

Table 2-2. Pin Operation States in Various Modes

During Reset

(Except When

Powe r I s

Turned On)

Pulled

Note 4

down

HALT Mode

Note 2

IDLE1, IDLE2,

Sub-IDLE

Mode

Held Held Held Held Held

Hi-Z Held Held Hi-Z Held Held

Note5

Hi-Z

Held Held Held Held Held

Note 6

Note7

Hi-Z Hi-Z Held Hi-Z

− − − − −

Note 7

Hi-Z

H H H

Operating

− − −

Note 2

STOP

Mode

Note 2

Idle

State

Note 3

Bus Hold

Operating

RTC Back up mode

Undefined

Note9

Remark Hi-Z: High impedance

Held: The state during the immediately preceding external bus cycle is held.

L: Low-level output

H: High-level output

−: Input without sampling (not acknowledged)

R01UH0001EJ0300 Rev.3.00 Page 44 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins

(1/3)

I/O Circuit

Type

10-D

12-D

10-D

Recommended Connection of Unused Pin

Input: Independently connect to EV

via a resistor.

Output: Leave open.

Input: Independently connect to EV

resistor. Fixing to V

DD level is prohibited.

Output: Leave open.

Internally pull-down after reset by RESET pin.

Input: Independently connect to EV

via a resistor.

Output: Leave open.

Input: Independently connect to AV

via a resistor.

Output: Leave open.

Input: Independently connect to EV

via a resistor.

Output: Leave open.

DD or EVSS

SS via a

DD or EVSS

REF1 or AVSS

DD or EVSS

Pin No. Pin Alternate Function

GC F1

P02 NMI/A21 7

P03 INTP0/ADTRG/UCLK/RTC1HZ 18 G3

P04 INTP1/RTCDIV/RTCCL 19 H4

P05 INTP2/DRST 20 J3 10-N

P06 INTP3 21 J4 10-D

P10 ANO0 3 E3

P11 ANO1 4 E4

P30 TXDA0/SOB4 25 L3 10-G

P31 RXDA0/INTP7/SIB4 26 K3

P32 ASCKA0/SCKB4/TIP00

27 L4

P36 TXDA3 31 H5

P37 RXDA3 32 J6

P38 TXDA2/SDA00

P39 RXDA2/SCL00

35 H6

36 H7

P40 SIB0/SDA01 22 K1

P41 SOB0/SCL01 23 K2

P42 SCKB0 24 L2

P50

P51

P52 TIQ03/KR2/TOQ03/RTP02/DDI

P53

P54 SOB2/KR4/RTP04/DCK

P55 SCKB2/KR5/RTP05/DMS

TIQ01/KR0/TOQ01/RTP00

TIQ02/KR1/TOQ02/RTP01

SIB2/KR3/TIQ00/TOQ00 /RTP03/DDO

37 L7

38 K7

39 J7

40 L8

41 K8

42 J8

Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14) F1: 121-pin plastic FBGA (8 × 8)

R01UH0001EJ0300 Rev.3.00 Page 45 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

P70 to P711 ANI0 to ANI11 100 to 89

<R>

P90 KR6/TDXA1/SDA02 43 H8

P91 KR7/RXDA1/SCL02 44 L9

P92 TIP41/TOP41/TXDA4 45 K9

P93 TIP40/TOP40/RXDA4 46 J9

P94 TIP31/TOP31/TXDA5 47 L10

P95 TIP30/TOP30/RXDA5 48 K10

P96 TXDC0/TIP21/TOP21 49 K11

P97 SIB1/RXDC0/TIP20/TOP20 50 J11

P98 SOB1 51 J10 10-G

P99 SCKB1 52 H11

P910 SIB3 53 H10

P911 SOB3 54 H9 10-G

P912 SCKB3 55 G11

P913 INTP4 56 G10

P914 INTP5/TIP51/TOP51 57 G9

P915 INTP6/TIP50/TOP50 58 G8

PCM0 WAIT 61 F11

PCM1 CLKOUT 62 F10

PCM2 HLDAK 63 E10

PCM3 HLDRQ 64 E9

PCT0, PCT1 WR0, WR1 65, 66 E8, D10

PCT4 RD 67 D9

PCT6 ASTB 68 D8

PDH0 toPDH4 A16 to A20

PDL0 to PDL4 AD0 to AD4 71 to 75

PDL5 AD5/FLMD1 76 A10

Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14) F1: 121-pin plastic FBGA (8 × 8)

Pin No. Pin Alternate Function

GC F1

A3 to A5, B3 to B5,

C3 to C5,

D3 to D5

87, 88,

59, 60, 6

C6, D6,

F9, F8, F4

B10, B11,

C9 to C11

I/O Circuit

Type

11-G

10-D

Recommended Connection of Unused Pin

Input: Independently connect to AV

SS via a resistor.

or AV

Output: Leave open.

Input: Independently connect to EV

SS via a resistor.

Output: Leave open.

(2/3)

REF0

DD or

R01UH0001EJ0300 Rev.3.00 Page 46 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

(3/3)

Pin No. Pin Alternate Function

GC F1

PDL6 to PDL15

UDMF

UDPF

UVDD

AVREF0

AVREF1

AVSS

RVDD

EVDD

EVSS

FLMD0

REGC

RESET

VDD

VSS

XT1

XT2

AD6 to AD15 77 to 86

−

28 K4

29 K5

30 K6 − Directly connect to VDD and always supply power.

5 B2 − Directly connect to VDD and always supply power.

2 C1, C2 − Directly connect to VSS and always supply power.

17 D2 − Directly connect to VDD and always supply power.

34, 70

33, 69 Note

8 F3

10 E1, E2

14 H3 2

9 D1

12 F1

13 F2

15 H1 16-C Connect to VSS.

16 H2 16-C Leave open.

A7 to A9, B6 to B9, C7, C8, D7

A11, D11, K6, L11,

Note A6, E5 to E7, E11, F5 to F7, G5 to G7, L1, L5

Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14)

F1: 121-pin plastic FBGA (8 × 8)

A1, A2,

G1,

G2, J1

I/O

Circuit

Type

−

− −

Recommended Connection of Unused Pin

Input: Independently connect to EVDD or EVSS via

a resistor.

Output: Leave open.

Pull this pin down to the level of V resistor with a resistance of 50 kΩ or higher.

Directly connect to V

Directly connect to VSS and always supply power.

Directly connect to V flash memory programming mode.

Connection of regulator output stabilization capacitance

F (recommended value))

(4.7

SS by using a

DD and always supply power.

SS in a mode other than the

−

R01UH0001EJ0300 Rev.3.00 Page 47 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 2 PIN FUNCTION

Figure 2-1. Pin I/O Circuits

Type 2

Type 10-N

Schmitt-triggered input with hysteresis characteristics

Type 5

Data

Output

disable

Input

enable

P-ch

N-ch

IN/OUT

Type 10-D

Data

Open drain

Output disable

Note

P-ch

N-ch

IN/OUT

Data

Open drain

Output disable

Input enable

Type 11-G

Data

Output disable

Comparator

(Threshold voltage)

Input enable

OCDM0 bit

+ _

REF0

Note

P-ch

IN/OUT

N-ch

REF0

P-ch

IN/OUT

N-ch

P-ch

N-ch

Type 10-G

Data

Open drain

Output disable

Input enable

P-ch

IN/OUT

N-ch

Type 12-D

Data

Output disable

Input enable

Type 16-C

Analog output

voltage

P-ch

N-ch

REF1

P-ch

N-ch

IN/OUT

Feedback cut-off

P-ch

XT1 XT2

Note Hysteresis characteristics are not available in port mode.

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V850ES/JG3-L CHAPTER 2 PIN FUNCTION

2.4 Cautions

When the power is turned on, the following pins may output an undefined level temporarily even during reset.

• P10/ANO0 pin

• P11/ANO1 pin

• P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin

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V850ES/JG3-L CHAPTER 3 CPU FUNCTION

CHAPTER 3 CPU FUNCTION

The CPU of the V850ES/JG3-L is based on RISC architecture and executes almost all instructions in one clock cycle by

using a 5-stage pipeline.

3.1 Features

Variable length instructions (16 bits/32 bits)

Minimum instruction execution time: 50 ns (operating on main clock (fXX) of 20 MHz: VDD = 2.7 to 3.6 V,

When USB is not used)

62.5 ns (operating on main clock (f

When USB is used)

200 ns (operating on main clock (f

400 ns (operating on main clock (f

30.5

s (operating on subclock (fXT) of 32.768 kHz: VDD = 2.0 to 3.6 V))

Memory space Program space: 64 MB linear

Data space: 4 GB linear

General-purpose registers: 32 bits × 32 registers

Internal 32-bit architecture

5-stage pipeline control

Multiplication/division instruction

Saturation operation instruction

32-bit shift instruction: 1 clock

Load/store instruction with long/short format

Four types of bit manipulation instructions

• SET1

• CLR1

• NOT1

• TST1

XX) of 16 MHz: VDD = 3.0 to 3.6 V,

XX) of 5 MHz: VDD = 2.2 to 3.6 V)

XX) of 2.5 MHz: VDD = 2.0 to 3.6 V)

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V850ES/JG3-L CHAPTER 3 CPU FUNCTION

3.2 CPU Register Set

The registers of the V850ES/JG3-L can be classified into two types: general-purpose program registers and dedicated

system registers. All the registers are 32 bits wide.

For details, refer to the V850ES Architecture User’s Manual.

(1) Program register set

(2) System register set

31 0 31 0

r10

r11

r12

r13

r14

r15

r16

r17

r18

r19

r20

r21

r22

r23

r24

r25

r26

r27

r28

r29

r30

r31

General-purpose registers

(Zero register)

(Assembler-reserved register)

(Stack pointer (SP))

(Global pointer (GP))

(Text pointer (TP))

(Element pointer (EP))

(Link pointer (LP))

EIPC

EIPSW

FEPC

FEPSW

ECR

PSW

CTPC

CTPSW

DBPC

DBPSW

CTBP

(Interrupt status saving register)

(NMI status saving register)

(Interrupt source register)

(Program status word)

(CALLT execution status saving register)

(Exception/debug trap status saving register)

(CALLT base pointer)

31 0

(Program counter)

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3.2.1 Program register set

The program registers include general-purpose registers and a program counter.

(1) General-purpose registers (r0 to r31)

Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data

variable or an address variable.

However, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used.

r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the SLD and

SST instructions as a base pointer when these instructions access the memory. r1, r3 to r5, and r31 are implicitly

used by the assembler and C compiler. When using these registers, save their contents for protection, and then

restore the contents after using the registers. r2 is sometimes used by the real-time OS. If the real-time OS does

not use r2, it can be used as a register for variables.

Table 3-1. Program Registers

Name Usage Operation

r0 Zero register Always holds 0.

r1 Assembler-reserved register Used as working register to create 32-bit immediate data

r2 Register for address/data variable (if real-time OS does not use r2)

r3 Stack pointer Used to create a stack frame when a function is called

r4 Global pointer Used to access a global variable in the data area

r5 Text pointer Used as register that indicates the beginning of a text area (area

where program codes are located)

r6 to r29 Register for address/data variable

r30 Element pointer Used as base pointer to access memory

r31 Link pointer Used when the compiler calls a function

PC Program counter Holds the instruction address during program execution

Remark For further details on the r1, r3 to r5, and r31 that are used in the assembler and C compiler, refer to the

CA850 (C Compiler Package) Assembly Language User’s Manual.

(2) Program counter (PC)

The program counter holds the instruction address during program execution. The lower 32 bits of this register are

valid. Bits 31 to 26 are fixed to 0. A carry from bit 25 to 26 is ignored even if it occurs.

Bit 0 is fixed to 0. This means that execution cannot branch to an odd address.

31 26 25 1 0

Fixed to 0 Instruction address during program execution

Default value

00000000H

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3.2.2 System register set

The system registers control the status of the CPU and hold interrupt information.

These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the

system register numbers listed below.

Table 3-2. System Register Numbers

System Register Name

Number

Note 1

0 Interrupt status saving register (EIPC)

1 Interrupt status saving register (EIPSW)

2 NMI status saving register (FEPC)

3 NMI status saving register (FEPSW)

4 Interrupt source register (ECR)

5 Program status word (PSW)

6 to 15 Reserved for future function expansion (operation is not guaranteed if these

Operand Specification System

LDSR Instruction STSR Instruction

√ √

× √

√ √

× ×

registers are accessed)

16 CALLT execution status saving register (CTPC)

17 CALLT execution status saving register (CTPSW)

18 Exception/debug trap status saving register (DBPC) √

19 Exception/debug trap status saving register (DBPSW) √

20 CALLT base pointer (CTBP)

21 to 31 Reserved for future function expansion (operation is not guaranteed if these

√ √

Note 2

√

Note 2

√

√ √

× ×

Note 2

registers are accessed)

Notes 1. Because only one set of these registers is available, the contents of these registers must be saved by

program if multiple interrupts are enabled.

2. These registers can be accessed only during the interval between the execution of the DBTRAP instruction

or illegal opcode and DBRET instruction execution.

Caution Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when

execution is returned to the main routine by the RETI instruction after interrupt servicing (this is

because bit 0 of the PC is fixed to 0). Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0).

Remark √: Can be accessed

×: Access prohibited

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V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(1) Interrupt status saving registers (EIPC and EIPSW)

EIPC and EIPSW are used to save the status when an interrupt occurs.

If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC,

and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI

status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).

The address of the instruction next to the instruction under execution, except some instructions (see 22.9 Periods

in Which Interrupts Are Not Acknowledged by CPU), is saved to EIPC when a software exception or a maskable

interrupt occurs.

The current contents of the PSW are saved to EIPSW.

Because only one set of interrupt status saving registers is available, the contents of these registers must be saved

by program when multiple interrupts are enabled.

Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved for future function expansion (these bits are always

fixed to 0).

The value of EIPC is restored to the PC and the value of EIPSW to the PSW by the RETI instruction.

31 0

EIPC

EIPSW

31 0

26 25

0 0 0 0

0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

(Contents of saved PC)

(Contents of

saved PSW)

Default value

0xxxxxxxH

(x: Undefined)

Default value

000000xxH

(x: Undefined)

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V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(2) NMI status saving registers (FEPC and FEPSW)

FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs.

If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status

word (PSW) are saved to FEPSW.

The address of the instruction next to the one of the instruction under execution, except some instructions, is saved

to FEPC when an NMI occurs.

The current contents of the PSW are saved to FEPSW.

Because only one set of NMI status saving registers is available, the contents of these registers must be saved by

program when multiple interrupts are enabled (for multiple interrupt servicing using the NMI pin and the INTWDT2

interrupt request signal).

Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these bits are always

fixed to 0).

The value of FEPC is restored to the PC and the value of FEPSW to the PSW by the RETI instruction.

31 0

FEPC

FEPSW

31 0

(3) Interrupt source register (ECR)

The interrupt source register (ECR) holds the source of an exception or interrupt if an exception or interrupt occurs.

This register holds the exception code of each interrupt source. Because this register is a read-only register, data

cannot be written to this register using the LDSR instruction.

31 0

ECR

Bit position Bit name Meaning

31 to 16 FECC Exception code of non-maskable interrupt (NMI)

15 to 0 EICC Exception code of exception or maskable interrupt

26 25

0 0 0 0

0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

FECC EICC

(Contents of saved PC)

16 15

(Contents of saved PSW)

Default value

0xxxxxxxH

(x: Undefined)

Default value

000000xxH

(x: Undefined)

Default value

00000000H

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V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(4) Program status word (PSW)

The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction

execution) and the status of the CPU.

If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated

immediately after completion of LDSR instruction execution. However if the ID flag is set to 1, interrupt requests will

not be acknowledged while the LDSR instruction is being executed.

Bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0).

(1/2)

31 0

PSW

Bit position Flag name Meaning

7 NP Indicates that a non-maskable interrupt (NMI) is being serviced. This bit is set to 1 when an

NMI request is acknowledged, disabling multiple interrupts.

0: NMI is not being serviced. 1: NMI is being serviced.

6 EP Indicates that an exception is being processed. This bit is set to 1 when an exception

occurs. Even if this bit is set, interrupt requests are acknowledged.

0: Exception is not being processed. 1: Exception is being processed.

5 ID Indicates whether a maskable interrupt can be acknowledged.

0: Interrupt enabled 1: Interrupt disabled

4 SAT

3 CY Indicates whether a carry or a borrow occurs as a result of an operation.

2 OV

1 S

0 Z Indicates whether the result of an operation is 0.

Note

Indicates that the result of a saturation operation has overflowed and is saturated. Because

this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. Use the LDSR instruction to clear this bit. This flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction.

0: Not saturated 1: Saturated

0: Carry or borrow does not occur. 1: Carry or borrow occurs.

Note

Indicates whether an overflow occurs during operation.

0: Overflow does not occur. 1: Overflow occurs.

Note

Indicates whether the result of an operation is negative.

0: The result is positive or 0. 1: The result is negative.

0: The result is not 0. 1: The result is 0.

87NP6EP5ID4

000000000000000000000000

SAT3CY2OV

Default value

00000020H

Remark Also read Note on the next page.

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V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(2/2)

Note The result of the operation that has performed saturation processing is determined by the contents of the

OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is

performed.

SAT OV S

Maximum positive value is exceeded 1 1 0 7FFFFFFFH

Maximum negative value is exceeded 1 1 1 80000000H

Positive (maximum value is not exceeded) 0

Negative (maximum value is not exceeded)

Holds value before operation

Flag Status Status of Operation Result

(5) CALLT execution status saving registers (CTPC and CTPSW)

CTPC and CTPSW are CALLT execution status saving registers.

When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and those

of the program status word (PSW) are saved to CTPSW.

The contents saved to CTPC are the address of the instruction next to CALLT.

The current contents of the PSW are saved to CTPSW.

Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved for future function expansion (fixed to 0).

CTPC

CTPSW

31 0

26 25

0 0 0 0

0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

(Saved PC contents)

(Saved PSW

contents)

Result of Operation of Saturation Processing

Operation result itself

Default value

0xxxxxxxH

(x: Undefined)

Default value

000000xxH

(x: Undefined)

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V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(6) Exception/debug trap status saving registers (DBPC and DBPSW)

DBPC and DBPSW are exception/debug trap status registers.

If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those

of the program status word (PSW) are saved to DBPSW.

The contents to be saved to DBPC are the address of the instruction next to the one that is being executed when

an exception trap or debug trap occurs.

The current contents of the PSW are saved to DBPSW.

This register can be read or written only during the interval between the execution of the DBTRAP instruction or

illegal opcode and the DBRET instruction.

Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (fixed to 0).

The value of DBPC is restored to the PC and the value of DBPSW to the PSW by the DBRET instruction.

31 0

DBPC

DBPSW

31 0

(7) CALLT base pointer (CTBP)

The CALLT base pointer (CTBP) is used to specify a table address or generate a target address (bit 0 is fixed to 0).

Bits 31 to 26 of this register are reserved for future function expansion (fixed to 0).

31 0

CTBP

0 0 0 0 0

26 25

0 0 0 0

0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

26 25

(Saved PC contents)

(Base address)

(Saved PSW

contents)

Default value

0xxxxxxxH

(x: Undefined)

Default value

000000xxH

(x: Undefined)

Default value

0xxxxxxxH

(x: Undefined)

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3.3 Operation Modes

The V850ES/JG3-L has the following operation modes.

• Normal operation mode

• Flash memory programming mode

• Self programming mode

• On-chip debug mode

The operation mode is specified according to the status (input level) of the FLMD0 and FLMD1 pins.

To specify the normal operation mode, input a low level to the FLMD0 pin during the reset period.

A high level is input to the FLMD0 pin by the flash memory programmer in the flash memory programming mode if a

flash programmer is connected. In the self-programming mode, input a high level to this pin from an external circuit.

Fix the specification of these pins in the application system and do not change the setting of these pins during

operation.

FLMD0 FLMD1 Operation Mode

H L Flash memory programming mode

H H Setting prohibited

Normal operation mode

Remark H: High level

L: Low level ×: don’t care

(1) Normal operation mode

After the system has been released from the reset state, the pins related to the bus interface are set to the port

mode, execution branches to the reset entry address of the internal ROM, and instruction processing is started.

(2) Flash memory programming mode

When this mode is specified, the internal flash memory can be programmed by using a flash programmer.

(3) Self programming mode

Data can be erased and written from/to the flash memory by using a user application program. For details, see

CHAPTER 31 FLASH MEMORY.

(4) On-chip debug mode

The V850ES/JG3-L is provided with an on-chip debug function that employs the JTAG (Joint Test Action Group)

communication specifications.

For details, see CHAPTER 32 ON-CHIP DEBUG FUNCTION.

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3.4 Address Space

3.4.1 CPU address space

For instruction addressing, up to a combined total of 16 MB of external memory area and internal ROM area, plus an

internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand addressing

(data access), up to 4 GB of a linear address space (data space) is supported. The 4 GB address space, however, is

viewed as 64 images of a 64 MB physical address space. This means that the same 64 MB physical address space is

accessed regardless of the value of bits 31 to 26.

Figure 3-1. Address Space Image

Data space

Program space

Access-prohibited area

Internal RAM area

Access-prohibited area

Image 63

Image 62

4 GB

Image 2

Image 1

On-chip peripheral I/O area

Internal RAM area

Note

•

Note

Access-prohibited area

Image 0

USB function area

External memory area, etc.

16 MB

Internal ROM area (external memory)

16 MB

USB function area

External memory area, etc.

Internal ROM area

(external memory)

64 MB

Note Image 0 appears repeatedly for images 1 to 63.

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3.4.2 Memory map

The areas shown below are reserved in the V850ES/JG3-L.

Figure 3-2. Data Memory Map (Physical Addresses)

FFFFFFFFH

Image 63

FC000000H FBFFFFFFH

Image 62

F8000000H F7FFFFFFH

F4000000H F3FFFFFFH

F0000000H EFFFFFFFH

Image 61

Image 60

03FFFFFFH

03FF0000H 03FEFFFFH

(64 KB)

On-chip peripheral I/O area

(4 KB)

Internal RAM area

(60 KB)

03FFFFFFH

03FFF000H 03FFEFFFH

<R>

03FF0000H

Use prohibited

01000000H 00FFFFFFH

003FFFFFH

Note 1

003FA000H 003F9FFFH

00250000H 0024FFFFH

00200000H

001FFFFFH

00100000H 000FFFFFH

00000000H

10000000H 0FFFFFFFH

0C000000H 0BFFFFFFH

08000000H 07FFFFFFH

04000000H 03FFFFFFH

00000000H

Image 3

Image 2

Image 1

Image 0

(Physical memory

address)

00200000H 001FFFFFH

00000000H

External memory

Note 2

area

(12 MB)

(2 MB)

Expanded internal

RAM area(24 KB)

Use prohibited

USB function area

External memory

Note 2

area

(1 MB)

Internal ROM

Note 3

area

(1 MB)

Notes 1.

PD70F3843, 70F3844 only

2. The V850ES/JG3-L has 22 bits address bus, so the external memory area appears as a repeated 4

MB image.

3. Fetch and read accesses to addresses 00000000H to 000FFFFFH are made to the internal ROM

area. However, data write accesses to these addresses are made to the external memory area.

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Figure 3-3. Program Memory Map

03FFFFFFH

03FFF000H 03FFEFFFH

03FF0000H 03FEFFFFH

01000000H 00FFFFFFH

Use prohibited

(program fetch prohibited area)

Internal RAM area (60 KB)

Use prohibited

(program fetch prohibited area)

<R>

Note

00400000H 003FFFFFH

00200000H 001FFFFFH

00100000H 000FFFFFH

00000000H

External memory area

(program fetch prohibited area)

(12 MB)

Use prohibited

External memory area

(1 MB)

Internal ROM area

(1 MB)

Note The V850ES/JG3-L has 22 bits address bus, so the external memory area appears as a repeated 4 MB

image.

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V850ES/JG3-L CHAPTER 3 CPU FUNCTION

3.4.3 Areas

(1) Internal ROM area

Up to 1 MB is reserved as an internal ROM area.

(a) Internal ROM (256 KB)

256 KB are allocated to addresses 00000000H to 0003FFFFH in the

Accessing addresses 00040000H to 000FFFFFH is prohibited.

Figure 3-4. Internal ROM Area (256 KB)

000FFFFFH

Access-prohibited

area

PD70F3794.

(b) Internal ROM (384 KB)

384 KB are allocated to addresses 00000000H to 0005FFFFH in the

Accessing addresses 00060000H to 000FFFFFH is prohibited.

00040000H 0003FFFFH

Internal ROM

(256 KB)

00000000H

Figure 3-5. Internal ROM Area (384 KB)

000FFFFFH

Access-prohibited

area

00060000H 0005FFFFH

PD70F3795.

Internal ROM

(384 KB)

00000000H

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512 KB are allocated to addresses 00000000H to 0007FFFFH in the μPD70F3796.

Accessing addresses 00080000H to 000FFFFFH is prohibited.

Figure 3-6. Internal ROM Area (512 KB)

000FFFFFH

Access-prohibited

00080000H 0007FFFFH

area

Internal ROM

(512 KB)

(d) Internal ROM (768 KB)

768 KB are allocated to addresses 00000000H to 000BFFFFH in the

Accessing addresses 000C0000H to 000FFFFFH is prohibited.

00000000H

Figure 3-7. Internal ROM Area (768 KB)

000FFFFFH

000C0000H 000BFFFFH

Access-prohibited

area

Internal ROM

(768 KB)

PD70F3843.

00000000H

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V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(e) Internal ROM (1 MB)

1 MB are allocated to addresses 00000000H to 000FFFFFH in the μPD70F3844.

Figure 3-8. Internal ROM Area (1 MB)

000FFFFFH

Internal ROM

(1 MB)

00000000H

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(2) Internal RAM area

Up to 60 KB allocated to physical addresses 03FF0000H to 03FFEFFFH are reserved as the internal RAM area.

PD70F3843, 70F3844 include a expanded internal RAM in addition to the internal RAM.

The RAM capacity of V850ES/JG3-L is as follows.

Table 3-3 RAM area

Product Name Internal RAM Expanded internal RAM Total RAM

PD70F3794 40 KB - 40 KB

PD70F3795 40 KB - 40 KB

PD70F3796 40 KB - 40 KB

PD70F3843 56 KB 24 KB 80 KB

PD70F3844 56 KB 24 KB 80 KB

(a) Internal RAM (40 KB)

40 KB are allocated to addresses 03FF5000H to 03FFEFFFH of

Accessing addresses 03FF0000H to 03FF4FFFH is prohibited.

Figure 3-9. Internal RAM Area (40 KB)

Physical address space

03FFEFFFH

PD70F3794, 70F3795, 70F3796.

Logical address space

FFFFEFFFH

03FF5000H 03FF4FFFH

03FF0000H

Internal RAM

(40 KB)

FFFF5000H FFFF4FFFH

Access-prohibited

area

FFFF0000H

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V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(b) Internal RAM (56 KB)

56 KB are allocated to addresses 03FF1000H to 03FFEFFFH of μPD70F3843, 70F3844.

Accessing addresses 03FF0000H to 03FF0FFFH is prohibited.

Figure 3-10. Internal RAM Area (56 KB)

Physical address space

03FFEFFFH

Internal RAM

(56 KB)

Logical address space

FFFFEFFFH

03FF1000H 03FF0FFFH

03FF0000H

Access-prohibited

area

FFFF1000H FFFF0FFFH FFFF0000H

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(3) Expanded internal RAM (24 KB)

The expanded internal RAM of 24 KB is allocated to addresses 003FA000H to 003FFFFFH of the μPD70F3843,

70F3844.

The expanded internal RAM area is accessed via the external bus interface. Before accessing the expanded

internal RAM area, be sure to set the registers related to the external bus interface (initialization of the expanded

internal RAM).

Figure 3-11. Expanded internal RAM (24 KB)

Physical address space

Access-prohibited

area

003FFFFFH

Expaned internal RAM

003FA000H 003F9FFFH

The initial settings for the expanded internal RAM are shown below.

Cautions 1. If the expanded internal RAM is used with any but the following initial settings, operation

is not guaranteed.

2. When using the external memory and expanded internal RAM simultaneously, set the

external bus interface and expanded internal RAM at the same time.

• BSC register setting

Bits 2 must be set to 1.

• DWC0 register setting

Bits 6 to 4 must be set to 001.

• AWC register setting

Bits 3 to 2 must be set to 00.

• BCC register setting

Bits 3 must be set to 0.

(24 KB)

Access-prohibited

area

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V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(4) On-chip peripheral I/O area

4 KB allocated to physical addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area.

Figure 3-12. On-Chip Peripheral I/O Area

Physical address space Logical address space

<R>

03FFFFFFH

On-chip peripheral I/O area

(4 KB)

03FFF000H

FFFFFFFFH

FFFFF000H

Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the on-chip

peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area.

Cautions 1. When a peripheral I/O register is accessed in word units, a word area is accessed twice in

halfword units in the order of lower area then higher area, with the lower 2 bits of the address

ignored.

2. If a peripheral I/O register that can be accessed in byte units is accessed in halfword units,

the lower 8 bits are valid. The higher 8 bits are undefined when the register is read and are

invalid when the register is written.

3. Addresses not defined as registers are reserved for future expansion. The operation is

undefined and not guaranteed when these addresses are accessed.

4. The internal ROM/RAM area and on-chip peripheral I/O area are assigned to successive

addresses.

When accessing the internal ROM/RAM area by incrementing or decrementing addresses

using a pointer operation for example, be careful not to access the on-chip peripheral I/O area

by mistakenly extending over the internal ROM/RAM area boundary.

(5) External memory area

13 MB (00100000H to 001FFFFFH, 00400000H to 00FFFFFFH) are allocated as the external memory area. For

details, see CHAPTER 5 BUS CONTROL FUNCTION.

Caution The V850ES/JG3-L has 22 bits address bus, so the external memory area appears as a repeated 4

MB image.

R01UH0001EJ0300 Rev.3.00 Page 69 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

3.4.4 Wraparound of data space

The result of an operand address calculation operation that exceeds 32 bits is ignored.

Therefore, the highest address of the data space, FFFFFFFFH, and the lowest address, 00000000H, are contiguous,

and wraparound occurs at the boundary of these addresses.

Figure 3-13. Wraparound of Data Space

00000001H

00000000H

FFFFFFFFH

FFFFFFFEH

Data space

(+) direction (−) direction

Data space

3.4.5 Recommended use of address space

The architecture of the V850ES/JG3-L requires that a register that serves as a pointer be secured for address

generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be directly

accessed by an instruction for operand data. Because the number of general-purpose registers that can be used as a

pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is

changed, as many general-purpose registers as possible can be secured for variables, and the program size can be

reduced.

(1) Program space

Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid.

Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H

unconditionally corresponds to the memory map.

To use the internal RAM area as the program space, access the following addresses.

Caution If a branch instruction is at the upper limit of the internal RAM area, a prefetch operation (invalid

fetch) straddling the on-chip peripheral I/O area does not occur.

Product Name RAM Size Access Address

PD70F3794

PD70F3795

PD70F3796

PD70F3843

PD70F3844

40 KB 03FF5000H to 03FFEFFFH

56 KB 03FF1000H to 03FFEFFFH

R01UH0001EJ0300 Rev.3.00 Page 70 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(2) Data space

With the V850ES/JG3-L, it seems that there are sixty-four 64 MB (26-bit address) physical address spaces on the 4

GB (32-bit address) CPU address space. Therefore, the most significant bit (bit 25) of a 26-bit address of these 64

MB spaces is sign-extended to 32 bits and allocated as an address.

Figure 3-14. Sign Extension in Data Space

31 0

31 026 25

0 0 0 0

26 25

A 26-bit address (64 MB) can be specified.

3FFFFFFH

0000000H

Image 0

64 MB

A 32-bit address (4 GB) can be specified. An image of 64 MB appears repeatedly in the 4 GB space.

FFFFFFFFH

FC000000H FBFFFFFFH

F8000000H F7FFFFFFH

F4000000H F3FFFFFFH

F0000000H EFFFFFFFH

10000000H 0FFFFFFFH

0C000000H 0BFFFFFFH

08000000H 07FFFFFFH

04000000H 03FFFFFFH

00000000H

Image 63

Image 62

Image 61

Image 60

Image 3

Image 2

Image 1

Image 0

64 MB

4 GB

64 MB

R01UH0001EJ0300 Rev.3.00 Page 71 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(a) Application example of wraparound

If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32

KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can be

addressed by one pointer.

The zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers

dedicated to pointers.

Figure 3-15. Example of Data Space Usage in

0003FFFFH

00007FFFH

PD70F3794

(R = )

00000000H

FFFFF000H FFFFEFFFH

FFFF8000H

Internal ROM area

On-chip peripheral

I/O area

Internal RAM area

32 KB

4 KB

28 KB

R01UH0001EJ0300 Rev.3.00 Page 72 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

Figure 3-16. Recommended Memory Map (μPD70F3794)

FFFFFFFFH

FFFFF000H FFFFEFFFH

FFFF0000H FFFEFFFFH

04000000H 03FFFFFFH

Access-prohibited

03FFF000H 03FFEFFFH

03FFB000H 03FFAFFFH

03FF0000H 03FEFFFFH

Internal RAM

Data spaceProgram space

On-chip

peripheral I/O

Internal RAM

On-chip

peripheral I/O

Internal RAM

Access-prohibited

FFFFFFFFH

FFFFF000H FFFFEFFFH

FFFFB000H FFFFAFFFH FFFF0000H FFFEFFFFH

<R>

Program space

64 MB

01000000H 00FFFFFFH

00100000H 000FFFFFH 00040000H 0003FFFFH

00000000H

Access-prohibited

External

Note

memory

Internal ROM

External

Note

memory

Internal ROM

00100000H 000FFFFFH

00000000H

Note The V850ES/JG3-L has 22 bits address bus, so the external memory area appears as a repeated 4 MB

image.

Remark indicates the recommended area.

R01UH0001EJ0300 Rev.3.00 Page 73 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

3.4.6 Peripheral I/O registers

(1/11)

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFF004H Port DL register PDL √ 0000H

FFFFF004H Port DL register L PDLL

FFFFF005H Port DL register H PDLH

FFFFF006H Port DH register PDH

FFFFF00AH Port CT register PCT

FFFFF00CH Port CM register PCM

R/W

√ √ √ √ √ √ √ √ √ √

FFFFF024H Port DL mode register PMDL

FFFFF024H Port DL mode register L PMDLL

FFFFF025H Port DL mode register H PMDLH

FFFFF026H Port DH mode register PMDH

FFFFF02AH Port CT mode register PMCT

FFFFF02CH Port CM mode register PMCM

√ √ √ √ √ √ √ √ √ √

FFFFF044H Port DL mode control register PMCDL

FFFFF044H Port DL mode control register L PMCDLL

FFFFF045H Port DL mode control register H PMCDLH

FFFFF046H Port DH mode control register PMCDH

FFFFF04AH Port CT mode control register PMCCT

FFFFF04CH Port CM mode control register PMCCM

√ √ √ √ √ √ √ √ √ √

FFFFF066H Bus size configuration register BSC

FFFFF06EH System wait control register VSWC

√

FFFFF080H DMA source address register 0L DSA0L

FFFFF082H DMA source address register 0H DSA0H

FFFFF084H DMA destination address register 0L DDA0L

FFFFF086H DMA destination address register 0H DDA0H

FFFFF088H DMA source address register 1L DSA1L

FFFFF08AH DMA source address register 1H DSA1H

FFFFF08CH DMA destination address register 1L DDA1L

FFFFF08EH DMA destination address register 1H DDA1H

FFFFF090H DMA source address register 2L DSA2L

FFFFF092H DMA source address register 2H DSA2H

FFFFF094H DMA destination address register 2L DDA2L

FFFFF096H DMA destination address register 2H DDA2H

FFFFF098H DMA source address register 3L DSA3L

FFFFF09AH DMA source address register 3H DSA3H

FFFFF09CH DMA destination address register 3L DDA3L

FFFFF09EH DMA destination address register 3H DDA3H

FFFFF0C0H DMA transfer count register 0 DBC0

FFFFF0C2H DMA transfer count register 1 DBC1

FFFFF0C4H DMA transfer count register 2 DBC2

FFFFF0C6H DMA transfer count register 3 DBC3

FFFFF0D0H DMA addressing control register 0 DADC0

√ 0000H

Note The output latch is 00H or 0000H. When these registers are in the input mode, the pin statuses are read.

Default Value

Note

00H

Note

00H

Note

00H

Note

00H

Note

00H

FFFFH

√

FFH

0000H

√

00H

5555H

√

77H

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Note

R01UH0001EJ0300 Rev.3.00 Page 74 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

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Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFF0D2H DMA addressing control register 1 DADC1

FFFFF0D4H DMA addressing control register 2 DADC2

FFFFF0D6H DMA addressing control register 3 DADC3

FFFFF0E0H DMA channel control register 0 DCHC0

FFFFF0E2H DMA channel control register 1 DCHC1

FFFFF0E4H DMA channel control register 2 DCHC2

FFFFF0E6H DMA channel control register 3 DCHC3

FFFFF100H Interrupt mask register 0 IMR0

FFFFF100H Interrupt mask register 0L IMR0L

FFFFF101H Interrupt mask register 0H IMR0H

FFFFF102H Interrupt mask register 1 IMR1

FFFFF102H Interrupt mask register 1L IMR1L

FFFFF103H Interrupt mask register 1H IMR1H

FFFFF104H Interrupt mask register 2 IMR2

FFFFF104H Interrupt mask register 2L IMR2L

FFFFF105H Interrupt mask register 2H IMR2H

FFFFF106H Interrupt mask register 3 IMR3

FFFFF106H Interrupt mask register 3L IMR3L

FFFFF107H Interrupt mask register 3H IMR3H

FFFFF110H Interrupt control register (INTLVI) LVIIC

FFFFF112H Interrupt control register (INTP0) PIC0

FFFFF114H Interrupt control register (INTP1) PIC1

FFFFF116H Interrupt control register (INTP2) PIC2

FFFFF118H Interrupt control register (INTP3) PIC3

FFFFF11AH Interrupt control register (INTP4) PIC4

FFFFF11CH Interrupt control register (INTP5) PIC5

FFFFF11EH Interrupt control register (INTP6) PIC6

FFFFF120H Interrupt control register (INTP7) PIC7

FFFFF122H Interrupt control register (INTTQ0OV) TQ0OVIC

FFFFF124H Interrupt control register (INTTQ0CC0) TQ0CCIC0

FFFFF126H Interrupt control register (INTTQ0CC1) TQ0CCIC1

FFFFF128H Interrupt control register (INTTQ0CC2) TQ0CCIC2

FFFFF12AH Interrupt control register (INTTQ0CC3) TQ0CCIC3

FFFFF12CH Interrupt control register (INTTP0OV) TP0OVIC

FFFFF12EH Interrupt control register (INTTP0CC0) TP0CCIC0

FFFFF130H Interrupt control register (INTTP0CC1) TP0CCIC1

FFFFF132H Interrupt control register (INTTP1OV) TP1OVIC

FFFFF134H Interrupt control register (INTTP1CC0) TP1CCIC0

FFFFF136H Interrupt control register (INTTP1CC1) TP1CCIC1

FFFFF138H Interrupt control register (INTTP2OV) TP2OVIC

FFFFF13AH Interrupt control register (INTTP2CC0) TP2CCIC0

FFFFF13CH Interrupt control register (INTTP2CC1) TP2CCIC1

FFFFF13EH Interrupt control register (INTTP3OV) TP3OVIC

R/W

√ √ √ √ √ √ √ √

√ √ √ √

√ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √

Default Value

0000H

√

0000H

√

0000H

√

00H

FFFFH

√

FFH

FFFFH

√

FFH

FFFFH

√

FFH

FFFFH

√

FFH

47H

R01UH0001EJ0300 Rev.3.00 Page 75 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(3/11)

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFF140H Interrupt control register (INTTP3CC0) TP3CCIC0

FFFFF142H Interrupt control register (INTTP3CC1) TP3CCIC1

FFFFF144H Interrupt control register (INTTP4OV) TP4OVIC

FFFFF146H Interrupt control register (INTTP4CC0) TP4CCIC0

FFFFF148H Interrupt control register (INTTP4CC1) TP4CCIC1

FFFFF14AH Interrupt control register (INTTP5OV) TP5OVIC

FFFFF14CH Interrupt control register (INTTP5CC0) TP5CCIC0

FFFFF14EH Interrupt control register (INTTP5CC1) TP5CCIC1

FFFFF150H Interrupt control register (INTTM0EQ0) TM0EQIC0

FFFFF152H Interrupt control register (INTCB0R/INTIIC1) CB0RIC/IICIC1

FFFFF154H Interrupt control register (INTCB0T) CB0TIC

FFFFF156H Interrupt control register (INTCB1R) CB1RIC

FFFFF158H Interrupt control register (INTCB1T) CB1TIC

FFFFF15AH Interrupt control register (INTCB2R) CB2RIC

FFFFF15CH Interrupt control register (INTCB2T) CB2TIC

FFFFF15EH Interrupt control register (INTCB3R) CB3RIC

FFFFF160H Interrupt control register (INTCB3T) CB3TIC

FFFFF162H Interrupt control register (INTUA0R/INTCB4R)

FFFFF164H Interrupt control register (INTUA0T/INTCB4T) UA0TIC/CB4TIC

FFFFF166H Interrupt control register (INTUA1R/INTIIC2) UA1RIC/IICIC2

FFFFF168H Interrupt control register (INTUA1T) UA1TIC

FFFFF16AH Interrupt control register (INTUA2R/INTIIC0) UA2RIC/IICIC0

FFFFF16CH Interrupt control register (INTUA2T) UA2TIC

FFFFF16EH Interrupt control register (INTAD) ADIC

FFFFF170H Interrupt control register (INTDMA0) DMAIC0

FFFFF172H Interrupt control register (INTDMA1) DMAIC1

FFFFF174H Interrupt control register (INTDMA2) DMAIC2

FFFFF176H Interrupt control register (INTDMA3) DMAIC3

FFFFF178H Interrupt control register (INTKR) KRIC

FFFFF17AH Interrupt control register (INTWTI/INTRTC2) WTIIC/RTC2IC

FFFFF17CH Interrupt control register (INTWT/INTRTC0) WTIC/RTC0IC

FFFFF17EH Interrupt control register (INTRTC1) RTC1C

FFFFF180H Interrupt control register (INTUA3R) UA3RIC

FFFFF182H Interrupt control register (INTUA3T) UA3TI

FFFFF184H Interrupt control register (INTUA4R) UA4RIC

FFFFF186H Interrupt control register (INTUA4T) UA4TIC

FFFFF188H Interrupt control register (INTUC0R) UC0RIC

FFFFF18AH Interrupt control register (INTUC0T) UC0TIC

FFFFF1FAH In-service priority register ISPR R

FFFFF1FCH Command register PRCMD W

FFFFF1FEH Power save control register PSC

UA0RIC/CB4RIC

Note

R/W

√ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √

√ √

Note This is a special register.

√

Default Value

47H

00H

Undefined

00H

R01UH0001EJ0300 Rev.3.00 Page 76 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(4/11)

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFF200H A/D converter mode register 0 ADA0M0

FFFFF201H A/D converter mode register 1 ADA0M1

FFFFF202H A/D converter channel specification register ADA0S

FFFFF203H A/D converter mode register 2 ADA0M2

FFFFF204H Power-fail compare mode register ADA0PFM

FFFFF205H Power-fail compare threshold value register ADA0PFT

FFFFF210H A/D conversion result register 0 ADA0CR0

FFFFF211H A/D conversion result register 0H ADA0CR0H

FFFFF212H A/D conversion result register 1 ADA0CR1

FFFFF213H A/D conversion result register 1H ADA0CR1H

FFFFF214H A/D conversion result register 2 ADA0CR2

FFFFF215H A/D conversion result register 2H ADA0CR2H

FFFFF216H A/D conversion result register 3 ADA0CR3

FFFFF217H A/D conversion result register 3H ADA0CR3H

FFFFF218H A/D conversion result register 4 ADA0CR4

FFFFF219H A/D conversion result register 4H ADA0CR4H

FFFFF21AH A/D conversion result register 5 ADA0CR5

FFFFF21BH A/D conversion result register 5H ADA0CR5H

FFFFF21CH A/D conversion result register 6 ADA0CR6

FFFFF21DH A/D conversion result register 6H ADA0CR6H

FFFFF21EH A/D conversion result register 7 ADA0CR7

FFFFF21FH A/D conversion result register 7H ADA0CR7H

FFFFF220H A/D conversion result register 8 ADA0CR8

FFFFF221H A/D conversion result register 8H ADA0CR8H

FFFFF222H A/D conversion result register 9 ADA0CR9

FFFFF223H A/D conversion result register 9H ADA0CR9H

FFFFF224H A/D conversion result register 10 ADA0CR10

FFFFF225H A/D conversion result register 10H ADA0CR10H

FFFFF226H A/D conversion result register 11 ADA0CR11

FFFFF227H A/D conversion result register 11H ADA0CR11H

FFFFF280H D/A conversion value setting register 0 DA0CS0

FFFFF281H D/A conversion value setting register 1 DA0CS1

FFFFF282H D/A converter mode register DA0M

FFFFF300H Key return mode register KRM

FFFFF308H Selector operation control register 0 SELCNT0

FFFFF310H CRC input register CRCIN

FFFFF312H CRC data register CRCD √ 0000H

FFFFF318H Noise elimination control register NFC

FFFFF320H Prescaler mode register 1 PRSM1

FFFFF321H Prescaler compare register 1 PRSCM1

FFFFF324H Prescaler mode register 2 PRSM2

FFFFF325H Prescaler compare register 2 PRSCM2

FFFFF328H Prescaler mode register 3 PRSM3

FFFFF329H Prescaler compare register 3 PRSCM3

R/W

√ √ √ √ √ √ √ √ √ √ √ √

√ √ √ √ √ √

√ √

√

√ √ √

√

Default Value

00H

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

00H

R01UH0001EJ0300 Rev.3.00 Page 77 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(5/11)

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFF331H Regulator protection register REGPR

FFFFF332H Regulator output voltage level control register REGOVL0

FFFFF340H IIC division clock select register OCKS0

FFFFF344H IIC division clock select register OCKS1

FFFFF348H Clock select register OCKS2

FFFFF380H Clock through select register CKTHSEL

FFFFF400H Port 0 register P0

FFFFF402H Port 1 register P1

R/W

√ √ √ √

√ √ √ √ √ √ √

FFFFF406H Port 3 register P3 √ 0000H

FFFFF406H Port 3 register L P3L

FFFFF407H Port 3 register H P3H

FFFFF408H Port 4 register P4

FFFFF40AH Port 5 register P5

FFFFF40EH Port 7 register L P7L

FFFFF40FH Port 7 register H P7H

√ √ √ √ √ √

FFFFF412H Port 9 register P9 √ 0000H

FFFFF412H Port 9 register L P9L

FFFFF413H Port 9 register H P9H

FFFFF420H Port 0 mode register PM0

FFFFF422H Port 1 mode register PM1

√ √ √ √ √ √ √ √

FFFFF426H Port 3 mode register PM3

FFFFF426H Port 3 mode register L PM3L

FFFFF427H Port 3 mode register H PM3H

FFFFF428H Port 4 mode register PM4

FFFFF42AH Port 5 mode register PM5

FFFFF42EH Port 7 mode register L PM7L

FFFFF42FH Port 7 mode register H PM7H

√ √ √ √ √ √ √ √ √ √ √ √

FFFFF432H Port 9 mode register PM9

FFFFF432H Port 9 mode register L PM9L

FFFFF433H Port 9 mode register H PM9H

FFFFF440H Port 0 mode control register PMC0

√ √ √ √ √ √

FFFFF446H Port 3 mode control register PMC3

FFFFF446H Port 3 mode control register L PMC3L

FFFFF447H Port 3 mode control register H PMC3H

FFFFF448H Port 4 mode control register PMC4

FFFFF44AH Port 5 mode control register PMC5

√ √ √ √ √ √ √ √

FFFFF452H Port 9 mode control register PMC9

FFFFF452H Port 9 mode control register L PMC9L

FFFFF453H Port 9 mode control register H PMC9H

FFFFF460H Port 0 function control register PFC0

√ √ √ √ √ √

FFFFF466H Port 3 function control register PFC3

FFFFF466H Port 3 function control register L PFC3L

FFFFF467H Port 3 function control register H PFC3H

√ √ √ √

Note The output latch is 00H or 0000H. When these registers are input, the pin statuses are read.

Default Value

00H

Note

00H

Note

00H

Note

00H

Note

00H

Note

00H

Note

00H

Note

00H

Note

00H

Note

00H

Note

00H

FFH

FFFFH

√

FFH

FFFFH

√

FFH

00H

0000H

√

00H

0000H

√

00H

0000H

√

00H

Note

R01UH0001EJ0300 Rev.3.00 Page 78 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(6/11)

Manipulatable Bits Default Value Address Function Register Name Symbol R/W

1 8 16

FFFFF468H Port 4 function control register PFC4

FFFFF46AH Port 5 function control register PFC5

FFFFF472H Port 9 function control register PFC9

FFFFF472H Port 9 function control register L PFC9L

FFFFF473H Port 9 function control register H PFC9H

FFFFF484H Data wait control register 0 DWC0

FFFFF488H Address wait control register AWC

FFFFF48AH Bus cycle control register BCC

FFFFF540H TMQ0 control register 0 TQ0CTL0

FFFFF541H TMQ0 control register 1 TQ0CTL1

FFFFF542H TMQ0 I/O control register 0 TQ0IOC0

FFFFF543H TMQ0 I/O control register 1 TQ0IOC1

FFFFF544H TMQ0 I/O control register 2 TQ0IOC2

FFFFF545H TMQ0 option register 0 TQ0OPT0

FFFFF546H TMQ0 capture/compare register 0 TQ0CCR0

FFFFF548H TMQ0 capture/compare register 1 TQ0CCR1

FFFFF54AH TMQ0 capture/compare register 2 TQ0CCR2

FFFFF54CH TMQ0 capture/compare register 3 TQ0CCR3

FFFFF54EH TMQ0 counter read buffer register TQ0CNT R

FFFFF590H TMP0 control register 0 TP0CTL0

FFFFF591H TMP0 control register 1 TP0CTL1

FFFFF592H TMP0 I/O control register 0 TP0IOC0

FFFFF593H TMP0 I/O control register 1 TP0IOC1

FFFFF594H TMP0 I/O control register 2 TP0IOC2

FFFFF595H TMP0 option register 0 TP0OPT0

FFFFF596H TMP0 capture/compare register 0 TP0CCR0

FFFFF598H TMP0 capture/compare register 1 TP0CCR1

FFFFF59AH TMP0 counter read buffer register TP0CNT R

FFFFF5A0H TMP1 control register 0 TP1CTL0

FFFFF5A6H TMP1 capture/compare register 0 TP1CCR0

FFFFF5A8H TMP1 capture/compare register 1 TP1CCR1

FFFFF5AAH TMP1 counter read buffer register TP1CNT R

FFFFF5B0H TMP2 control register 0 TP2CTL0

FFFFF5B1H TMP2 control register 1 TP2CTL1

FFFFF5B2H TMP2 I/O control register 0 TP2IOC0

FFFFF5B3H TMP2 I/O control register 1 TP2IOC1

FFFFF5B4H TMP2 I/O control register 2 TP2IOC2

FFFFF5B5H TMP2 option register 0 TP2OPT0

FFFFF5B6H TMP2 capture/compare register 0 TP2CCR0

R/W

√ √ √ √

√ √ √ √ √ √ √ √ √ √ √ √

√ 0000H

√ √ √ √ √ √ √ √ √ √ √ √

√ 0000H

√ √

√ 0000H

√ √ √ √ √ √ √ √ √ √ √ √

√ 0000H

00H

√

00H

√ √ √

00H

√ √ √

√

00H

√

00H

√

00H

0000H

7777H

FFFFH

AAAAH

0000H

R01UH0001EJ0300 Rev.3.00 Page 79 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(7/11)

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFF5B8H TMP2 capture/compare register 1 TP2CCR1 R/W

FFFFF5BAH TMP2 counter read buffer register TP2CNT R

FFFFF5C0H TMP3 control register 0 TP3CTL0

FFFFF5C1H TMP3 control register 1 TP3CTL1

FFFFF5C2H TMP3 I/O control register 0 TP3IOC0

FFFFF5C3H TMP3 I/O control register 1 TP3IOC1

FFFFF5C4H TMP3 I/O control register 2 TP3IOC2

FFFFF5C5H TMP3 option register 0 TP3OPT0

FFFFF5C6H TMP3 capture/compare register 0 TP3CCR0

FFFFF5C8H TMP3 capture/compare register 1 TP3CCR1

FFFFF5CAH TMP3 counter read buffer register TP3CNT R

FFFFF5D0H TMP4 control register 0 TP4CTL0

FFFFF5D1H TMP4 control register 1 TP4CTL1

FFFFF5D2H TMP4 I/O control register 0 TP4IOC0

FFFFF5D3H TMP4 I/O control register 1 TP4IOC1

FFFFF5D4H TMP4 I/O control register 2 TP4IOC2

FFFFF5D5H TMP4 option register 0 TP4OPT0

FFFFF5D6H TMP4 capture/compare register 0 TP4CCR0

FFFFF5D8H TMP4 capture/compare register 1 TP4CCR1

FFFFF5DAH TMP4 counter read buffer register TP4CNT R

FFFFF5E0H TMP5 control register 0 TP5CTL0

FFFFF5E1H TMP5 control register 1 TP5CTL1

FFFFF5E2H TMP5 I/O control register 0 TP5IOC0

FFFFF5E3H TMP5 I/O control register 1 TP5IOC1

FFFFF5E4H TMP5 I/O control register 2 TP5IOC2

FFFFF5E5H TMP5 option register 0 TP5OPT0

FFFFF5E6H TMP5 capture/compare register 0 TP5CCR0

FFFFF5E8H TMP5 capture/compare register 1 TP5CCR1

FFFFF5EAH TMP5 counter read buffer register TP5CNT R

FFFFF680H Watch timer operation mode register WTM

FFFFF690H TMM0 control register 0 TM0CTL0

FFFFF694H TMM0 compare register 0 TM0CMP0

FFFFF6C0H Oscillation stabilization time select register OSTS

FFFFF6C1H PLL lockup time specification register PLLS

FFFFF6D0H Watchdog timer mode register 2 WDTM2

FFFFF6D1H Watchdog timer enable register WDTE

FFFFF6E0H Real-time output buffer register 0L RTBL0

FFFFF6E2H Real-time output buffer register 0H RTBH0

FFFFF6E4H Real-time output port mode register 0 RTPM0

FFFFF6E5H Real-time output port control register 0 RTPC0

FFFFF700H Port 0 function control expansion register PFCE0

FFFFF706H Port 3 function control expansion register L PFCE3L

FFFFF70AH Port 5 function control expansion register PFCE5

R/W

√ √ √ √ √ √ √ √ √ √ √ √

√ 0000H

√ √ √ √ √ √ √ √ √ √ √ √

√ 0000H

√ √ √ √ √ √ √ √ √ √ √ √

√ 0000H

√ √ √ √

√ √ √ √ √ √ √ √ √ √ √ √ √ √

√ √ √ √

Default Value

0000H

√

0000H

√

00H

0000H

√

0000H

√

00H

0000H

√

0000H

√

00H

0000H

√

0000H

√

00H

0000H

√

06H

03H

67H

9AH

00H

R01UH0001EJ0300 Rev.3.00 Page 80 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(8/11)

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFF712H Port 9 function control expansion register PFCE9

FFFFF712H Port 9 function control expansion register L PFCE9L

FFFFF713H Port 9 function control expansion register H PFCE9H

FFFFF802H System status register SYS

FFFFF80CH Internal oscillation mode register RCM

FFFFF810H DMA trigger factor register 0 DTFR0

FFFFF812H DMA trigger factor register 1 DTFR1

FFFFF814H DMA trigger factor register 2 DTFR2

FFFFF816H DMA trigger factor register 3 DTFR3

FFFFF820H Power save mode register PSMR

FFFFF822H Clock control register CKC

FFFFF824H Lock register LOCKR R

FFFFF828H Processor clock control register PCC

FFFFF82CH PLL control register PLLCTL

FFFFF82EH CPU operation clock status register CCLS R

FFFFF870H Clock monitor mode register CLM

FFFFF888H Reset source flag register RESF

FFFFF890H Low-voltage detection register LVIM

FFFFF891H Low-voltage detection level select register LVIS

FFFFF8B0H Prescaler mode register 0 PRSM0

FFFFF8B1H Prescaler compare register 0 PRSCM0

FFFFF9FCH On-chip debug mode register OCDM

FFFFFA00H UARTA0 control register 0 UA0CTL0

FFFFFA01H UARTA0 control register 1 UA0CTL1

FFFFFA02H UARTA0 control register 2 UA0CTL2

FFFFFA03H UARTA0 option control register 0 UA0OPT0

FFFFFA04H UARTA0 status register UA0STR

FFFFFA06H UARTA0 receive data register UA0RX R

FFFFFA07H UARTA0 transmit data register UA0TX

FFFFFA10H UARTA1 control register 0 UA1CTL0

FFFFFA11H UARTA1 control register 1 UA1CTL1

FFFFFA12H UARTA1 control register 2 UA1CTL2

FFFFFA13H UARTA1 option control register 0 UA1OPT0

FFFFFA14H UARTA1 status register UA1STR

FFFFFA16H UARTA1 receive data register UA1RX R

FFFFFA17H UARTA1 transmit data register UA1TX

FFFFFA20H UARTA2 control register 0 UA2CTL0

FFFFFA21H UARTA2 control register 1 UA2CTL1

FFFFFA22H UARTA2 control register 2 UA2CTL2

FFFFFA23H UARTA2 option control register 0 UA2OPT0

FFFFFA24H UARTA2 status register UA2STR

FFFFFA26H UARTA2 receive data register UA2RX R

FFFFFA27H UARTA2 transmit data register UA2TX R/W

Note

R/W

√ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √

R/W

√ √ √ √ √ √ √ √ √ √ √ √

√ √

√ √ √ √

√ √

√ √ √ √

√ √

√ √ √ √

Note This is a special register.

√

√ √

Default Value

0000H

00H

0AH

00H

03H

01H

00H

01H

10H

00H

FFH

14H

00H

FFH

10H

00H

FFH

14H

00H

FFH

10H

00H

FFH

14H

00H

FFH

R01UH0001EJ0300 Rev.3.00 Page 81 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(9/11)

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFFA30H UARTA3 control register 0 UA3CTL0

FFFFFA31H UARTA3 control register 1 UA3CTL1

FFFFFA32H UARTA3 control register 2 UA3CTL2

FFFFFA33H UARTA3 option control register 0 UA3OPT0

FFFFFA34H UARTA3 status register UA3STR

FFFFFA36H UARTA3 receive data register UA3RX R √ FFH

FFFFFA37H UARTA3 transmit data register UA3TX R/W √ FFH

FFFFFA40H UARTA4 control register 0 UA4CTL0

FFFFFA41H UARTA4 control register 1 UA4CTL1

FFFFFA42H UARTA4 control register 2 UA4CTL2 √ FFH

FFFFFA43H UARTA4 option control register 0 UA4OPT0

FFFFFA44H UARTA4 status register UA4STR

FFFFFA46H UARTA4 receive data register UA4RX R √ FFH

FFFFFA47H UARTA4 transmit data register UA4TX

FFFFFA50H UARTA5 control register 0 UA5CTL0

FFFFFA51H UARTA5 control register 1 UA5CTL1 √ 00H

FFFFFA52H UARTA5 control register 2 UA5CTL2 √ FFH

FFFFFA53H UARTA5 option control register 0 UA5OPT0

FFFFFA54H UARTA5 status register UA5STR

FFFFFA56H UARTA5 receive data register UA5RX R

FFFFFA57H UARTA5 transmit data register UA5TX

FFFFFAA0H UARTC0 control register 0 UC0CTL0

FFFFFAA1H UARTC0 control register 1 UC0CTL1

FFFFFAA2H UARTC0 control register 2 UC0CTL2

FFFFFAA3H UARTC0 option control register 0 UC0OPT0

FFFFFAA4H UARTC0 status register UC0STR

FFFFFAA6H UARTC0 receive data register UC0RX

FFFFFAA6H UARTC0 receive data register L UC0RXL

FFFFFAA8H UARTC0 transmit data register UC0TX

FFFFFAA8H UARTC0 transmit data register L UC0TXL

FFFFFAAAH UARTC0 option control register 1 UC0OPT1

FFFFFAD0H Sub-count register RC1SUBC R

FFFFFAD2H Second count register RC1SEC

FFFFFAD3H Minute count register RC1MIN √ 00H

FFFFFAD4H Hour count register RC1HOUR √ 12H

FFFFFAD5H Week count register RC1WEEK

FFFFFAD6H Day count register RC1DAY √ 01H

FFFFFAD7H Month count register RC1MONTH √ 01H

FFFFFAD8H Year count register RC1YEAR √ 00H

FFFFFAD9H Time error correction register RC1SUBU √ 00H

FFFFFADAH Alarm minute set register RC1ALM

FFFFFADBH Alarm time set register RC1ALH √ 12H

FFFFFADCH Alarm week set register RC1ALW

R/W

√ √

√ √ √ √

√ √

√ √ √ √

√ √

√ √ √ √

√ √

√ √ √ √

√ √

√

√ √

√

00H

√

00H

√

00H

√

00H

Default Value

10H

00H

FFH

14H

00H

10H

00H

14H

00H

FFH

10H

14H

00H

FFH

10H

00H

FFH

14H

00H

01FFH

√

FFH

01FFH

√

FFH

00H

0000H

√

R01UH0001EJ0300 Rev.3.00 Page 82 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(10/11)

Manipulatable Bits Default Value Address Function Register Name Symbol R/W

1 8 16

Note

R/W

√ √ √ √ √ √ √ √ √ √ √ √

√ √

√ √ √ √ √ √ √ √ √ √ √ √

√ √ √ √ √ √ √ √

√

R/W

√ √ √ √

√ √

R/W

√ √

00H

√ √

00H

√

00H

√

00H

√

00H

√ √

√

00H

√

00H

0000H

√

00H

0000H

√

00H

01H

00H

0000H

√

0000H

√

01H

00H

0000H

√

0000H

√

01H

00H

0000H

√

FFFFFADDH RTC control register 0 RC1CC0

FFFFFADEH RTC control register 1 RC1CC1

FFFFFADFH RTC control register 2 RC1CC2

FFFFFAE0H RTC control register 3 RC1CC3

FFFFFB00H RTC backup control register 0 RTCBUMCTL0

FFFFFB03H Subclock low-power operation control register SOSCAMCTL

FFFFFC00H External interrupt falling edge specification register 0 INTF0

FFFFFC06H External interrupt falling edge specification register 3 INTF3

FFFFFC13H External interrupt falling edge specification register 9H INTF9H

FFFFFC20H External interrupt rising edge specification register 0 INTR0

FFFFFC26H External interrupt rising edge specification register 3 INTR3

FFFFFC33H External interrupt rising edge specification register 9H INTR9H

FFFFFC60H Port 0 function register PF0

FFFFFC66H Port 3 function register PF3

FFFFFC66H Port 3 function register L PF3L

FFFFFC67H Port 3 function register H PF3H

FFFFFC68H Port 4 function register PF4

FFFFFC6AH Port 5 function register PF5

FFFFFC72H Port 9 function register PF9

FFFFFC72H Port 9 function register L PF9L

FFFFFC73H Port 9 function register H PF9H

FFFFFD00H CSIB0 control register 0 CB0CTL0

FFFFFD01H CSIB0 control register 1 CB0CTL1

FFFFFD02H CSIB0 control register 2 CB0CTL2

FFFFFD03H CSIB0 status register CB0STR

FFFFFD04H CSIB0 receive data register CB0RX

FFFFFD04H CSIB0 receive data register L CB0RXL

FFFFFD06H CSIB0 transmit data register CB0TX

FFFFFD06H CSIB0 transmit data register L CB0TXL

FFFFFD10H CSIB1 control register 0 CB1CTL0

FFFFFD11H CSIB1 control register 1 CB1CTL1

FFFFFD12H CSIB1 control register 2 CB1CTL2

FFFFFD13H CSIB1 status register CB1STR

FFFFFD14H CSIB1 receive data register CB1RX

FFFFFD14H CSIB1 receive data register L CB1RXL

FFFFFD16H CSIB1 transmit data register CB1TX

FFFFFD16H CSIB1 transmit data register L CB1TXL

FFFFFD20H CSIB2 control register 0 CB2CTL0

FFFFFD21H CSIB2 control register 1 CB2CTL1

FFFFFD22H CSIB2 control register 2 CB2CTL2

FFFFFD23H CSIB2 status register CB2STR

FFFFFD24H CSIB2 receive data register CB2RX

FFFFFD24H CSIB2 receive data register L CB2RXL

Note This is a special register.

R01UH0001EJ0300 Rev.3.00 Page 83 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(11/11)

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFFD26H CSIB2 transmit data register CB2TX

FFFFFD26H CSIB2 transmit data register L CB2TXL

FFFFFD30H CSIB3 control register 0 CB3CTL0

FFFFFD31H CSIB3 control register 1 CB3CTL1

FFFFFD32H CSIB3 control register 2 CB3CTL2

FFFFFD33H CSIB3 status register CB3STR

FFFFFD34H CSIB3 receive data register CB3RX

FFFFFD34H CSIB3 receive data register L CB3RXL

FFFFFD36H CSIB3 transmit data register CB3TX

FFFFFD36H CSIB3 transmit data register L CB3TXL

FFFFFD40H CSIB4 control register 0 CB4CTL0

FFFFFD41H CSIB4 control register 1

FFFFFD42H CSIB4 control register 2 CB4CTL2

FFFFFD43H CSIB4 status register CB4STR

FFFFFD44H CSIB4 receive data register CB4RX

FFFFFD44H CSIB4 receive data register L CB4RXL

FFFFFD46H CSIB4 transmit data register CB4TX

FFFFFD46H CSIB4 transmit data register L CB4TXL

FFFFFD80H IIC shift register 0 IIC0

FFFFFD82H IIC control register 0 IICC0

FFFFFD83H Slave address register 0 SVA0

FFFFFD84H IIC clock select register 0 IICCL0

FFFFFD85H IIC function expansion register 0 IICX0

FFFFFD86H IIC status register 0 IICS0 R

FFFFFD8AH IIC flag register 0 IICF0

FFFFFD90H IIC shift register 1 IIC1

FFFFFD92H IIC control register 1 IICC1

FFFFFD93H Slave address register 1 SVA1

FFFFFD94H IIC clock select register 1 IICCL1

FFFFFD95H IIC function expansion register 1 IICX1

FFFFFD96H IIC status register 1 IICS1 R

FFFFFD9AH IIC flag register 1 IICF1

FFFFFDA0H IIC shift register 2 IIC2

FFFFFDA2H IIC control register 2 IICC2

FFFFFDA3H Slave address register 2 SVA2

FFFFFDA4H IIC clock select register 2 IICCL2

FFFFFDA5H IIC function expansion register 2 IICX2

FFFFFDA6H IIC status register 2 IICS2 R

FFFFFDAAH IIC flag register 2 IICF2

FFFFFF40H USB clock control register UCKSEL

FFFFFF41H USB function control register UFCKMSK

CB4CTL1

R/W

√ √ √ √

√ √

√ √ √ √

√ √

√ √ √ √ √ √ √ √

√ √

√ √ √ √ √ √ √ √

√ √

√ √ √ √ √ √ √ √ √ √ √ √

√

√ √

√

Default Value

0000H

√

00H

01H

00H

0000H

√

00H

0000H

√

00H

01H

00H

0000H

√

00H

0000H

√

00H

03H

R01UH0001EJ0300 Rev.3.00 Page 84 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

3.4.7 Special registers

Special registers are registers that are protected from being written with illegal data due to a program hang-up. The

V850ES/JG3-L has the following nine special registers.

• Power save control register (PSC)

• Clock control register (CKC)

• Processor clock control register (PCC)

• Clock monitor mode register (CLM)

• Reset source flag register (RESF)

• Low-voltage detection register (LVIM)

• On-chip debug mode register (OCDM)

•

RTC backup control register 0 (RTCBUMCTL0)

•

Subclock low-power operation control register 0 (SOSCAMCTL)

In addition, the PRCDM register is provided to protect against a write access to the special registers so that the

application system does not inadvertently stop due to a program hang-up. A write access to the special registers is made

in a specific sequence, and an illegal store operation is reported to the SYS register.

R01UH0001EJ0300 Rev.3.00 Page 85 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(1) Setting data to special registers

Set data to the special registers in the following sequence.

<1> Disable DMA operation.

<2> Prepare data to be set to the special register in a general-purpose register.

<3> Write the data prepared in <2> to the PRCMD register.

<4> Write the setting data to the special register (by using the following instructions).

• Store instruction (ST/SST instruction)

• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)

(<5> to <9> Insert NOP instructions (5 instructions).)

<10> Enable DMA operation if necessary.

Note When switching to the IDLE mode or the STOP mode (PSC.STP bit = 1), 5 NOP instructions must be

inserted immediately after switching is performed.

Caution To resume the DMA operation in the status before the DMA operation was disabled after a

special sequence, the DCHCn register status must be stored before the DMA operation is

disabled.

After the DCHCn register status is stored, the DCHCn.TCn bit must be checked before the DMA

operation is resumed and the following processing must be executed according to the TCn bit

status, because completion of DMA transfer may occur before the DMA operation is disabled.

• When the TCn bit is 0 (DMA transfer not completed), the contents of the DCHCn register stored

before the DMA operation was disabled are written to the DCHCn register again.

• When the TCn bit is 1 (DMA transfer completed), DMA transfer completion processing is

executed.

Remark n = 0 to 3

[Example] PSC register (setting standby mode)

ST.B r11, PSMR[r0] ; Set PSMR register (setting IDLE1, IDLE2, and STOP modes).

<1>CLR1 0, DCHCn[r0] ; Disable DMA operation. n = 0 to 3

<2>MOV0x02, r10

<3>ST.B r10, PRCMD[r0] ; Write PRCMD register.

<4>ST.B r10, PSC[r0] ; Set PSC register.

<5>NOP

<6>NOP

<7>NOP

<8>NOP

<9>NOP

Note

; Dummy instruction

Note

; Dummy instruction

Note

; Dummy instruction

Note

; Dummy instruction

Note

; Dummy instruction

<10>SET1 0, DCHCn[r0] ; Enable DMA operation. n = 0 to 3

(next instruction)

There is no special sequence required to read a special register.

Note

R01UH0001EJ0300 Rev.3.00 Page 86 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

Note Five NOP instructions or more must be inserted immediately after setting the IDLE1 mode, IDLE2 mode, or

STOP mode (by setting the PSC.STP bit to 1).

Caution When a store instruction is executed to store data in the command register, interrupts are not

acknowledged. This is because it is assumed that steps <3> and <4> above are performed by

successive store instructions. If another instruction is placed between <3> and <4>, and if an

interrupt is acknowledged by that instruction, the above sequence may not be established,

causing malfunction.

Remark Although dummy data is written to the PRCMD register, use the same general-purpose register used to

set the special register (<4> in the example) to write data to the PRCMD register (<3> in the example).

The same applies when a general-purpose register is used for addressing.

(2) Command register (PRCMD)

The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system

from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access

to a special register is valid after data has been written in advance to the PRCMD register. In this way, the value of

the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write

access.

The PRCMD register is write-only, in 8-bit units (undefined data is read when this register is read).

After reset: Undefined W Address: FFFFF1FCH

REG7PRCMD

REG65REG54REG43REG32REG21REG10REG0

R01UH0001EJ0300 Rev.3.00 Page 87 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(3) System status register (SYS)

Status flags that indicate the operation status of the overall system are allocated to this register.

This register can be read or written in 8-bit or 1-bit units.

Reset sets this register to 00H.

After reset: 00H R/W Address: FFFFF802H

< >

SYS 0 0 0 0 0 0 PRERR

PRERR

Protection error did not occur.

Protection error occurred.

The PRERR flag operates under the following conditions.

(a) Set condition (PRERR flag = 1)

(i) When data is written to a special register without writing anything to the PRCMD register (when <4> is

executed without executing <3> in 3.4.7 (1) Setting data to special registers)

(ii) When data is written to an on-chip peripheral I/O register other than a special register (including execution

of a bit manipulation instruction) after writing data to the PRCMD register (if <4> in 3.4.7 (1) Setting data

to special registers is not the setting of a special register)

Remark Even if an on-chip peripheral I/O register is read (except by a bit manipulation instruction) or the

internal RAM is accessed between an operation to write the PRCMD register and an operation to

write a special register, the PRERR flag is not set, and the set data can be written to the special

(b) Clear condition (PRERR flag = 0)

(i) When 0 is written to the PRERR flag

(ii) When the system is reset

Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register,

immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0 (the

write access takes precedence).

2. If data is written to the PRCMD register, which is not a special register, immediately after a

write access to the PRCMD register, the PRERR bit is set to 1.

Detects protection error

R01UH0001EJ0300 Rev.3.00 Page 88 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

3.4.8 Registers to be set first

Be sure to set the following registers first when using the V850ES/JG3-L.

• System wait control register (VSWC)

• On-chip debug mode register (OCDM)

• Watchdog timer mode register 2 (WDTM2)

After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.

When using the external bus, set each pin to the alternate-function bus control pin mode by using the port-related

registers after setting the above registers.

(a) System wait control register (VSWC)

The VSWC register controls wait of bus access to the on-chip peripheral I/O registers.

Three clock cycles are required to access an on-chip peripheral I/O register (without a wait cycle). The

V850ES/JG3-L requires wait cycles according to the operating frequency. Set the following value to the VSWC

This register can be read or written in 8-bit units.

Reset sets this register to 77H (number of waits: 14).

After reset: 77H R/W Address: FFFFF06EH

76543210

VSWC

Operating Frequency (fCLK) Set Value of VSWC Number of Waits

32 kHz ≤ fCLK < 16.6 MHz 00H 0 (no waits)

16.6 MHz ≤ fCLK ≤ 20 MHz 01H 1

(b) On-chip debug mode register (OCDM)

For details, see CHAPTER 32 ON-CHIP DEBUG FUNCTION.

The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2.

Watchdog timer 2 automatically starts in the reset mode after reset is released. To specify the operation of

watchdog timer 2, write to the WDTM2 register after reset is released.

For details, see CHAPTER 12 WATCHDOG TIMER 2.

R01UH0001EJ0300 Rev.3.00 Page 89 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

3.4.9 Cautions

(1) Accessing special on-chip peripheral I/O registers

This product has two types of internal system buses.

One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.

The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and an

access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is a

possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is

accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next instruction

but enters the wait status. If this wait status occurs, the number of clocks required to execute an instruction

increases by the number of wait clocks shown below.

This must be taken into consideration if real-time processing is required.

When special on-chip peripheral I/O registers are accessed, more wait states may be required in addition to the

wait states set by the VSWC register.

The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks) at this

time are shown below.

Table 3-4. Registers That Requires Waits

Peripheral Function Register Name Access k

16-bit timer/event counter P (TMP) (n = 0 to 5)

16-bit timer/event counter Q (TMQ)

Watchdog timer 2 (WDT2) WDTM2

Real-time output function (RTO) RTBL0, RTBH0

A/D converter

I2C00 to I2C02 IICS0 to IICS2 Read 1

CRC CRCD Write 1

TPnCNT Read 1 or 2

TPnCCR0, TPnCCR1

TQ0CNT Read 1 or 2

TQ0CCR0 to TQ0CCR3

ADA0M0 Read 1 or 2

ADA0CR0 to ADA0CR11 Read 1 or 2

ADA0CR0H to ADA0CR11H Read 1 or 2

Write

Read 1 or 2

Write

Read 1 or 2

Write (when WDT2 operating)

Write (RTPC0.RTPOE0 bit = 0)

• 1

• Continuous write: 3 or 4

• 1

• Continuous write: 3 or 4

access: No wait

Number of clocks necessary for access = 3 + i + j + (2 + j) × k

Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is

generated, it can only be cleared by a reset.

• When the CPU operates on the subclock and main clock oscillation is stopped

• When the CPU operates on the internal oscillator clock

(However, this only applies immediately after reset ends or if a WDT2 overflow occurs during

the oscillation stabilization time.)

Remark i: Value (0) of higher 4 bits of VSWC register

j: Value (0 or 1) of lower 4 bits of VSWC register

R01UH0001EJ0300 Rev.3.00 Page 90 of 1248 Aug 3, 2012

V850ES/JG3-L CHAPTER 3 CPU FUNCTION

(2) Conflict between sld instruction and interrupt request

(a) Description

If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction

following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution

result of the instruction in <1> may not be stored in a register.

Instruction <1>

• ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu

• sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu

• Multiplication instruction: mul, mulh, mulhi, mulu

Instruction <2>

satsub reg1, reg2

xor reg1, reg2

sub reg1, reg2

cmp imm5, reg2

shl imm5, reg2

<i> ld.w [r11], r10 If the decode operation of the mov instruction <ii> immediately before the sld

<ii> mov r10, r28

<iii> sld.w 0x28, r10

(b) Countermeasure

<1> When compiler (CA850) is used

Use CA850 Ver. 2.61 or later because generation of the corresponding instruction sequence can be

<2> For assembler

When executing the sld instruction immediately after instruction <ii>, avoid the above operation using

mov reg1, reg2

satadd reg1, reg2

and reg1, reg2

add reg1, reg2

mulh reg1, reg2

•

not reg1, reg2

satadd imm5, reg2

tst reg1, reg2

add imm5, reg2

shr imm5, reg2

instruction <iii> and an interrupt request conflict before execution of the ld instruction

<i> is complete, the execution result of instruction <i> may not be stored in a register.

satsubr reg1, reg2

or reg1, reg2

subr reg1, reg2

cmp reg1, reg2

sar imm5, reg2

automatically suppressed.

either of the following methods.

• Insert a nop instruction immediately before the sld instruction.

• Do not use the same register as the sld instruction destination register in the above instruction <ii>

executed immediately before the sld instruction.

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V850ES/JG3-L CHAPTER 4 PORT FUNCTIONS

CHAPTER 4 PORT FUNCTIONS

4.1 Features

{ I/O port pins: 80

• N-ch open-drain output selectable: 37 (5 V tolerant: 28)

{ Input/output specifiable in 1-bit units

4.2 Basic Port Configuration

The V850ES/JG3-L features a total of 80 I/O port pins organized as ports 0, 1, 3 to 5, 7, 9, CM, CT, DH, and DL. The

port configuration is shown below.

Figure 4-1. Port Configuration

Port 0

Port 1

Port 3

Port 4

Port 5

P02

P06

P10

P11

P30

P32 P36

P39

P40

P42

P50

P55

Caution Ports 0, 3 to 5, and 9 (P90 to P96) are 5 V tolerant.

Table 4-1. I/O Buffer Power Supplies for Pins

P70

P711

P90

P915

PCM0

PCM3

PCT0

PCT1

PCT4

PCT6

PDH0

PDH4

PDL0

PDL15

Port 7

Port 9

Port CM

Port CT

Port DH

Port DL

Power Supply Corresponding Pins

AVREF0 Port 7

AVREF1 Port 1

EVDD RESET, ports 0, 3 to 5, 9, CM, CT, DH, DL

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V850ES/JG3-L CHAPTER 4 PORT FUNCTIONS

4.3 Port Configuration

The ports consist of the following hardware.

Table 4-2. Port Configuration

Item Configuration

Control registers

Port pins I/O: 80

Port n mode register (PMn: n = 0, 1, 3 to 5, 7, 9, CD, CM, CT, DH, DL) Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM, CT, DH, DL) Port n function control register (PFCn: n = 0, 3 to 5, 9) Port n function control expansion register (PFCEn: n = 0, 3, 5, 9 ) Port n function register (PFn: n = 0, 3 to 5, 9)

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V850ES/JG3-L CHAPTER 4 PORT FUNCTIONS

(1) Port n register (Pn)

Data I/O with external devices is performed by writing to and reading from the Pn register. The Pn register is made

up of a port latch that retains the output data and a circuit that reads the pin status.

Each bit of the Pn register corresponds to one pin of port n and can be read or written in 1-bit units.

After reset: 00H

Note

(output latch) R/W

Pn7

Pn6 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0

01237567

Pnm

0 is output.

1 is output.

Control of output data (in output mode)

Note This value is undefined for input-only ports.

The operation when writing or reading the Pn register differs depending on the specified mode.

Table 4-3. Reading and Writing Pn Register

PMCn Register Setting PMn Register Setting Writing Pn Register Reading Pn Register

Port mode

(PMCnm bit = 0)

Alternate-function mode

(PMCnm bit = 1)

Output mode

(PMnm bit = 0)

Input mode

(PMnm bit = 1)

Output mode

(PMnm bit = 0)

Input mode

(PMnm bit = 1)

Write to the output latch The contents of the output latch are output from the pin.

Write to the output latch The status of the pin is not affected.

Write to the output latch The status of the pin is not affected. The pin operates as an alternate-function pin.

Note

The value of the output latch is read.

The pin status is read.

The value of the output latch is read.

The pin status is read.

Note The value written to the output latch is retained until a new value is written to the output latch.

The output latch value is cleared by a reset.

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V850ES/JG3-L CHAPTER 4 PORT FUNCTIONS

(2) Port n mode register (PMn)

PMn specifies the input mode or output mode of the port.

Each bit of the PMn register corresponds to one pin of port n and can be specified in 1-bit units.

After reset: FFH R/W

PMn

PMn7

PMnm

PMn6 PMn5 PMn4 PMn3 PMn2 PMn1 PMn0

Control of I/O mode

Output mode

Input mode

(3) Port n mode control register (PMCn)

If the port function and the alternate function need to be switched, specify the port mode or the alternate function

mode by using this register.

Each bit of the PMCn register corresponds to one pin of port n and can be specified in 1-bit units.

After reset: 00H R/W

PMCn

PMCn7 PMCn6 PMCn5 PMCn4 PMCn3 PMCn2 PMCn1 PMCn0

PMCnm

Port mode

Alternate function mode

Specification of operation mode

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V850ES/JG3-L CHAPTER 4 PORT FUNCTIONS

(4) Port n function control register (PFCn)

PFCn is a register that specifies the alternate function to be used when one pin has two or more alternate functions.

Each bit of the PFCn register corresponds to one pin of port n and can be specified in 1-bit units.

After reset: 00H R/W

PFCn

PFCn7 PFCn6 PFCn5 PFCn4 PFCn3 PFCn2 PFCn1 PFCn0

PFCnm

Alternate function 1

Alternate function 2

Specification of alternate function

(5) Port n function control expansion register (PFCEn)

The PFCEn register specifies the alternate function of a port pin in combination with the PFCn register if the pin

has three or more alternate functions.

Each bit of the PFCEn register corresponds to one pin of port n and can be specified in 1-bit units.

After reset: 00H R/W

PFCEn

PFCn

PFCEn7 PFCEn6 PFCEn5 PFCEn4 PFCEn3 PFCEn2 PFCEn1 PFCEn0

PFCn7 PFCn6 PFCn5 PFCn4 PFCn3 PFCn2 PFCn1 PFCn0

PFCEnm

PFCnm

Alternate function 1

Alternate function 2

Alternate function 3

Alternate function 4

Specification of alternate function

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V850ES/JG3-L CHAPTER 4 PORT FUNCTIONS

(6) Port n function register (PFn)

PFn is a register that specifies normal output (CMOS output) or N-ch open-drain output.

Each bit of the PFn register corresponds to one pin of port n and can be specified in 1-bit units.

After reset: 00H R/W

PFn

PFn7 PFn6 PFn5 PFn4 PFn3 PFn2 PFn1 PFn0

Note

PFnm

Specification of normal output (CMOS output)/N-ch open-drain output

Normal output (CMOS output)

N-ch open-drain output

Note Regardless of the settings of the PMCn register, the PFnm bit is valid only if the

PMn.PMnm bit is set to 0 (output mode). If the PMnm bit is set to 1 (input mode), the

values specified for the PFn register are invalid.

Example <1> The PFn register values are valid when:

PFnm bit = 1 … N-ch open drain output is specified.

PMnm bit = 0 … Output mode is specified.

PMCnm bit = Any value

<2> The PFn register values are invalid when:

PFnm bit = 1 … N-ch open drain output is specified.

PMnm bit = 1 … Input mode is specified.

PMCnm bit = Any value

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V850ES/JG3-L CHAPTER 4 PORT FUNCTIONS

(7) Port setting

Set a port as illustrated below.

Figure 4-2. Setting of Each Register and Pin Function

Port mode

Output mode

Input mode

Alternate function

(when two alternate

functions are available)

Alternate function 1

Alternate function 2

Alternate function

(when three or more alternate

functions are available)

Alternate function 1

Alternate function 2

Alternate function 3

Alternate function 4

(a)

(b)

(c)

(d)

“0”

“1”

“0”

“1”

PMn register

PFCn register

PFCEn register

“0”

“1”

(a) (b) (c) (d)

PMCn register

PFCEnm

0 0 1 1

PFCnm

0 1 0 1

Remark Set the alternate functions in the following sequence.

<1> Set the PFCn and PFCEn registers.

<2> Set the PMCn register.

<3> Set the INTRn or INTFn register (to specify an external interrupt pin).

If the PMCn register is set first, an unintended function may be set while the PFCn and PFCEn

registers are being set.

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V850ES/JG3-L CHAPTER 4 PORT FUNCTIONS

4.3.1 Port 0

Port 0 is a 5-bit port for which I/O settings can be controlled in 1-bit units.

Port 0 includes the following alternate-function pins.

Table 4-4. Port 0 Alternate-Function Pins

Pin No. Alternate Function

GC F1

7 G4 P02 NMI/A21 Input/Output N-2

18 G3 P03 INTP0/ADTRG/UCLK/RTC1HZ Input/Output U-17

19 H4 P04 INTP1/RTCDIV/RTCCL Input/Output N-2

20 J3 P05 INTP2/DRST

21 J4 P06 INTP3 Input

Function Name

Remark Block Type

Name I/O

Selectable as N-ch

open-drain output

Note

Input AA-1

L-1

Note The DRST pin is used for on-chip debugging.

If on-chip debugging is not used, fix the P05/INTP2/DRST pin to low level between when the reset signal of the

RESET pin is released and when the OCDM.OCDM0 bit is cleared (0).

For details, see 4.6.3 Cautions on on-chip debug pins.

Caution The P02 to P06 pins have hysteresis characteristics in the input mode of the alternate function, but

do not have hysteresis characteristics in the port mode.

Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14)

F1: 121-pin plastic FBGA (8 × 8)

(1) Port 0 register (P0)

After reset: 00H (output latch) R/W Address: FFFFF400H

P0 P06 P05 P04 P03 P02 0 0

P0n

Outputs 0

Outputs 1

Output data control (in output mode) (n = 2 to 6)

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V850ES/JG3-L CHAPTER 4 PORT FUNCTIONS

(2) Port 0 mode register (PM0)

After reset: FFH R/W Address: FFFFF420H

PM0 PM06 PM05 PM04 PM03 PM02 1 1

PM0n

Output mode

Input mode

(3) Port 0 mode control register (PMC0)

After reset: 00H R/W Address: FFFFF440H

0PMC0 PMC06 PMC05 PMC04 PMC03 PMC02 0 0

PMC06

I/O port (p06)

INTP3 input

PMC05

I/O port (p05)

INTP2 input

I/O mode control (n = 2 to 6)

Specification of pin operation

PMC04

PMC03

PMC02

I/O port (p04)

INTP1 input/RTCDIV output/RTCCL output

I/O port (p03)

INTP0 input/ADTRG input/UCLK input/RTC1HZ output

I/O port (p02)

NMI input/A21 output

Specification of pin operation

Caution The P05/INTP2/DRST pin becomes the DRST pin regardless of the value of the PMC05 bit

when the OCDM.OCDM0 bit is 1.

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Renesas V850ES/JG3-L User’s Manual: Hardware

Specifications and Main Features

Frequently Asked Questions

User Manual

Notice

NOTES FOR CMOS DEVICES

How to Use This Manual

Table of Contents

CHAPTER 1 INTRODUCTION

1.1 General

1.2 Features

1.3 Application Fields

1.4 Ordering Information

1.5 Pin Configuration (Top View)

1.6 Function Block Configuration

1.6.1 Internal block diagram

1.6.2 Internal units

CHAPTER 2 PIN FUNCTIONS

2.1 List of Pin Functions

2.2 Pin States

2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins

2.4 Cautions

CHAPTER 3 CPU FUNCTION

3.1 Features

3.2 CPU Register Set

3.2.1 Program register set

3.2.2 System register set

3.3 Operation Modes

3.4 Address Space

3.4.1 CPU address space

3.4.2 Memory map

3.4.3 Areas

3.4.4 Wraparound of data space

3.4.5 Recommended use of address space

3.4.6 Peripheral I/O registers

3.4.7 Special registers

3.4.8 Registers to be set first

3.4.9 Cautions

CHAPTER 4 PORT FUNCTIONS

4.1 Features

4.2 Basic Port Configuration

4.3 Port Configuration

4.3.1 Port 0