Renesas V850ES/JF3-L, V850ES/JG3-L User Manual

User’s Manual

V850ES/JF3-L

RENESAS MCU V850ES/JF3-L Microcontrollers

μ PD70F3735 μPD70F3736

User’s Manual: Hardware

All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com).

www.renesas.com

Rev.4.00 Sep 2010

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

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4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

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“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

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“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

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NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V

(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

(MAX) and VIH (MIN) due to noise, etc., the device may

(MAX) and

or GND

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

How to Use This Manual

Readers This manual is intended for users who wish to understand the functions of the

V850ES/JF3-L and design application systems using these products.

Purpose This manual is intended to give users an understanding of the hardware functions of the

V850ES/JF3-L shown in the Organization below.

Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES

Architecture User’s Manual).

Hardware Architecture

• Pin functions • Data types

• CPU function • Register set

• On-chip peripheral functions • Instruction format and instruction set

• Flash memory programming • Interrupts and exceptions

• Electrical specifications • Pipeline operation

How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of

electrical engineering, logic circuits, and microcontrollers.

To understand the overall functions of the V850ES/JF3-L → Read this manual according to the CONTENTS.

To find the details of a register where the name is known → Use APPENDIX B REGISTER INDEX.

format of each register is defined as a reserved word in the device file.

To understand the details of an instruction function → Refer to the V850ES Architecture User’s Manual available separately.

To know the electrical specifications of the V850ES/JF3-L → See CHAPTER 30 ELECTRICAL SPECIFICATIONS.

The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note with

caution that if “xxx.yyy” is described as is in a program, however, the compiler/assembler

cannot recognize it correctly.

The mark <R> shows major revised points. The revised points can be easily searched by

copying an “<R>” in the PDF file and specifying it in the "Find what:" field.

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representation: xxx (overscore over pin or signal name)

Memory map address: Higher addresses on the top and lower addresses on the

bottom

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numeric representation: Binary ... xxxx or xxxxB

Decimal ... xxxx

Hexadecimal ... xxxxH

Prefix indicating power of 2 (address space, memory capacity):

K (kilo): 2

M (mega): 2

G (giga): 230 = 1,024

= 1,024

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents related to V850ES/JF3-L

Document Name Document No.

V850ES Architecture User’s Manual U15943E

V850ES/JF3-L Hardware User’s Manual This manual

Documents related to development tools

Document Name Document No.

QB-V850ESSX2 In-Circuit Emulator U17091E

QB-V850MINI On-Chip Debug Emulator U17638E

QB-MINI2 On-Chip Debug Emulator with Flash Programming Function U18371E

CA850 Ver. 3.20 C Compiler Package

PM+ Ver. 6.30 Project Manager U18416E

ID850QB Ver. 3.40 Integrated Debugger Operation U18604E

SM850 Ver. 2.50 System Simulator Operation U16218E

SM850 Ver. 2.00 or Later System Simulator External Part User Open

RX850 Ver. 3.20 Real-Time OS

RX850 Pro Ver. 3.21 Real-Time OS

AZ850 Ver. 3.30 System Performance Analyzer U17423E

PG-FP4 Flash Memory Programmer U15260E

PG-FP5 Flash Memory Programmer U18865E

Operation U18512E

C Language U18513E

Assembly Language U18514E

Link Directives U18515E

U14873E

Interface Specification

Operation U18601E SM+ System Simulator

User Open Interface U18212E

Basics U13430E

Installation U17419E

Task Debugger U17420E

Basics U18165E

Installation U17421E

Task Debugger U17422E

Caution: This product uses SuperFlash

technology licensed from Silicon Storage Technology, Inc.

IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany.

MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in

the United States of America.

EEPROM is a trademark of Renesas Electronics Corporation.

Applilet is a registered trademark of Renesas Electronics in Japan, Germany, Hong Kong, China, the Republic of

Korea, the United Kingdom, and the United States of America.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United

States and/or other countries.

SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United

States and Japan.

PC/AT is a trademark of International Business Machines Corporation.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

TRON is an abbreviation of The Realtime Operating System Nucleus.

ITRON is an abbreviation of Industrial TRON.

CONTENTS

CHAPTER 1 INTRODUCTION....................................................................................................................1

1.1 General .......................................................................................................................................1

1.2 Features......................................................................................................................................3

1.3 Application Fields......................................................................................................................4

1.4 Ordering Information.................................................................................................................4

1.5 Pin Configuration (Top View) ...................................................................................................5

1.6 Function Block Configuration ..................................................................................................7

1.6.1 Internal block diagram..................................................................................................................7

1.6.2 Internal units ................................................................................................................................8

CHAPTER 2 PIN FUNCTIONS ................................................................................................................11

2.1 List of Pin Functions ...............................................................................................................11

2.2 Pin States .................................................................................................................................18

2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins ........19

2.4 Cautions ...................................................................................................................................22

CHAPTER 3 CPU FUNCTION .................................................................................................................23

3.1 Features....................................................................................................................................23

3.2 CPU Register Set .....................................................................................................................24

3.2.1 Program register set ..................................................................................................................25

3.2.2 System register set ....................................................................................................................26

3.3 Operation Modes .....................................................................................................................32

3.3.1 Specifying operation mode ........................................................................................................32

3.4 Address Space.........................................................................................................................33

3.4.1 CPU address space ................................................................................................................... 33

3.4.2 Wraparound of CPU address space ..........................................................................................34

3.4.3 Memory map..............................................................................................................................35

3.4.4 Areas .........................................................................................................................................37

3.4.5 Recommended use of address space........................................................................................ 40

3.4.6 Peripheral I/O registers .............................................................................................................. 43

3.4.7 Special registers ........................................................................................................................52

3.4.8 Cautions.....................................................................................................................................56

CHAPTER 4 PORT FUNCTIONS ............................................................................................................59

4.1 Features....................................................................................................................................59

4.2 Basic Port Configuration ........................................................................................................59

4.3 Port Configuration ...................................................................................................................60

4.3.1 Port 0 .........................................................................................................................................65

4.3.2 Port 1 .........................................................................................................................................68

4.3.3 Port 3 .........................................................................................................................................69

4.3.4 Port 4 .........................................................................................................................................75

4.3.5 Port 5 .........................................................................................................................................77

4.3.6 Port 7 .........................................................................................................................................81

4.3.7 Port 9 .........................................................................................................................................82

4.3.8 Port CM .....................................................................................................................................88

4.3.9 Port CT ......................................................................................................................................90

4.3.10 Port DH...................................................................................................................................... 92

4.3.11 Port DL ......................................................................................................................................93

4.4 Block Diagrams........................................................................................................................96

4.5 Port Register Settings When Alternate Function Is Used ................................................ 124

4.6 Cautions ................................................................................................................................ 131

4.6.1 Cautions on setting port pins ...................................................................................................131

4.6.2 Cautions on bit manipulation instruction for port n register (Pn)............................................... 134

4.6.3 Cautions on on-chip debug pins............................................................................................... 135

4.6.4 Cautions on P05/INTP2/DRST pin...........................................................................................135

4.6.5 Cautions on P10 and P53 pins when power is turned on......................................................... 135

4.6.6 Hysteresis characteristics ........................................................................................................135

CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 136

5.1 Features................................................................................................................................. 136

5.2 Bus Control Pins................................................................................................................... 137

5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed...............137

5.2.2 Pin status in each operation mode...........................................................................................137

5.3 Memory Block Function....................................................................................................... 138

5.4 Bus Access ........................................................................................................................... 139

5.4.1 Number of clocks for access....................................................................................................139

5.4.2 Bus size setting function ..........................................................................................................139

5.4.3 Access by bus size ..................................................................................................................140

5.5 Wait Function ........................................................................................................................ 147

5.5.1 Programmable wait function ....................................................................................................147

5.5.2 External wait function...............................................................................................................148

5.5.3 Relationship between programmable wait and external wait ...................................................149

5.5.4 Programmable address wait function.......................................................................................150

5.6 Idle State Insertion Function ............................................................................................... 151

5.7 Bus Hold Function................................................................................................................ 152

5.7.1 Functional outline.....................................................................................................................152

5.7.2 Bus hold procedure..................................................................................................................153

5.7.3 Operation in power save mode ................................................................................................153

5.8 Bus Priority ........................................................................................................................... 154

5.9 Bus Timing ............................................................................................................................ 155

CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 158

6.1 Overview................................................................................................................................ 158

6.2 Configuration ........................................................................................................................ 159

6.3 Registers ............................................................................................................................... 161

6.4 Operation............................................................................................................................... 166

6.4.1 Operation of each clock ...........................................................................................................166

6.4.2 Clock output function ...............................................................................................................166

6.5 PLL Function......................................................................................................................... 167

6.5.1 Overview..................................................................................................................................167

6.5.2 Registers.................................................................................................................................. 167

6.5.3 Usage ......................................................................................................................................171

CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) ................................................................ 172

7.1 Overview................................................................................................................................ 172

7.2 Functions............................................................................................................................... 172

7.3 Configuration ........................................................................................................................ 173

7.4 Registers ............................................................................................................................... 175

7.5 Operation............................................................................................................................... 187

7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) .............................................................188

7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) .................................................198

7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) .....................................206

7.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011)............................................... 218

7.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) .............................................................. 225

7.5.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) ....................................................234

7.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110)......................................... 251

7.5.8 Timer output operations ........................................................................................................... 257

7.6 Selector Function ................................................................................................................. 258

7.7 Cautions ................................................................................................................................ 259

CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)................................................................ 260

8.1 Overview................................................................................................................................ 260

8.2 Functions............................................................................................................................... 260

8.3 Configuration ........................................................................................................................ 261

8.4 Registers ............................................................................................................................... 263

8.5 Operation............................................................................................................................... 279

8.5.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) ............................................................280

8.5.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) ................................................289

8.5.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) ....................................298

8.5.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011)..............................................311

8.5.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) .............................................................320

8.5.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101) ................................................... 331

8.5.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110)........................................351

8.5.8 Timer output operations ........................................................................................................... 357

8.6 Cautions ................................................................................................................................ 358

CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) ............................................................................ 359

9.1 Overview................................................................................................................................ 359

9.2 Configuration ........................................................................................................................ 360

9.3 Register ................................................................................................................................. 361

9.4 Operation............................................................................................................................... 362

9.4.1 Interval timer mode ..................................................................................................................362

9.4.2 Cautions................................................................................................................................... 366

CHAPTER 10 WATCH TIMER FUNCTIONS ...................................................................................... 367

10.1 Functions............................................................................................................................... 367

10.2 Configuration ........................................................................................................................ 368

10.3 Control Registers ................................................................................................................. 370

10.4 Operation............................................................................................................................... 374

10.4.1 Operation as watch timer.........................................................................................................374

10.4.2 Operation as interval timer....................................................................................................... 375

10.4.3 Cautions...................................................................................................................................376

CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 ................................................................... 377

11.1 Functions............................................................................................................................... 377

11.2 Configuration ........................................................................................................................ 378

11.3 Registers ............................................................................................................................... 379

11.4 Operation............................................................................................................................... 381

CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)................................................................... 382

12.1 Function................................................................................................................................. 382

12.2 Configuration ........................................................................................................................ 383

12.3 Registers ............................................................................................................................... 385

12.4 Operation............................................................................................................................... 387

12.5 Usage..................................................................................................................................... 388

12.6 Cautions ................................................................................................................................ 388

CHAPTER 13 A/D CONVERTER ......................................................................................................... 389

13.1 Overview................................................................................................................................ 389

13.2 Functions............................................................................................................................... 389

13.3 Configuration ........................................................................................................................ 390

13.4 Registers ............................................................................................................................... 393

13.5 Operation............................................................................................................................... 404

13.5.1 Basic operation........................................................................................................................404

13.5.2 Conversion operation timing ....................................................................................................405

13.5.3 Trigger mode ...........................................................................................................................406

13.5.4 Operation mode.......................................................................................................................408

13.5.5 Power-fail compare mode........................................................................................................412

13.6 Cautions ................................................................................................................................ 417

13.7 How to Read A/D Converter Characteristics Table........................................................... 421

CHAPTER 14 D/A CONVERTER ......................................................................................................... 425

14.1 Functions............................................................................................................................... 425

14.2 Configuration ........................................................................................................................ 425

14.3 Registers ............................................................................................................................... 426

14.4 Operation............................................................................................................................... 428

14.4.1 Operation in normal mode .......................................................................................................428

14.4.2 Operation in real-time output mode..........................................................................................428

14.4.3 Cautions...................................................................................................................................429

CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ............................................. 430

15.1 Mode Switching of UARTA2 and I2C00 ............................................................................... 430

15.2 Features................................................................................................................................. 431

15.3 Configuration ........................................................................................................................ 432

15.4 Registers ............................................................................................................................... 434

15.5 Interrupt Request Signals.................................................................................................... 440

15.6 Operation............................................................................................................................... 441

15.6.1 Data format..............................................................................................................................441

15.6.2 SBF transmission/reception format.......................................................................................... 443

15.6.3 SBF transmission.....................................................................................................................445

15.6.4 SBF reception..........................................................................................................................446

15.6.5 UART transmission.................................................................................................................. 447

15.6.6 Continuous transmission procedure.........................................................................................448

15.6.7 UART reception ....................................................................................................................... 450

15.6.8 Reception errors ......................................................................................................................451

15.6.9 Parity types and operations .....................................................................................................453

15.6.10 Receive data noise filter........................................................................................................... 454

15.7 Dedicated Baud Rate Generator ......................................................................................... 455

15.8 Cautions ................................................................................................................................ 463

CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB).................................................... 464

16.1 Mode Switching of CSIB0 and I2C01 ................................................................................... 464

16.2 Features................................................................................................................................. 465

16.3 Configuration ........................................................................................................................ 466

16.4 Registers ............................................................................................................................... 468

16.5 Interrupt Request Signals.................................................................................................... 475

16.6 Operation............................................................................................................................... 476

16.6.1 Single transfer mode (master mode, transmission mode)........................................................476

16.6.2 Single transfer mode (master mode, reception mode).............................................................478

16.6.3 Single transfer mode (master mode, transmission/reception mode)........................................480

16.6.4 Single transfer mode (slave mode, transmission mode) .......................................................... 482

16.6.5 Single transfer mode (slave mode, reception mode)................................................................484

16.6.6 Single transfer mode (slave mode, transmission/reception mode)...........................................486

16.6.7 Continuous transfer mode (master mode, transmission mode) ...............................................488

16.6.8 Continuous transfer mode (master mode, reception mode)..................................................... 490

16.6.9 Continuous transfer mode (master mode, transmission/reception mode)................................ 493

16.6.10 Continuous transfer mode (slave mode, transmission mode) ..................................................497

16.6.11 Continuous transfer mode (slave mode, reception mode) .......................................................499

16.6.12 Continuous transfer mode (slave mode, transmission/reception mode) ..................................502

16.6.13 Reception error ........................................................................................................................506

16.6.14 Clock timing .............................................................................................................................507

16.7 Output Pins ........................................................................................................................... 509

16.8 Baud Rate Generator............................................................................................................ 510

16.8.1 Baud rate generation ...............................................................................................................511

16.9 Cautions ................................................................................................................................ 512

CHAPTER 17 I2C BUS .......................................................................................................................... 513

17.1 Mode Switching of I2C Bus and Other Serial Interfaces ................................................... 513

17.1.1 UARTA2 and I2C00 mode switching.........................................................................................513

17.1.2 CSIB0 and I2C01 mode switching ............................................................................................514

17.2 Features................................................................................................................................. 515

17.3 Configuration ........................................................................................................................ 516

17.4 Registers ............................................................................................................................... 520

17.5 I2C Bus Mode Functions....................................................................................................... 536

17.5.1 Pin configuration......................................................................................................................536

17.6 I2C Bus Definitions and Control Methods .......................................................................... 537

17.6.1 Start condition.......................................................................................................................... 537

17.6.2 Addresses................................................................................................................................ 538

17.6.3 Transfer direction specification ................................................................................................539

17.6.4 ACK .........................................................................................................................................540

17.6.5 Stop condition..........................................................................................................................541

17.6.6 Wait state.................................................................................................................................542

17.6.7 Wait state cancellation method................................................................................................544

17.7 I2C Interrupt Request Signals (INTIICn) .............................................................................. 545

17.7.1 Master device operation...........................................................................................................545

17.7.2 Slave device operation (when receiving slave address data (address match))........................ 548

17.7.3 Slave device operation (when receiving extension code) ........................................................552

17.7.4 Operation without communication............................................................................................556

17.7.5 Arbitration loss operation (operation as slave after arbitration loss).........................................556

17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) ................... 558

17.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control....................... 565

17.9 Address Match Detection Method ...................................................................................... 567

17.10 Error Detection...................................................................................................................... 567

17.11 Extension Code..................................................................................................................... 567

17.12 Arbitration ............................................................................................................................. 568

17.13 Wakeup Function.................................................................................................................. 569

17.14 Communication Reservation............................................................................................... 570

17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) .......................570

17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1)....................... 574

17.15 Cautions ................................................................................................................................ 575

17.16 Communication Operations ................................................................................................ 576

17.16.1 Master operation in single master system................................................................................ 577

17.16.2 Master operation in multimaster system ..................................................................................577

17.16.3 Slave operation........................................................................................................................581

17.17 Timing of Data Communication .......................................................................................... 584

CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) ................................................................... 591

18.1 Features................................................................................................................................. 591

18.2 Configuration ........................................................................................................................ 592

18.3 Registers ............................................................................................................................... 593

18.4 Transfer Targets ................................................................................................................... 600

18.5 Transfer Modes..................................................................................................................... 600

18.6 Transfer Types...................................................................................................................... 601

18.7 DMA Channel Priorities........................................................................................................ 602

18.8 Time Related to DMA Transfer ............................................................................................ 602

18.9 DMA Transfer Start Factors................................................................................................. 603

18.10 DMA Abort Factors ............................................................................................................... 604

18.11 End of DMA Transfer ............................................................................................................ 604

18.12 Operation Timing .................................................................................................................. 604

18.13 Cautions ................................................................................................................................ 609

CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................... 614

19.1 Features................................................................................................................................. 614

19.2 Non-Maskable Interrupts ..................................................................................................... 618

19.2.1 Operation.................................................................................................................................620

19.2.2 Restore .................................................................................................................................... 621

19.2.3 NP flag..................................................................................................................................... 622

19.3 Maskable Interrupts.............................................................................................................. 623

19.3.1 Operation.................................................................................................................................623

19.3.2 Restore .................................................................................................................................... 625

19.3.3 Priorities of maskable interrupts...............................................................................................626

19.3.4 Interrupt control register (xxICn) .............................................................................................. 630

19.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)........................................................................632

19.3.6 In-service priority register (ISPR)............................................................................................. 634

19.3.7 ID flag ......................................................................................................................................635

19.3.8 Watchdog timer mode register 2 (WDTM2) .............................................................................635

19.4 Software Exception .............................................................................................................. 636

19.4.1 Operation.................................................................................................................................636

19.4.2 Restore .................................................................................................................................... 637

19.4.3 EP flag..................................................................................................................................... 638

19.5 Exception Trap...................................................................................................................... 639

19.5.1 Illegal opcode...........................................................................................................................639

19.5.2 Debug trap...............................................................................................................................641

19.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7) ................................... 643

19.6.1 Noise elimination .....................................................................................................................643

19.6.2 Edge detection......................................................................................................................... 643

19.7 Interrupt Acknowledge Time of CPU .................................................................................. 648

19.8 Periods in Which Interrupts Are Not Acknowledged by CPU.......................................... 649

19.9 Cautions ................................................................................................................................ 649

CHAPTER 20 KEY INTERRUPT FUNCTION ..................................................................................... 650

20.1 Function................................................................................................................................. 650

20.2 Register ................................................................................................................................. 651

20.3 Cautions ................................................................................................................................ 651

CHAPTER 21 STANDBY FUNCTION .................................................................................................. 652

21.1 Overview................................................................................................................................ 652

21.2 Registers ............................................................................................................................... 654

21.3 HALT Mode............................................................................................................................ 659

21.3.1 Setting and operation status ....................................................................................................659

21.3.2 Releasing HALT mode............................................................................................................. 659

21.4 IDLE1 Mode ........................................................................................................................... 661

21.4.1 Setting and operation status ....................................................................................................661

21.4.2 Releasing IDLE1 mode............................................................................................................661

21.5 IDLE2 Mode ........................................................................................................................... 663

21.5.1 Setting and operation status ....................................................................................................663

21.5.2 Releasing IDLE2 mode............................................................................................................663

21.5.3 Securing setup time when releasing IDLE2 mode ...................................................................665

21.6 STOP Mode/Low-Voltage STOP Mode................................................................................ 666

21.6.1 Setting and operation status ....................................................................................................666

21.6.2 Releasing STOP mode/low-voltage STOP mode ....................................................................670

21.6.3 Re-setting after release of low-voltage STOP mode................................................................671

21.6.4 Securing oscillation stabilization time when releasing STOP mode.........................................672

21.7 Subclock Operation Mode/Low-Voltage Subclock Operation Mode............................... 673

21.7.1 Setting and operation status ....................................................................................................673

21.7.2 Releasing subclock operation mode ........................................................................................ 677

21.7.3 Releasing low-voltage subclock operation mode ..................................................................... 677

21.8 Sub-IDLE Mode/Low-Voltage Sub-IDLE Mode................................................................... 678

21.8.1 Setting and operation status ....................................................................................................678

21.8.2 Releasing sub-IDLE mode/low-voltage sub-IDLE mode ..........................................................681

CHAPTER 22 RESET FUNCTIONS ..................................................................................................... 682

22.1 Overview................................................................................................................................ 682

22.2 Registers to Check Reset Source....................................................................................... 683

22.3 Operation............................................................................................................................... 684

22.3.1 Reset operation via RESET pin ...............................................................................................684

22.3.2 Reset operation by watchdog timer 2.......................................................................................687

22.3.3 Reset operation by low-voltage detector.................................................................................. 689

22.3.4 Operation after reset release ................................................................................................... 690

22.3.5 Reset function operation flow...................................................................................................691

22.4 Cautions ................................................................................................................................ 692

CHAPTER 23 CLOCK MONITOR ........................................................................................................ 693

23.1 Functions............................................................................................................................... 693

23.2 Configuration ........................................................................................................................ 693

23.3 Register ................................................................................................................................. 694

23.4 Operation............................................................................................................................... 695

CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) ............................................................................. 698

24.1 Functions............................................................................................................................... 698

24.2 Configuration ........................................................................................................................ 698

24.3 Registers ............................................................................................................................... 699

24.4 Operation............................................................................................................................... 701

24.4.1 To use for internal reset signal.................................................................................................701

24.4.2 To use for interrupt ..................................................................................................................702

CHAPTER 25 CRC FUNCTION............................................................................................................ 703

25.1 Functions............................................................................................................................... 703

25.2 Configuration ........................................................................................................................ 703

25.3 Registers ............................................................................................................................... 704

25.4 Operation............................................................................................................................... 705

25.5 Usage Method ....................................................................................................................... 706

CHAPTER 26 REGULATOR ................................................................................................................. 708

26.1 Outline ................................................................................................................................... 708

26.2 Operation............................................................................................................................... 709

CHAPTER 27 OPTION BYTE............................................................................................................... 710

CHAPTER 28 FLASH MEMORY.......................................................................................................... 712

28.1 Features................................................................................................................................. 712

28.2 Memory Configuration ......................................................................................................... 713

28.3 Functional Outline ................................................................................................................ 714

28.4 Rewriting by Dedicated Flash Programmer....................................................................... 717

28.4.1 Programming environment.......................................................................................................717

28.4.2 Communication mode..............................................................................................................718

28.4.3 Flash memory control ..............................................................................................................723

28.4.4 Selection of communication mode ........................................................................................... 724

28.4.5 Communication commands .....................................................................................................725

28.4.6 Pin connection .........................................................................................................................726

28.5 Rewriting by Self Programming.......................................................................................... 730

28.5.1 Overview..................................................................................................................................730

28.5.2 Features...................................................................................................................................731

28.5.3 Standard self programming flow ..............................................................................................732

28.5.4 Flash functions.........................................................................................................................733

28.5.5 Pin processing .........................................................................................................................733

28.5.6 Internal resources used ...........................................................................................................734

CHAPTER 29 ON-CHIP DEBUG FUNCTION ..................................................................................... 735

29.1 Debugging with DCU............................................................................................................ 736

29.1.1 Connection circuit example...................................................................................................... 736

29.1.2 Interface signals.......................................................................................................................736

29.1.3 Maskable functions .................................................................................................................. 738

29.1.4 Register ...................................................................................................................................738

29.1.5 Operation.................................................................................................................................740

29.1.6 Cautions...................................................................................................................................741

29.2 Debugging Without Using DCU........................................................................................... 742

29.2.1 Circuit connection examples....................................................................................................742

29.2.2 Maskable functions .................................................................................................................. 744

29.2.3 Securement of user resources................................................................................................. 744

29.2.4 Cautions...................................................................................................................................750

29.3 ROM Security Function........................................................................................................ 751

29.3.1 Security ID ............................................................................................................................... 751

29.3.2 Setting .....................................................................................................................................752

CHAPTER 30 ELECTRICAL SPECIFICATIONS................................................................................. 753

CHAPTER 31 PACKAGE DRAWINGS ................................................................................................ 783

CHAPTER 32 RECOMMENDED SOLDERING CONDITIONS........................................................... 785

APPENDIX A DEVELOPMENT TOOLS............................................................................................... 786

A.1 Software Package................................................................................................................. 788

A.2 Language Processing Software.......................................................................................... 788

A.3 Control Software................................................................................................................... 788

A.4 Debugging Tools (Hardware) .............................................................................................. 789

A.4.1 When using IECUBE® QB-V850ESSX2 ..................................................................................789

A.4.2 When using MINICUBE QB-V850MINI ....................................................................................792

A.4.3 When using MINICUBE2 QB-MINI2 ........................................................................................793

A.5 Debugging Tools (Software)................................................................................................ 794

A.6 Embedded Software ............................................................................................................. 795

A.7 Flash Memory Writing Tools ............................................................................................... 796

APPENDIX B REGISTER INDEX ......................................................................................................... 797

APPENDIX C INSTRUCTION SET LIST ............................................................................................. 806

C.1 Conventions .......................................................................................................................... 806

C.2 Instruction Set (in Alphabetical Order) .............................................................................. 809

APPENDIX D REVISION HISTORY ..................................................................................................... 816

D.1 Major Revisions in This Edition.............................................................................................. 816

D.2 Revision History of Previous Editions................................................................................... 816

V850ES/JF3-L RENESAS MCU

R01UH0017EJ0400

Rev.4.00

Sep 30, 2010

CHAPTER 1 INTRODUCTION

The V850ES/JF3-L is one of the products in the Renesas Electronics V850 single-chip microcontrollers designed for

low-power operation for real-time control applications.

1.1 General

The V850ES/JF3-L is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions

such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter.

In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/JF3-L features

multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware multiplier,

as optimum instructions for digital servo control applications. Moreover, as a real-time control system, the V850ES/JF3-L

enables an extremely high cost-performance for applications that require ultra low power consumption, such as digital

cameras, power meters, and mobile terminals.

Table 1-1 lists the products of the V850ES/JF3-L and V850ES/JG3-L.

The V850ES/JG3-L is a model of the V850ES/JF3-L with expanded I/O, timer/counter, and serial interface functions.

R01UH0017EJ0400 Rev.4.00 Page 1 of 816 Sep 30, 2010

V850ES/JF3-L CHAPTER 1 INTRODUCTION

Generic Name V850ES/JF3-L V850ES/JG3-L

Part Number

Flash memory 128 KB 256 KB 128 KB 256 KB Internal

memory

RAM 8 KB 16 KB 8 KB 16 KB

Logical space 64 MB Memory

space

External memory area 15 MB

External bus interface Address bus: 18

General-purpose register 32 bits × 32 registers

Clock

Main clock (oscillation frequency)

Subclock (oscillation frequency)

Internal oscillator fR = 220 kHz (TYP.)

Minimum instruction execution time

DSP function 32 × 32 = 64: 200 to 250 ns (at 20 MHz)

I/O port I/O: 66 (5 V tolerant/N-ch open-drain output

Timer

16-bit TMP 4 channels 6 channels

16-bit TMQ 1 channel 1 channel

16-bit TMM 1 channel 1 channel

Watch timer 1 channel 1 channel

WDT 1 channel 1 channel

Real-time output port 4 bits × 1 channel, 2 bits × 1 channel, or 6 bits × 1 channel

10-bit A/D converter 8 channels 12 channels

8-bit D/A converter 1 channel 2 channels

Serial interface CSIB: 2 channels

DMA controller 4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory)

External 9 (9)

Internal 40 48

Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE/

Reset source RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)

CRC function 16-bit error detection code generated for 8-bit unit data

On-chip debug MINICUBE®, MINICUBE2 supported

Operating power supply voltage 2.2 to 3.6 V @5 MHz, 2.7 to 3.6 V @20 MHz Operating ambient temperature −40 to +85°C Package 80-pin LQFP (12 × 12 mm)

Note The figure in parentheses indicates the number of external interrupts that can release STOP mode.

Table 1-1. V850ES/Jx3-L Product List

PD70F3735

Address data bus: 16 Multiplexed bus mode output supported

Ceramic/crystal (in PLL mode: f

X = 2.5 to 5 MHz (multiplied by 4), in clock through mode: fX = 2.5 to 10 MHz)

External clock (in PLL mode: f

X = 2.5 to 5 MHz (multiplied by 4), in clock through mode: fX = 2.5 to 5 MHz)

Crystal (fXT = 32.768 kHz)

50 ns (main clock (fXX) = 20 MHz)

32 × 32 + 32 = 32: 300 ns (at 20 MHz) 16 × 16 = 32: 50 to 100 ns (at 20 MHz) 16 × 16 + 32 = 32: 150 ns (at 20 MHz)

selectable: 25)

UARTA: 2 channels

CSIB/I

C bus: 1 channel

UARTA/I

C bus: 1 channel

low-voltage STOP/low-voltage subclock/low-voltage sub-IDLE mode

80-pin LQFP (14 × 14 mm)

PD70F3736

PD70F3737

Address bus: 22 Address data bus: 16 Separate bus/multiplexed bus mode selectable

I/O: 84 (5 V tolerant/N-ch open-drain output selectable: 31)

CSIB: 3 channels UARTA/CSIB: 1 channel

CSIB/I

C bus: 1 channel

UARTA/I

Note

9 (9)

C bus: 2 channels

100-pin LQFP (14 × 14 mm) 100-pin LQFP (14 × 20 mm)

PD70F3738

Note

Interrupt source

R01UH0017EJ0400 Rev.4.00 Page 2 of 816 Sep 30, 2010

V850ES/JF3-L CHAPTER 1 INTRODUCTION

1.2 Features

{ Minimum instruction execution time: 50 ns (operating with main clock (f

200 ns (operating with main clock (f

30.5 μs (operating with subclock (fXT) of 32.768 kHz)

{ General-purpose registers: 32 bits × 32 registers { CPU features: Signed multiplication (16 × 16 → 32): 1 to 2 clocks

Signed multiplication (32 × 32 → 64): 1 to 5 clocks

Saturated operations (overflow and underflow detection functions included)

32-bit shift instruction: 1 clock

Bit manipulation instructions

Load/store instructions with long/short format

{ Memory space: 64 MB of linear address space (for programs and data)

External expansion: Up to 16 MB (including 1 MB used as internal ROM/RAM)

• Internal memory: RAM: 8/16 KB (see Table 1-1)

Flash memory: 128/256 KB (see Table 1-1)

• External bus interface: Multiplexed bus output

8/16 bit data bus sizing function

Wait function

• Programmable wait function

• External wait function

Idle state function

Bus hold function

{ Interrupts and exceptions: Non-maskable interrupts: 2 sources

Maskable interrupts: 47 sources

Software exceptions: 32 sources

Exception trap: 2 sources

{ I/O lines: I/O ports: 66

{ Timer function: 16-bit interval timer M (TMM): 1 channel

16-bit timer/event counter P (TMP): 4 channels

16-bit timer/event counter Q (TMQ): 1 channel

Watch timer: 1 channel

Watchdog timer: 1 channel

{ Real-time output port: 6 bits × 1 channel

{ Serial interface: Asynchronous serial interface A (UARTA)

3-wire variable-length serial interface B (CSIB)

C bus interface (I2C)

UARTA: 2 channels

UARTA/I

CSIB/I

C: 1 channel

CSIB: 2 channels

{ A/D converter: 10-bit resolution: 8 channels

{ D/A converter: 8-bit resolution: 1 channel

{ DMA controller: 4 channels

{ DCU (debug control unit): JTAG interface

{ Clock generator: During main clock or subclock operation

7-level CPU clock (f

XX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)

Clock-through mode/PLL mode selectable

XX) of 20 MHz: VDD = 2.7 to 3.6 V)

XX) of 5 MHz: VDD = 2.2 to 3.6 V)

R01UH0017EJ0400 Rev.4.00 Page 3 of 816 Sep 30, 2010

V850ES/JF3-L CHAPTER 1 INTRODUCTION

{ Internal oscillation clock: 220 kHz (TYP.)

{ Power-save functions: HALT/IDLE1/IDLE2/STOP/low-voltage STOP mode/subclock/sub-IDLE/

low-voltage subclock/low-voltage sub-IDLE mode { Package: 80-pin plastic LQFP (fine pitch) (12 × 12) 80-pin plastic LQFP (14 × 14)

1.3 Application Fields

Digital cameras, power meters, mobile terminals, digital home electronics, and other consumer devices

1.4 Ordering Information

Part Number Package Internal Flash Memory

PD70F3735GK-GAK-AX

PD70F3736GK-GAK-AX

PD70F3735GC-GAD-AX

PD70F3736GC-GAD-AX

Remark V850ES/JF3-L microcontrollers are lead-free products.

80-pin plastic LQFP (fine pitch) (12 × 12) 80-pin plastic LQFP (fine pitch) (12 × 12) 80-pin plastic LQFP (14 × 14) 80-pin plastic LQFP (14 × 14)

128 KB

256 KB

128 KB

256 KB

R01UH0017EJ0400 Rev.4.00 Page 4 of 816 Sep 30, 2010

V850ES/JF3-L CHAPTER 1 INTRODUCTION

1.5 Pin Configuration (Top View)

80-pin plastic LQFP (fine pitch) (12 × 12) 80-pin plastic LQFP (14 × 14)

PD70F3735GK-GAK-AX

PD70F3736GK-GAK-AX

P70/ANI0

PD70F3735GC-GAD-AX

PD70F3736GC-GAD-AX

P71/ANI1

P72/ANI2

P73/ANI3

P74/ANI4

P75/ANI5

P76/ANI6

P77/ANI7

PDH1/A17

PDL15/AD15

PDL14/AD14

PDH0/A16

PDL13/AD13

PDL12/AD12

PDL11/AD11

PDL10/AD10

PDL9/AD9

PDL8/AD8

PDL7/AD7

PDL6/AD6

REF0

P10/ANO0

REF1

P03/INTP0/ADTRG

P04/INTP1

P06/INTP3

Note 1

FLMD0

Note 2

REGC

RESET

XT1

XT2

P02/NMI

P05/INTP2/DRST

P40/SIB0/SDA01

P41/SOB0/SCL01

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

PDL5/AD5/FLMD1

PDL4/AD4

PDL3/AD3

PDL2/AD2

PDL1/AD1

PDL0/AD0

PCT6/ASTB

PCT4/RD

PCT1/WR1

PCT0/WR0

PCM3/HLDRQ

PCM2/HLDAK

PCM1/CLKOUT

PCM0/WAIT

P915/INTP6/TIP50/TOP50

P914/INTP5/TIP51/TOP51

P913/INTP4

P99/SCKB1

P98/SOB1

P97/SIB1/TIP20/TOP20

P30/TXDA0

P42/SCKB0

P90/KR6/TXDA1

P35/TIP11/TOP11

P33/TIP01/TOP01

P31/RXDA0/INTP7

P34/TIP10/TOP10

P38/TXDA2/SDA00

P32/ASCKA0/TIP00/TOP00

P39/RXDA2/SCL00

P50/TIQ01/KR0/TOQ01/RTP00

P51/TIQ02/KR1/TOQ02/RTP01

P54/SOB2/KR4/RTP04/DCK

P52/TIQ03/KR2/TOQ03/RTP02/DDI

P53/SIB2/TIQ00/KR3/TOQ00/RTP03/DDO

P91/KR7/RXDA1

P96/TIP21/TOP21

P55/SCKB2/KR5/RTP05/DMS

Notes 1. Connect this pin to V

2. Connect the REGC pin to V

SS in the normal mode.

SS via a 4.7

F (recommended value) capacitor.

R01UH0017EJ0400 Rev.4.00 Page 5 of 816 Sep 30, 2010

V850ES/JF3-L CHAPTER 1 INTRODUCTION

Pin names

A16, A17:

AD0 to AD15:

ADTRG:

ANI0 to ANI7:

ANO0:

ASCKA0:

ASTB:

REF0, AVREF1:

AVSS:

CLKOUT:

DCK:

DDI:

DDO:

DMS:

DRST:

DD:

SS:

FLMD0, FLMD1:

HLDAK:

HLDRQ:

INTP0 to INTP7:

KR0 to KR7:

NMI:

P02 to P06:

P10:

P30 to P35:

P38, P39

P40 to P42:

P50 to P55:

P70 to P77:

P90, P91:

P96 to P99,

P913 to P915

Address bus

Address/data bus

A/D trigger input

Analog input

Analog output

Asynchronous serial clock

Address strobe

Analog reference voltage

Analog V

Clock output

Debug clock

Debug data input

Debug data output

Debug mode select

Debug reset

Power supply for external pin

Ground for external pin

Flash programming mode

Hold acknowledge

Hold request

External interrupt input

Key return

Non-maskable interrupt request

Port 0

Port 1

Port 3

Port 4

Port 5

Port 7

Port 9

PCM0 to PCM3:

PCT0, PCT1,

PCT4, PCT6:

PDH0, PDH1:

PDL0 to PDL15:

RD:

REGC:

RESET:

RTP00 to RTP05:

RXDA0 to RXDA2:

SCKB0 to SCKB2:

SCL00, SCL01:

SDA00, SDA01:

SIB0 to SIB2:

SOB0 to SOB2:

TIP00, TIP01,

TIP10, TIP11,

TIP20, TIP21,

TIP50, TIP51,

TIQ00 to TIQ03:

TOP00, TOP01,

TOP10, TOP11,

TOP20, TOP21,

TOP50, TOP51,

TOQ00 to TOQ03:

TXDA0 to TXDA2:

DD:

SS:

WAIT:

WR0:

WR1:

X1, X2:

XT1, XT2:

Port CM

Port CT

Port DH

Port DL

Read strobe

Regulator control

Reset

Real-time output port

Receive data

Serial clock

Serial data

Serial input

Serial output

Timer input

Timer output

Transmit data

Power supply

Ground

Wait

Lower byte write strobe

Upper byte write strobe

Crystal for main clock

Crystal for subclock

R01UH0017EJ0400 Rev.4.00 Page 6 of 816 Sep 30, 2010

V850ES/JF3-L CHAPTER 1 INTRODUCTION

1.6 Function Block Configuration

1.6.1 Internal block diagram

INTP to INTP7

TIQ00 to TIQ03

TOQ00 to TOQ03

TIP00 to TIP20, TIP50 TIP01 to TIP21, TIP51

TOP00 to TOP20, TOP50 TOP01 to TOP21, TOP51

NMI

INTC

16-bit timer/

counter Q:

1 ch

16-bit timer/

counter P:

4 ch

16-bit interval

timer M:

1 ch

Flash

memory

Note 1

RAM

Note 2

DMAC

32-bit barrel

shifter

System

registers

General-purpose

registers 32 bits × 32

CPU

Multiplier

16 × 16 → 32

ALU

Instruction

queue

BCU

HLDRQ HLDAK ASTB RD WAIT

WR0, WR1

A16, A17 AD0 to AD15

RTP00 to RTP05

SOB0/SCL01

SIB0/SDA01

SCKB0

SOB1

SIB1

SCKB1

SOB2

SIB2

SCKB2

TXDA0

RXDA0

ASCKA0

TXDA1

RXDA1

TXDA2/SDA00 RXDA2/SCL00

RTO

CSIB0 I2C01

CSIB1

CSIB2

UARTA0

UARTA1

UARTA2

I2C00

Ports

P70-P77

P50-P55

P40-P42

PDH0, PDH1

PDL0-PDL15

PCM0b to PCM3

PCT0, PCT1, PCT4, PCT6

P90, P91, P96-P99, P913-P915

A/D

converter

D/A

converter

Key return

function

Watchdog

timer 2

Watch timer

Internal

oscillator

P10

P02-P06

P30-P35, P38, P39

ANI0 to ANI7 AV

REF0

ADTRG

REF1

ANO0

KR0 to KR7

CLM

CRC

DCU

PLL

LVI

Regulator

CLKOUT

XT1

XT2 X1 X2

RESET

REGC

FLMD0

FLMD1

DRST

DMS

DDI

DCK

DDO

Notes 1.

PD70F3735: 128 KB

PD70F3736: 256 KB

2. μPD70F3735: 8 KB

PD70F3736: 16 KB

R01UH0017EJ0400 Rev.4.00 Page 7 of 816 Sep 30, 2010

V850ES/JF3-L CHAPTER 1 INTRODUCTION

1.6.2 Internal units

(1) CPU

The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic

operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits)

contribute to faster complex processing.

(2) Bus control unit (BCU)

The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an

instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU

generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an

instruction queue.

(3) Flash memory (ROM)

This is a 256/128 KB flash memory mapped to addresses 0000000H to 003FFFFH/0000000H to 001FFFFH.

It can be accessed from the CPU in one clock during instruction fetch.

(4) RAM

This is a 16/8 KB RAM mapped to addresses 3FFB000H to 3FFEFFFH/3FFD000H to 3FFEFFFH. It can be

accessed from the CPU in one clock during data access.

(5) Interrupt controller (INTC)

This controller handles hardware interrupt requests (NMI, INTP0 to INTP7) from on-chip peripheral hardware and

external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed

servicing control can be performed.

(6) Clock generator (CG)

A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (f

and subclock frequency (f

clock frequency (f

XX) as is. In the PLL mode, fX is used multiplied by 4.

XT), respectively. There are two modes: In the clock-through mode, fX is used as the main

The CPU clock frequency (fCPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT.

(7) Internal oscillator

An internal oscillator is provided on chip. The oscillation frequency is 220 kHz (TYP). The internal oscillator

supplies the clock for watchdog timer 2 and timer M.

(8) Timer/counter

Four-channel 16-bit timer/event counter P (TMP), one-channel 16-bit timer/event counter Q (TMQ), and one-

channel 16-bit interval timer M (TMM), are provided on chip.

(9) Watch timer

This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz subclock or the 32.768

kHz clock f

BRG from prescaler 3). The watch timer can also be used as an interval timer for the main clock.

R01UH0017EJ0400 Rev.4.00 Page 8 of 816 Sep 30, 2010

V850ES/JF3-L CHAPTER 1 INTRODUCTION

(10) Watchdog timer 2

A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc.

The internal oscillation clock, the main clock, or the subclock can be selected as the source clock.

Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal

(WDT2RES) after an overflow occurs.

(11) Serial interface

The V850ES/JF3-L includes three kinds of serial interfaces: asynchronous serial interface A (UARTA), 3-wire

variable-length serial interface B (CSIB), and an I

In the case of UARTA, data is transferred via the TXDA0 to TXDA2 pins and RXDA0 to RXDA2 pins.

In the case of CSIB, data is transferred via the SOB0 to SOB2 pins, SIB0 to SIB2 pins, and SCKB0 to SCKB2

pins.

In the case of I

C, data is transferred via the SDA00, SDA01, SCL00, and SCL01 pins.

(12) A/D converter

This 10-bit A/D converter includes 8 analog input pins. Conversion is performed using the successive

approximation method.

(13) D/A converter

A one-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip.

(14) DMA controller

A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and on-

chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.

(15) Key interrupt function

A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8

channels).

(16) Real-time output function

The real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer compare

(17) CRC function

A CRC operation circuit that generates a 16-bit CRC (Cyclic Redundancy Check) code upon setting of 8-bit data

is provided on-chip.

(18) DCU (debug control unit)

An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is provided.

Switching between the normal port function and on-chip debugging function is done with the control pin input

level and the OCDM register.

C bus interface (I2C).

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V850ES/JF3-L CHAPTER 1 INTRODUCTION

(19) Ports

The following general-purpose port functions and control pin functions are available.

Port I/O Alternate Function

P0 5-bit I/O NMI, external interrupt, A/D converter trigger, debug reset

P1 1-bit I/O D/A converter analog output

P3 8-bit I/O External interrupt, serial interface, timer I/O

P4 3-bit I/O Serial interface

P5 6-bit I/O Timer I/O, real-time output, key interrupt input, serial interface, debug I/O

P7 8-bit I/O A/D converter analog input

P9 9-bit I/O Serial interface, key interrupt input, timer I/O, external interrupt

PCM 4-bit I/O External control signal

PCT 4-bit I/O External control signal

PDH 2-bit I/O External address bus

PDL 16-bit I/O External address/data bus

R01UH0017EJ0400 Rev.4.00 Page 10 of 816 Sep 30, 2010

V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS

CHAPTER 2 PIN FUNCTIONS

2.1 List of Pin Functions

The names and functions of the pins in the V850ES/JF3-L are described below.

There are three types of pin I/O buffer power supplies: AV

supplies and the pins is described below.

Table 2-1. Pin I/O Buffer Power Supplies

Power Supply Corresponding Pins

AVREF0 Port 7

AVREF1 Port 1

EVDD RESET, ports 0, 3 to 5, 9, CM, CT, DH, DL

REF0, AVREF1, and EVDD. The relationship between these power

R01UH0017EJ0400 Rev.4.00 Page 11 of 816 Sep 30, 2010

V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS

(1) Port pins

(1/2)

Pin Name Pin No. I/O Function Alternate Function

P02 17 NMI

P03 5 INTP0/ADTRG

P04 6 INTP1

Note

P05

18 INTP2/DRST

P06 7

P10 3 I/O

P30

P31

P32

P33

P34

P35

P38

P39

P40 19 SIB0/SDA01

P41 20 SOB0/SCL01

P42 21

P50 32 TIQ01/KR0/TOQ01/RTP00

P51 33 TIQ02/KR1/TOQ02/RTP01

P52 34 TIQ03/KR2/TOQ03/RTP02/DDI

P53 35 SIB2/KR3/TIQ00/TOQ00/RTP03/DDO

P54 36 SOB2/KR4/RTP04/DCK

P55 37

P70 80 ANI0

P71 79 ANI1

P72 78 ANI2

P73 77 ANI3

P74 76 ANI4

P75 75 ANI5

P76 74 ANI6

P77 73

I/O

Por t 0

5-bit I/O port

Input/output can be specified in 1-bit units.

N-ch open-drain output can be specified in 1-bit units.

5 V tolerant.

Por t 1

1-bit I/O port

Input/output can be specified in 1-bit units.

Por t 3

10-bit I/O port

Input/output can be specified in 1-bit units.

N-ch open-drain output can be specified in 1-bit units.

5 V tolerant.

Por t 4

3-bit I/O port

Input/output can be specified in 1-bit units.

N-ch open-drain output can be specified in 1-bit units.

5 V tolerant.

Por t 5

6-bit I/O port

Input/output can be specified in 1-bit units.

N-ch open-drain output can be specified in 1-bit units.

5 V tolerant.

Por t 7

8-bit I/O port

Input/output can be specified in 1-bit units.

INTP3

ANO0

TXDA0

RXDA0/INTP7

ASCKA0/TIP00/TOP00

TIP01/TOP01

TIP10/TOP10

TIP11/TOP11

TXDA2/SDA00

RXDA2/SCL00

SCKB0

SCKB2/KR5/RTP05/DMS

ANI7

Note Incorporates a pull-down resistor. It can be disconnected by clearing the OCDM.OCDM0 bit to 0.

R01UH0017EJ0400 Rev.4.00 Page 12 of 816 Sep 30, 2010

V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS

Pin Name Pin No. I/O Function Alternate Function

P90 38 KR6/TXDA1

P91 39 KR7/RXDA1

P96 40 TIP21/TOP21

P97 41 SIB1/TIP20/TOP20

P98 42 SOB1

P99 43 SCKB1

P913 44 INTP4

P914 45 INTP5/TIP51/TOP51

P915 46

PCM0 47 WAIT

PCM1 48 CLKOUT

PCM2 49 HLDAK

PCM3 50

PCT0 51 WR0

PCT1 52 WR1

PCT4 53 RD

PCT6 54

PDH0 71 A16

PDH1 72

PDL0 55 AD0

PDL1 56 AD1

PDL2 57 AD2

PDL3 58 AD3

PDL4 59 AD4

PDL5 60 AD5/FLMD1

PDL6 61 AD6

PDL7 62 AD7

PDL8 63 AD8

PDL9 64 AD9

PDL10 65 AD10

PDL11 66 AD11

PDL12 67 AD12

PDL13 68 AD13

PDL14 69 AD14

PDL15 70

I/O

Por t 9

9-bit I/O port

Input/output can be specified in 1-bit units.

N-ch open-drain output can be specified in 1-bit units.

5 V tolerant. (only P90, P91, P96)

Por t CM

4-bit I/O port

Input/output can be specified in 1-bit units.

Por t CT

4-bit I/O port

Input/output can be specified in 1-bit units.

Port DH

2-bit I/O port

Input/output can be specified in 1-bit units.

Por t DL

16-bit I/O port

Input/output can be specified in 1-bit units.

INTP6/TIP50/TOP50

HLDRQ

ASTB

A17

AD15

(2/2)

R01UH0017EJ0400 Rev.4.00 Page 13 of 816 Sep 30, 2010

V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS

(2) Non-port pins

(1/4)

Pin Name Pin No. I/O Function Alternate Function

A16 89 PDH0

A17 90

AD0 55 PDL0

AD1 56 PDL1

AD2 57 PDL2

AD3 58 PDL3

AD4 59 PDL4

AD5 60 PDL5/FLMD1

AD6 61 PDL6

AD7 62 PDL7

AD8 63 PDL8

AD9 64 PDL9

AD10 65 PDL10

AD11 66 PDL11

AD12 67 PDL12

AD13 68 PDL13

AD14 69 PDL14

AD15 70

ADTRG 5 Input A/D converter external trigger input. 5 V tolerant. P03/INTP0

ANI0 80 P70

ANI1 79 P71

ANI2 78 P72

ANI3 77 P73

ANI4 76 P74

ANI5 75 P75

ANI6 74 P76

ANI7 73

ANO0 3 Output Analog voltage output for D/A converter P10

ASCKA0 24 Input UARTA0 baud rate clock input. 5 V tolerant. P32/TIP00/TOP00

ASTB 54 Output Address strobe signal output for external memory PCT6

AVREF0 1 Reference voltage input for A/D converter/positive power

AVREF1 4

AVSS 2 − Ground potential for A/D and D/A converters (same

CLKOUT 48 Output Internal system clock output PCM1

DCK 36 Input Debug clock input. 5 V tolerant. P54/SOB2/KR4/RTP04

DDI 34 Input Debug data input. 5 V tolerant. P52/TIQ03/KR2/TOQ03/RTP02

Note

DDO

35 Output Debug data output. N-ch open-drain output selectable.

DMS 37 Input Debug mode select input. 5 V tolerant. P55/SCKB2/KR5/RTP05

Note In the on-chip debug mode, high-level output is forcibly set.

R01UH0017EJ0400 Rev.4.00 Page 14 of 816 Sep 30, 2010

Output Address bus for external memory

I/O Address bus/data bus for external memory

Input Analog voltage input for A/D converter

−

supply for port 7

Reference voltage input for D/A converter/positive power

supply for port 1

potential as V

5 V tolerant.

SS)

PDH1

PDL15

P77

−

P53/SIB2/KR3/TIQ00/TOQ00/

RTP03

+ 805 hidden pages

Renesas V850ES/JF3-L, V850ES/JG3-L User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

How to Use This Manual

CHAPTER 1 INTRODUCTION

1.1 General

1.2 Features

1.3 Application Fields

1.4 Ordering Information

1.5 Pin Configuration (Top View)

1.6 Function Block Configuration

1.6.1 Internal block diagram

1.6.2 Internal units

CHAPTER 2 PIN FUNCTIONS

2.1 List of Pin Functions