Renesas V850ES/JE3-L, V850ES/JC3-L User Manual

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User’s Manual

V850ES/JC3-L, V850ES/JE3-L

User’s Manual: Hardware

RENESAS MCU V850ES/Jx3-L Microcontrollers

— Preliminary —

V850ES/JC3-L V850ES/JE3-L

μPD70F3797 μPD70F3802 μPD70F3805 μPD70F3798 μPD70F3803 μPD70F3806 μPD70F3799 μPD70F3804 μPD70F3807 μPD70F3800 μPD70F3838 μPD70F3808 μPD70F3801 μPD70F3839 μPD70F3840

All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com).

www.renesas.com

Rev.0.01 Jul, 2010

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Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such informatio n is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and “Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise expressly specified in a Ren esas E lectronics data sheets or data books, etc.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

equipment; home electron ic appliances; machine tools; personal electronic equipment; and industrial robots.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

crime systems; safety equipment; and medical equipment not specifically designed for life support.

“Specific”: Aircraft; aerospace equip ment; submersible repeaters; nuclear reactor control systems; medical equipment or

systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other appli cations or purposes that pose a di rect threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as t he occu rrence o f failure at a certai n rate an d malfunct io ns under cert ain u se con dition s. Further, Renesas Electronics prod ucts are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the en vironmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Ele ct ronics Corporation and also in cludes its majority-

owned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

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NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V

(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

(MAX) and VIH (MIN) due to noise, etc., the device may

(MAX) and

or GND

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

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How to Use This Manual

Readers This manual is intended for users who wish to understand the functions of the

V850ES/JC3-L, V850ES/JE3-L and design application systems using these products.

Purpose This manual is intended to give users an understanding of the hardware functions of the

V850ES/JC3-L, V850ES/JE3-L shown in the Organization below.

Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES

Architecture User’s Manual).

Hardware Architecture

• Pin functions • Data types

• CPU function • Register set

• On-chip peripheral functions • Instruction format and instruction set

• Flash memory programming • Interrupts and exceptions

• Electrical specifications (Target) • Pipeline operation

How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of

electrical engineering, logic circuits, and microcontrollers.

To understand the overall functions of the V850ES/JC3-L, V850ES/JE3-L → Read this manual according to the CONTENTS.

To find the details of a register where the name is known → Use APPENDIX C REGISTER INDEX.

format of each register is defined as a reserved word in the device file.

To understand the details of an instruction function → Refer to the V850ES Architecture User’s Manual available separately.

To know the electrical specifications of the V850ES/JC3-L (40-pin)

→ See CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin))

(Target)

To know the electrical specifications of the V850ES/JC3-L (48-pin)

→ See CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin))

(Target)

To know the electrical specifications of the V850ES/JE3-L → See CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target)

The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note with

caution that if “xxx.yyy” is described as is in a program, however, the compiler/assembler

cannot recognize it correctly.

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Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representation: xxx (overscore over pin or signal name)

Memory map address: Higher addresses on the top and lower addresses on the

bottom

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numeric representation: Binary ... xxxx or xxxxB

Decimal ... xxxx

Hexadecimal ... xxxxH

Prefix indicating power of 2 (address space, memory capacity):

K (kilo): 2

M (mega): 2

G (giga): 2

= 1,024

= 1,0242

= 1,024

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Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents related to V850ES/JC3-L, V850ES/JE3-L

Document Name Document No.

V850ES Architecture User’s Manual U15943E

V850ES/JC3-L, V850ES/JE3-L Hardware User’s Manual This manual

Documents related to development tools

Document Name Document No.

QB-V850ESJX3L In-Circuit Emulator To be prepared

QB-V850MINI, QB-V850MINIL On-Chip Debug Emulator U17638E

QB-MINI2 On-Chip Debug Emulator with Programming Function U18371E

CA850 Ver. 3.20 C Compiler Package

PM+ Ver. 6.30 Project Manager U18416E

ID850QB Ver. 3.40 Integrated Debugger Operation U18604E

SM850 Ver. 2.50 System Simulator Operation U16218E

SM850 Ver. 2.00 or Later System Simulator External Part User Open

RX850 Ver. 3.20 Real-Time OS

RX850 Pro Ver. 3.21 Real-Time OS

AZ850 Ver. 3.30 System Performance Analyzer U17423E

PG-FP5 Flash Memory Programmer U18865E

Operation U18512E

C Language U18513E

Assembly Language U18514E

Link Directives U18415E

U14873E

Interface Specification

Operation U18601E SM+ System Simulator

User Open Interface U18212E

Basics U13430E

Installation U17419E

Technical U13431E

Task Debugger U17420E

Basics U18165E

Installation U17421E

Task Debugger U17422E

Page 7

Other Documents

Document Name Document No.

SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X

Semiconductor Device Mount Manual

Quality Grades on Renesas Semiconductor Devices

Renesas Semiconductor Device Reliability/Quality Control System

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

Note

C11531E

C10983E

C11892E

Note See the “Semiconductor Device Mount Manual” website

(http://www2.renesas.com/pkg/en/mount/index.html).

Caution The related documents listed above are subject to change without notice.

Be sure to use the latest version of each document when designing.

Caution: This product uses SuperFlash

technology licensed from Silicon Storage Technology, Inc.

IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany.

MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in

the United States of America.

EEPROM is a trademark of Renesas Electronics Corporation

Applilet is a registered trademark of Renesas Electronics in Japan, Germany, Hong Kong, China, the Republic of

Korea, the United Kingdom, and the United States of America.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United

States and/or other countries.

SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United

States and Japan.

PC/AT is a trademark of International Business Machines Corporation.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

TRON is an abbreviation of The Realtime Operating System Nucleus.

ITRON is an abbreviation of Industrial TRON.

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Table of Contents

CHAPTER 1 INTRODUCTION................................................................................................................. 19

1.1 General...................................................................................................................................... 19

1.2 Features .................................................................................................................................... 23

1.3 Application Fields .................................................................................................................... 25

1.4 Ordering Information ............................................................................................................... 25

1.4.1 V850ES/JC3-L ................................................................................................................................25

1.4.2 V850ES/JE3-L ................................................................................................................................25

1.5 Pin Configuration (Top View).................................................................................................. 26

1.6 Function Block Configuration................................................................................................. 31

1.6.1 Internal block diagram.....................................................................................................................31

1.6.2 Internal units ...................................................................................................................................34

CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 37

2.1 List of Pin Functions................................................................................................................ 37

2.2 Pin States.................................................................................................................................. 45

2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins......... 46

2.4 Cautions.................................................................................................................................... 49

CHAPTER 3 CPU FUNCTION ................................................................................................................ 50

3.1 Features .................................................................................................................................... 50

3.2 CPU Register Set...................................................................................................................... 51

3.2.1 Program register set .......................................................................................................................52

3.2.2 System register set .........................................................................................................................53

3.3 Operation Modes...................................................................................................................... 59

3.4 Address Space ......................................................................................................................... 60

3.4.1 CPU address space........................................................................................................................60

3.4.2 Memory map...................................................................................................................................61

3.4.3 Areas ..............................................................................................................................................63

3.4.4 Wraparound of data space..............................................................................................................68

3.4.5 Recommended use of address space.............................................................................................68

3.4.6 Peripheral I/O registers...................................................................................................................72

3.4.7 Special registers .............................................................................................................................82

3.4.8 Registers to be set first ...................................................................................................................86

3.4.9 Cautions..........................................................................................................................................87

CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 89

4.1 Features .................................................................................................................................... 89

4.1.1 V850ES/JC3-L (40-pin)...................................................................................................................89

4.1.2 V850ES/JC3-L (48-pin)...................................................................................................................89

4.1.3 V850ES/JE3-L ................................................................................................................................89

4.2 Basic Port Configuration......................................................................................................... 90

4.2.1 V850ES/JC3-L (40-pin)...................................................................................................................90

4.2.2 V850ES/JC3-L (48-pin)...................................................................................................................91

4.2.3 V850ES/JE3-L ................................................................................................................................92

4.3 Port Configuration ................................................................................................................... 93

4.3.1 Port 0 ..............................................................................................................................................99

4.3.2 Port 1 (V850ES/JC3-L (48-pin), V850ES/JE3-L)...........................................................................105

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4.3.3 Port 3 ............................................................................................................................................106

4.3.4 Port 4 ............................................................................................................................................114

4.3.5 Port 5 ............................................................................................................................................116

4.3.6 Port 7 ............................................................................................................................................121

4.3.7 Port 9 ............................................................................................................................................124

4.3.8 Port CM.........................................................................................................................................136

4.3.9 Port DL..........................................................................................................................................137

4.4 Block Diagrams...................................................................................................................... 139

4.5 Port Register Settings When Alternate Function Is Used.................................................. 171

4.6 Cautions.................................................................................................................................. 177

4.6.1 Cautions on setting port pins.........................................................................................................177

4.6.2 Cautions on bit manipulation instruction for port n register (Pn)....................................................180

4.6.3 Cautions on on-chip debug pins....................................................................................................181

4.6.4 Cautions on P05/INTP2/DRST pin................................................................................................181

4.6.5 Cautions on P10, P11, and P53 pins when power is turned on ....................................................181

4.6.6 Hysteresis characteristics .............................................................................................................181

CHAPTER 5 CLOCK GENERATOR .................................................................................................... 182

5.1 Overview ................................................................................................................................. 182

5.2 Configuration.......................................................................................................................... 183

5.3 Registers................................................................................................................................. 185

5.4 Operations .............................................................................................................................. 190

5.4.1 Operation of each clock ................................................................................................................190

5.4.2 External clock signal input.............................................................................................................190

5.5 PLL Function .......................................................................................................................... 191

5.5.1 Overview.......................................................................................................................................191

5.5.2 Registers.......................................................................................................................................191

5.5.3 Usage ...........................................................................................................................................195

5.6 How to Connect a Resonator................................................................................................ 196

5.6.1 Main clock oscillator......................................................................................................................196

5.6.2 Subclock oscillator ........................................................................................................................196

CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) ................................................................ 199

6.1 Overview ................................................................................................................................. 199

6.2 Configuration.......................................................................................................................... 200

6.2.1 Pins used by TMPn.......................................................................................................................202

6.2.2 Register configuraiton ...................................................................................................................203

6.2.3 Interrupts.......................................................................................................................................206

6.3 Registers................................................................................................................................. 207

6.4 Operations .............................................................................................................................. 219

6.4.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) ..................................................................227

6.4.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) ......................................................238

6.4.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) ..........................................247

6.4.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011)....................................................259

6.4.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) ...................................................................267

6.4.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) .........................................................276

6.4.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110)..............................................292

6.4.8 Timer output operations ................................................................................................................296

6.5 Selector (V850ES/JE3-L only)............................................................................................... 297

6.6 Cautions.................................................................................................................................. 298

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)................................................................ 299

7.1 Functions ................................................................................................................................ 299

7.2 Configuration.......................................................................................................................... 300

7.2.1 Pins used by TMQ0 ......................................................................................................................302

7.2.2 Interrupts.......................................................................................................................................302

7.3 Registers................................................................................................................................. 303

7.4 Operations .............................................................................................................................. 318

7.4.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) .................................................................325

7.4.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) .....................................................336

7.4.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) .........................................347

7.4.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011)...................................................362

7.4.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) ..................................................................372

7.4.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101).........................................................383

7.4.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110).............................................403

7.4.8 Timer output operations ................................................................................................................408

7.5 Cautions.................................................................................................................................. 409

CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) ............................................................................ 410

8.1 Features .................................................................................................................................. 410

8.2 Configuration.......................................................................................................................... 411

8.3 Registers................................................................................................................................. 412

8.4 Operation ................................................................................................................................ 414

8.4.1 Interval timer mode .......................................................................................................................414

8.4.2 Cautions........................................................................................................................................418

CHAPTER 9 WATCH TIMER................................................................................................................ 419

9.1 Functions ................................................................................................................................ 419

9.2 Configuration.......................................................................................................................... 420

9.3 Control Registers................................................................................................................... 422

9.4 Operation ................................................................................................................................ 426

9.4.1 Watch timer operations .................................................................................................................426

9.4.2 Interval timer operations................................................................................................................427

9.5 Cautions.................................................................................................................................. 429

CHAPTER 10 REAL-TIME COUNTER................................................................................................. 430

10.1 Functions ................................................................................................................................ 430

10.2 Configuration.......................................................................................................................... 431

10.2.1 Pin configuration ...........................................................................................................................433

10.2.2 Interrupt functions .........................................................................................................................433

10.3 Registers ................................................................................................................................. 434

10.4 Operation ................................................................................................................................ 449

10.4.1 Initial settings ................................................................................................................................449

10.4.2 Rewriting each counter during real-time counter operation ...........................................................450

10.4.3 Reading each counter during real-time counter operation ............................................................451

10.4.4 Changing INTRTC0 interrupt setting during real-time counter operation ......................................452

10.4.5 Changing INTRTC1 interrupt setting during real-time counter operation ......................................453

10.4.6 Initial INTRTC2 interrupt settings ..................................................................................................454

10.4.7 Changing INTRTC2 interrupt setting during real-time counter operation ......................................455

10.4.8 Initializing real-time counter ..........................................................................................................456

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10.4.9 Watch error correction example of real-time counter ....................................................................457

CHAPTER 11 WATCHDOG TIMER 2 ................................................................................................. 461

11.1 Functions ................................................................................................................................ 461

11.2 Configuration.......................................................................................................................... 462

11.3 Registers ................................................................................................................................. 463

11.4 Operation ................................................................................................................................ 465

CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)................................................................... 466

12.1 Function .................................................................................................................................. 466

12.2 Configuration.......................................................................................................................... 467

12.3 Registers ................................................................................................................................. 469

12.4 Operation ................................................................................................................................ 471

12.5 Usage....................................................................................................................................... 472

12.6 Cautions .................................................................................................................................. 472

CHAPTER 13 A/D CONVERTER ......................................................................................................... 473

13.1 Overview ................................................................................................................................. 473

13.2 Functions ................................................................................................................................ 473

13.3 Configuration.......................................................................................................................... 474

13.4 Registers ................................................................................................................................. 477

13.5 Operation ................................................................................................................................ 488

13.5.1 Basic operation .............................................................................................................................488

13.5.2 Conversion timing .........................................................................................................................489

13.5.3 Trigger modes ...............................................................................................................................490

13.5.4 Operation mode ............................................................................................................................492

13.5.5 Power-fail compare mode .............................................................................................................498

13.6 Cautions .................................................................................................................................. 505

13.7 How to Read A/D Converter Characteristics Table ............................................................ 510

CHAPTER 14 D/A CONVERTER (V850ES/JC3-L (48-pin), V850ES/JE3-L) ..................................... 514

14.1 Functions ................................................................................................................................ 514

14.2 Configuration.......................................................................................................................... 515

14.3 Registers ................................................................................................................................. 516

14.4 Operation ................................................................................................................................ 518

14.4.1 Operation in normal mode.............................................................................................................518

14.4.2 Operation in real-time output mode...............................................................................................518

14.4.3 Cautions........................................................................................................................................519

CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ............................................. 520

15.1 Features .................................................................................................................................. 520

15.2 Configuration.......................................................................................................................... 521

15.2.1 Pin functions of each channel .......................................................................................................523

15.3 Mode Switching of UARTA and Other Serial Interfaces..................................................... 524

15.3.1 UARTA0 and CSIB4 mode switching ............................................................................................524

15.3.2 UARTA1 and I2C02 mode switching..............................................................................................525

15.3.3 UARTA2 and I2C00 mode switching..............................................................................................526

15.4 Registers ................................................................................................................................. 527

15.5 Interrupt Request Signals ..................................................................................................... 534

15.6 Operation ................................................................................................................................ 535

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15.6.1 Data format ...................................................................................................................................535

15.6.2 UART transmission .......................................................................................................................537

15.6.3 Continuous transmission procedure..............................................................................................538

15.6.4 UART reception ............................................................................................................................540

15.6.5 Reception errors ...........................................................................................................................542

15.6.6 Parity types and operations...........................................................................................................544

15.6.7 LIN transmission/reception format ................................................................................................545

15.6.8 SBF transmission ..........................................................................................................................547

15.6.9 SBF reception ...............................................................................................................................548

15.6.10 Receive data noise filter ...........................................................................................................549

15.7 Dedicated Baud Rate Generator ........................................................................................... 550

15.8 Cautions .................................................................................................................................. 558

CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)............................................................... 559

16.1 Features .................................................................................................................................. 559

16.2 Configuration.......................................................................................................................... 560

16.2.1 Pin functions of each channel .......................................................................................................561

16.3 Mode Switching of CSIB and Other Serial Interfaces......................................................... 562

16.3.1 CSIB0 and I2C01 mode switching .................................................................................................562

16.3.2 CSIB4 and UARTA0 mode switching ............................................................................................563

16.4 Registers ................................................................................................................................. 564

16.5 Interrupt Request Signals ..................................................................................................... 573

16.6 Operation ................................................................................................................................ 574

16.6.1 Single transfer mode (master mode, transmission mode) .............................................................574

16.6.2 Single transfer mode (master mode, reception mode) ..................................................................576

16.6.3 Single transfer mode (master mode, transmission/reception mode) .............................................578

16.6.4 Single transfer mode (slave mode, transmission mode) ...............................................................580

16.6.5 Single transfer mode (slave mode, reception mode).....................................................................582

16.6.6 Single transfer mode (slave mode, transmission/reception mode)................................................585

16.6.7 Continuous transfer mode (master mode, transmission mode).....................................................587

16.6.8 Continuous transfer mode (master mode, reception mode) ..........................................................589

16.6.9 Continuous transfer mode (master mode, transmission/reception mode) .....................................592

16.6.10 Continuous transfer mode (slave mode, transmission mode) ..................................................596

16.6.11 Continuous transfer mode (slave mode, reception mode)........................................................598

16.6.12 Continuous transfer mode (slave mode, transmission/reception mode)...................................601

16.6.13 Reception errors.......................................................................................................................604

16.6.14 Clock timing..............................................................................................................................605

16.7 Output Pins ............................................................................................................................. 607

16.8 Baud Rate Generator ............................................................................................................. 608

16.8.1 Baud rate generation ....................................................................................................................609

16.9 Cautions .................................................................................................................................. 610

CHAPTER 17 I

C BUS .......................................................................................................................... 611

17.1 Mode Switching of I2C Bus and Other Serial Interfaces..................................................... 612

17.1.1 UARTA2 and I2C00 mode switching..............................................................................................612

17.1.2 CSIB0 and I2C01 mode switching .................................................................................................613

17.1.3 UARTA1 and I2C02 mode switching..............................................................................................614

17.2 Features .................................................................................................................................. 615

17.3 Configuration.......................................................................................................................... 616

17.4 Registers ................................................................................................................................. 620

Page 13

17.5.1 Pin configuration ...........................................................................................................................636

17.6 I2C Bus Definitions and Control Methods ............................................................................ 637

17.6.1 Start condition ...............................................................................................................................637

17.6.2 Addresses .....................................................................................................................................638

17.6.3 Transfer direction specification .....................................................................................................639

17.6.4 ACK ..............................................................................................................................................640

17.6.5 Stop condition ...............................................................................................................................641

17.6.6 Wait state ......................................................................................................................................642

17.6.7 Wait state cancellation method .....................................................................................................644

17.7 I2C Interrupt Request Signals (INTIICn)................................................................................ 645

17.7.1 Master device operation................................................................................................................645

17.7.2 Slave device operation (when receiving slave address data (address match)) .............................648

17.7.3 Slave device operation (when receiving extension code)..............................................................652

17.7.4 Operation without communication .................................................................................................656

17.7.5 Operation when arbitration loss occurs (operation as slave after arbitration loss) ........................656

17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) ........................658

17.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control ........................ 665

17.9 Address Match Detection Method ........................................................................................ 667

17.10 Error Detection ....................................................................................................................... 667

17.11 Extension Code ...................................................................................................................... 667

17.12 Arbitration............................................................................................................................... 668

17.13 Wakeup Function ................................................................................................................... 669

17.14 Communication Reservation ................................................................................................ 670

17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0)........................670

17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) .......................674

17.15 Cautions.................................................................................................................................. 675

17.16 Communication Operations.................................................................................................. 676

17.16.1 Master operation in single master system ................................................................................677

17.16.2 Master operation in multimaster system...................................................................................678

17.16.3 Slave operation ........................................................................................................................681

17.17 Timing of Data Communication............................................................................................ 684

CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) ................................................................... 691

18.1 Features .................................................................................................................................. 691

18.2 Configuration.......................................................................................................................... 692

18.3 Registers ................................................................................................................................. 694

18.4 Transfer Sources and Destinations ..................................................................................... 702

18.5 Transfer Modes ...................................................................................................................... 702

18.6 Transfer Types ....................................................................................................................... 703

18.7 DMA Channel Priorities ......................................................................................................... 704

18.8 Time Related to DMA Transfer.............................................................................................. 705

18.9 DMA Transfer Start Factors .................................................................................................. 706

18.10 End of DMA Transfer ............................................................................................................. 707

18.11 Cautions.................................................................................................................................. 707

CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION......................... 712

19.1 Features .................................................................................................................................. 712

19.2 Non-Maskable Interrupts ....................................................................................................... 716

19.2.1 Operation ......................................................................................................................................718

19.2.2 Restoration....................................................................................................................................719

Page 14

19.2.3 NP flag ..........................................................................................................................................720

19.3 Maskable Interrupts ............................................................................................................... 721

19.3.1 Operation ......................................................................................................................................721

19.3.2 Restoration....................................................................................................................................723

19.3.3 Priorities of maskable interrupts ....................................................................................................724

19.3.4 Interrupt control register (xxICn) ...................................................................................................728

19.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) .............................................................................730

19.3.6 In-service priority register (ISPR) ..................................................................................................732

19.3.7 ID flag ...........................................................................................................................................733

19.3.8 Watchdog timer mode register 2 (WDTM2)...................................................................................733

19.4 Software Exception................................................................................................................ 734

19.4.1 Operation ......................................................................................................................................734

19.4.2 Restoration....................................................................................................................................735

19.4.3 EP flag ..........................................................................................................................................736

19.5 Exception Trap ....................................................................................................................... 737

19.5.1 Illegal opcode ................................................................................................................................737

19.6 Multiple Interrupt Servicing Control..................................................................................... 741

19.7 External Interrupt Request Input Pins (NMI, INTP0 to INTP7) ........................................... 742

19.7.1 Noise elimination...........................................................................................................................742

19.7.2 Edge detection ..............................................................................................................................742

19.8 Interrupt Response Time of CPU.......................................................................................... 748

19.9 Periods in Which Interrupts Are Not Acknowledged by CPU ........................................... 749

19.10 Cautions.................................................................................................................................. 749

19.10.1 Restored PC.............................................................................................................................749

CHAPTER 20 KEY INTERRUPT FUNCTION ..................................................................................... 750

20.1 Function .................................................................................................................................. 750

20.2 Pin Functions.......................................................................................................................... 751

20.3 Registers ................................................................................................................................. 751

20.4 Cautions .................................................................................................................................. 752

CHAPTER 21 STANDBY FUNCTION .................................................................................................. 753

21.1 Overview ................................................................................................................................. 753

21.2 Registers ................................................................................................................................. 755

21.3 HALT Mode ............................................................................................................................. 760

21.3.1 Setting and operation status .........................................................................................................760

21.3.2 Releasing HALT mode ..................................................................................................................760

21.4 IDLE1 Mode............................................................................................................................. 762

21.4.1 Setting and operation status .........................................................................................................762

21.4.2 Releasing IDLE1 mode .................................................................................................................763

21.5 IDLE2 Mode............................................................................................................................. 765

21.5.1 Setting and operation status .........................................................................................................765

21.5.2 Releasing IDLE2 mode .................................................................................................................766

21.5.3 Securing setup time when releasing IDLE2 mode.........................................................................768

21.6 STOP Mode/Low-Voltage STOP Mode ................................................................................. 769

21.6.1 Setting and operation status .........................................................................................................769

21.6.2 Releasing STOP mode/low-voltage STOP mode..........................................................................773

21.6.3 Re-setting after release of low-voltage STOP mode .....................................................................774

21.6.4 Securing oscillation stabilization time when releasing STOP mode ..............................................775

21.7 Subclock Operation Mode/Low-Voltage Subclock Operation Mode ................................ 776

Page 15

21.7.1 Setting and operation status .........................................................................................................776

21.7.2 Releasing subclock operation mode .............................................................................................780

21.7.3 Releasing low-voltage subclock operation mode ..........................................................................780

21.8 Sub-IDLE Mode/Low-Voltage Sub-IDLE Mode .................................................................... 781

21.8.1 Setting and operation status .........................................................................................................781

21.8.2 Releasing sub-IDLE mode/low-voltage sub-IDLE mode ...............................................................784

CHAPTER 22 RESET FUNCTION........................................................................................................ 785

22.1 Overview ................................................................................................................................. 785

22.2 Configuration.......................................................................................................................... 786

22.3 Register to Check Reset Source .......................................................................................... 787

22.4 Operation ................................................................................................................................ 788

22.4.1 Reset operation via RESET pin ....................................................................................................788

22.4.2 Reset operation by watchdog timer 2............................................................................................791

22.4.3 Reset operation by low-voltage detector .......................................................................................793

22.4.4 Operation immediately after reset ends ........................................................................................794

22.4.5 Reset function operation ...............................................................................................................796

22.5 Cautions .................................................................................................................................. 797

CHAPTER 23 CLOCK MONITOR ........................................................................................................ 798

23.1 Functions ................................................................................................................................ 798

23.2 Configuration.......................................................................................................................... 798

23.3 Registers ................................................................................................................................. 799

23.4 Operation ................................................................................................................................ 800

CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) ............................................................................. 803

24.1 Functions ................................................................................................................................ 803

24.2 Configuration.......................................................................................................................... 803

24.3 Registers ................................................................................................................................. 804

24.4 Operation ................................................................................................................................ 806

24.4.1 To use for internal reset signal ......................................................................................................806

24.4.2 To use for interrupt........................................................................................................................807

CHAPTER 25 CRC FUNCTION............................................................................................................ 808

25.1 Functions ................................................................................................................................ 808

25.2 Configuration.......................................................................................................................... 808

25.3 Registers ................................................................................................................................. 809

25.4 Operation ................................................................................................................................ 810

25.5 Usage....................................................................................................................................... 811

CHAPTER 26 REGULATOR ................................................................................................................. 813

26.1 Outline ..................................................................................................................................... 813

26.2 Operation ................................................................................................................................ 815

CHAPTER 27 OPTION BYTE............................................................................................................... 816

27.1 Program Example................................................................................................................... 817

CHAPTER 28 FLASH MEMORY.......................................................................................................... 818

28.1 Features .................................................................................................................................. 818

28.2 Memory Configuration........................................................................................................... 819

Page 16

28.3 Functional Outline.................................................................................................................. 821

28.4 Rewriting by Dedicated Flash Memory Programmer ......................................................... 824

28.4.1 Programming environment ............................................................................................................824

28.4.2 Communication mode ...................................................................................................................825

28.4.3 Flash memory control ...................................................................................................................827

28.4.4 Selection of communication mode ................................................................................................828

28.4.5 Communication commands...........................................................................................................829

28.4.6 Pin connection in on-board programming .....................................................................................830

28.5 Rewriting by Self Programming............................................................................................ 834

28.5.1 Overview .......................................................................................................................................834

28.5.2 Features........................................................................................................................................835

28.5.3 Standard self programming flow ...................................................................................................836

28.5.4 Flash functions ..............................................................................................................................837

28.5.5 Pin processing ..............................................................................................................................837

28.5.6 Internal resources used.................................................................................................................838

CHAPTER 29 ON-CHIP DEBUG FUNCTION ..................................................................................... 839

29.1 Debugging with DCU ............................................................................................................. 841

29.1.1 Connection circuit example ...........................................................................................................841

29.1.2 Interface signals ............................................................................................................................842

29.1.3 Mask function................................................................................................................................843

29.1.4 Registers.......................................................................................................................................844

29.1.5 Operation ......................................................................................................................................845

29.1.6 Cautions........................................................................................................................................846

29.2 Debugging Without Using DCU ............................................................................................ 847

29.2.1 Circuit connection examples .........................................................................................................847

29.2.2 Mask function................................................................................................................................850

29.2.3 Allocation of user resources ..........................................................................................................851

29.2.4 Cautions........................................................................................................................................858

29.3 ROM Security Function ......................................................................................................... 859

29.3.1 Security ID ....................................................................................................................................859

29.3.2 Setting...........................................................................................................................................860

CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) ........................ 861

30.1 Absolute Maximum Ratings .................................................................................................. 861

30.2 Capacitance ............................................................................................................................ 862

30.3 Operating Conditions ............................................................................................................ 863

30.4 Oscillator Characteristics...................................................................................................... 864

30.4.1 Main clock oscillator characteristics ..............................................................................................864

30.4.2 Subclock oscillator characteristics ................................................................................................865

30.4.3 PLL characteristics........................................................................................................................866

30.4.4 Internal oscillator characteristics ...................................................................................................866

30.5 Regulator Characteristics ..................................................................................................... 866

30.6 DC Characteristics ................................................................................................................. 867

30.6.1 Pin characteristics .........................................................................................................................867

30.6.2 Supply current characteristics .......................................................................................................869

30.6.3 Data retention characteristics (in STOP mode) .............................................................................870

30.7 AC Characteristics ................................................................................................................. 871

30.7.1 Measurement conditions ...............................................................................................................871

30.7.2 Power on/power off/reset timing....................................................................................................872

Page 17

30.8 Peripheral Function Characteristics .................................................................................... 873

30.8.1 Interrupt timing ..............................................................................................................................873

30.8.2 Key return timing ...........................................................................................................................873

30.8.3 Timer timing ..................................................................................................................................873

30.8.4 UART timing..................................................................................................................................874

30.8.5 CSIB timing ...................................................................................................................................874

30.8.6 I2C bus mode.................................................................................................................................876

30.8.7 A/D converter ................................................................................................................................877

30.8.8 LVI circuit characteristics ..............................................................................................................878

30.9 Flash Memory Programming Characteristics ..................................................................... 879

CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) ........................ 881

31.1 Absolute Maximum Ratings .................................................................................................. 881

31.2 Capacitance ............................................................................................................................ 882

31.3 Operating Conditions ............................................................................................................ 883

31.4 Oscillator Characteristics...................................................................................................... 884

31.4.1 Main clock oscillator characteristics ..............................................................................................884

31.4.2 Subclock oscillator characteristics ................................................................................................885

31.4.3 PLL characteristics........................................................................................................................886

31.4.4 Internal oscillator characteristics ...................................................................................................886

31.5 Regulator Characteristics ..................................................................................................... 886

31.6 DC Characteristics ................................................................................................................. 887

31.6.1 Pin characteristics .........................................................................................................................887

31.6.2 Supply current characteristics .......................................................................................................889

31.6.3 Data retention characteristics (in STOP mode) .............................................................................890

31.7 AC Characteristics ................................................................................................................. 891

31.7.1 Measurement conditions ...............................................................................................................891

31.7.2 Power on/power off/reset timing....................................................................................................892

31.8 Peripheral Function Characteristics .................................................................................... 893

31.8.1 Interrupt timing ..............................................................................................................................893

31.8.2 Key return timing ...........................................................................................................................893

31.8.3 Timer timing ..................................................................................................................................893

31.8.4 UART timing..................................................................................................................................894

31.8.5 CSIB timing ...................................................................................................................................894

31.8.6 I2C bus mode.................................................................................................................................896

31.8.7 A/D converter ................................................................................................................................897

31.8.8 D/A converter ................................................................................................................................898

31.8.9 LVI circuit characteristics ..............................................................................................................898

31.9 Flash Memory Programming Characteristics ..................................................................... 899

CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target)....................................... 901

32.1 Absolute Maximum Ratings .................................................................................................. 901

32.2 Capacitance ............................................................................................................................ 902

32.3 Operating Conditions ............................................................................................................ 903

32.4 Oscillator Characteristics...................................................................................................... 904

32.4.1 Main clock oscillator characteristics ..............................................................................................904

32.4.2 Subclock oscillator characteristics ................................................................................................905

32.4.3 PLL characteristics........................................................................................................................906

32.4.4 Internal oscillator characteristics ...................................................................................................906

32.5 Regulator Characteristics ..................................................................................................... 906

Page 18

32.6 DC Characteristics ................................................................................................................. 907

32.6.1 Pin characteristics .........................................................................................................................907

32.6.2 Supply current characteristics .......................................................................................................909

32.6.3 Data retention characteristics (in STOP mode) .............................................................................910

32.7 AC Characteristics ................................................................................................................. 911

32.7.1 Measurement conditions ...............................................................................................................911

32.7.2 Power on/power off/reset timing....................................................................................................912

32.8 Peripheral Function Characteristics .................................................................................... 913

32.8.1 Interrupt timing ..............................................................................................................................913

32.8.2 Key return timing ...........................................................................................................................913

32.8.3 Timer timing ..................................................................................................................................913

32.8.4 UART timing..................................................................................................................................914

32.8.5 CSIB timing ...................................................................................................................................914

32.8.6 I2C bus mode.................................................................................................................................916

32.8.7 A/D converter ................................................................................................................................917

32.8.8 D/A converter ................................................................................................................................918

32.8.9 LVI circuit characteristics ..............................................................................................................918

32.9 Flash Memory Programming Characteristics ..................................................................... 919

APPENDIX A DEVELOPMENT TOOLS............................................................................................... 925

A.1 Software Package .................................................................................................................. 927

A.2 Language Processing Software ........................................................................................... 927

A.3 Control Software .................................................................................................................... 927

A.4 Debugging Tools (Hardware) ................................................................................................ 928

A.4.1 When using IECUBE QB-V850ESJX3L, QB-V850ESSX2............................................................928

A.4.2 When using MINICUBE QB-V850MINIL .......................................................................................931

A.4.3 When using MINICUBE2 QB-MINI2..............................................................................................932

A.5 Debugging Tools (Software) ................................................................................................. 932

A.6 Embedded Software............................................................................................................... 933

A.7 Flash Memory Writing Tools ................................................................................................. 933

APPENDIX B MAJOR DIFFERENCES BETWEEN PRODUCTS....................................................... 934

APPENDIX C REGISTER INDEX ......................................................................................................... 935

APPENDIX D INSTRUCTION SET LIST ............................................................................................. 945

D.1 Conventions............................................................................................................................ 945

D.2 Instruction Set (in Alphabetical Order) ................................................................................ 948

Page 19

Preliminar

Specifications in this document are tetative and subject to change

V850ES/JC3-L, V850ES/JE3-L RENESAS MCU

R01UH0018EJ0001

Rev.0.01

Jul 23, 2010

CHAPTER 1 INTRODUCTION

The V850ES/JC3-L and V850ES/JE3-L are one of the products in the Renesas Electronics V850 single-chip

microcontroller series designed for low-power operation for real-time control applications.

1.1 General

The V850ES/JC3-L and V850ES/JE3-L are 32-bit single-chip microcontrollers that include the V850ES CPU core and

peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a D/A converter.

In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the The V850ES/JC3-L and

V850ES/JE3-L feature multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by

a hardware multiplier, as optimum instructions for digital servo control applications. Moreover, as a real-time control

system, the V850ES/JC3-L and V850ES/JE3-L enable an extremely high cost-performance for applications that require

super low power consumption, such as PC peripheral device, ECR peripheral device, and industrial instrument.

R01UH0018EJ0001 Rev.0.01 Page 19 of 958 Jul 23, 2010

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Preliminary document

Specifications in this document are tentative and subject to change.

V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

Generic Name

Part Number

Internal memory

Memory space 64 MB

General-purpose register

Clock

I/O port I/O: 27 (5 V tolerant/N-ch open-drain output selectable: 17)

Timer

Real-time output port

10-bit A/D converter 5 channels

8-bit D/A converter

Serial interface

DMA controller 4 channels (transfer target: on-chip peripheral I/O, internal RAM)

Interrupt source

Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE/

Reset source RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)

CRC function 16-bit error detection code generated for 8-bit unit data

On-chip debug

Operating power supply voltage 2.2 to 3.6 V @5 MHz, 2.7 to 3.6 V @20 MHz

Operating ambient temperature

Package

Flash memory 16 KB 32 KB 64 KB 128 KB 256 KB

RAM 8 KB 8 KB 8 KB 8 KB 16 KB

Main clock (oscillation frequency)

Subclock (oscillation frequency)

Internal oscillator fR = 220 kHz (TYP.)

Minimum instruction execution time

16-bit TMP 6 channels

16-bit TMQ 1 channel

16-bit TMM 1 channel

Watch timer 1 channel

RTC 1 channel

WDT 1 channel

CSIB 1 channel

UARTA/CSIB

CSIB/I2C bus 1 channel

UARTA/I2C bus 1 channel

UARTA 1 channel

External

Internal 42

Note The figure in parentheses indicates the number of external interrupts that can release STOP mode.

Table 1-1. V850ES/JC3-L Product List (1/2)

V850ES/JC3-L

PD70F3797

32 bits × 32 registers

Ceramic/crystal (in PLL mode: f External clock (in PLL mode: f

Crystal (fXT = 32.768 kHz)

50 ns (main clock (f

low-voltage STOP/low-voltage subclock/low-voltage sub-IDLE mode

MINICUBE

−40 to +85°C 40-pin WQFN (6 × 6 mm)

, MINICUBE2 supported

PD70F3798

X = 2.5 to 5 MHz (multiplied by 4), in clock through mode: fX = 2.5 to 10 MHz)

X = 2.5 to 5 MHz (multiplied by 4), in clock through mode: fX = 2.5 to 5 MHz

XX) = 20 MHz)

4 bits × 1 channel, 2 bits × 1 channel, or 6 bits × 1 channel

PD70F3799

−

Note

6 (6)

PD70F3800

PD70F3838

R01UH0018EJ0001 Rev. 0.01 Page 20 of 958 Jul 23, 2010

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Preliminary document

Specifications in this document are tentative and subject to change.

V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

Generic Name

Part Number

Internal memory

Memory space 64 MB

General-purpose register

Clock

I/O port I/O: 34 (5 V tolerant/N-ch open-drain output selectable: 20)

Timer

Real-time output port

10-bit A/D converter 6 channels

8-bit D/A converter 1 channel

Serial interface

DMA controller 4 channels (transfer target: on-chip peripheral I/O, internal RAM)

Interrupt source

Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE/

Reset source RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)

CRC function 16-bit error detection code generated for 8-bit unit data

On-chip debug MINICUBE, MINICUBE2 suppor ted

Operating power supply voltage 2.2 to 3.6 V @5 MHz, 2.7 to 3.6 V @20 MHz

Operating ambient temperature

Package

Flash memory 16 KB 32 KB 64 KB 128 KB 256 KB

RAM 8 KB 8 KB 8 KB 8 KB 16 KB

Main clock (oscillation frequency)

Subclock (oscillation frequency)

Internal oscillator fR = 220 kHz (TYP.)

Minimum instruction execution time

16-bit TMP 6 channels

16-bit TMQ 1 channel

16-bit TMM 1 channel

Watch timer 1 channel

RTC 1 channel

WDT 1 channel

CSIB 2 channels

UARTA/CSIB 1 channel

CSIB/I2C bus 1 channel

UARTA/I2C bus 2 channels

UARTA

External

Internal 46

Note The figure in parentheses indicates the number of external interrupts that can release STOP mode.

Table 1-1. V850ES/JC3-L Product List (2/2)

V850ES/JC3-L

PD70F3801

32 bits × 32 registers

Ceramic/crystal (in PLL mode: f External clock (in PLL mode: f

Crystal (fXT = 32.768 kHz)

50 ns (main clock (f

low-voltage STOP/low-voltage subclock/low-voltage sub-IDLE mode

−40 to +85°C 48-pin LQFP (7 × 7 mm), 48-pin WQFN (7 × 7 mm)

PD70F3802

X = 2.5 to 5 MHz (multiplied by 4), in clock through mode: fX = 2.5 to 10 MHz)

X = 2.5 to 5 MHz (multiplied by 4), in clock through mode: fX = 2.5 to 5 MHz

XX) = 20 MHz)

4 bits × 1 channel, 2 bits × 1 channel, or 6 bits × 1 channel

PD70F3803

−

Note

6 (6)

PD70F3804

PD70F3839

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Preliminary document

Specifications in this document are tentative and subject to change.

V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

Generic Name

Part Number

Internal memory

Memory space 64 MB

General-purpose register

Clock

I/O port I/O: 50 (5 V tolerant/N-ch open-drain output selectable: 28)

Timer

Real-time output port

10-bit A/D converter 10 channels

8-bit D/A converter 1 channel

Serial interface

DMA controller 4 channels (transfer target: on-chip peripheral I/O, internal RAM)

Interrupt source

Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE/

Reset source RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)

CRC function 16-bit error detection code generated for 8-bit unit data

On-chip debug MINICUBE, MINICUBE2 suppor ted

Operating power supply voltage 2.2 to 3.6 V @5 MHz, 2.7 to 3.6 V @20 MHz

Operating ambient temperature

Package

Flash memory 16 KB 32 KB 64 KB 128 KB 256 KB

RAM 8 KB 8 KB 8 KB 8 KB 16 KB

Main clock (oscillation frequency)

Subclock (oscillation frequency)

Internal oscillator fR = 220 kHz (TYP.)

Minimum instruction execution time

16-bit TMP 6 channels

16-bit TMQ 1 channel

16-bit TMM 1 channel

Watch timer 1 channel

RTC 1 channel

WDT 1 channel

CSIB 3 channels

UARTA/CSIB 1 channel

CSIB/I2C bus 1 channel

UARTA/I2C bus 2 channels

UARTA

External

Internal 48

Note The figure in parentheses indicates the number of external interrupts that can release STOP mode.

Table 1-1. V850ES/JE3-L Product List

V850ES/JE3-L

PD70F3805

32 bits × 32 registers

Ceramic/crystal (in PLL mode: f External clock (in PLL mode: f

Crystal (fXT = 32.768 kHz)

50 ns (main clock (f

low-voltage STOP/low-voltage subclock/low-voltage sub-IDLE mode

−40 to +85°C 64-pin LQFP (10 × 10 mm)

PD70F3806

X = 2.5 to 5 MHz (multiplied by 4), in clock through mode: fX = 2.5 to 10 MHz)

X = 2.5 to 5 MHz (multiplied by 4), in clock through mode: fX = 2.5 to 5 MHz)

XX) = 20 MHz)

4 bits × 1 channel, 2 bits × 1 channel, or 6 bits × 1 channel

PD70F3807

−

Note

9 (9)

PD70F3808

PD70F3840

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Preliminary document

Specifications in this document are tentative and subject to change.

V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

1.2 Features

{ Minimum instruction execution time: 50 ns (operating on main clock (f

200 ns (operating on main clock (f

30.5 μ s (operating on subclock (fXT) of 32.768 kHz)

{ General-purpose registers: 32 bits × 32 registers { CPU features: Signed multiplication (16 × 16 → 32): 1 to 2 clocks

Signed multiplication (32 × 32 → 64): 1 to 5 clocks

Saturated operations (overflow and underflow detection functions included)

Most instructions can be executed in 1 clock cycle by using 32-bit RISC-based 5-stage

pipeline architecture

Instruction fetching from internal ROM and accessing internal RAM for data can be

executed separately, by using Harvard architecture

High code efficiency achieved by using variable length instructions

32-bit shift instruction: 1 clock cycle

Bit manipulation instructions

Load/store instructions with long/short format

{ Memory space: 64 MB of linear address space (for programs and data)

• Internal memory: RAM: 8/16 KB (see Tables 1-1 and 1-2)

Flash memory: 16/32/64/128/256 KB (see Tables 1-1 and 1-2)

{ Interrupts and exceptions:

Internal external:

V850ES/JC3-L

( 40-pin )

V850ES/JC3-L

( 48-pin )

V850ES/JE3-L

PD70F3797

PD70F3798

PD70F3799

PD70F3800

PD70F3838

PD70F3801

PD70F3802

PD70F3803

PD70F3804

PD70F3839

PD70F3805

PD70F3806

PD70F3807

PD70F3808

PD70F3840

maskable Non-

maskable

1 42 43 1 5 6

1 46 47 1 5 6

1 48 49 1 8 9

total maskable Non-

XX) of 20 MHz: VDD = 2.7 to 3.6 V)

XX) of 5 MHz: VDD = 2.2 to 3.6 V)

total

maskable

Software exceptions: 32 sources

Exception trap: 2 sources

{ Ports: I/O ports: 27/34/50 (see Tables 1-1 and 1-2)

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

{ Timer function: 16-bit interval timer M (TMM): 1 channel

16-bit timer/event counter P (TMP): 6 channels

Note

16-bit timer/event counter Q (TMQ): 1 channel

Watch timer: 1 channel

Watchdog timer: 1 channel

Note The available functions differ for each product. For details, see CHAPTER 6

16-BIT TIMER/EVENT COUNTER P (TMP).

{ Real-time counter: 1 channel { Real-time output port: 6 bits × 1 channel

{ Serial interface: For details about the number of incorporated channels, see Tables 1-1 and 1-2.

Asynchronous serial interface A (UARTA)

Clocked serial interface B (CSIB)

C bus interface (I2C)

{ A/D converter: 10-bit resolution: 5/6/10 channels (see Tables 1-1 and 1-2)

{ D/A converter: 8-bit resolution: 0/1 channels (see Tables 1-1 and 1-2)

{ DMA controller: 4 channels

{ DCU (debug control unit): JTAG interface

{ Clock generator: During main clock or subclock operation

7-level CPU clock (f

XX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)

Clock-through mode/PLL mode selectable

{ Internal oscillator clock: 220 kHz (TYP.)

{ Power-save functions: HALT/IDLE1/IDLE2/STOP/low-voltage STOP/subclock/sub-IDLE/

low-voltage subclock/low-voltage sub-IDLE mode

{ Package: V850ES/JC3-L

40-pin plastic WQFN (6 × 6)

48-pin plastic LQFP (fine pitch) (7 × 7) 48-pin plastic WQFN (7 × 7)

V850ES/JE3-L 64-pin plastic LQFP (fine pitch) (8 × 8)

{ Power supply voltage: V

DD = 2.2 V to 3.6 V (5 MHz)

DD = 2.7 V to 3.6 V (20 MHz)

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

1.3 Application Fields

Digital cameras, electrical power meters, mobile terminals, digital home electronics, other consumer devices

1.4 Ordering Information

1.4.1 V850ES/JC3-L

Part Number Package Internal Flash Memory

PD70F3797K8-4B4-AX

PD70F3798K8-4B4-AX

PD70F3799K8-4B4-AX

PD70F3800K8-4B4-AX

PD70F3838K8-4B4-AX

PD70F3801GA-GAM-AX

PD70F3802GA-GAM-AX

PD70F3803GA-GAM-AX

PD70F3804GA-GAM-AX

PD70F3839GA-GAM-AX

PD70F3801K8-5B4-AX

PD70F3802K8-5B4-AX

PD70F3803K8-5B4-AX

PD70F3804K8-5B4-AX

PD70F3839K8-5B4-AX

Remark The V850ES/JC3-L is a lead-free product.

1.4.2 V850ES/JE3-L

Part Number Package Internal Flash Memory

PD70F3805GB-GAH-AX

PD70F3806GB-GAH-AX

PD70F3807GB-GAH-AX

PD70F3808GB-GAH-AX

PD70F3840GB-GAH-AX

Remark The V850ES/JE3-L is a lead-free product.

40-pin plastic WQFN (6 × 6) 40-pin plastic WQFN (6 × 6) 40-pin plastic WQFN (6 × 6) 40-pin plastic WQFN (6 × 6) 40-pin plastic WQFN (6 × 6) 48-pin plastic LQFP (fine pitch) (7 × 7) 48-pin plastic LQFP (fine pitch) (7 × 7) 48-pin plastic LQFP (fine pitch) (7 × 7) 48-pin plastic LQFP (fine pitch) (7 × 7) 48-pin plastic LQFP (fine pitch) (7 × 7) 48-pin plastic WQFN (7 × 7) 48-pin plastic WQFN (7 × 7) 48-pin plastic WQFN (7 × 7) 48-pin plastic WQFN (7 × 7) 48-pin plastic WQFN (7 × 7)

64-pin plastic LQFP (fine pitch) (10 × 10) 64-pin plastic LQFP (fine pitch) (10 × 10) 64-pin plastic LQFP (fine pitch) (10 × 10) 64-pin plastic LQFP (fine pitch) (10 × 10) 64-pin plastic LQFP (fine pitch) (10 × 10)

16 KB

32 KB

64 KB

128 KB

256 KB

16 KB

32 KB

64 KB

128 KB

256 KB

16 KB

32 KB

64 KB

128 KB

256 KB

16 KB

32 KB

64 KB

128 KB

256 KB

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

1.5 Pin Configuration (Top View)

• V850ES/JC3-L 40-pin plastic WQFN (6 × 6)

PD70F3797K8-4B4-AX

PD70F3800K8-4B4-AX

PD70F3798K8-4B4-AX

PD70F3838K8-4B4-AX

P915/INTP6/TIP50/TOP50

PCM0

P74/ANI4

P73/ANI3

P72/ANI2

P71/ANI1

P70/ANI0

P914/INTP5/TIP51/TOP51

PD70F3799K8-4B4-AX

PDL5/FLMD1

P97/TIP20/TOP20

AVREF0

REGC

RESET

AVSS

VDD

Note2

VSS

XT1

XT2

P02/NMI

P96/TIP21/TOP21

exposed die pad

P42/SCKB0

P40/SIB0/SDA01

P41/SOB0/SCL01

P31/RXDA0/INTP7

P30/TXDA0

Note1

FLMD0

P05/INTP2/DRST

P55/SCKB2/KR5/RTP05/DMS

P54/SOB2/KR4/RTP04/DCK

P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO

P52/TIQ03/KR2/TOQ03/RTP02/DDI

P51/TIQ02/KR1/TOQ02/RTP01

P50/TIQ01/KR0/TOQ01/RTP00

P90/KR6/TXDA1/SDA02

P91/KR7/RXDA1/SCL02

P03/INTP0/ADTRG/RTC1HZ

Notes 1. The FLMD0 pin is used in flash programming. Connect this pin to VSS in the normal operation mode.

2. Connect the REGC pin to V

SS via a 4.7

F (recommended value) capacitor.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

• V850ES/JC3-L 48-pin plastic WQFN (7 × 7)

PD70F3801K8-5B4-AX

PD70F3804K8-5B4-AX

P70/ANI0

PD70F3802K8-5B4-AX

PD70F3839K8-5B4-AX

P914/INTP5/TIP51/TOP51

P915/INTP6/TIP50/TOP50

PCM0

P75/ANI5

P74/ANI4

P73/ANI3

P72/ANI2

P71/ANI1

PD70F3803K8-5B4-AX

PDL5/FLMD1

P97/SIB1/TIP20/TOP20

P98/SOB1

REF0

P10/ANO0

REF1

Note2

REGC

RESET

XT1

XT2

P02/NMI

P96/TIP21/TOP21

P03/INTP0/ADTRG/RTC1HZ

P38/TXDA2/SDA00

exposed die pad

P40/SIB0/SDA01

P39/RXDA2/SCL00

P42/SCKB0

P41/SOB0/SCL01

P90/KR6/TXDA1/SDA02

Notes 1. The FLMD0 pin is used in flash programming. Connect this pin to V

2. Connect the REGC pin to V

SS via a 4.7

F (recommended value) capacitor.

P91/KR7/RXDA1/SCL02

P99/SCKB1

P32/ASCKA0/SCKB4/TIP00/TOP00

P31/RXDA0/INTP7/SIB4

P30/TXDA0/SOB4

Note1

FLMD0

P05/INTP2/DRST

P55/SCKB2/KR5/RTP05/DMS

P54/SOB2/KR4/RTP04/DCK

P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO

P52/TIQ03/KR2/TOQ03/RTP02/DDI

P51/TIQ02/KR1/TOQ02/RTP01

P50/TIQ01/KR0/TOQ01/RTP00

SS in the normal operation mode.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

• V850ES/JC3-L 48-pin plastic LQFP (fine pitch) (7 × 7)

PD70F3801GA-GAM-AX

PD70F3804GA-GAM-AX

P71/ANI1

P70/ANI0

PD70F3802GA-GAM-AX

PD70F3839GA-GAM-AX

P914/INTP5/TIP51/TOP51

P915/INTP6/TIP50/TOP50

PCM0

P79/ANI9

P78/ANI8

P77/ANI7

P76/ANI6

P75/ANI5

P74/ANI4

P73/ANI3

P72/ANI2

PD70F3803GA-GAM-AX

PDL5/FLMD1

P97/SIB1/TIP20/TOP20

P98/SOB1

REF0

P10/ANO0

REF1

Note2

REGC

RESET

XT1

XT2

P913/INTP4

P912/SCKB3

P911/SOB3

P910/SIB3

646362616059585756555453525150

171819202122232425262728293031

P02/NMI

P04/INTP1/RTCDIV/RTCCL

P03/INTP0/ADTRG/RTC1HZ

P06/INTP3

P96/TIP21/TOP21

P94/TIP31/TOP31

P35/TIP11/TOP11

P38/TXDA2/SDA00

P40/SIB0/SDA01

P41/SOB0/SCL01

P39/RXDA2/SCL00

P42/SCKB0

P90/KR6/TXDA1/SDA02

P91/KR7/RXDA1/SCL02

Notes 1. The FLMD0 pin is used in flash programming. Connect this pin to V

2. Connect the REGC pin to VSS via a 4.7 μF (recommended value) capacitor.

P99/SCKB1

P32/ASCKA0/SCKB4/TIP00/TOP00

P31/RXDA0/INTP7/SIB4

P30/TXDA0/SOB4

P34/TIP10/TOP10

P33/TIP01/TOP01

Note1

FLMD0

P05/INTP2/DRST

P55/SCKB2/KR5/RTP05/DMS

P54/SOB2/KR4/RTP04/DCK

P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO

P52/TIQ03/KR2/TOQ03/RTP02/DDI

P51/TIQ02/KR1/TOQ02/RTP01

P50/TIQ01/KR0/TOQ01/RTP00

P93/TIP40/TOP40

P92/TIP41/TOP41

SS in the normal operation mode.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

• V850ES/JE3-L 64-pin plastic LQFP (fine pitch) (10 × 10)

PD70F3805GB-GAH-AX

PD70F3808GB-GAH-AX

P71/ANI1

P70/ANI0

PD70F3806GB-GAH-AX

PD70F3840GB-GAH-AX

P914/INTP5/TIP51/TOP51

P915/INTP6/TIP50/TOP50

PCM0

P79/ANI9

P78/ANI8

P77/ANI7

P76/ANI6

P75/ANI5

P74/ANI4

P73/ANI3

P72/ANI2

PD70F3807GB-GAH-AX

PDL5/FLMD1

P97/SIB1/TIP20/TOP20

P98/SOB1

REF0

P10/ANO0

REF1

Note2

REGC

RESET

XT1

XT2

P913/INTP4

P912/SCKB3

P911/SOB3

P910/SIB3

646362616059585756555453525150

171819202122232425262728293031

P02/NMI

P04/INTP1/RTCDIV/RTCCL

P03/INTP0/ADTRG/RTC1HZ

P06/INTP3

P96/TIP21/TOP21

P94/TIP31/TOP31

P35/TIP11/TOP11

P38/TXDA2/SDA00

P40/SIB0/SDA01

P39/RXDA2/SCL00

P41/SOB0/SCL01

P42/SCKB0

P90/KR6/TXDA1/SDA02

P91/KR7/RXDA1/SCL02

P99/SCKB1

P32/ASCKA0/SCKB4/TIP00/TOP00

P31/RXDA0/INTP7/SIB4

P30/TXDA0/SOB4

P34/TIP10/TOP10

P33/TIP01/TOP01

Note1

FLMD0

P05/INTP2/DRST

P55/SCKB2/KR5/RTP05/DMS

P54/SOB2/KR4/RTP04/DCK

P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO

P52/TIQ03/KR2/TOQ03/RTP02/DDI

P51/TIQ02/KR1/TOQ02/RTP01

P50/TIQ01/KR0/TOQ01/RTP00

P93/TIP40/TOP40

P92/TIP41/TOP41

Notes 1. The FLMD0 pin is used in flash programming. Connect this pin to VSS in the normal operation mode.

2. Connect the REGC pin to V

SS via a 4.7

F (recommended value) capacitor.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

Pin functions

ADTRG:

ANI0 to ANI9:

ANO0:

ASCKA0:

REF0, AVREF1:

AVSS:

DCK:

DDI:

DDO:

DMS:

DRST:

DD:

SS:

FLMD0, FLMD1:

INTP0 to INTP7:

KR0 to KR7:

NMI:

P02 to P06:

P10:

P30 to P35,

P38, P39:

P40 to P42:

P50 to P55:

P70 to P79:

P90 to P94,

P96 to P915:

PCM0:

PDL15:

REGC:

A/D trigger input

Analog input

Analog output

Asynchronous serial clock

Analog reference voltage

Analog V

Debug clock

Debug data input

Debug data output

Debug mode select

Debug reset

Power supply for external pin

Ground for external pin

Flash programming mode

External interrupt input

Key return

Non-maskable interrupt request

Port 0

Port 1

Port 3

Port 4

Port 5

Port 7

Port 9

Port CM

Port DL

Regulator control

RESET:

RTC1HZ,

RTCCL, RTCDIV

RTP00 to RTP05:

RXDA0 to RXDA2:

SCKB0 to SCKB4:

SCL00 to SCL02:

SDA00 to SDA02:

SIB0 to SIB4:

SOB0 to SOB4:

TIP00, TIP01,

TIP10, TIP11,

TIP20, TIP21,

TIP31,

TIP40, TIP41,

TIP50, TIP51,

TIQ00 to TIQ03:

TOP00, TOP01,

TOP10, TOP11,

TOP20, TOP21,

TOP31,

TOP40, TOP41,

TOP50, TOP51,

TOQ00 to TOQ03:

TXDA0 to TXDA2:

DD:

VSS:

X1, X2:

XT1, XT2:

Reset

Real-time Counter Clock Output

Real-time output port

Receive data

Serial clock

Serial data

Serial input

Serial output

Timer input

Timer output

Transmit data

Power supply

Ground

Crystal for main clock

Crystal for subclock

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

1.6 Function Block Configuration

1.6.1 Internal block diagram

(1) V850ES/JC3-L (40-pin)

Timer/counter function

TOP20, TOP50,

TOP21, TOP51

TIQ00 to TIQ03

TOQ00 to TOQ03

TIP20, TIP50, TIP21, TIP51

16-bit timer/

event counter P:

6 ch

16-bit timer/

event counter Q:

1 ch

ROM

Note1

CPU

Multiplier

16 × 16 → 32

RAM

Note2

32-bit barrel

shifter

DMA

RTC1HZ

RTP00 to RTP05 RTO : 1 ch

Serial interface function

SOB0, SOB2

SIB0, SIB2

SCKB0,SCKB2

SDA00, SDA02

SCL00, SCL02

TXDA0, TXDA2

RXDA0, RXDA2

16-bit interval

timer M:

1 ch

Watchdog

timer 2: 1ch

Watch timer:

1ch

Real-time

counter:

1 ch

CSIB : 2 ch

2 ch

UARTA

2ch

CRC

ALU

General-purpose

registers 32 bits × 32

Ports

PDL5

PCM0

P70 to P74

P50 to P55

P40 to P42

P90,P91,P96, P97,P914,P915

Interrupt function

INTC

Key interrupt

function

INTP0, INTP2, INTP5 to INTP7

KR0 to KR7

System

registers

P30, P31

P02, P03, P05

NMI

BCU

A/D

converter

REF0

ADTRG

ANI0 to ANI4

Flash

controller

PLL

Internal

oscillator

CLM

LVI

Regulator

CLKOUT X1 X2 XT1 XT2 RESET

FLMD0

FLMD1

REGC

Debug function

DRST

DMS

DCU

DDI

DCK

DDO

Notes1.

R01UH0018EJ0001 Rev. 0.01 Page 31 of 958 Jul 23, 2010

PD70F3797: 16 KB, μPD70F3798: 32 KB, μPD70F3799: 64 KB, μPD70F3800: 128 KB,

PD70F3838: 256 KB

PD70F3797, 70F3798, 70F3799, 70F3800: 8 KB,

PD70F3838: 16 KB

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

(2) V850ES/JC3-L (48-pin)

Timer/counter function

TIP00, TIP20, TIP50,

TIP21, TIP51

TOP00, TOP20, TOP50,

TOP21, TOP51

TIQ00 to TIQ03

TOQ00 to TOQ03

16-bit timer/

event counter P:

6 ch

16-bit timer/

event counter Q:

1 ch

ROM

Note1

CPU

Multiplier

16 × 16 → 32

RAM

Note2

32-bit barrel

shifter

DMA

RTC1HZ

RTP00 to RTP05 RTO : 1 ch

Serial interface function

SOB0 to SOB2,SOB4

SIB0 to SIB2,SIB4

SCKB0 to SCKB2,SCKB4

SDA00 to SDA02

SCL00 to SCL02

TXDA0 to TXDA2

RXDA0 to RXDA2

ASCKA0

16-bit interval

timer M:

1 ch

Watchdog

timer 2: 1ch

Watch timer:

1ch

Real-time

counter:

1 ch

CSIB : 4 ch

3 ch

UARTA

3ch

CRC

System

ALU

Ports

PDL5

PCM0

P70 to P75

P90,P91,P96 to P99,P914,P915

registers

General-purpose

registers 32 bits × 32

P50 to P55

P40 to P42

P30 to P32

P10

Interrupt function

INTC

Key interrupt

function

NMI

INTP0, INTP2, INTP5 to INTP7

KR0 to KR7

D/A

converter

REF1

ANO0

P02, P03, P05

BCU

A/D

converter

REF0

ADTRG

ANI0 to ANI5

Flash

controller

PLL

Internal

oscillator

CLM

LVI

Regulator

CLKOUT X1 X2 XT1 XT2 RESET

FLMD0

FLMD1

REGC

Debug function

DRST

DMS

DCU

DDI

DCK

DDO

Notes1.

PD70F3801: 16 KB, μPD70F3802: 32 KB, μPD70F3803: 64 KB, μPD70F3804: 128 KB,

PD70F3839: 256 KB

2. μPD70F3801, 70F3802, 70F3803, 70F3804: 8 KB,

PD70F3839: 16 KB

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

(3) V850ES/JE3-L

Timer/counter function

TIP00 to TIP20, TIP40, TIP50,

TOP00 to TOP20, TOP40, TOP50,

TIP00 to TIP51

TOP00 to TOP51

TIQ00 to TIQ03

TOQ00 to TOQ03

16-bit timer/

event counter P:

6 ch

16-bit timer/

event counter Q:

1 ch

ROM

Note1

CPU

Multiplier

16 × 16 → 32

RAM

Note2

32-bit barrel

shifter

DMA

RTC1HZ RTCCL RTCDIV

RTP00 to RTP05 RTO : 1 ch

Serial interface function

SOB0 to SOB4

SIB0 to SIB4

SCKB0 to SCKB4

SDA00 to SDA02

SCL00 to SCL02

TXDA0 to TXDA2

RXDA0 to RXDA2

ASCKA0

16-bit interval

timer M:

1 ch

Watchdog

timer 2: 1ch

Watch timer:

1ch

Real-time

counter:

1 ch

CSIB : 5 ch

3 ch

UARTA

3ch

CRC

ALU

Ports

PDL5

PCM0

P70 to P79

P50 to P55

P90 to P94, P96 to P915

Interrupt function

INTC

Key interrupt

function

System

registers

General-purpose

registers 32 bits × 32

D/A

converter

P10

P40 to P42

P30 to P35, P38, P39

NMI

INTP0 to INTP7

KR0 to KR7

ANO0

P02 to P06

REF1

BCU

A/D

converter

REF0

ADTRG

ANI0 to ANI9

Flash

controller

PLL

Internal

oscillator

CLM

LVI

Regulator

CLKOUT X1 X2 XT1 XT2 RESET

FLMD0

FLMD1

REGC

Debug function

DRST

DMS

DCU

DDI

DCK

DDO

Notes1. μPD70F3805: 16 KB, μPD70F3806: 32 KB, μPD70F3807: 64 KB, μPD70F3808: 128 KB,

PD70F3840: 256 KB

PD70F3805, 70F3806, 70F3807, 70F3808: 8 KB,

PD70F3840: 16 KB

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

1.6.2 Internal units

(1) CPU

The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic

operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits)

contribute to faster complex processing.

(2) Bus control unit (BCU)

The BCU controls the internal bus.

(3) Flash memory (ROM)

This is a 256/128/64/32/16 KB flash memory mapped to addresses 0000000H to 003FFFFH/0000000H to

001FFFFH/0000000H to 000FFFFH/0000000H-0007FFFH/0000000H-0003FFFH.

It can be accessed from the CPU in one clock during instruction fetch.

(4) RAM

This is a 16/8 KB RAM mapped to addresses 3FFB000H to 3FFEFFFH/3FFD000H to 3FFEFFFH. It can be

accessed from the CPU in one clock during data access.

(5) Interrupt controller (INTC)

This controller handles hardware interrupt requests (NMI, INTP0 to INTP7) from on-chip peripheral hardware and

external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed

interrupt servicing control can be performed.

(6) Clock generator (CG)

A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (f

and subclock frequency (f

XT), respectively. There are two modes: In the clock-through mode, fX is used as the main

clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 4.

The CPU clock frequency (f

CPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT.

(7) Internal oscillator

An internal oscillator is provided on chip. The oscillation frequency is 220 kHz (TYP). The internal oscillator

supplies the clock for watchdog timer 2 and timer M.

(8) Timer/counter

Six-channel 16-bit timer/event counter P (TMP), one-channel 16-bit timer/event counter Q (TMQ), and one-channel

16-bit interval timer M (TMM), are provided on chip.

(9) Watch timer

This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz subclock or the 32.768

kHz f

BRG clock from the prescaler). The watch timer can also be used as an interval timer based on the main clock.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

(10) Real-time counter (for watch)

The real-time counter counts the reference time (one second) for watch counting based on the subclock (32.768

kHz) or main clock. This can simultaneously be used as the interval timer based on the main clock. Hardware

counters dedicated to year, month, day of week, day, hour, minute, and second are provided, and can count up to

99 years.

(11) Watchdog timer 2

A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc.

The internal oscillator clock, the main clock, or the subclock can be selected as the source clock.

Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal

(WDT2RES) after an overflow occurs.

(12) Serial interface

The V850ES/JC3-L, V850ES/JE3-L include three kinds of serial interfaces: asynchronous serial interface A

(UARTA), 3-wire variable-length serial interface B (CSIB), and an I

(13) A/D converter

This 10-bit A/D converter includes 10/6/5 analog input pins. Conversion is performed using the successive

approximation method.

(14) D/A converter

A 1/0-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip.

(15) DMA controller

A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and on-

chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.

(16) Key interrupts function

A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8

channels).

(17) Real-time output function

The real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer compare

(18) CRC function

A CRC operation circuit that generates a 16-bit CRC (Cyclic Redundancy Check) code upon the setting of 8-bit

data is provided on-chip.

C bus interface (I2C).

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION

(19) DCU (debug control unit)

An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is provided.

Switching between the normal port function and on-chip debugging function is done with the control pin input

level and the OCDM register.

(20) Ports

The following general-purpose port functions and control pin functions are available.

Table 1-2. Port Functions (V850ES/JC3-L (40-pin))

Port I/O Alternate Function

P0 3-bit I/O NMI, external interrupt, A/D converter trigger, debug reset, real-time counter output

P3 2-bit I/O External interrupt, serial interface

P4 3-bit I/O Serial interface

P5 6-bit I/O Timer I/O, real-time output, key interrupt input, serial interface, debug I/O

P7 5-bit I/O A/D converter analog input

P9 6-bit I/O Serial interface, key interrupt input, timer I/O, external interrupt

PCM 1-bit I/O

PDL 1-bit I/O

−

Table 1-3. Port Functions (V850ES/JC3-L (48-pin))

Port I/O Alternate Function

P0 3-bit I/O NMI, external interrupt, A/D converter trigger, debug reset, real-time counter output

P1 1-bit I/O D/A converter analog output

P3 5-bit I/O External interrupt, serial interface, timer I/O

P4 3-bit I/O Serial interface

P5 6-bit I/O Timer I/O, real-time output, key interrupt input, serial interface, debug I/O

P7 6-bit I/O A/D converter analog input

P9 8-bit I/O Serial interface, key interrupt input, timer I/O, external interrupt

PCM 1-bit I/O

PDL 1-bit I/O

−

Table 1-4. Port Functions (V850ES/JE3-L)

Port I/O Alternate Function

P0 5-bit I/O NMI, external interrupt, A/D converter trigger, debug reset, real-time counter output

P1 1-bit I/O D/A converter analog output

P3 8-bit I/O External interrupt, serial interface, timer I/O

P4 3-bit I/O Serial interface

P5 6-bit I/O Timer I/O, real-time output, key interrupt input, serial interface, debug I/O

P7 10-bit I/O A/D converter analog input

P9 15-bit I/O Serial interface, key interrupt input, timer I/O, external interrupt

PCM 1-bit I/O

PDL 1-bit I/O

−

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION

CHAPTER 2 PIN FUNCTIONS

2.1 List of Pin Functions

The functions of the pins in the V850ES/JC3-L, V850ES/JE3-L are described below.

There are 2 or 3 types of pin I/O buffer power supplies: AV

power supplies and the pins is described below.

Table 2-1. Pin I/O Buffer Power Supplies (V850ES/JC3-L : 40-pin products)

Power Supply Corresponding Pins

AVREF0 Port 7

EVDD RESET, ports 0, 3 to 5, 9, CM, DL, FLMD0

Table 2-2. Pin I/O Buffer Power Supplies (V850ES/JC3-L : 48-pin products)

REF0, AVREF1, and EVDD. The relationship between these

Power Supply Corresponding Pins

AVREF0 Port 7

AVREF1 Port 1

EVDD RESET, ports 0, 3 to 5, 9, CM, DL, FLMD0

Table 2-3. Pin I/O Buffer Power Supplies (V850ES/JE3-L : 64-pin products)

Power Supply Corresponding Pins

AVREF0 Port 7

AVREF1 Port 1

EVDD RESET, ports 0, 3 to 5, 9, CM, DL, FLMD0

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION

(1) Port functions

(1/2)

Pin No. Function

JC3L

(40)

(48)

P02 11 13 17 NMI

P03 12 14 18 INTP0/ADTRG/RTC1HZ

P04

Note

P05

P06

P10

P30

P31

P32

P33

P34

P35

P38

P39

P40

P41

P42

P50

P51

P52

P53

P54

P55 26 30

− −

27 31 41 INTP2/DRST

− −

3 3

−

33 45

−

− −

34 46

−

− −

35 47

−

− −

18 26 TXDA2/SDA00

−

19 27

−

16 20 28 SIB0/SDA01

17 21 29 SOB0/SCL01

18 22 30

21 25 35 TIQ01/KR0/TOQ01/RTP00

22 26 36 TIQ02/KR1/TOQ02/RTP01

23 27 37 TIQ03/KR2/TOQ03/RTP02/DDI

24 28 38

25 29 39 SOB2/KR4/RTP04/DCK

Note Incorporates a pull-down resistor. It can be disconnected by clearing the OCDM.OCDM0 bit to 0.

Remark JC3L (40): V850ES/JC3-L (40-pin products)

JC3L (48): V850ES/JC3-L (48-pin products)

JE3L: V850ES/JE3-L

I/O Description Alternate Function

JE3L

Port 0 (refer to 4.3.1)

I/O

5-bit I/O port

19 INTP1/RTCDIV/RTCCL

I/O

43 TIP01/TOP01

I/O

Input/output can be specified in 1-bit units.

N-ch open-drain output can be specified in 1-bit units.

5 V tolerant.

Port 1 (refer to 4.3.2)

1-bit I/O port (V850ES/JC3-L: 48-pin, V850ES/JE3-L

only).

Input/output can be specified in 1-bit units.

Port 3 (refer to 4.3.3)

2-bit I/O port (V850ES/JC3-L : 40-pin)

5-bit I/O port (V850ES/JC3-L : 48-pin)

8-bit I/O port (V850ES/JE3-L)

Input/output can be specified in 1-bit units.

N-ch open-drain output can be specified in 1-bit units.

5 V tolerant.

Port 4 (refer to 4.3.4)

3-bit I/O port

Input/output can be specified in 1-bit units.

N-ch open-drain output can be specified in 1-bit units.

5 V tolerant.

Port 5 (refer to 4.3.5)

6-bit I/O port

Input/output can be specified in 1-bit units.

N-ch open-drain output can be specified in 1-bit units.

5 V tolerant.

INTP3

ANO0

TXDA0/SOB4

TXDA0

RXDA0/INTP7/SIB4

RXDA0/INTP7

ASCKA0/SCKB4/TIP00/TOP00

TIP10/TOP10

TIP11/TOP11

RXDA2/SCL00

SCKB0

SIB2/KR3/TIQ00/TOQ00/RTP03/DDO

SCKB2/KR5/RTP05/DMS

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION

Pin No. Function

JC3L

(40)

(48)

P70

P71 39 47 63 ANI1

P72 38 46 62 ANI2

P73 37 45 61 ANI3

P74 36 44 60 ANI4

P75

P76

P77

P78

P79

P90 19 23 31 KR6/TXDA1/SDA02

P91 20 24 32 KR7/RXDA1/SCL02

P92

P93

P94

P96 13 15 22 TXDC0/TIP21/TOP21

P97

P98

P99

P910

P911

P912

P913

P914 33 40 52 INTP5/TIP51/TOP51

P915 34 41 53

PCM0 35 42 54 I/O

PDL5 31 37 49 I/O

40 48 64

43 59 ANI5

−

− −

38 50 SIB1/TIP20/TOP20

−

− −

39 51 SOB1

−

36 48 SCKB1

−

− −

I/O Description Alternate Function

JE3L

Port 7 (refer to 4.3.6)

I/O

5-bit I/O port (V850ES/JC3-L : 40-pin)

6-bit I/O port (V850ES/JC3-L : 48-pin)

10-bit I/O port (V850ES/JE3-L)

Input/output can be specified in 1-bit units.

58 ANI6

57 ANI7

56 ANI8

Port 9 (refer to 4.3.7)

I/O

6-bit I/O port (V850ES/JC3-L : 40-pin)

33 TIP41/TOP41/TXDA4

34 TIP40/TOP40/RXDA4

21 TIP31/TOP31/TXDA5

16 SIB3

15 SOB3

14 SCKB3

13 INTP4

8-bit I/O port (V850ES/JC3-L : 48-pin)

15-bit I/O port (V850ES/JE3-L)

Input/output can be specified in 1-bit units.

N-ch open-drain output can be specified in 1-bit

units.

5 V tolerant.(P90 to P96)

Port CM (refer to 4.3.8)

1-bit I/O port

Input/output can be specified in 1-bit units.

Port DL (refer to 4.3.9)

1-bit I/O port

Input/output can be specified in 1-bit units.

ANI0

ANI9

TIP20/TOP20

INTP6/TIP50/TOP50

FLMD1

−

(2/2)

Remark JC3L (40): V850ES/JC3-L (40-pin products)

JC3L (48): V850ES/JC3-L (48-pin products)

JE3L: V850ES/JE3-L

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION

(2) Non-port functions

(1/5)

SS)

Description

P79

P53/SIB2/KR3/TIQ00/TOQ00/ RTP03

P05/INTP2

SS)

PDL5

Alternate Function

−

Function

ADTRG 12 14 18 Input A/D converter external trigger input. 5 V tolerant. P03/INTP0/RTC1HZ

ANI0 40 48 64 P70

ANI1 39 47 63 P71

ANI2 38 46 62 P72

ANI3 37 45 61 P73

ANI4 36 44 60 P74

ANI5

ANI6

ANI7

ANI8

ANI9

ANO0

ASCKA0

AVREF0 1 1 1 Reference voltage input for A/D converter/positive

AVREF1

AVSS

DCK 25 29 39 Input Debug clock input. 5 V tolerant. P54/SOB2/KR4/RTP04

DDI 23 27 37 Input Debug data input. 5 V tolerant. P52/TIQ03/KR2/TOQ03/RTP02

Note

DDO

24 28 38 Output Debug data output.

DMS 26 30 40 Input Debug mode select input. 5 V tolerant. P55/SCKB2/KR5/RTP05

DRST

EVDD 14 16

EVSS 15 17

FLMD0 28 32 42

FLMD1 31 37 49

Pin No.

JC3L

JE3L

(40)

(48)

43 59 P75

−

− −

3 3 Output Analog voltage output for D/A converter P10

−

35 47 Input UARTA0 baud rate clock input. 5 V tolerant. P32/SCKB4/TIP00/TOP00

−

4 4

−

2 2

27 31

I/O

Input Analog voltage input for A/D converter

58 P76

57 P77

56 P78

−

power supply for port 7

Reference voltage input for D/A converter/positive power supply for port 1

Ground potential for A/D and D/A converters (same

−

potential as V

N-ch open-drain output selectable. 5 V tolerant.

41 Input Debug reset input. 5 V tolerant.

Input Flash memory programming mode setting pin

Positive power supply for external (same potential as

−

DD)

Ground potential for external (same potential as V

−

Note In the on-chip debug mode, high-level output is forcibly set.

Remark JC3L (40): V850ES/JC3-L (40-pin products)

JC3L (48): V850ES/JC3-L (48-pin products)

JE3L: V850ES/JE3-L

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION

Function

JC3L

(40)

Pin No.

JC3L

(48)

JE3L

INTP0 12 14 18 P03/ADTRG/RTC1HZ

INTP1

− −

INTP2 27 31 41 P05/DRST

INTP3

INTP4

− −

I/O

Input External interrupt request input

19 P04/RTCDIV/RTCCL

(maskable, analog noise elimination). Analog noise elimination or digital noise elimination selectable for INTP3 pin.

20 P06

5 V tolerant.

13 P913

INTP5 33 40 52 P914/TIP51/TOP51

INTP6 34 41 53 P915/TIP50/TOP50

INTP7

−

Note 1

KR0

21 25 35 P50/TIQ01/TOQ01/RTP00

Note 1

KR1

22 26 36 P51/TIQ02/TOQ02/RTP01

Note 1

KR2

23 27 37 P52/TIQ03/TOQ03/RTP02/DDI

Note 1

KR3

24 28 38 P53/SIB2/TIQ00/TOQ00/

Note 1

KR4

25 29 39 P54/SOB2/RTP04/DCK

Note 1

KR5

26 30 40 P55/SCKB2/RTP05/DMS

Note 1

KR6

19 23 31 P90/TXDA1/SDA02

Note 1

KR7

20 24 32

Note 2

NMI

11 13 17 Input External interrupt input (non-maskable, analog

46 P31/RXDA0/SIB4

− −

Input Key interrupt input (on-chip analog noise

eliminator). 5 V tolerant.

noise elimination). 5 V tolerant.

REGC 4 6 6 − Connection of regulator output stabilization

capacitance (4.7

RESET 8 10 10 Input System reset input

RTC1HZ

RTCCL

12 14

− −

18 Output Real-time counter correction clock (1 Hz) output P03/INTP0/ADTRG

19 Output Real-time counter clock (32 kHz primary oscillation)

output

RTCDIV

RTP00 21 25 35 P50/TIQ01/KR0/TOQ01

RTP01 22 26 36 P51/TIQ02/KR1/TOQ02

RTP02 23 27 37 P52/TIQ03/KR2/TOQ03/DDI

− −

19 Output Real-time counter clock (32 kHz division) output P04/INTP1/RTCCL

Output Real-time output port.

N-ch open-drain output selectable. 5 V tolerant.

RTP03 24 28 38 P53/SIB2/KR3/TIQ00/TOQ00/DDO

RTP04 25 29 39 P54/SOB2/KR4/DCK

RTP05 26 30 40

Description

F (recommended value))

Alternate Function

P31/RXDA0

RTP03/DDO

P91/RXDA1/SCL02

P02

−

P04/INTP1/RTCDIV

P55/SCKB2/KR5/DMS

Notes1. Connect a pull-up resistor externally.

2. The NMI pin alternately functions as the P02 pin. It functions as the P02 pin after reset. To enable the NMI

function, set the PMC0.PMC02 bit to 1. The initial setting of the NMI pin is “No edge detected”. Select the NMI pin valid edge using the INTF0 and INTR0 registers.

Remark JC3L (40): V850ES/JC3-L (40-pin products)

JC3L (48): V850ES/JC3-L (48-pin products)

JE3L: V850ES/JE3-L

(2/5)

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION

Function

RXDA0

RXDA1 20 24 32 P91/KR7/SCL02

RXDA2

SCKB0 18 22 30 P42

SCKB1

SCKB2 26 30 40 P55/KR5/RTP05/DMS

SCKB3

SCKB4

SCL00

SCL01 17 21 29 P41/SOB0

SCL02 20 24 32

SDA00

SDA01 16 20 28 P40/SIB0

SDA02 19 23 31

SIB0 16 20 28 P40/SDA01

SIB1

SIB2 24 28 38 P53/KR3/TIQ00/TOQ00/RTP03/DDO

SIB3

SIB4

SOB0 17 21 29 P41/SCL01

SOB1

SOB2 25 29 39 P54/KR4/RTP04/DCK

SOB3

SOB4

JC3L

(40)

−

− −

−

− −

−

− −

−

Pin No.

JC3L

JE3L

(48)

34 46

− −

19 27

36 48 P99

35 47

19 27 P39/RXDA2

18 26 P38/TXDA2

38 50 P97/TIP20/TOP20

34 46

39 51 P98

33 45

I/O

Serial receive data input (UARTA0 to UARTA2)

Input

5 V tolerant.

Serial clock I/O (CSIB0 to CSIB4)

I/O

N-ch open-drain output selectable.

5 V tolerant.

14 P912

Serial clock I/O (I

I/O

N-ch open-drain output selectable.

5 V tolerant.

Serial transmit/receive data I/O (I

I/O

N-ch open-drain output selectable.

5 V tolerant.

Serial receive data input (CSIB0 to CSIB4)

Input

5 V tolerant.

16 P910

Serial transmit data output (CSIB0 to CSIB4)

Output

N-ch open-drain output selectable.

5 V tolerant.

15 P911

Description

C00 to I2C02)

Alternate Function

P31/INTP7/SIB4

P31/INTP7

P39/SCL00

P32/ASCKA0/TIP00/TOP00

P91/KR7/RXDA1

P90/KR6/TXDA1

P31/RXDA0/INTP7

P30/TXDA0

Remark JC3L (40): V850ES/JC3-L (40-pin products)

JC3L (48): V850ES/JC3-L (48-pin products)

JE3L: V850ES/JE3-L

(3/5)

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION

Function

TIP00

TIP01

TIP10

TIP11

TIP20

TIP21 13 15

TIP31

TIP40

TIP41

TIP50 34 41

TIP51 33 40

TIQ00 24 28 38

TIQ01 21 28 38 P50/KR0/TOQ01/RTP00

TIQ02 22 26 36 P51/KR1/TOQ02/RTP01

TIQ03 23 27 37

TOP00

TOP01

TOP10

TOP11

TOP20

TOP21 13 15 22

TOP31

TOP40

TOP41

TOP50 34 41 53 P915/INTP6/TIP50

TOP51 33 40 52

JC3L

Pin No.

JC3L

(40)

(48)

35 47

−

− −

38 50

−

− −

35 47 P32/ASCKA0/SCKB4/TIP00

−

− −

38 50 P97/SIB1/TIP20

−

− −

I/O

JE3L

External event count input/capture trigger input/external

Input

trigger input (TMP0). 5 V tolerant.

43 Capture trigger input (TMP0). 5 V tolerant.

43 Capture trigger input (TMP1). 5 V tolerant.

22 Capture trigger input (TMP2). 5 V tolerant.

21 Capture trigger input (TMP3). 5 V tolerant.

33 Capture trigger input (TMP4). 5 V tolerant.

44 P34/TIP10

34 P93/TIP40

External event count input/capture trigger input/external

trigger input (TMP1). 5 V tolerant.

External event count input/capture trigger input/external

trigger input (TMP2). 5 V tolerant.

External event count input/capture trigger input/external

trigger input (TMP4). 5 V tolerant.

External event count input/capture trigger input/external

trigger input (TMP5). 5 V tolerant.

Capture trigger input (TMP5). 5 V tolerant.

External event count input/capture trigger input/external

Input

trigger input (TMQ0).

5 V tolerant.

Capture trigger input (TMQ0).

5 V tolerant.

Timer output (TMP0)

Output

N-ch open-drain output selectable. 5 V tolerant.

Timer output (TMP1)

N-ch open-drain output selectable. 5 V tolerant.

Timer output (TMP2)

N-ch open-drain output selectable. 5 V tolerant.

Timer output (TMP3)

N-ch open-drain output selectable. 5 V tolerant.

Timer output (TMP4) N-ch open-drain output selectable. 5 V tolerant.

Timer output (TMP5) N-ch open-drain output selectable. 5 V tolerant.

Description

P32/ASCKA0/SCKB4/TOP00

P33/TOP01

P34/TOP10

P35/TOP11

P97/SIB1/TOP20

P97/TOP20

P96/A6/TOP21

P94/A4/TOP31

P93/A3/TOP40

P92/A2/TOP41

P915/A15/INTP6/TOP50

P914/A14/INTP5/TOP51

P53/SIB2/KR3/TOQ00/RTP03

/DDO

P52/KR2/TOQ03/RTP02/DDI

P33/TIP01

P35/TIP11

P97/TIP20

P96/TIP21

P94/TIP31

P92/TIP41

P914/INTP5/TIP51

Alternate Function

Remark JC3L (40): V850ES/JC3-L (40-pin products)

JC3L (48): V850ES/JC3-L (48-pin products)

JE3L: V850ES/JE3-L

(4/5)

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Specifications in this document are tentative and subject to change.

V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION

Function

JC3L

(40)

Pin No.

JC3L

(48)

JE3L

I/O

Description

Alternate Function

(5/5)

TOQ00 24 28 38 P53/SIB2/KR3/TIQ00/RTP03/DDO

TOQ01 21 25 35 P50/TIQ01/KR0/RTP00

TOQ02 22 26 36 P51/TIQ02/KR1/RTP01

TOQ03 23 27 37

TXDA0

TXDA1 19 23 31 P90/KR6/SDA02

TXDA2

VDD 3 5 5 − Positive power supply pin for internal circuits

VSS 5 7 7 − Ground potential for internal circuits

X1 6 8 8 Input

X2 7 9 9

XT1 9 11 11 Input

XT2 10 12 12

33 45 P30/SOB4

−

− −

18 26

−

Output

Timer output (TMQ0)

N-ch open-drain output selectable.

5 V tolerant.

Serial transmit data output (UARTA0 to UARTA5)

N-ch open-drain output selectable.

5 V tolerant.

Connection of resonator for main clock

−

Connection of resonator for subclock

−

P52/TIQ03/KR2/RTP02/DDI

P30

P38/SDA00

−

Remark JC3L (40): V850ES/JC3-L (40-pin products)

JC3L (48): V850ES/JC3-L (48-pin products)

JE3L: V850ES/JE3-L

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION

2.2 Pin States

The operation states of pins in the various modes are described below.

Table 2-2. Pin Operation States in Various Modes

Pin Name

P05/DRST Pulled down Pulled down

P10/ANO0 Hi-Z Held Held Held

P53/DDO

Other port pins Hi-Z Hi-Z Held Held Held

When Power Is

Turned On

Undefined

Note 1

During Reset

(Except When Power

Is Turned On)

Note3

Held Held Held

Note4

Hi-Z

Held Held Held

HALT Mode

Note 2

Sub-IDLE Mode

IDLE1, IDLE2,

Note 2

STOP Mode

Notes 1. Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower limit)

when the power is turned on.

2. Operates while an alternate function is operating. (For details about the operating status of alternate functions,

see CHAPTER 21 STANDBY FUNCTION.)

3 Pulled down during external reset. During internal reset by the watchdog timer, clock monitor, etc., the state of

this pin differs according to the OCDM.OCDM0 bit setting.

4 DDO output is specified in the on-chip debug mode.

Note 2

Remark Hi-Z: High impedance

Held: The state during the level of pins is held.

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2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins

(1/2)

JC3L

(40)

Pin No. Pin Alternate Function

JC3L

(48)

JE3L

I/O Circuit

Type

Recommended Connection of Unused Pin

P02 NMI 11 13 17

P03 INTP0/ADTRG/RTC1HZ 12 14 18

P04 INTP1/RTCDIV/RTCCL

P05 INTP2/DRST 27 31 41 10-N

P06 INTP3

P10 ANO0

TXDA0/SOB4

TXDA0 29

RXDA0/INTP7/SIB4

RXDA0/INTP7 30

P32 ASCKA0/SCKB4/TIP00

P33

P34

P35

P38 TXDA2/SDA00

P39 RXDA2/SCL00

P40 SIB0/SDA01 16 20 28

P41 SOB0/SCL01 17 21 29

P42 SCKB0 18 22 30

P50

P51

P52 TIQ03/KR2/TOQ03/RTP02/DDI 23 27 37

P53

P54 SOB2/KR4/RTP04/DCK

P55 SCKB2/KR5/RTP05/DMS

TIP01/TOP01

TIP10/TOP10

TIP11/TOP11

TIQ01/KR0/TOQ01/RTP00

TIQ02/KR1/TOQ02/RTP01

SIB2/KR3/TIQ00/TOQ00

/RTP03/DDO

− −

−

− −

−

21 25 35

22 26 36

24 28 38

25 29 39

26 30 40

20 10-D

3 3 12-D

33 45P30

− −

34 46P31

− −

35 47

18 26

19 27

Remark JC3L (40): V850ES/JC3-L (40-pin products)

JC3L (48): V850ES/JC3-L (48-pin products)

JE3L: V850ES/JE3-L

10-D

10-G

10-D

Input: Independently connect to EV

via a resistor.

Output: Leave open.

Input: Independently connect to EV

resistor. Fixing to V

Output: Leave open.

Internally pull-down after reset by

RESET pin.

Input: Independently connect to EV

via a resistor.

Output: Leave open.

Input: Independently connect to AV

via a resistor.

Output: Leave open.

Input: Independently connect to EV

via a resistor.

Output: Leave open.

DD level is prohibited.

DD or EVSS

SS via a

DD or EVSS

REF1 or AVSS

DD or EVSS

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION

JC3L

(40)

Pin No. Pin Alternate Function

JC3L

(48)

JE3L

I/O

Circuit

Type

Recommended Connection of Unused Pin

(2/2)

P70 to P74 ANI0 to ANI4 40 to 36 48 to 44 64 to 60

P75 ANI5

P76 to P79 ANI6 to ANI9

P90 KR6/TDXA1/SDA02 19 23 31

P91 KR7/RXDA1/SCL02 20 24 32

P92 TIP41/TOP41/TXDA4

P93 TIP40/TOP40/RXDA4

P94 TIP31/TOP31/TXDA5

P96 TIP21/TOP21 13 15 22

SIB1/TIP20/TOP20

TIP20/TOP20 32

P98 SOB1

P99 SCKB1

P910 SIB3

P911 SOB3

P912 SCKB3

P913 INTP4

P914 INTP5/TIP51/TOP51 33 40 52

P915 INTP6/TIP50/TOP50 34 41 53

PCM0

PDL5 FLMD1 31 37 49

AVREF0

AVREF1

AVSS

EVDD

EVSS

FLMD0

REGC

RESET

VDD

VSS

XT1

XT2

−

− −

−

− −

−

− −

35 42 54

1 1 1

2 2 2

14 16 24

15 17 25

28 32 42

4 6 6

8 10 10 2

3 5 5

5 7 7

6 8 8

7 9 9

9 11 11 16-C Connect to VSS.

10 12 12 16-C Leave open.

43 59

58 to 55

38 50 P97

− −

39 51 10-G

36 48

15 10-G

4 4

Remark JC3L (40): V850ES/JC3-L (40-pin products)

JC3L (48): V850ES/JC3-L (48-pin products)

JE3L: V850ES/JE3-L

11-G

10-D

Input: Independently connect to AV

via a resistor.

Output: Leave open.

Input: Independently connect to EV

via a resistor.

Output: Leave open.

Directly connect to V

−

Directly connect to VSS and always supply power.

−

Directly connect to VDD and always supply power.

−

Directly connect to VSS and always supply power.

−

Directly connect to V

−

flash memory programming mode.

Connection of regulator output stabilization

−

capacitance (4.7 μF (recommended value))

− −

REF0 or AVSS

DD or EVSS

DD and always supply power.

SS in a mode other than the

−

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION

Type 2

Figure 2-1. Pin I/O Circuits

Type 10-N

Schmitt-triggered input with hysteresis characteristics

Type 5

Data

Output

disable

Input

enable

Type 10-D

Data

Open drain

Output disable

Note

P-ch

N-ch

IN/OUT

P-ch

N-ch

IN/OUT

Data

Open drain

Output disable

Input enable

Type 11-G

Data

Output disable

Comparator

(Threshold voltage)

Input enable

Note

OCDM0 bit

+ _

REF0

P-ch

IN/OUT

N-ch

REF0

P-ch

N-ch

P-ch

N-ch

IN/OUT

Type 10-G

Data

Open drain

Output disable

Input enable

P-ch

IN/OUT

N-ch

Type 12-D

Data

Output disable

Input enable

Analog output

Type 16-C

Feedback cut-off

XT1 XT2

voltage

P-ch

N-ch

REF1

P-ch

N-ch

IN/OUT

Note Hysteresis characteristics are not available in port mode.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION

2.4 Cautions

When the power is turned on, the following pins may output an undefined level temporarily even during reset.

• P10/ANO0 pin

• P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

CHAPTER 3 CPU FUNCTION

The CPU of the V850ES/JC3-L and V850ES/JE3-L are based on RISC architecture and executes almost all instructions

in one clock cycle by using a 5-stage pipeline.

3.1 Features

Variable length instructions (16 bits/32 bits)

Minimum instruction execution time: 50 ns (operating on main clock (fXX) of 20 MHz: VDD = 2.7 to 3.6 V)

200 ns (operating on main clock (fXX) of 5 MHz: VDD = 2.2 to 3.6 V)

30.5

Memory space Program space: 64 MB linear

Data space: 4 GB linear

General-purpose registers: 32 bits × 32 registers

Internal 32-bit architecture

5-stage pipeline control

Multiplication/division instruction

Saturation operation instruction

32-bit shift instruction: 1 clock

Load/store instruction with long/short format

Four types of bit manipulation instructions

• SET1

• CLR1

• NOT1

• TST1

s (operating on subclock (fXT) of 32.768 kHz)

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3.2 CPU Register Set

The registers of the V850ES/JC3-L and V850ES/JE3-L can be classified into two types: general-purpose program

registers and dedicated system registers. All the registers are 32 bits wide.

For details, refer to the V850ES Architecture User’s Manual.

(1) Program register set

(2) System register set

31 0 31 0

r10

r11

r12

r13

r14

r15

r16

r17

r18

r19

r20

r21

r22

r23

r24

r25

r26

r27

r28

r29

r30

r31

General-purpose registers

(Zero register)

(Assembler-reserved register)

(Stack pointer (SP))

(Global pointer (GP))

(Text pointer (TP))

(Element pointer (EP))

(Link pointer (LP))

EIPC

EIPSW

FEPC

FEPSW

ECR

PSW

CTPC

CTPSW

DBPC

DBPSW

CTBP

(Interrupt status saving register)

(NMI status saving register)

(Interrupt source register)

(Program status word)

(CALLT execution status saving register)

(Exception/debug trap status saving register)

(CALLT base pointer)

31 0

(Program counter)

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3.2.1 Program register set

The program registers include general-purpose registers and a program counter.

(1) General-purpose registers (r0 to r31)

Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data

variable or an address variable.

However, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used.

r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the SLD and

SST instructions as a base pointer when these instructions access the memory. r1, r3 to r5, and r31 are implicitly

used by the assembler and C compiler. When using these registers, save their contents for protection, and then

restore the contents after using the registers. r2 is sometimes used by the real-time OS. If the real-time OS does

not use r2, it can be used as a register for variables.

Table 3-1. Program Registers

Name Usage Operation

r0 Zero register Always holds 0.

r1 Assembler-reserved register Used as working register to create 32-bit immediate data

r2 Register for address/data variable (if real-time OS does not use r2)

r3 Stack pointer Used to create a stack frame when a function is called

r4 Global pointer Used to access a global variable in the data area

r5 Text pointer Used as register that indicates the beginning of a text area (area

where program codes are located)

r6 to r29 Register for address/data variable

r30 Element pointer Used as base pointer to access memory

r31 Link pointer Used when the compiler calls a function

PC Program counter Holds the instruction address during program execution

Remark For further details on the r1, r3 to r5, and r31 that are used in the assembler and C compiler, refer to the

CA850 (C Compiler Package) Assembly Language User’s Manual.

(2) Program counter (PC)

The program counter holds the instruction address during program execution. The lower 32 bits of this register are

valid. Bits 31 to 26 are fixed to 0. A carry from bit 25 to 26 is ignored even if it occurs.

Bit 0 is fixed to 0. This means that execution cannot branch to an odd address.

31 2625 1 0

Fixed to 0 Instruction address during program execution

Default value

00000000H

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3.2.2 System register set

The system registers control the status of the CPU and hold interrupt information.

These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the

system register numbers listed below.

Table 3-2. System Register Numbers

System Register Name

Number

Note 1

0 Interrupt status saving register (EIPC)

1 Interrupt status saving register (EIPSW)

2 NMI status saving register (FEPC)

3 NMI status saving register (FEPSW)

4 Interrupt source register (ECR)

5 Program status word (PSW)

6 to 15 Reserved for future function expansion (operation is not guaranteed if these

registers are accessed)

16 CALLT execution status saving register (CTPC)

17 CALLT execution status saving register (CTPSW)

18 Exception/debug trap status saving register (DBPC) √

19 Exception/debug trap status saving register (DBPSW) √

20 CALLT base pointer (CTBP)

21 to 31 Reserved for future function expansion (operation is not guaranteed if these

registers are accessed)

Operand Specification System

LDSR Instruction STSR Instruction

√ √

× √

√ √

× ×

√ √

Note 2

√

Note 2

√

√ √

× ×

Note 2

Notes 1. Because only one set of these registers is available, the contents of these registers must be saved by

program if multiple interrupts are enabled.

2. These registers can be accessed only during the interval between the execution of the DBTRAP instruction

or illegal opcode and DBRET instruction execution.

Caution Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when

execution is returned to the main routine by the RETI instruction after interrupt servicing (this is

because bit 0 of the PC is fixed to 0). Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0).

Remark √: Can be accessed

×: Access prohibited

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

(1) Interrupt status saving registers (EIPC and EIPSW)

EIPC and EIPSW are used to save the status when an interrupt occurs.

If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC,

and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI

status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).

The address of the instruction next to the instruction under execution, except some instructions (see 19.8 Periods

in Which Interrupts Are Not Acknowledged by CPU), is saved to EIPC when a software exception or a maskable

interrupt occurs.

The current contents of the PSW are saved to EIPSW.

Because only one set of interrupt status saving registers is available, the contents of these registers must be saved

by program when multiple interrupts are enabled.

Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved for future function expansion (these bits are always

fixed to 0).

The value of EIPC is restored to the PC and the value of EIPSW to the PSW by the RETI instruction.

31 0

EIPC

EIPSW

31 0

26 25

0 0 0 0

0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

(Contents of saved PC)

(Contents of

saved PSW)

Default value

0xxxxxxxH

(x: Undefined)

Default value

000000xxH

(x: Undefined)

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(2) NMI status saving registers (FEPC and FEPSW)

FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs.

If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status

word (PSW) are saved to FEPSW.

The address of the instruction next to the one of the instruction under execution, except some instructions, is saved

to FEPC when an NMI occurs.

The current contents of the PSW are saved to FEPSW.

Because only one set of NMI status saving registers is available, the contents of these registers must be saved by

program when multiple interrupts are enabled (for multiple interrupt servicing using the NMI pin and the INTWDT2

interrupt request signal).

Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these bits are always

fixed to 0).

The value of FEPC is restored to the PC and the value of FEPSW to the PSW by the RETI instruction.

31 0

FEPC

FEPSW

31 0

(3) Interrupt source register (ECR)

The interrupt source register (ECR) holds the source of an exception or interrupt if an exception or interrupt occurs.

This register holds the exception code of each interrupt source. Because this register is a read-only register, data

cannot be written to this register using the LDSR instruction.

31 0

ECR

Bit position Bit name Meaning

31 to 16 FECC Exception code of non-maskable interrupt (NMI)

15 to 0 EICC Exception code of exception or maskable interrupt

26 25

0 0 0 0

0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

FECC EICC

(Contents of saved PC)

16 15

(Contents of

saved PSW)

Default value

0xxxxxxxH

(x: Undefined)

Default value

000000xxH

(x: Undefined)

Default value

00000000H

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(4) Program status word (PSW)

The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction

execution) and the status of the CPU.

If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated

immediately after completion of LDSR instruction execution. However if the ID flag is set to 1, interrupt requests will

not be acknowledged while the LDSR instruction is being executed.

Bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0).

(1/2)

31 0

PSW

Bit position Flag name Meaning

7 NP Indicates that a non-maskable interrupt (NMI) is being serviced. This bit is set to 1 when an

NMI request is acknowledged, disabling multiple interrupts.

0: NMI is not being serviced.

1: NMI is being serviced.

6 EP Indicates that an exception is being processed. This bit is set to 1 when an exception

occurs. Even if this bit is set, interrupt requests are acknowledged.

0: Exception is not being processed.

1: Exception is being processed.

5 ID Indicates whether a maskable interrupt can be acknowledged.

0: Interrupt enabled

1: Interrupt disabled

4 SAT

3 CY Indicates whether a carry or a borrow occurs as a result of an operation.

2 OV

1 S

0 Z Indicates whether the result of an operation is 0.

Note

Indicates that the result of a saturation operation has overflowed and is saturated. Because

this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is

saturated, and is not cleared to 0 even if the subsequent operation result is not saturated.

Use the LDSR instruction to clear this bit. This flag is neither set to 1 nor cleared to 0 by

execution of an arithmetic operation instruction.

0: Not saturated

1: Saturated

0: Carry or borrow does not occur.

1: Carry or borrow occurs.

Note

Indicates whether an overflow occurs during operation.

0: Overflow does not occur.

1: Overflow occurs.

Note

Indicates whether the result of an operation is negative.

0: The result is positive or 0.

1: The result is negative.

0: The result is not 0.

1: The result is 0.

87NP6EP5ID4

000000000000000000000000

SAT3CY2OV

Default value

00000020H

Remark Also read Note on the next page.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

Note The result of the operation that has performed saturation processing is determined by the contents of the

OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is

performed.

SAT OV S

Maximum positive value is exceeded 1 1 0 7FFFFFFFH

Maximum negative value is exceeded 1 1 1 80000000H

Positive (maximum value is not exceeded) 0

Negative (maximum value is not exceeded)

Holds value

before operation

Flag Status Status of Operation Result

Result of Operation of

Saturation Processing

Operation result itself

(5) CALLT execution status saving registers (CTPC and CTPSW)

CTPC and CTPSW are CALLT execution status saving registers.

When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and those

of the program status word (PSW) are saved to CTPSW.

The contents saved to CTPC are the address of the instruction next to CALLT.

The current contents of the PSW are saved to CTPSW.

Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved for future function expansion (fixed to 0).

CTPC

CTPSW

31 0

26 25

0 0 0 0

0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

(Saved PC contents)

(Saved PSW

contents)

Default value

0xxxxxxxH

(x: Undefined)

Default value

000000xxH

(x: Undefined)

(2/2)

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(6) Exception/debug trap status saving registers (DBPC and DBPSW)

DBPC and DBPSW are exception/debug trap status registers.

If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those

of the program status word (PSW) are saved to DBPSW.

The contents to be saved to DBPC are the address of the instruction next to the one that is being executed when

an exception trap or debug trap occurs.

The current contents of the PSW are saved to DBPSW.

This register can be read or written only during the interval between the execution of the DBTRAP instruction or

illegal opcode and the DBRET instruction.

Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (fixed to 0).

The value of DBPC is restored to the PC and the value of DBPSW to the PSW by the DBRET instruction.

31 0

DBPC

DBPSW

31 0

(7) CALLT base pointer (CTBP)

The CALLT base pointer (CTBP) is used to specify a table address or generate a target address (bit 0 is fixed to 0).

Bits 31 to 26 of this register are reserved for future function expansion (fixed to 0).

31 0

CTBP

0 0 0 0 0

26 25

0 0 0 0

0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

26 25

(Saved PC contents)

(Base address)

(Saved PSW

contents)

Default value

0xxxxxxxH

(x: Undefined)

Default value

000000xxH

(x: Undefined)

Default value

0xxxxxxxH

(x: Undefined)

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

3.3 Operation Modes

The V850ES/JC3-L and V850ES/JE3-L have the following operation modes.

• Normal operation mode

• Flash memory programming mode

• Self programming mode

• On-chip debug mode

The operation mode is specified according to the status (input level) of the FLMD0 and FLMD1 pins.

To specify the normal operation mode, input a low level to the FLMD0 pin during the reset period.

A high level is input to the FLMD0 pin by the flash memory programmer in the flash memory programming mode if a

flash programmer is connected. In the self-programming mode, input a high level to this pin from an external circuit.

Fix the specification of these pins in the application system and do not change the setting of these pins during operation.

FLMD0 FLMD1 Operation Mode

H L Flash memory programming mode

H H Setting prohibited

Normal operation mode

Remark H: High level

L: Low level ×: don’t care

(1) Normal operation mode

After the system has been released from the reset state, the pins related to the bus interface are set to the port

mode, execution branches to the reset entry address of the internal ROM, and instruction processing is started.

(2) Flash memory programming mode

When this mode is specified, the internal flash memory can be programmed by using a flash programmer.

(3) Self programming mode

Data can be erased and written from/to the flash memory by using a user application program. For details, see

CHAPTER 28 FLASH MEMORY.

(4) On-chip debug mode

The V850ES/JC3-L, V850ES/JE3-L is provided with an on-chip debug function that employs the JTAG (Joint Test

Action Group) communication specifications.

For details, see CHAPTER 29 ON-CHIP DEBUG FUNCTION.

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3.4 Address Space

3.4.1 CPU address space

For instruction addressing, up to a combined total of 16 MB of external memory area and internal ROM area, plus an

internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand addressing

(data access), up to 4 GB of a linear address space (data space) is supported. The 4 GB address space, however, is

viewed as 64 images of a 64 MB physical address space. This means that the same 64 MB physical address space is

accessed regardless of the value of bits 31 to 26.

Figure 3-1. Address Space Image

Data space

Program space

Access-prohibited area

Internal RAM area

Access-prohibited area

Image 63

Image 62

4 GB

Image 2

Image 1

On-chip peripheral I/O area

Internal RAM area

64 MB

Access-prohibited area

Note

•

Note

Image 0

Access-prohibited area

16 MB

Internal ROM area

16 MB

Note Image 0 appears repeatedly for images 1 to 63.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

3.4.2 Memory map

The areas shown below are reserved in the V850ES/JC3-L, V850ES/JE3-L.

Figure 3-2. Data Memory Map (Physical Addresses)

FFFFFFFFH

Image 63

FC000000H FBFFFFFFH

Image 62

F8000000H F7FFFFFFH

F4000000H F3FFFFFFH

F0000000H EFFFFFFFH

Image 61

Image 60

03FFFFFFH

03FF0000H 03FEFFFFH

(64 KB)

On-chip peripheral I/O area

(4 KB)

Internal RAM area

(60 KB)

03FFFFFFH

03FFF000H 03FFEFFFH

10000000H 0FFFFFFFH

0C000000H 0BFFFFFFH

08000000H 07FFFFFFH

04000000H 03FFFFFFH

00000000H

Image 3

Image 2

Image 1

Image 0

(Physical memory

address)

00200000H 001FFFFFH

00000000H

Use prohibited

(2 MB)

Use prohibited

Internal ROM area

(1 MB)

03FF0000H

001FFFFFH

00100000H 000FFFFFH

00000000H

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Figure 3-3. Program Memory Map

03FFFFFFH

03FFF000H 03FFEFFFH

03FF0000H 03FEFFFFH

Use prohibited

(program fetch prohibited area)

Internal RAM area (60 KB)

Use prohibited

(program fetch prohibited area)

00100000H 000FFFFFH

00000000H

Internal ROM area

(1 MB)

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

3.4.3 Areas

(1) Internal ROM area

Up to 1 MB is reserved as an internal ROM area.

(a) Internal ROM (16 KB)

16 KB are allocated to addresses 00000000H to 00003FFFH in the following versions.

Accessing addresses 00004000H to 000FFFFFH is prohibited.

•

PD70F3797, 70F3801, 70F3805

Figure 3-4. Internal ROM Area (16 KB)

000FFFFFH

(b) Internal ROM (32 KB)

32 KB are allocated to addresses 00000000H to 00007FFFH in the following versions.

Accessing addresses 00008000H to 000FFFFFH is prohibited.

•

PD70F3798, 70F3802, 70F3806

Access-prohibited

area

00004000H 00003FFFH

00000000H

Internal ROM

(16 KB)

Figure 3-5. Internal ROM Area (32 KB)

000FFFFFH

Access-prohibited

area

00008000H 00007FFFH

00000000H

Internal ROM

(32 KB)

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64 KB are allocated to addresses 00000000H to 0000FFFFH in the following versions.

Accessing addresses 00010000H to 000FFFFFH is prohibited.

•

PD70F3799, 70F3803, 70F3807

Figure 3-6. Internal ROM Area (64 KB)

000FFFFFH

Access-prohibited

area

00010000H 0000FFFFH

Internal ROM

(64 KB)

(d) Internal ROM (128 KB)

128 KB are allocated to addresses 00000000H to 0001FFFFH in the following versions.

Accessing addresses 00020000H to 000FFFFFH is prohibited.

•

PD70F3800, 70F3804, 70F3808

00000000H

Figure 3-7. Internal ROM Area (128 KB)

000FFFFFH

Access-prohibited

area

00020000H 0001FFFFH

Internal ROM

(128 KB)

00000000H

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

(e) Internal ROM (256 KB)

256 KB are allocated to addresses 00000000H to 0003FFFFH in the following versions.

Accessing addresses 00040000H to 000FFFFFH is prohibited.

•

PD70F3838, 70F3839, 70F3840

Figure 3-8. Internal ROM Area (256 KB)

000FFFFFH

Access-prohibited

area

00040000H

0003FFFFH

Internal ROM

(256 KB)

00000000H

(2) Internal RAM area

Up to 60 KB allocated to physical addresses 03FF0000H to 03FFEFFFH are reserved as the internal RAM area.

(a) Internal RAM (8 KB)

8 KB are allocated to addresses 03FFD000H to 03FFEFFFH in the following versions.

Accessing addresses 03FF0000H to 03FFCFFFH is prohibited.

•

PD70F3797, 70F3798, 70F3799, 70F3800, 70F3801, 70F3802, 70F3803, 70F3804, 70F3805,

70F3806, 70F3807, 70F3808

Figure 3-9. Internal RAM Area (8 KB)

Physical address space Logical address space

03FFEFFFH

03FFD000H 03FFCFFFH

Internal RAM

(8 KB)

FFFFEFFFH

FFFFD000H FFFFCFFFH

Access-prohibited

area

03FF0000H

FFFF0000H

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

(b) Internal RAM (16 KB)

16 KB are allocated to addresses 03FFB000H to 03FFEFFFH in the following versions.

Accessing addresses 03FF0000H to 03FFAFFFH is prohibited.

•

PD70F3838, 70F3839, 70F3840

Figure 3-10. Internal RAM Area (16 KB)

Physical address space Logical address space

03FFEFFFH

Internal RAM

(16 KB)

03FFB000H

03FFAFFFH

Access-prohibited

area

03FF0000H

FFFFEFFFH

FFFFB000H FFFFAFFFH

FFFF0000H

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

(3) On-chip peripheral I/O area

4 KB allocated to physical addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area.

Figure 3-11. On-Chip Peripheral I/O Area

Physical address space Logical address space

03FFFFFFH

On-chip peripheral I/O area

(4 KB)

03FFF000H

FFFFFFFFH

FFFFF000H

Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the on-chip

peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area.

Cautions 1. When a peripheral I/O register is accessed in word units, a word area is accessed twice in

halfword units in the order of lower area then higher area, with the lower 2 bits of the address

ignored.

2. If a peripheral I/O register that can be accessed in byte units is accessed in halfword units,

the lower 8 bits are valid. The higher 8 bits are undefined when the register is read and are

invalid when the register is written.

3. Addresses not defined as registers are reserved for future expansion. The operation is

undefined and not guaranteed when these addresses are accessed.

4. The internal ROM/RAM area and on-chip peripheral I/O area are assigned to successive

addresses.

When accessing the internal ROM/RAM area by incrementing or decrementing addresses

using a pointer operation for example, be careful not to access the on-chip peripheral I/O area

by mistakenly extending over the internal ROM/RAM area boundary.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

3.4.4 Wraparound of data space

The result of an operand address calculation operation that exceeds 32 bits is ignored.

Therefore, the highest address of the data space, FFFFFFFFH, and the lowest address, 00000000H, are contiguous,

and wraparound occurs at the boundary of these addresses.

Figure 3-12. Wraparound of Data Space

00000001H

00000000H

FFFFFFFFH

FFFFFFFEH

Data space

(+) direction (−) direction

Data space

3.4.5 Recommended use of address space

The architecture of the V850ES/JC3-L, V850ES/JE3-L requires that a register that serves as a pointer be secured for

address generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be

directly accessed by an instruction for operand data. Because the number of general-purpose registers that can be used

as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer

value is changed, as many general-purpose registers as possible can be secured for variables, and the program size can

be reduced.

(1) Program space

Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid.

Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H

unconditionally corresponds to the memory map.

To use the internal RAM area as the program space, access the following addresses.

Caution If a branch instruction is at the upper limit of the internal RAM area, a prefetch operation (invalid

fetch) straddling the on-chip peripheral I/O area does not occur.

Product Name RAM Size Access Address

PD70F3797, 70F3798, 70F3799,

70F3800, 70F3801, 70F3802,

70F3803, 70F3804, 70F3805,

70F3806, 70F3807, 70F3808

PD70F3838, 70F3839, 70F3840 16 KB 03FFB000H to 03FFEFFFH

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8 KB 03FFD000H to 03FFEFFFH

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

(2) Data space

With the V850ES/JC3-L, V850ES/JE3-L, it seems that there are sixty-four 64 MB (26-bit address) physical address

spaces on the 4 GB (32-bit address) CPU address space. Therefore, the most significant bit (bit 25) of a 26-bit

address of these 64 MB spaces is sign-extended to 32 bits and allocated as an address.

Figure 3-13. Sign Extension in Data Space

31 0

31 026 25

0 0 0 0

26 25

A 26-bit address (64 MB) can be specified.

3FFFFFFH

0000000H

Image 0

64 MB

A 32-bit address (4 GB) can be specified. An image of 64 MB appears repeatedly in the 4 GB space.

FFFFFFFFH

FC000000H FBFFFFFFH

F8000000H F7FFFFFFH

F4000000H F3FFFFFFH

F0000000H EFFFFFFFH

10000000H 0FFFFFFFH

0C000000H 0BFFFFFFH

08000000H 07FFFFFFH

04000000H 03FFFFFFH

00000000H

Image 63

Image 62

Image 61

Image 60

Image 3

Image 2

Image 1

Image 0

64 MB

4 GB

64 MB

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

(a) Application example of wraparound

If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32

KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can be

addressed by one pointer.

The zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers

dedicated to pointers.

Figure 3-14. Example of Data Space Usage in

0003FFFFH

00007FFFH

PD70F3840

(R = )

00000000H

FFFFF000H

FFFFEFFFH

FFFFB000H

FFFFAFFFH

FFFF8000H

Internal ROM area

On-chip peripheral

I/O area

Internal RAM area

Access-prohibited

area

32 KB

4 KB

16 KB

12 KB

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

FFFFFFFFH

FFFFF000H FFFFEFFFH

FFFF0000H FFFEFFFFH

04000000H 03FFFFFFH

03FFF000H 03FFEFFFH

03FFB000H 03FFAFFFH

03FF0000H 03FEFFFFH

Figure 3-12. Recommended Memory Map (

Data spaceProgram space

On-chip

peripheral I/O

Internal RAM

Access-prohibited

Internal RAM

PD70F3840)

On-chip

peripheral I/O

Internal RAM

Access-prohibited

FFFFFFFFH

FFFFF000H FFFFEFFFH

FFFFB000H FFFFAFFFH FFFF0000H FFFEFFFFH

Program space

Remark

64 MB

Access-prohibited

00100000H 000FFFFFH 00040000H 0003FFFFH

00000000H

Internal ROM

indicates the recommended area.

00100000H 000FFFFFH

Internal ROM

00000000H

Internal ROM

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

3.4.6 Peripheral I/O registers

(1/10)

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFF004H Port DL register PDL √ 0000H

FFFFF004H Port DL register L PDLL

FFFFF00CH Port CM register PCM

FFFFF024H Port DL mode register PMDL

FFFFF024H Port DL mode register L PMDLL

FFFFF02CH Port CM mode register PMCM

FFFFF06EH System wait control register VSWC

FFFFF080H DMA source address register 0L DSA0L

FFFFF082H DMA source address register 0H DSA0H

FFFFF084H DMA destination address register 0L DDA0L

FFFFF086H DMA destination address register 0H DDA0H

FFFFF088H DMA source address register 1L DSA1L

FFFFF08AH DMA source address register 1H DSA1H

FFFFF08CH DMA destination address register 1L DDA1L

FFFFF08EH DMA destination address register 1H DDA1H

FFFFF090H DMA source address register 2L DSA2L

FFFFF092H DMA source address register 2H DSA2H

FFFFF094H DMA destination address register 2L DDA2L

FFFFF096H DMA destination address register 2H DDA2H

FFFFF098H DMA source address register 3L DSA3L

FFFFF09AH DMA source address register 3H DSA3H

FFFFF09CH DMA destination address register 3L DDA3L

FFFFF09EH DMA destination address register 3H DDA3H

FFFFF0C0H DMA transfer count register 0 DBC0

FFFFF0C2H DMA transfer count register 1 DBC1

FFFFF0C4H DMA transfer count register 2 DBC2

FFFFF0C6H DMA transfer count register 3 DBC3

FFFFF0D0H DMA addressing control register 0 DADC0

FFFFF0D2H DMA addressing control register 1 DADC1

FFFFF0D4H DMA addressing control register 2 DADC2

FFFFF0D6H DMA addressing control register 3 DADC3

FFFFF0E0H DMA channel control register 0 DCHC0

FFFFF0E2H DMA channel control register 1 DCHC1

FFFFF0E4H DMA channel control register 2 DCHC2

FFFFF0E6H DMA channel control register 3 DCHC3

FFFFF100H Interrupt mask register 0 IMR0

FFFFF100H Interrupt mask register 0L IMR0L

FFFFF101H Interrupt mask register 0H IMR0H

R/W

√ √ √ √

√

√ √ √ √ √ √ √ √

√ √ √ √

Note The output latch is 00H or 0000H. When these registers are in the input mode, the pin statuses are read.

Default Value

Note

00H

Note

00H

FFFFH

√

FFH

77H

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

0000H

√

0000H

√

0000H

√

0000H

√

00H

FFFFH

√

FFH

Note

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

Manipulatable Bits Address Function Register Name Symbol R/W

FFFFF102H Interrupt mask register 1 IMR1

FFFFF102H Interrupt mask register 1L IMR1L

FFFFF103H Interrupt mask register 1H IMR1H

FFFFF104H Interrupt mask register 2 IMR2

FFFFF104H Interrupt mask register 2L IMR2L

FFFFF105H Interrupt mask register 2H IMR2H

FFFFF106H Interrupt mask register 3 IMR3

FFFFF106H Interrupt mask register 3L IMR3L

FFFFF110H Interrupt control register (INTLVI) LVIIC

FFFFF112H Interrupt control register (INTP0) PIC0

FFFFF114H Interrupt control register (INTP1) PIC1

FFFFF116H Interrupt control register (INTP2) PIC2

FFFFF118H Interrupt control register (INTP3) PIC3

FFFFF11AH Interrupt control register (INTP4) PIC4

FFFFF11CH Interrupt control register (INTP5) PIC5

FFFFF11EH Interrupt control register (INTP6) PIC6

FFFFF120H Interrupt control register (INTP7) PIC7

FFFFF122H Interrupt control register (INTTQ0OV) TQ0OVIC

FFFFF124H Interrupt control register (INTTQ0CC0) TQ0CCIC0

FFFFF126H Interrupt control register (INTTQ0CC1) TQ0CCIC1

FFFFF128H Interrupt control register (INTTQ0CC2) TQ0CCIC2

FFFFF12AH Interrupt control register (INTTQ0CC3) TQ0CCIC3

FFFFF12CH Interrupt control register (INTTP0OV) TP0OVIC

FFFFF12EH Interrupt control register (INTTP0CC0) TP0CCIC0

FFFFF130H Interrupt control register (INTTP0CC1) TP0CCIC1

FFFFF132H Interrupt control register (INTTP1OV) TP1OVIC

FFFFF134H Interrupt control register (INTTP1CC0) TP1CCIC0

FFFFF136H Interrupt control register (INTTP1CC1) TP1CCIC1

FFFFF138H Interrupt control register (INTTP2OV) TP2OVIC

FFFFF13AH Interrupt control register (INTTP2CC0) TP2CCIC0

FFFFF13CH Interrupt control register (INTTP2CC1) TP2CCIC1

FFFFF13EH Interrupt control register (INTTP3OV) TP3OVIC

FFFFF140H Interrupt control register (INTTP3CC0) TP3CCIC0

FFFFF142H Interrupt control register (INTTP3CC1) TP3CCIC1

FFFFF144H Interrupt control register (INTTP4OV) TP4OVIC

FFFFF146H Interrupt control register (INTTP4CC0) TP4CCIC0

FFFFF148H Interrupt control register (INTTP4CC1) TP4CCIC1

FFFFF14AH Interrupt control register (INTTP5OV) TP5OVIC

FFFFF14CH Interrupt control register (INTTP5CC0) TP5CCIC0

FFFFF14EH Interrupt control register (INTTP5CC1) TP5CCIC1

FFFFF150H Interrupt control register (INTTM0EQ0) TM0EQIC0

R/W

1 8 16

FFFFH

√ √ √ √ √

√ √ √ √

√ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √

√ √

FFH

FFFFH

√

FFH

FFFFH

√

FFH

47H

(2/10)

Default Value

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

Manipulatable Bits Address Function Register Name Symbol R/W

FFFFF152H Interrupt control register (INTCB0R/INTIIC1) CB0RIC/IICIC1

FFFFF154H Interrupt control register (INTCB0T) CB0TIC

FFFFF156H Interrupt control register (INTCB1R) CB1RIC

FFFFF158H Interrupt control register (INTCB1T) CB1TIC

FFFFF15AH Interrupt control register (INTCB2R) CB2RIC

FFFFF15CH Interrupt control register (INTCB2T) CB2TIC

FFFFF15EH Interrupt control register (INTCB3R) CB3RIC

FFFFF160H Interrupt control register (INTCB3T) CB3TIC

FFFFF162H Interrupt control register (INTUA0R/INTCB4R)

FFFFF164H Interrupt control register (INTUA0T/INTCB4T) UA0TIC/CB4TIC

FFFFF166H Interrupt control register (INTUA1R/INTIIC2) UA1RIC/IICIC2

FFFFF168H Interrupt control register (INTUA1T) UA1TIC

FFFFF16AH Interrupt control register (INTUA2R/INTIIC0) UA2RIC/IICIC0

FFFFF16CH Interrupt control register (INTUA2T) UA2TIC

FFFFF16EH Interrupt control register (INTAD) ADIC

FFFFF170H Interrupt control register (INTDMA0) DMAIC0

FFFFF172H Interrupt control register (INTDMA1) DMAIC1

FFFFF174H Interrupt control register (INTDMA2) DMAIC2

FFFFF176H Interrupt control register (INTDMA3) DMAIC3

FFFFF178H Interrupt control register (INTKR) KRIC

FFFFF17AH Interrupt control register (INTWTI/INTRTC2) WTIIC/RTC2IC

FFFFF17CH Interrupt control register (INTWT/INTRTC0) WTIC/RTC0IC

FFFFF17EH Interrupt control register (INTRTC1) RTC1C

FFFFF1FAH In-service priority register ISPR R

FFFFF1FCH Command register PRCMD W

FFFFF1FEH Power save control register PSC

FFFFF200H A/D converter mode register 0 ADA0M0

FFFFF201H A/D converter mode register 1 ADA0M1

FFFFF202H A/D converter channel specification register ADA0S

FFFFF203H A/D converter mode register 2 ADA0M2

FFFFF204H Power-fail compare mode register ADA0PFM

FFFFF205H Power-fail compare threshold value register ADA0PFT

FFFFF210H A/D conversion result register 0 ADA0CR0

FFFFF211H A/D conversion result register 0H ADA0CR0H

FFFFF212H A/D conversion result register 1 ADA0CR1

FFFFF213H A/D conversion result register 1H ADA0CR1H

FFFFF214H A/D conversion result register 2 ADA0CR2

FFFFF215H A/D conversion result register 2H ADA0CR2H

FFFFF216H A/D conversion result register 3 ADA0CR3

FFFFF217H A/D conversion result register 3H ADA0CR3H

UA0RIC/CB4RIC

Note

R/W

Note This is a special register.

1 8 16

√ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √

√ √ √ √ √ √ √ √ √ √ √ √ √ √

47H

00H

Undefined

√

00H

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

(3/10)

Default Value

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFF218H A/D conversion result register 4 ADA0CR4

FFFFF219H A/D conversion result register 4H ADA0CR4H

FFFFF21AH A/D conversion result register 5 ADA0CR5

FFFFF21BH A/D conversion result register 5H ADA0CR5H

FFFFF21CH A/D conversion result register 6 ADA0CR6

FFFFF21DH A/D conversion result register 6H ADA0CR6H

FFFFF21EH A/D conversion result register 7 ADA0CR7

FFFFF21FH A/D conversion result register 7H ADA0CR7H

FFFFF220H A/D conversion result register 8 ADA0CR8

FFFFF221H A/D conversion result register 8H ADA0CR8H

FFFFF222H A/D conversion result register 9 ADA0CR9

FFFFF223H A/D conversion result register 9H ADA0CR9H

FFFFF280H D/A conversion value setting register 0 DA0CS0

FFFFF281H D/A conversion value setting register 1 DA0CS1

FFFFF282H D/A converter mode register DA0M

FFFFF300H Key return mode register KRM

FFFFF308H Selector operation control register 0 SELCNT0

FFFFF310H CRC input register CRCIN

R/W

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

Undefined

√

√ √ √ √ √ √

Undefined

√

00H

√

00H

√

00H

√

FFFFF312H CRC data register CRCD √ 0000H

FFFFF318H Noise elimination control register NFC

FFFFF320H Prescaler mode register 1 PRSM1

FFFFF321H Prescaler compare register 1 PRSCM1

FFFFF324H Prescaler mode register 2 PRSM2

FFFFF325H Prescaler compare register 2 PRSCM2

FFFFF328H Prescaler mode register 3 PRSM3

FFFFF329H Prescaler compare register 3 PRSCM3

FFFFF331H Regulator protection register REGPR

FFFFF332H Regulator output voltage level control register REGOVL0

FFFFF340H IIC division clock select register OCKS0

FFFFF344H IIC division clock select register OCKS1

FFFFF400H Port 0 register P0

FFFFF402H Port 1 register P1

√ √

√ √ √ √

√

√ √ √ √ √

00H

FFFFF406H Port 3 register P3 √ 0000H

FFFFF406H Port 3 register L P3L

FFFFF407H Port 3 register H P3H

FFFFF408H Port 4 register P4

FFFFF40AH Port 5 register P5

FFFFF40EH Port 7 register L P7L

FFFFF40FH Port 7 register H P7H

√ √ √ √ √ √ √ √ √ √ √ √

00H

FFFFF412H Port 9 register P9 √ 0000H

FFFFF412H Port 9 register L P9L

FFFFF413H Port 9 register H P9H

FFFFF420H Port 0 mode register PM0

√ √ √ √ √ √

00H

FFH

Note The output latch is 00H or 0000H. When these registers are input, the pin statuses are read.

Default Value

Undefined

Note

(4/10)

Note

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFF422H Port 1 mode register PM1

FFFFF426H Port 3 mode register PM3

FFFFF426H Port 3 mode register L PM3L

FFFFF427H Port 3 mode register H PM3H

FFFFF428H Port 4 mode register PM4

FFFFF42AH Port 5 mode register PM5

FFFFF42EH Port 7 mode register L PM7L

FFFFF42FH Port 7 mode register H PM7H

FFFFF432H Port 9 mode register PM9

FFFFF432H Port 9 mode register L PM9L

FFFFF433H Port 9 mode register H PM9H

FFFFF440H Port 0 mode control register PMC0

FFFFF446H Port 3 mode control register PMC3

FFFFF446H Port 3 mode control register L PMC3L

FFFFF447H Port 3 mode control register H PMC3H

FFFFF448H Port 4 mode control register PMC4

FFFFF44AH Port 5 mode control register PMC5

FFFFF452H Port 9 mode control register PMC9

FFFFF452H Port 9 mode control register L PMC9L

FFFFF453H Port 9 mode control register H PMC9H

FFFFF460H Port 0 function control register PFC0

FFFFF466H Port 3 function control register PFC3

FFFFF466H Port 3 function control register L PFC3L

FFFFF467H Port 3 function control register H PFC3H

FFFFF468H Port 4 function control register PFC4

FFFFF46AH Port 5 function control register PFC5

FFFFF472H Port 9 function control register PFC9

FFFFF472H Port 9 function control register L PFC9L

FFFFF473H Port 9 function control register H PFC9H

FFFFF540H TMQ0 control register 0 TQ0CTL0

FFFFF541H TMQ0 control register 1 TQ0CTL1

FFFFF542H TMQ0 I/O control register 0 TQ0IOC0

FFFFF543H TMQ0 I/O control register 1 TQ0IOC1

FFFFF544H TMQ0 I/O control register 2 TQ0IOC2

FFFFF545H TMQ0 option register 0 TQ0OPT0

FFFFF546H TMQ0 capture/compare register 0 TQ0CCR0

FFFFF548H TMQ0 capture/compare register 1 TQ0CCR1

FFFFF54AH TMQ0 capture/compare register 2 TQ0CCR2

FFFFF54CH TMQ0 capture/compare register 3 TQ0CCR3

FFFFF54EH TMQ0 counter read buffer register TQ0CNT R

R/W

√ √

√ √ √ √ √ √ √ √ √ √ √ √

√ √ √ √ √ √

√ √ √ √ √ √ √ √

√ √ √ √ √ √

√ √ √ √ √ √ √ √

√ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √

√ 0000H

Note The output latch is 00H or 0000H. When these registers are input, the pin statuses are read.

FFH

FFFFH

√

FFH

FFFFH

√

FFH

00H

0000H

√

00H

0000H

√

00H

0000H

√

00H

0000H

√

00H

0000H

√

0000H

√

0000H

√

0000H

√

(5/10)

Default Value

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

Manipulatable Bits Default Value Address Function Register Name Symbol R/W

1 8 16

FFFFF590H TMP0 control register 0 TP0CTL0

FFFFF591H TMP0 control register 1 TP0CTL1

FFFFF592H TMP0 I/O control register 0 TP0IOC0

FFFFF593H TMP0 I/O control register 1 TP0IOC1

FFFFF594H TMP0 I/O control register 2 TP0IOC2

FFFFF595H TMP0 option register 0 TP0OPT0

FFFFF596H TMP0 capture/compare register 0 TP0CCR0

FFFFF598H TMP0 capture/compare register 1 TP0CCR1

FFFFF59AH TMP0 counter read buffer register TP0CNT R

FFFFF5A0H TMP1 control register 0 TP1CTL0

FFFFF5A1H TMP1 control register 1 TP1CTL1

FFFFF5A2H TMP1 I/O control register 0 TP1IOC0

FFFFF5A3H TMP1 I/O control register 1 TP1IOC1

FFFFF5A4H TMP1 I/O control register 2 TP1IOC2

FFFFF5A5H TMP1 option register 0 TP1OPT0

FFFFF5A6H TMP1 capture/compare register 0 TP1CCR0

FFFFF5A8H TMP1 capture/compare register 1 TP1CCR1

FFFFF5AAH TMP1 counter read buffer register TP1CNT R

FFFFF5B0H TMP2 control register 0 TP2CTL0

FFFFF5B1H TMP2 control register 1 TP2CTL1

FFFFF5B2H TMP2 I/O control register 0 TP2IOC0

FFFFF5B3H TMP2 I/O control register 1 TP2IOC1

FFFFF5B4H TMP2 I/O control register 2 TP2IOC2

FFFFF5B5H TMP2 option register 0 TP2OPT0

FFFFF5B6H TMP2 capture/compare register 0 TP2CCR0

FFFFF5B8H TMP2 capture/compare register 1 TP2CCR1

FFFFF5BAH TMP2 counter read buffer register TP2CNT R

FFFFF5C0H TMP3 control register 0 TP3CTL0

FFFFF5C1H TMP3 control register 1 TP3CTL1

FFFFF5C2H TMP3 I/O control register 0 TP3IOC0

FFFFF5C3H TMP3 I/O control register 1 TP3IOC1

FFFFF5C5H TMP3 option register 0 TP3OPT0

FFFFF5C6H TMP3 capture/compare register 0 TP3CCR0

FFFFF5C8H TMP3 capture/compare register 1 TP3CCR1

FFFFF5CAH TMP3 counter read buffer register TP3CNT R

FFFFF5D0H TMP4 control register 0 TP4CTL0

FFFFF5D1H TMP4 control register 1 TP4CTL1

FFFFF5D2H TMP4 I/O control register 0 TP4IOC0

FFFFF5D3H TMP4 I/O control register 1 TP4IOC1

FFFFF5D4H TMP4 I/O control register 2 TP4IOC2

FFFFF5D5H TMP4 option register 0 TP4OPT0

R/W

√ √ √ √ √ √ √ √ √ √ √ √

√ 0000H

√ √ √ √ √ √ √ √ √ √ √ √

√ 0000H

√ √ √ √ √ √ √ √ √ √ √ √

√ 0000H

√ √ √ √ √ √ √ √ √ √

√ 0000H

√ √ √ √ √ √ √ √ √ √ √ √

00H

0000H

√

0000H

√

00H

0000H

√

0000H

√

00H

0000H

√

0000H

√

00H

0000H

√

0000H

√

00H

(6/10)

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFF5D6H TMP4 capture/compare register 0 TP4CCR0

FFFFF5D8H TMP4 capture/compare register 1 TP4CCR1

FFFFF5DAH TMP4 counter read buffer register TP4CNT R

FFFFF5E0H TMP5 control register 0 TP5CTL0

FFFFF5E1H TMP5 control register 1 TP5CTL1

FFFFF5E2H TMP5 I/O control register 0 TP5IOC0

FFFFF5E3H TMP5 I/O control register 1 TP5IOC1

FFFFF5E4H TMP5 I/O control register 2 TP5IOC2

FFFFF5E5H TMP5 option register 0 TP5OPT0

FFFFF5E6H TMP5 capture/compare register 0 TP5CCR0

FFFFF5E8H TMP5 capture/compare register 1 TP5CCR1

FFFFF5EAH TMP5 counter read buffer register TP5CNT R

FFFFF680H Watch timer operation mode register WTM

FFFFF690H TMM0 control register 0 TM0CTL0

FFFFF694H TMM0 compare register 0 TM0CMP0

FFFFF6C0H Oscillation stabilization time select register OSTS

FFFFF6C1H PLL lockup time specification register PLLS

FFFFF6D0H Watchdog timer mode register 2 WDTM2

FFFFF6D1H Watchdog timer enable register WDTE

FFFFF6E0H Real-time output buffer register 0L RTBL0

FFFFF6E2H Real-time output buffer register 0H RTBH0

FFFFF6E4H Real-time output port mode register 0 RTPM0

FFFFF6E5H Real-time output port control register 0 RTPC0

FFFFF700H Port 0 function control expansion register PFCE0

FFFFF706H Port 3 function control expansion register L PFCE3L

FFFFF70AH Port 5 function control expansion register PFCE5

FFFFF712H Port 9 function control expansion register PFCE9

FFFFF712H Port 9 function control expansion register L PFCE9L

FFFFF713H Port 9 function control expansion register H PFCE9H

FFFFF802H System status register SYS

FFFFF80CH Internal oscillation mode register RCM

FFFFF810H DMA trigger factor register 0 DTFR0

FFFFF812H DMA trigger factor register 1 DTFR1

FFFFF814H DMA trigger factor register 2 DTFR2

FFFFF816H DMA trigger factor register 3 DTFR3

FFFFF820H Power save mode register PSMR

FFFFF822H Clock control register CKC

FFFFF824H Lock register LOCKR R

FFFFF828H Processor clock control register PCC

FFFFF82CH PLL control register PLLCTL

FFFFF82EH CPU operation clock status register CCLS R

Note

R/W

√ 0000H

√ √ √ √ √ √ √ √ √ √ √ √

√ 0000H

√ √ √ √

√ √ √ √ √ √ √ √ √ √ √ √ √ √

√ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √

√ √ √ √

Note This is a special register.

√ √ √ √

Default Value

0000H

√

0000H

√

00H

0000H

√

0000H

√

00H

0000H

√

06H

03H

67H

9AH

00H

0000H

√

00H

0AH

00H

03H

01H

00H

(7/10)

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFF870H Clock monitor mode register CLM

FFFFF888H Reset source flag register RESF

FFFFF890H Low-voltage detection register LVIM

FFFFF891H Low-voltage detection level select register LVIS

FFFFF8B0H Prescaler mode register 0 PRSM0

FFFFF8B1H Prescaler compare register 0 PRSCM0

FFFFF9FCH On-chip debug mode register OCDM

FFFFFA00H UARTA0 control register 0 UA0CTL0

FFFFFA01H UARTA0 control register 1 UA0CTL1

FFFFFA02H UARTA0 control register 2 UA0CTL2

FFFFFA03H UARTA0 option control register 0 UA0OPT0

FFFFFA04H UARTA0 status register UA0STR

FFFFFA06H UARTA0 receive data register UA0RX R

FFFFFA07H UARTA0 transmit data register UA0TX

FFFFFA10H UARTA1 control register 0 UA1CTL0

FFFFFA11H UARTA1 control register 1 UA1CTL1

FFFFFA12H UARTA1 control register 2 UA1CTL2

FFFFFA13H UARTA1 option control register 0 UA1OPT0

FFFFFA14H UARTA1 status register UA1STR

FFFFFA16H UARTA1 receive data register UA1RX R

FFFFFA17H UARTA1 transmit data register UA1TX

FFFFFA20H UARTA2 control register 0 UA2CTL0

FFFFFA21H UARTA2 control register 1 UA2CTL1

FFFFFA22H UARTA2 control register 2 UA2CTL2

FFFFFA23H UARTA2 option control register 0 UA2OPT0

FFFFFA24H UARTA2 status register UA2STR

FFFFFA26H UARTA2 receive data register UA2RX R

FFFFFA27H UARTA2 transmit data register UA2TX R/W

FFFFFAD0H Sub-count register RC1SUBC R √ 0000H

FFFFFAD2H Second count register RC1SEC

FFFFFAD3H Minute count register RC1MIN

FFFFFAD4H Hour count register RC1HOUR

FFFFFAD5H Week count register RC1WEEK

FFFFFAD6H Day count register RC1DAY

FFFFFAD7H Month count register RC1MONTH

FFFFFAD8H Year count register RC1YEAR

FFFFFAD9H Time error correction register RC1SUBU

FFFFFADAH Alarm minute set register RC1ALM

FFFFFADBH Alarm time set register RC1ALH

FFFFFADCH Alarm week set register RC1ALW

Note

R/W

√ √ √ √ √ √

√ √

√ √ √ √

√ √

√ √ √ √

√ √

√ √ √ √

√ √

√

√ √

√ √ √ √ √ √ √ √ √ √

00H

01H

10H

00H

FFH

14H

00H

FFH

10H

00H

FFH

14H

00H

FFH

10H

00H

FFH

14H

00H

FFH

00H

12H

00H

01H

00H

12H

00H

Note This is a special register.

Default Value

(8/10)

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

Manipulatable Bits Default ValueAddress Function Register Name Symbol R/W

1 8 16

FFFFFADDH RTC control register 0 RC1CC0

FFFFFADEH RTC control register 1 RC1CC1

FFFFFADFH RTC control register 2 RC1CC2

FFFFFAE0H RTC control register 3 RC1CC3

FFFFFC00H External interrupt falling edge specification register 0 INTF0

FFFFFC06H External interrupt falling edge specification register 3 INTF3

FFFFFC13H External interrupt falling edge specification register 9H INTF9H

FFFFFC20H External interrupt rising edge specification register 0 INTR0

FFFFFC26H External interrupt rising edge specification register 3 INTR3

FFFFFC33H External interrupt rising edge specification register 9H INTR9H

FFFFFC60H Port 0 function register PF0

FFFFFC66H Port 3 function register PF3

FFFFFC66H Port 3 function register L PF3L

FFFFFC67H Port 3 function register H PF3H

FFFFFC68H Port 4 function register PF4

FFFFFC6AH Port 5 function register PF5

FFFFFC72H Port 9 function register PF9

FFFFFC72H Port 9 function register L PF9L

FFFFFC73H Port 9 function register H PF9H

FFFFFD00H CSIB0 control register 0 CB0CTL0

FFFFFD01H CSIB0 control register 1 CB0CTL1

FFFFFD02H CSIB0 control register 2 CB0CTL2

FFFFFD03H CSIB0 status register CB0STR

FFFFFD04H CSIB0 receive data register CB0RX

FFFFFD04H CSIB0 receive data register L CB0RXL

FFFFFD06H CSIB0 transmit data register CB0TX

FFFFFD06H CSIB0 transmit data register L CB0TXL

FFFFFD10H CSIB1 control register 0 CB1CTL0

FFFFFD11H CSIB1 control register 1 CB1CTL1

FFFFFD12H CSIB1 control register 2 CB1CTL2

FFFFFD13H CSIB1 status register CB1STR

FFFFFD14H CSIB1 receive data register CB1RX

FFFFFD14H CSIB1 receive data register L CB1RXL

FFFFFD16H CSIB1 transmit data register CB1TX

FFFFFD16H CSIB1 transmit data register L CB1TXL

FFFFFD20H CSIB2 control register 0 CB2CTL0

FFFFFD21H CSIB2 control register 1 CB2CTL1

FFFFFD22H CSIB2 control register 2 CB2CTL2

FFFFFD23H CSIB2 status register CB2STR

FFFFFD24H CSIB2 receive data register CB2RX

FFFFFD24H CSIB2 receive data register L CB2RXL

R/W

√ √ √ √ √ √ √ √

√ √

√ √ √ √ √ √ √ √ √ √ √ √

√ √ √ √ √ √ √ √

√

√ √ √ √

√ √

00H

√

00H

√

00H

01H

00H

√

00H

√

00H

√

00H

√

01H

00H

√

00H

√

00H

√

00H

√

01H

√

00H

√

00H

√

00H

√

00H

√

0000H

(9/10)

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

Manipulatable Bits Address Function Register Name Symbol R/W

1 8 16

FFFFFD26H CSIB2 transmit data register CB2TX

FFFFFD26H CSIB2 transmit data register L CB2TXL

FFFFFD30H CSIB3 control register 0 CB3CTL0

FFFFFD31H CSIB3 control register 1 CB3CTL1

FFFFFD32H CSIB3 control register 2 CB3CTL2

FFFFFD33H CSIB3 status register CB3STR

FFFFFD34H CSIB3 receive data register CB3RX

FFFFFD34H CSIB3 receive data register L CB3RXL

FFFFFD36H CSIB3 transmit data register CB3TX

FFFFFD36H CSIB3 transmit data register L CB3TXL

FFFFFD40H CSIB4 control register 0 CB4CTL0

FFFFFD41H CSIB4 control register 1

FFFFFD42H CSIB4 control register 2 CB4CTL2

FFFFFD43H CSIB4 status register CB4STR

FFFFFD44H CSIB4 receive data register CB4RX

FFFFFD44H CSIB4 receive data register L CB4RXL

FFFFFD46H CSIB4 transmit data register CB4TX

FFFFFD46H CSIB4 transmit data register L CB4TXL

FFFFFD80H IIC shift register 0 IIC0

FFFFFD82H IIC control register 0 IICC0

FFFFFD83H Slave address register 0 SVA0

FFFFFD84H IIC clock select register 0 IICCL0

FFFFFD85H IIC function expansion register 0 IICX0

FFFFFD86H IIC status register 0 IICS0 R

FFFFFD8AH IIC flag register 0 IICF0

FFFFFD90H IIC shift register 1 IIC1

FFFFFD92H IIC control register 1 IICC1

FFFFFD93H Slave address register 1 SVA1

FFFFFD94H IIC clock select register 1 IICCL1

FFFFFD95H IIC function expansion register 1 IICX1

FFFFFD96H IIC status register 1 IICS1 R

FFFFFD9AH IIC flag register 1 IICF1

FFFFFDA0H IIC shift register 2 IIC2

FFFFFDA2H IIC control register 2 IICC2

FFFFFDA3H Slave address register 2 SVA2

FFFFFDA4H IIC clock select register 2 IICCL2

FFFFFDA5H IIC function expansion register 2 IICX2

FFFFFDA6H IIC status register 2 IICS2 R

FFFFFDAAH IIC flag register 2 IICF2 R/W

CB4CTL1

R/W

√ √ √ √

√ √

√ √ √ √

√ √

√ √ √ √ √ √ √ √

√ √

√ √ √ √ √ √ √ √

√ √

√ √ √ √ √ √ √ √

√

√ √

√

0000H

√

00H

01H

00H

0000H

√

00H

0000H

√

00H

01H

00H

0000H

√

00H

0000H

√

00H

(10/10)

Default Value

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

3.4.7 Special registers

Special registers are registers that are protected from being written with illegal data due to a program hang-up. The

V850ES/JC3-L and V850ES/JE3-L have the following seven special registers.

• Power save control register (PSC)

• Clock control register (CKC)

• Processor clock control register (PCC)

• Clock monitor mode register (CLM)

• Reset source flag register (RESF)

• Low-voltage detection register (LVIM)

• On-chip debug mode register (OCDM)

In addition, the PRCDM register is provided to protect against a write access to the special registers so that the

application system does not inadvertently stop due to a program hang-up. A write access to the special registers is made

in a specific sequence, and an illegal store operation is reported to the SYS register.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

(1) Setting data to special registers

Set data to the special registers in the following sequence.

<1> Disable DMA operation.

<2> Prepare data to be set to the special register in a general-purpose register.

<3> Write the data prepared in <2> to the PRCMD register.

<4> Write the setting data to the special register (by using the following instructions).

• Store instruction (ST/SST instruction)

• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)

(<5> to <9> Insert NOP instructions (5 instructions).)

<10> Enable DMA operation if necessary.

Note When switching to the IDLE mode or the STOP mode (PSC.STP bit = 1), 5 NOP instructions must be

inserted immediately after switching is performed.

Caution To resume the DMA operation in the status before the DMA operation was disabled after a special

sequence, the DCHCn register status must be stored before the DMA operation is disabled.

After the DCHCn register status is stored, the DCHCn.TCn bit must be checked before the DMA

operation is resumed and the following processing must be executed according to the TCn bit

status, because completion of DMA transfer may occur before the DMA operation is disabled.

• When the TCn bit is 0 (DMA transfer not completed), the contents of the DCHCn register stored

before the DMA operation was disabled are written to the DCHCn register again.

• When the TCn bit is 1 (DMA transfer completed), DMA transfer completion processing is

executed.

Remark n = 0 to 3

[Example] PSC register (setting standby mode)

ST.B r11, PSMR[r0] ; Set PSMR register (setting IDLE1, IDLE2, and STOP modes).

<1>CLR1 0, DCHCn[r0] ; Disable DMA operation. n = 0 to 3

<2>MOV0x02, r10

<3>ST.B r10, PRCMD[r0] ; Write PRCMD register.

<4>ST.B r10, PSC[r0] ; Set PSC register.

<5>NOP

<6>NOP

<7>NOP

<8>NOP

<9>NOP

Note

; Dummy instruction

Note

; Dummy instruction

Note

; Dummy instruction

Note

; Dummy instruction

Note

; Dummy instruction

<10>SET1 0, DCHCn[r0] ; Enable DMA operation. n = 0 to 3

(next instruction)

There is no special sequence required to read a special register.

Note

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

Note Five NOP instructions or more must be inserted immediately after setting the IDLE1 mode, IDLE2 mode, or

STOP mode (by setting the PSC.STP bit to 1).

Caution When a store instruction is executed to store data in the command register, interrupts are not

acknowledged. This is because it is assumed that steps <3> and <4> above are performed by

successive store instructions. If another instruction is placed between <3> and <4>, and if an

interrupt is acknowledged by that instruction, the above sequence may not be established,

causing malfunction.

Remark Although dummy data is written to the PRCMD register, use the same general-purpose register used to

set the special register (<4> in the example) to write data to the PRCMD register (<3> in the example).

The same applies when a general-purpose register is used for addressing.

(2) Command register (PRCMD)

The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system

from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access

to a special register is valid after data has been written in advance to the PRCMD register. In this way, the value of

the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write

access.

The PRCMD register is write-only, in 8-bit units (undefined data is read when this register is read).

After reset: Undefined W Address: FFFFF1FCH

REG7PRCMD

REG65REG54REG43REG32REG21REG10REG0

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

(3) System status register (SYS)

Status flags that indicate the operation status of the overall system are allocated to this register.

This register can be read or written in 8-bit or 1-bit units.

Reset sets this register to 00H.

After reset: 00H R/W Address: FFFFF802H

< >

SYS 0 0 0 0 0 0 PRERR

PRERR

Protection error did not occur.

Protection error occurred.

The PRERR flag operates under the following conditions.

(a) Set condition (PRERR flag = 1)

(i) When data is written to a special register without writing anything to the PRCMD register (when <4> is

executed without executing <3> in 3.4.7 (1) Setting data to special registers)

(ii) When data is written to an on-chip peripheral I/O register other than a special register (including execution

of a bit manipulation instruction) after writing data to the PRCMD register (if <4> in 3.4.7 (1) Setting data

to special registers is not the setting of a special register)

Remark Even if an on-chip peripheral I/O register is read (except by a bit manipulation instruction) or the

internal RAM is accessed between an operation to write the PRCMD register and an operation to

write a special register, the PRERR flag is not set, and the set data can be written to the special

(b) Clear condition (PRERR flag = 0)

(i) When 0 is written to the PRERR flag

(ii) When the system is reset

Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register,

immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0 (the

write access takes precedence).

2. If data is written to the PRCMD register, which is not a special register, immediately after a

write access to the PRCMD register, the PRERR bit is set to 1.

Detects protection error

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

3.4.8 Registers to be set first

Be sure to set the following registers first when using the V850ES/JC3-L, V850ES/JE3-L.

• System wait control register (VSWC)

• On-chip debug mode register (OCDM)

• Watchdog timer mode register 2 (WDTM2)

After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.

(a) System wait control register (VSWC)

The VSWC register controls wait of bus access to the on-chip peripheral I/O registers.

Three clock cycles are required to access an on-chip peripheral I/O register (without a wait cycle). The

V850ES/JC3-L, V850ES/JE3-L require wait cycles according to the operating frequency. Set the following

value to the VSWC register in accordance with the frequency used.

This register can be read or written in 8-bit units.

Reset sets this register to 77H (number of waits: 14).

After reset: 77H R/W Address: FFFFF06EH

76543210

VSWC

Operating Frequency (fCLK) Set Value of VSWC Number of Waits

32 kHz ≤ fCLK < 16.6 MHz 00H 0 (no waits)

16.6 MHz ≤ fCLK ≤ 20 MHz 01H 1

(b) On-chip debug mode register (OCDM)

For details, see CHAPTER 29 ON-CHIP DEBUG FUNCTION.

The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2.

Watchdog timer 2 automatically starts in the reset mode after reset is released. To specify the operation of

watchdog timer 2, write to the WDTM2 register after reset is released.

For details, see CHAPTER 11 WATCHDOG TIMER 2.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION

3.4.9 Cautions

(1) Accessing special on-chip peripheral I/O registers

This product has two types of internal system buses.

One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.

The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and an

access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is a

possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is

accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next instruction

but enters the wait status. If this wait status occurs, the number of clocks required to execute an instruction

increases by the number of wait clocks shown below.

This must be taken into consideration if real-time processing is required.

When special on-chip peripheral I/O registers are accessed, more wait states may be required in addition to the

wait states set by the VSWC register.

The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks) at this

time are shown below.

Table 3-3. Registers That Requires Waits

Peripheral Function Register Name Access k

16-bit timer/event counter P (TMP)

(n = 0 to 5)

16-bit timer/event counter Q (TMQ)

Watchdog timer 2 (WDT2) WDTM2

Real-time output function (RTO) RTBL0, RTBH0

A/D converter

I2C00 to I2C02 IICS0 to IICS2 Read 1

CRC CRCD Write 1

TPnCNT Read 1 or 2

TPnCCR0, TPnCCR1

TQ0CNT Read 1 or 2

TQ0CCR0 to TQ0CCR3

ADA0M0 Read 1 or 2

ADA0CR0 to ADA0CR9 Read 1 or 2

ADA0CR0H to ADA0CR9H Read 1 or 2

Write

Read 1 or 2

Write

Read 1 or 2

Write

(when WDT2 operating)

Write

(RTPC0.RTPOE0 bit = 0)

• 1

• Continuous write: 3 or 4

• 1

• Continuous write: 3 or 4

access: No wait

Number of clocks necessary for access = 3 + i + j + (2 + j) × k

Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is generated,

it can only be cleared by a reset.

• When the CPU operates on the subclock and main clock oscillation is stopped

• When the CPU operates on the internal oscillator clock

Remark i: Value (0) of higher 4 bits of VSWC register

j: Value (0 or 1) of lower 4 bits of VSWC register

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(2) Conflict between sld instruction and interrupt request

(a) Description

If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction

following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution

result of the instruction in <1> may not be stored in a register.

Instruction <1>

• ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu

• sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu

• Multiplication instruction: mul, mulh, mulhi, mulu

Instruction <2>

satsub reg1, reg2

xor reg1, reg2

sub reg1, reg2

cmp imm5, reg2

shl imm5, reg2

<i> ld.w [r11], r10 If the decode operation of the mov instruction <ii> immediately before the sld

<ii> mov r10, r28

<iii> sld.w 0x28, r10

(b) Countermeasure

<1> When compiler (CA850) is used

Use CA850 Ver. 2.61 or later because generation of the corresponding instruction sequence can be

<2> For assembler

When executing the sld instruction immediately after instruction <ii>, avoid the above operation using

mov reg1, reg2

satadd reg1, reg2

and reg1, reg2

add reg1, reg2

mulh reg1, reg2

•

not reg1, reg2

satadd imm5, reg2

tst reg1, reg2

add imm5, reg2

shr imm5, reg2

instruction <iii> and an interrupt request conflict before execution of the ld instruction

<i> is complete, the execution result of instruction <i> may not be stored in a register.

satsubr reg1, reg2

or reg1, reg2

subr reg1, reg2

cmp reg1, reg2

sar imm5, reg2

automatically suppressed.

either of the following methods.

• Insert a nop instruction immediately before the sld instruction.

• Do not use the same register as the sld instruction destination register in the above instruction <ii>

executed immediately before the sld instruction.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS

CHAPTER 4 PORT FUNCTIONS

4.1 Features

4.1.1 V850ES/JC3-L (40-pin)

{ I/O port pins: 27

• N-ch open-drain output selectable: 20 (5 V tolerant: 17)

{ Input/output specifiable in 1-bit units

4.1.2 V850ES/JC3-L (48-pin)

{ I/O port pins: 34

• N-ch open-drain output selectable: 25 (5 V tolerant: 20)

{ Input/output specifiable in 1-bit units

4.1.3 V850ES/JE3-L

{ I/O port pins: 50

• N-ch open-drain output selectable: 37 (5 V tolerant: 28)

{ Input/output specifiable in 1-bit units

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS

4.2 Basic Port Configuration

4.2.1 V850ES/JC3-L (40-pin)

The V850ES/JC3-L (40-pin) features a total of 27 I/O port pins organized as ports 0, 3 to 5, 7, 9, CM, and DL. The port

configuration is shown below.

Figure 4-1. Port Configuration (V850ES/JC3-L (40-pin))

Port 0

Port 3

Port 4

Port 5

P02 P03 P05

P30 P31 P40

P42

P50

P55

Caution Ports 0, 3 to 5, and 9 (P90, P91, P96) are 5 V tolerant.

Table 4-1. I/O Buffer Power Supplies for Pins (V850ES/JC3-L (40-pin))

P70

Port 7

P74

P90 P91 P96

P97 P914 P915

PCM0 Port CM

PDL5 Port DL

Port 9

Power Supply Corresponding Pins

AVREF0 Port 7

EVDD RESET, ports 0, 3 to 5, 9, CM, DL

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4.2.2 V850ES/JC3-L (48-pin)

The V850ES/JC3-L (48-pin) features a total of 34 I/O port pins organized as ports 0, 1, 3 to 5, 7, 9, CM, and DL. The

port configuration is shown below.

Figure 4-2. Port Configuration (V850ES/JC3-L (48-pin))

Port 0

Port 1

Port 3

Port 4

Port 5

P02 P03 P05

P10

P30

P32 P38 P39

P40

P42

P50

P55

Caution Ports 0, 3 to 5, and 9 (P90, P91, P96) are 5 V tolerant.

Table 4-2. I/O Buffer Power Supplies for Pins (V850ES/JC3-L (48-pin))

P70

Port 7

P75

P90

P91

P96

Port 9

P99 P914 P915

PCM0 Port CM

PDL5 Port DL

Power Supply Corresponding Pins

AVREF0 Port 7

AVREF1 Port 1

EVDD RESET, ports 0, 3 to 5, 9, CM, DL

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS

4.2.3 V850ES/JE3-L

The V850ES/JE3-L features a total of 50 I/O port pins organized as ports 0, 1, 3 to 5, 7, 9, CM, and DL. The port

configuration is shown below.

Figure 4-3. Port Configuration (V850ES/JE3-L)

Port 0

Port 1

Port 3

Port 4

Port 5

P02

P06

P10

P30

P35 P38 P39

P40

P42

P50

P55

Caution Ports 0, 3 to 5, and 9 (P90 to P94, P96) are 5 V tolerant.

Table 4-3. I/O Buffer Power Supplies for Pins (V850ES/JE3-L)

P70

Port 7

P79

P90

P94

P96

P915

PCM0 Port CM

PDL5 Port DL

Port 9

Power Supply Corresponding Pins

AVREF0 Port 7

AVREF1 Port 1

EVDD RESET, ports 0, 3 to 5, 9, CM, DL

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS

4.3 Port Configuration

The ports consist of the following hardware.

Table 4-4. Port Configuration (V850ES/JC3-L (40-pin))

Item Configuration

Control registers

Port pins I/O: 34

Item Configuration

Control registers

Port pins I/O: 34

Port n mode register (PMn: n = 0, 3 to 5, 7, 9, CM, DL)

Port n mode control register (PMCn: n = 0, 3 to 5, 9)

Port n function control register (PFCn: n = 0, 3 to 5, 9)

Port n function control expansion register (PFCEn: n = 0, 5, 9 )

Port n function register (PFn: n = 0, 3 to 5, 9)

Table 4-5. Port Configuration (V850ES/JC3-L (48-pin))

Port n mode register (PMn: n = 0, 1, 3 to 5, 7, 9, CM, DL)

Port n mode control register (PMCn: n = 0, 3 to 5, 9)

Port n function control register (PFCn: n = 0, 3 to 5, 9)

Port n function control expansion register (PFCEn: n = 0, 3, 5, 9 )

Port n function register (PFn: n = 0, 3 to 5, 9)

Table 4-6. Port Configuration (V850ES/JE3-L)

Item Configuration

Control registers

Port pins I/O: 50

Port n mode register (PMn: n = 0, 1, 3 to 5, 7, 9, CM, DL)

Port n mode control register (PMCn: n = 0, 3 to 5, 9)

Port n function control register (PFCn: n = 0, 3 to 5, 9)

Port n function control expansion register (PFCEn: n = 0, 3, 5, 9 )

Port n function register (PFn: n = 0, 3 to 5, 9)

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS

(1) Port n register (Pn)

Data I/O with external devices is performed by writing to and reading from the Pn register. The Pn register is made

up of a port latch that retains the output data and a circuit that reads the pin status.

Each bit of the Pn register corresponds to one pin of port n and can be read or written in 1-bit units.

After reset: 00H

Note

(output latch) R/W

Pn7

Pn6 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0

01237567

Pnm

0 is output.

1 is output.

Control of output data (in output mode)

Note This value is undefined for input-only ports.

The operation when writing or reading the Pn register differs depending on the specified mode.

Table 4-7. Reading and Writing Pn Register

PMCn Register Setting PMn Register Setting Writing Pn Register Reading Pn Register

Port mode

(PMCnm bit = 0)

Alternate-function mode

(PMCnm bit = 1)

Output mode

(PMnm bit = 0)

Input mode

(PMnm bit = 1)

Output mode

(PMnm bit = 0)

Input mode

(PMnm bit = 1)

Write to the output latch

The contents of the output latch are output

from the pin.

Write to the output latch

The status of the pin is not affected.

Write to the output latch

The status of the pin is not affected.

The pin operates as an alternate-function

pin.

Write to the output latch

The status of the pin is not affected.

The pin operates as an alternate-function

pin.

Note

The value of the output

latch is read.

The pin status is read.

The value of the output

latch is read.

The pin status is read.

Note The value written to the output latch is retained until a new value is written to the output latch.

The output latch value is cleared by a reset.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS

(2) Port n mode register (PMn)

PMn specifies the input mode or output mode of the port.

Each bit of the PMn register corresponds to one pin of port n and can be specified in 1-bit units.

After reset: FFH R/W

PMn

PMn7

PMnm

PMn6 PMn5 PMn4 PMn3 PMn2 PMn1 PMn0

Control of I/O mode

Output mode

Input mode

(3) Port n mode control register (PMCn)

If the port function and the alternate function need to be switched, specify the port mode or the alternate function

mode by using this register.

Each bit of the PMCn register corresponds to one pin of port n and can be specified in 1-bit units.

After reset: 00H R/W

PMCn

PMCn7 PMCn6 PMCn5 PMCn4 PMCn3 PMCn2 PMCn1 PMCn0

PMCnm

Port mode

Alternate function mode

Specification of operation mode

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(4) Port n function control register (PFCn)

PFCn is a register that specifies the alternate function to be used when one pin has two or more alternate functions.

Each bit of the PFCn register corresponds to one pin of port n and can be specified in 1-bit units.

After reset: 00H R/W

PFCn

PFCn7 PFCn6 PFCn5 PFCn4 PFCn3 PFCn2 PFCn1 PFCn0

PFCnm

Alternate function 1

Alternate function 2

Specification of alternate function

(5) Port n function control expansion register (PFCEn)

The PFCEn register specifies the alternate function of a port pin in combination with the PFCn register if the pin

has three or more alternate functions.

Each bit of the PFCEn register corresponds to one pin of port n and can be specified in 1-bit units.

After reset: 00H R/W

PFCEn

PFCn

PFCEn7 PFCEn6 PFCEn5 PFCEn4 PFCEn3 PFCEn2 PFCEn1 PFCEn0

PFCn7 PFCn6 PFCn5 PFCn4 PFCn3 PFCn2 PFCn1 PFCn0

PFCEnm

PFCnm

Alternate function 1

Alternate function 2

Alternate function 3

Alternate function 4

Specification of alternate function

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS

(6) Port n function register (PFn)

PFn is a register that specifies normal output (CMOS output) or N-ch open-drain output.

Each bit of the PFn register corresponds to one pin of port n and can be specified in 1-bit units.

After reset: 00H R/W

PFn

PFn7 PFn6 PFn5 PFn4 PFn3 PFn2 PFn1 PFn0

Note

PFnm

Specification of normal output (CMOS output)/N-ch open-drain output

Normal output (CMOS output)

N-ch open-drain output

Note Regardless of the settings of the PMCn register, the PFnm bit is valid only if the

PMn.PMnm bit is set to 0 (output mode). If the PMnm bit is set to 1 (input mode), the

values specified for the PFn register are invalid.

Example <1> The PFn register values are valid when:

PFnm bit = 1 … N-ch open drain output is specified.

PMnm bit = 0 … Output mode is specified.

PMCnm bit = Any value

<2> The PFn register values are invalid when:

PFnm bit = 1 … N-ch open drain output is specified.

PMnm bit = 1 … Input mode is specified.

PMCnm bit = Any value

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS

(7) Port setting

Set a port as illustrated below.

Figure 4-4. Setting of Each Register and Pin Function

Port mode

Output mode

Input mode

Alternate function

(when two alternate

functions are available)

Alternate function 1

Alternate function 2

Alternate function

(when three or more alternate

functions are available)

Alternate function 1

Alternate function 2

Alternate function 3

Alternate function 4

(a)

(b)

(c)

(d)

“0”

“1”

“0”

“1”

PMn register

PFCn register

PFCEn register

“0”

“1”

(a) (b) (c) (d)

PMCn register

PFCEnm

0 0 1 1

PFCnm

0 1 0 1

Remark Set the alternate functions in the following sequence.

<1> Set the PFCn and PFCEn registers.

<2> Set the PMCn register.

<3> Set the INTRn or INTFn register (to specify an external interrupt pin).

If the PMCn register is set first, an unintended function may be set while the PFCn and PFCEn

registers are being set.

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS

4.3.1 Port 0

Port 0 is a 5-bit port (V850ES/JE3-L) or a 3-bit port (V850ES/JC3-L (40-pin), V850ES/JC3-L (48-pin)) for which I/O

settings can be controlled in 1-bit units.

Port 0 includes the following alternate-function pins.

Table 4-8. Port 0 Alternate-Function Pins

Pin No. Alternate Function

JC3L

(40)

(48)

11 13 17 P02 NMI Input L-1

12 14 18 P03 INTP0/ADTRG/RTC1HZ Input/Output U-15

− −

27 31 41 P05 INTP2/DRST

− −

Function Name

JE3L

19 P04 INTP1/RTCDIV/RTCCL Input/Output N-2

20 P06 INTP3 Input

Name I/O

Note

Input AA-1

Remark Block Type

Selectable as N-ch

open-drain output

L-1

Note The DRST pin is used for on-chip debugging.

If on-chip debugging is not used, fix the P05/INTP2/DRST pin to low level between when the reset signal of the

RESET pin is released and when the OCDM.OCDM0 bit is cleared (0).

For details, see 4.6.3 Cautions on on-chip debug pins.

Caution The P02 to P06 pins have hysteresis characteristics in the input mode of the alternate function, but

do not have hysteresis characteristics in the port mode.

Remark JC3L (40): V850ES/JC3-L (40-pin products)

JC3L (48): V850ES/JC3-L (48-pin products)

JE3L: V850ES/JE3-L

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V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS

(1) Port 0 register (P0)

(a) V850ES/JC3-L (40-pin), V850ES/JC3-L (48-pin)

After reset: 00H (output latch) R/W Address: FFFFF400H

(b) V850ES/JE3-L

P0 0 P05 0 P03 P02 0 0

P0n

Output data control (in output mode) (n = 2, 3, 5)

Outputs 0

Outputs 1

After reset: 00H (output latch) R/W Address: FFFFF400H

P0 P06 P05 P04 P03 P02 0 0

P0n

Output data control (in output mode) (n = 2 to 6)

Outputs 0

Outputs 1

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