RENESAS UPD 78F9177 AGB Datasheet

User’s Manual

µ

PD789167, 789177, 789167Y,

8-Bit Single-Chip Microcontrollers

µ

PD789166

789177Y Subseries

µ

PD789166Y

µ

PD789166(A1)

µ

PD789167

µ

PD789176

µ

PD789177

µ

PD78F9177

µ

PD78F9177A

µ

PD789166(A)

µ

PD789167(A)

µ

PD789176(A)

µ

PD789177(A)

µ

PD78F9177A(A) µPD78F9177AY(A)

Document No. U14186EJ6V0UD00 (6th edition)
Date Published March 2005 NS CP(K)

µ

PD789167Y

µ

PD789176Y

µ

PD789177Y

µ

PD78F9177Y

µ

PD78F9177AY

µ

PD789166Y(A)

µ

PD789167Y(A)

µ

PD789176Y(A)

µ

PD789177Y(A)

µ

PD789167(A1)

µ

PD789176(A1)

µ

PD789177(A1)

µ

PD78F9177A(A1)

µ

PD789166(A2)

µ

PD789167(A2)

µ

PD789176(A2)

µ

PD789177(A2)

©

Printed in Japan

2003

[MEMO]

2

User’s Manual U14186EJ6V0UD

NOTES FOR CMOS DEVICES

1

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

IL

CMOS device stays in the area between V

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V

IH

(MIN).

V

HANDLING OF UNUSED INPUT PINS

2

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

3

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

(MAX) and VIH (MIN) due to noise, etc., the device may

IL

(MAX) and

DD

or GND

4

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

5

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

6

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

FIP and EEPROM are trademarks of NEC Electronics Corporation.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the

United States and/or other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

User’s Manual U14186EJ6V0UD

3

These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.

Purchase of NEC Electronics I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I
defined by Philips.

2

C system, provided that the system conforms to the I2C Standard Specification as

•

The information in this document is current as of March, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

•

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative

•

purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.

•

While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.

•

NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer­designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.

"Standard":

Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.

"Special":

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).

"Specific":

Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.

(Note)
(1)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.

(2)

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).

M8E 02. 11-1

4

User’s Manual U14186EJ6V0UD

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:

•

Device availability

•

Ordering information

•

Product release schedule

•

Availability of related technical literature

•

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html

NEC Electronics America, Inc. (U.S.)

Santa Clara, California
Tel: [phone]
800-366-9782

N

EC Electronics (Europe) GmbH

Duesseldorf, Germany
Tel: [phone]

•

Sucursal en España

Madrid, Spain
Tel: [phone]

•

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Tel: [phone]

•

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•

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Tel: [phone]

•

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•

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Tel: [phone]

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Hong Kong
Tel: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]

NEC Electronics Shanghai Ltd.

Shanghai, P.R. China
Tel: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]

NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore
Tel: [phone]

J04.1

User’s Manual U14186EJ6V0UD

5

INTRODUCTION

Readers This manual is intended for user engineers who wish to understand the functions of

the

µ

PD789167, 789177, 789167Y, and 789177Y Subseries in order to design and

develop its application systems and programs.

Target products:

•

µ

PD789167 Subseries: µPD789166, 789167, 789166(A), 789167(A),

789166(A1), 789167(A1), 789166(A2), 789167(A2)

•

µ

PD789177 Subseries: µPD789176, 789177, 78F9177, 78F9177A,

789176(A), 789177(A), 78F9177A(A), 789176(A1),

789177(A1), 78F9177A(A1), 789176(A2),

789177(A2)

•

µ

PD789167Y Subseries: µPD789166Y, 789167Y, 789166Y(A), 789167Y(A)

•

µ

PD789177Y Subseries: µPD789176Y, 789177Y, 78F9177Y, 78F9177AY,

789176Y(A), 789177Y(A), 78F9177AY(A)

The

µ

PD789167, 789177, 789167Y, and 789177Y Subseries is a generic term for all

the target devices in this manual.

The generic terms used in this manual indicate the following products.

“Standard quality grade products”...

78F9177A, 789166Y, 789167Y, 789176Y, 789177Y, 78F9177Y, 78F9177AY

“(A) products”...

“(A1) products”...

“(A2) products”...

“Mask ROM versions”...

“Flash memory versions”...

Purpose This manual is intended to give users an understanding of the functions described in

the Organization below.

µ

PD789166(A), 789167(A), 789176(A), 789177(A),

78F9177A(A), 789166Y(A), 789167Y(A), 789176Y(A),

789177Y(A), 78F9177AY(A)

µ

PD789166(A1), 789167(A1), 789176(A1), 789177(A1),

78F9177A(A1)

µ

PD789166(A2), 789167(A2), 789176(A2), 789177(A2)

µ

PD789166, 789167, 789176, 789177, 78F9177,

µ

PD789166, 789167, 789176, 789177, 789166Y,

789167Y, 789176Y, 789177Y, 789166(A), 789167(A),

789176(A), 789177(A), 789166Y(A), 789167Y(A),

789176Y(A), 789177Y(A), 789166(A1), 789167(A1),

789176(A1), 789177(A1), 789166(A2), 789167(A2),

789176(A2), 789177(A2)

µ

PD78F9177, 78F9177A, 78F9177A(A),

78F9177A(A1), 78F9177Y, 78F9177AY,

78F9177AY(A)

6

User’s Manual U14186EJ6V0UD

Organization The

µ

PD789167, 789177, 789167Y, 789177Y Subseries manual is divided into two

parts: this manual and the instruction manual (common to the 78K/0S Series).

µ

PD789167, 789177, 789167Y,

789177Y Subseries

User's Manual

(This manual)

78K/0S Series

Instruction

User's Manual

• Pin functions

• Internal block functions

• Interrupts

• Other internal peripheral functions

• Electrical specifications

How to Read This Manual It is assumed that the readers of this manual have general knowledge of electric

engineering, logic circuits, and microcontrollers.

◊ For users who use this document as the manual for the µPD789166(A), 789167(A),

789176(A), 789177(A), 789166Y(A), 789167Y(A), 789176Y(A), 789177Y(A),

789166(A1), 789167(A1), 789176(A1), 789177(A1), 789166(A2), 789167(A2),

789176(A2), 789177(A2), 78F9177A(A), 78F9177AY(A), and 78F9177A(A1)
→ The only differences between standard products and (A) products, (A1)

products, and (A2) products are quality grades, power supply voltage,

operating ambient temperature, minimum instruction execution time, and

electrical specifications. (Refer to 1.10 Differences Between Standard Quality

Grade Products and (A) Products, (A1) Products, and (A2) Products, and 2.10

Differences Between Standard Quality Grade Products and (A) Products.) For

(A) products, (A1) products, and (A2) products, read the part numbers

indicated in Chapters 3 to 22 in the following manner.

µ

PD789166 → µPD789166(A), 789166(A1), 789166(A2)

µ

PD789167 → µPD789167(A), 789167(A1), 789167(A2)

µ

PD789176 → µPD789176(A), 789176(A1), 789176(A2)

µ

PD789177 → µPD789177(A), 789177(A1), 789177(A2)

µ

PD789166Y → µPD789166Y(A)

µ

PD789167Y → µPD789167Y(A)

µ

PD789176Y → µPD789176Y(A)

µ

PD789177Y → µPD789177Y(A)

µ

PD78F9177A → µPD789177A(A), 78F9177A(A1)

µ

PD78F9177AY → µPD78F9177AY(A)

◊ To understand the overall functions of the

789177Y Subseries

→ Read this manual in the order of the CONTENTS.

◊ How to read register formats
→ The name of a bit whose number is enclosed with < > is reserved in the

assembler and is defined as an sfr variable by the #pragma sfr directive in the C

compiler.

◊ To learn the detailed functions of a register whose register name is known
→ See APPENDIX C REGISTER INDEX.

• CPU function

• Instruction set

• Instruction description

µ

PD789167, 789177, 789167Y, and

User’s Manual U14186EJ6V0UD

7

◊ To learn the details of the instruction functions of the 78K/0S Series

→ Refer to 78K/0S Series Instructions User's Manual (U11047E) separately

available.

◊ To know the electrical specifications of the

789177Y Subseries

→ Refer to CHAPTER 23 ELECTRICAL SPECIFICATIONS (

16xY, 17xY, 16x(A), 17x(A), 16xY(A), 17xY(A)), CHAPTER 25

ELECTRICAL SPECIFICATIONS (

78917x(A2)), CHAPTER 27 ELECTRICAL SPECIFICATIONS

(

µ

PD78F9177A, 78F9177AY, 78F9177A(A), 78F9177AY(A)), CHAPTER 28

ELECTRICAL SPECIFICATIONS (

CHAPTER 30 ELECTRICAL SPECIFICATIONS (

Caution The application examples in this manual are created for “Standard”

quality grade products for general electric equipment. When using

the application examples in this manual for purposes which require

“Special” quality grades, thoroughly examine the quality grade of

each part and circuit actually used.

µ

PD789167, 789177, 789167Y, and

µ

PD78916x, 17x,

µ

PD78916x(A1), 78917x(A1), 78916x(A2),

µ

PD78F9177, 78F9177AY), and

µ

PD78F9177A(A1)).

8

User’s Manual U14186EJ6V0UD

Differences between µPD789167, 789177, 789167Y, and 789177Y Subseries

The

µ

PD789167, 789177, 789167Y, and 789177Y Subseries differ in their package type, A/D converter resolution,

and serial interface configuration.

Subseries
Item

Package • 44-pin plastic LQFP • 44-pin plastic LQFP

IC2 pin Not provided Provided

A/D converter resolution 8 bits 10 bits 8 bits 10 bits

3-wire serial I/O mode 1 channel Serial interface

configuration

SMB0 Not provided 1 channel

µ

PD789167

µ

PD789177

µ

PD789167Y

• 48-pin plastic TQFP

µ

PD789177Y

Configuration of This Manual This manual uses separate chapters to describe the functions that vary between the

subseries. The chapters related to each subseries are listed below.

For information about a certain subseries, see only the chapters indicated by

checkmarks in that subseries’ column.

Chapter

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES)

CHAPTER 3 PIN FUNCTIONS (µPD789167 AND 789177
SUBSERIES

CHAPTER 4 PIN FUNCTIONS (µPD789167Y AND 789177Y
SUBSERIES)

CHAPTER 5 CPU ARCHITECTURE

CHAPTER 6 PORT FUNCTIONS

CHAPTER 7 CLOCK GENERATOR

CHAPTER 8 16-BIT TIMER 90

CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 80 TO 82

CHAPTER 10 WATCH TIMER

CHAPTER 11 WATCHDOG TIMER

CHAPTER 12 8-BIT A/D CONVERTER (µPD789167 AND 789167Y
SUBSERIES)

CHAPTER 13 10-BIT A/D CONVERTER (µPD789177 AND 789177Y
SUBSERIES)

CHAPTER 14 SERIAL INTERFACE 20

CHAPTER 15 SMB0 (µPD789167Y AND 789177Y SUBSERIES)

CHAPTER 16 MULTIPLIER

CHAPTER 17 INTERRUPT FUNCTIONS

CHAPTER 18 STANDBY FUNCTION

CHAPTER 19 RESET FUNCTION

CHAPTER 20 FLASH MEMORY VERSION

CHAPTER 21 MASK OPTION

CHAPTER 22 INSTRUCTION SET

µ

PD789167

Subseries

√ √ − −

− − √ √

√ √ − −

− − √ √

√ √ √ √

√ √ √ √

√ √ √ √

√ √ √ √

√ √ √ √

√ √ √ √

√ √ √ √

√ − √ −

− √ − √

√ √ √ √

− − √ √

√ √ √ √

√ √ √ √

√ √ √ √

√ √ √ √

√ √ √ √

√ √ √ √

√ √ √ √

µ

PD789177

Subseries

µ

PD789167Y

Subseries

µ

PD789177Y

Subseries

User’s Manual U14186EJ6V0UD

9

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representation: ××× (overscore over pin or signal name)

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information
Numerical representation: Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents Related to Devices

Document Name Document No.

µ

PD789167, 789177, 789167Y, 789177Y Subseries User's Manual This manual

78K/0S Series Instructions User's Manual U11047E

Documents Related to Development Tools (Software) (User's Manuals)

Document Name Document No.

RA78K0S Assembler Package

ID78K0S-NS Ver. 2.52 Integrated Debugger Operation U16584E

PM plus Ver. 5.10 U16569E

Operation U16656E

Language U14877E

Structured Assembly Language U11623E

Operation U16654E CC78K0S C Compiler

Language U14872E

Operation U16768E SM78K Series Ver. 2.52 System Simulator

External Parts User Open Interface Specifications U15802E

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document for designing.

10

User’s Manual U14186EJ6V0UD

Documents Related to Development Tools (Hardware) (User’s Manuals)

Document Name Document No.

IE-78K0S-NS In-Circuit Emulator U13549E

IE-78K0S-NS-A In-Circuit Emulator U15207E

IE-789177-NS-EM1 Emulation Board U14621E

Documents Related to Flash Memory Writing

Document Name Document No.

PG-FP3 Flash Memory Programmer User’s Manual U13502E

PG-FP4 Flash Memory Programmer User’s Manual U15260E

Other Related Documents

Document Name Document No.

SEMICONDUCTORS SELECTION GUIDE Product & Packages X13769X

Semiconductor Device Mount Manual Note

Quality Grades on NEC Semiconductor Device C11531E

NEC Semiconductor Device Reliability/Quality Control System C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E

Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html)

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document for designing.

User’s Manual U14186EJ6V0UD

11

CONTENTS

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)....................................................19

1.1 Expanded-Specification Products and Conventional Products ...........................................19

1.2 Features ...................................................................................................................................... 20

1.3 Applications................................................................................................................................20

1.4 Ordering Information .................................................................................................................21

1.5 Quality Grades............................................................................................................................22

1.6 Pin Configuration (Top View)....................................................................................................23

1.7 78K/0S Series Lineup.................................................................................................................26

1.8 Block Diagram ............................................................................................................................29

1.9 Outline of Functions ..................................................................................................................30

1.10 Differences Between Standard Quality Grade Products and (A) Products,

(A1) Products, and (A2) Products ..........................................................................................32

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES) ...............................................33

2.1 Expanded-Specification Products and Conventional Products ...........................................33

2.2 Features ...................................................................................................................................... 34

2.3 Applications................................................................................................................................34

2.4 Ordering Information .................................................................................................................35

2.5 Quality Grades............................................................................................................................36

2.6 Pin Configuration (Top View)....................................................................................................37

2.7 78K/0S Series Lineup.................................................................................................................40

2.8 Block Diagram ............................................................................................................................42

2.9 Outline of Function ....................................................................................................................43

2.10 Differences Between Standard Quality Grade Products and (A) Products .........................45

CHAPTER 3 PIN FUNCTIONS (µPD789167 AND 789177 SUBSERIES) ........................................46

3.1 Pin Function List ........................................................................................................................46

3.2 Description of Pin Functions ....................................................................................................48

3.2.1 P00 to P05 (Port 0)....................................................................................................................... 48

3.2.2 P10, P11 (Port 1).......................................................................................................................... 48

3.2.3 P20 to P26 (Port 2)....................................................................................................................... 48

3.2.4 P30 to P33 (Port 3)....................................................................................................................... 49

3.2.5 P50 to P53 (Port 5)....................................................................................................................... 49

3.2.6 P60 to P67 (Port 6)....................................................................................................................... 50

3.2.7 RESET ......................................................................................................................................... 50

3.2.8 X1, X2........................................................................................................................................... 50

3.2.9 XT1, XT2 ......................................................................................................................................50

3.2.10 AVDD ............................................................................................................................................ 50

3.2.11 AVSS ............................................................................................................................................ 50

3.2.12 AVREF ........................................................................................................................................... 50

3.2.13 VDD0, VDD1 .................................................................................................................................... 50

3.2.14 VSS0, VSS1 ..................................................................................................................................... 50

12

User’s Manual U14186EJ6V0UD

3.2.15 VPP (flash memory version only) ...................................................................................................51

3.2.16 IC0 (mask ROM version only).......................................................................................................51

3.2.17 IC3 ...............................................................................................................................................51

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................52

CHAPTER 4 PIN FUNCTIONS (µPD789167Y AND 789177Y SUBSERIES)....................................54

4.1 Pin Function List ........................................................................................................................54

4.2 Description of Pin Functions ....................................................................................................56

4.2.1 P00 to P05 (Port 0)....................................................................................................................... 56

4.2.2 P10, P11 (Port 1).......................................................................................................................... 56

4.2.3 P20 to P26 (Port 2)....................................................................................................................... 56

4.2.4 P30 to P33 (Port 3)....................................................................................................................... 57

4.2.5 P50 to P53 (Port 5)....................................................................................................................... 57

4.2.6 P60 to P67 (Port 6)....................................................................................................................... 58

4.2.7 RESET.......................................................................................................................................... 58

4.2.8 X1, X2........................................................................................................................................... 58

4.2.9 XT1, XT2 ......................................................................................................................................58

4.2.10 AVDD ............................................................................................................................................58

4.2.11 AVSS .............................................................................................................................................58

4.2.12 AVREF ...........................................................................................................................................58

4.2.13 VDD0, VDD1 ....................................................................................................................................58

4.2.14 VSS0, VSS1 .....................................................................................................................................58

4.2.15 VPP (flash memory version only) ...................................................................................................59

4.2.16 IC0 (mask ROM version only).......................................................................................................59

4.2.17 IC2................................................................................................................................................ 59

4.3 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................60

CHAPTER 5 CPU ARCHITECTURE ......................................................................................................62

5.1 Memory Space ............................................................................................................................62

5.1.1 Internal program memory space................................................................................................... 65

5.1.2 Internal data memory (internal high-speed RAM) space............................................................... 66

5.1.3 Special-function register (SFR) area............................................................................................. 66

5.1.4 Data memory addressing.............................................................................................................. 66

5.2 Processor Registers ..................................................................................................................69

5.2.1 Control registers ...........................................................................................................................69

5.2.2 General-purpose registers ............................................................................................................72

5.2.3 Special-function registers (SFR) ................................................................................................... 73

5.3 Instruction Address Addressing ..............................................................................................76

5.3.1 Relative addressing ......................................................................................................................76

5.3.2 Immediate addressing ..................................................................................................................77

5.3.3 Table indirect addressing.............................................................................................................. 78

5.3.4 Register addressing......................................................................................................................78

5.4 Operand Address Addressing ..................................................................................................79

5.4.1 Direct addressing.......................................................................................................................... 79

5.4.2 Short direct addressing.................................................................................................................80

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13

5.4.3 Special-function register (SFR) addressing .................................................................................. 81

5.4.4 Register addressing...................................................................................................................... 82

5.4.5 Register indirect addressing ......................................................................................................... 83

5.4.6 Based addressing......................................................................................................................... 84

5.4.7 Stack addressing .......................................................................................................................... 84

CHAPTER 6 PORT FUNCTIONS ...........................................................................................................85

6.1 Port Functions............................................................................................................................85

6.2 Port Configuration .....................................................................................................................87

6.2.1 Port 0............................................................................................................................................ 87

6.2.2 Port 1............................................................................................................................................ 88

6.2.3 Port 2............................................................................................................................................ 89

6.2.4 Port 3............................................................................................................................................ 94

6.2.5 Port 5............................................................................................................................................ 97

6.2.6 Port 6............................................................................................................................................ 98

6.3 Port Function Control Registers ..............................................................................................99

6.4 Operation of Port Functions ...................................................................................................102

6.4.1 Writing to I/O port .......................................................................................................................102

6.4.2 Reading from I/O port .................................................................................................................102

6.4.3 Arithmetic operation of I/O port................................................................................................... 102

CHAPTER 7 CLOCK GENERATOR ....................................................................................................103

7.1 Clock Generator Functions.....................................................................................................103

7.2 Clock Generator Configuration ..............................................................................................103

7.3 Registers Controlling Clock Generator .................................................................................105

7.4 System Clock Oscillators........................................................................................................108

7.4.1 Main system clock oscillator ....................................................................................................... 108

7.4.2 Subsystem clock oscillator.......................................................................................................... 109

7.4.3 Examples of incorrect oscillator connection................................................................................ 110

7.4.4 Scaler .........................................................................................................................................111

7.4.5 When no subsystem clocks are used .........................................................................................111

7.5 Clock Generator Operation .....................................................................................................112

7.6 Changing Setting of System Clock and CPU Clock .............................................................113

7.6.1 Time required for switching between system clock and CPU clock ............................................ 113

7.6.2 Switching between system clock and CPU clock........................................................................114

CHAPTER 8 16-BIT TIMER 90............................................................................................................115

8.1 16-Bit Timer 90 Functions .......................................................................................................115

8.2 16-Bit Timer 90 Configuration.................................................................................................116

8.3 Registers Controlling 16-Bit Timer 90....................................................................................119

8.4 Operation of 16-Bit Timer 90...................................................................................................123

8.4.1 Operation as timer interrupt ........................................................................................................ 123

8.4.2 Operation as timer output ........................................................................................................... 125

8.4.3 Capture operation....................................................................................................................... 126

8.4.4 16-bit timer counter 90 readout................................................................................................... 127

14

User’s Manual U14186EJ6V0UD

8.4.5 Buzzer output operation.............................................................................................................. 128

8.5 Notes on 16-Bit Timer 90 .........................................................................................................129

8.5.1 Notes on using 16-bit timer 90.................................................................................................... 129

8.5.2 Restrictions on rewriting of 16-bit compare register 90............................................................... 131

CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 80 TO 82 .............................................................133

9.1 Functions of 8-Bit Timer/Event Counters 80 to 82 ...............................................................133

9.2 Configuration of 8-Bit Timer/Event Counters 80 to 82 .........................................................135

9.3 8-Bit Timer/Event Counters 80 to 82 Control Registers.......................................................138

9.4 Operation of 8-Bit Timer/Event Counters 80 to 82................................................................142

9.4.1 Operation as interval timer.......................................................................................................... 142

9.4.2 Operation as external event counter........................................................................................... 144

9.4.3 Operation as square wave output ............................................................................................... 145

9.4.4 PWM output operation ................................................................................................................ 147

9.5 Notes on Using 8-Bit Timer/Event Counters 80 to 82...........................................................149

CHAPTER 10 WATCH TIMER..............................................................................................................153

10.1 Watch Timer Functions ...........................................................................................................153

10.2 Watch Timer Configuration .....................................................................................................154

10.3 Watch Timer Control Register ................................................................................................155

10.4 Watch Timer Operation............................................................................................................156

10.4.1 Operation as watch timer ............................................................................................................ 156

10.4.2 Operation as interval timer.......................................................................................................... 156

CHAPTER 11 WATCHDOG TIMER .....................................................................................................158

11.1 Watchdog Timer Functions .....................................................................................................158

11.2 Watchdog Timer Configuration ..............................................................................................159

11.3 Watchdog Timer Control Registers........................................................................................160

11.4 Watchdog Timer Operation .....................................................................................................162

11.4.1 Operation as watchdog timer ...................................................................................................... 162

11.4.2 Operation as interval timer.......................................................................................................... 163

CHAPTER 12 8-BIT A/D CONVERTER (µPD789167 AND 789167Y SUBSERIES) .....................164

12.1 8-Bit A/D Converter Functions................................................................................................164

12.2 8-Bit A/D Converter Configuration .........................................................................................164

12.3 8-Bit A/D Converter Control Registers...................................................................................167

12.4 8-Bit A/D Converter Operation................................................................................................169

12.4.1 Basic operation of 8-bit A/D converter ........................................................................................ 169

12.4.2 Input voltage and conversion result ............................................................................................ 170

12.4.3 Operation mode of 8-bit A/D converter ....................................................................................... 172

12.5 Cautions Related to 8-Bit A/D Converter...............................................................................173

CHAPTER 13 10-BIT A/D CONVERTER (µPD789177 AND 789177Y SUBSERIES) ...................177

13.1 10-Bit A/D Converter Functions..............................................................................................177

13.2 10-Bit A/D Converter Configuration .......................................................................................177

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15

13.3 10-Bit A/D Converter Control Registers ................................................................................180

13.4 10-Bit A/D Converter Operation..............................................................................................182

13.4.1 Basic operation of 10-bit A/D converter ...................................................................................... 182

13.4.2 Input voltage and conversion result ............................................................................................ 183

13.4.3 Operation mode of 10-bit A/D converter ..................................................................................... 185

13.5 Cautions Related to 10-Bit A/D Converter.............................................................................186

CHAPTER 14 SERIAL INTERFACE 20 ..............................................................................................190

14.1 Functions of Serial Interface 20..............................................................................................190

14.2 Configuration of Serial Interface 20 .......................................................................................190

14.3 Control Registers of Serial Interface 20 ................................................................................194

14.4 Operation of Serial Interface 20 ..............................................................................................201

14.4.1 Operation stop mode .................................................................................................................. 201

14.4.2 Asynchronous serial interface (UART) mode.............................................................................. 203

14.4.3 3-wire serial I/O mode................................................................................................................. 217

CHAPTER 15 SMB0 (µPD789167Y AND 789177Y SUBSERIES)...................................................227

15.1 SMB0 Functions .......................................................................................................................227

15.2 SMB0 Configuration.................................................................................................................229

15.3 SMB0 Control Registers..........................................................................................................231

15.4 SMB0 Definition and Control Methods ..................................................................................245

15.4.1 Start condition............................................................................................................................. 245

15.4.2 Address ......................................................................................................................................246

15.4.3 Specification of transmission direction........................................................................................ 246

15.4.4 Acknowledge signal (ACK) .........................................................................................................247

15.4.5 Stop condition ............................................................................................................................. 248

15.4.6 Wait signal (WAIT)......................................................................................................................249

15.4.7 SMB0 interrupt (INTSMB0)......................................................................................................... 251

15.4.8 Interrupt request (INTSMB0) generation timing and wait control ................................................ 272

15.4.9 Matching address detection method ........................................................................................... 274

15.4.10 Error detection............................................................................................................................ 274

15.4.11 Extension code ........................................................................................................................... 274

15.4.12 Arbitration ................................................................................................................................... 275

15.4.13 Wakeup function......................................................................................................................... 276

15.4.14 Communication reservation ........................................................................................................ 277

15.4.15 Additional cautions...................................................................................................................... 279

15.4.16 Communication operation........................................................................................................... 280

15.5 Timing Charts ...........................................................................................................................282

CHAPTER 16 MULTIPLIER ..................................................................................................................289

16.1 Multiplier Function ...................................................................................................................289

16.2 Multiplier Configuration...........................................................................................................289

16.3 Multiplier Control Register......................................................................................................291

16.4 Multiplier Operation .................................................................................................................292

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User’s Manual U14186EJ6V0UD

CHAPTER 17 INTERRUPT FUNCTIONS ............................................................................................293

17.1 Interrupt Function Types.........................................................................................................293

17.2 Interrupt Sources and Configuration .....................................................................................293

17.3 Interrupt Function Control Registers .....................................................................................296

17.4 Interrupt Processing Operation..............................................................................................301

17.4.1 Non-maskable interrupt request acknowledgment operation......................................................301

17.4.2 Maskable interrupt request acknowledgment operation..............................................................303

17.4.3 Multiple interrupt processing ....................................................................................................... 305

17.4.4 Interrupt request hold.................................................................................................................. 307

CHAPTER 18 STANDBY FUNCTION ..................................................................................................308

18.1 Standby Function and Configuration.....................................................................................308

18.1.1 Standby function ......................................................................................................................... 308

18.1.2 Standby function control register ................................................................................................309

18.2 Operation of Standby Function ..............................................................................................310

18.2.1 HALT mode ................................................................................................................................310

18.2.2 STOP mode................................................................................................................................313

CHAPTER 19 RESET FUNCTION .......................................................................................................316

CHAPTER 20 FLASH MEMORY VERSION........................................................................................320

20.1 Flash Memory Characteristics ................................................................................................321

20.1.1 Programming environment .........................................................................................................321

20.1.2 Communication mode.................................................................................................................322

20.1.3 On-board pin processing ............................................................................................................ 326

20.1.4 Connection of adapter for flash writing .......................................................................................329

CHAPTER 21 MASK OPTION..............................................................................................................337

CHAPTER 22 INSTRUCTION SET ......................................................................................................338

22.1 Operation ..................................................................................................................................338

22.1.1 Operand identifiers and description methods.............................................................................. 338

22.1.2 Description of “Operation” column .............................................................................................. 339

22.1.3 Description of “Flag” column ....................................................................................................... 339

22.2 Operation List ...........................................................................................................................340

22.3 Instructions Listed by Addressing Type ...............................................................................345

CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD78916x, 17x, 16xY, 17xY, 16x(A), 17x(A),

16xY(A), 17xY(A))...........................................................................................................348

CHAPTER 24 CHARACTERISTICS CURVES (µPD78916x, 17x, 16xY, 17xY, 16x(A), 17x(A),

16xY(A), 17xY(A))...........................................................................................................367

User’s Manual U14186EJ6V0UD

17

µ

CHAPTER 25 ELECTRICAL SPECIFICATIONS (

PD78916x(A1), 17x(A1), 16x(A2), 17x(A2)).......370

CHAPTER 26 CHARACTERISTICS CURVES (µPD78916x(A1), 17x(A1), 16x(A2), 17x(A2)) ..........384

CHAPTER 27 ELECTRICAL SPECIFICATIONS (µPD78F9177A, 78F9177AY, 78F9177A(A),

78F9177AY(A)) ...............................................................................................................387

CHAPTER 28 ELECTRICAL SPECIFICATIONS (µPD78F9177, 78F9177Y) ......................................406

CHAPTER 29 CHARACTERISTICS CURVES (µPD78F9177, 78F9177Y)..........................................423

CHAPTER 30 ELECTRICAL SPECIFICATIONS (µPD78F9177A(A1)) ...............................................424

CHAPTER 31 PACKAGE DRAWINGS.................................................................................................439

CHAPTER 32 RECOMMENDED SOLDERING CONDITIONS.............................................................441

APPENDIX A DEVELOPMENT TOOLS...............................................................................................445

A.1 Software Package ....................................................................................................................447

A.2 Language Processing Software .............................................................................................447

A.3 Control Software ......................................................................................................................448

A.4 Flash Memory Writing Tools...................................................................................................448

A.5 Debugging Tools (Hardware)..................................................................................................449

A.6 Debugging Tools (Software)...................................................................................................450

APPENDIX B NOTES ON TARGET SYSTEM DESIGN ..................................................................451

APPENDIX C REGISTER INDEX ........................................................................................................455

C.1 Register Name Index................................................................................................................455

C.2 Register Symbol Index ............................................................................................................457

APPENDIX D REVISION HISTORY ....................................................................................................459

D.1 Major Revisions in This Edition..............................................................................................459

D.2 Revision History up to Previous Edition ...............................................................................460

18

User’s Manual U14186EJ6V0UD

µ

k

CHAPTER 1 GENERAL (

PD789167 AND 789177 SUBSERIES)

1.1 Expanded-Specification Products and Conventional Products

The expanded-specification products and conventional products refer to the following products.

Expanded-specification product... Products with a rank

• Mask ROM versions for which orders were received after December 1, 2001 (except (A1) products and (A2)

products

•

µ

Conventional product... Products with rank

Note 2

).

PD78F9177A, 78F9177A(A)

Note 1

K

• Products other than the above expanded-specification products.

Notes 1. The rank is indicated by the 5th digit from the left in the lot number marked on the package.

Lot number × × × ×

Year
code

Week
code

2. For the (A1) products and (A2) products, refer to 1.10 Differences Between Standard Quality Grade

Products and (A) Products, (A1) Products, and (A2) Products.

Expanded-specification products and conventional products differ in operating frequency ratings. The differences

are shown in Table 1-1.

Table 1-1. Differences Between Expanded-Specification Products and Conventional Products

Guaranteed Operating Speed (Operating Frequency) Power Supply Voltage (VDD)

Conventional Products Expanded-Specification Products

Note 1

NEC Electronics
control code

Ran

other than K

4.5 to 5.5 V 5 MHz (0.4 µs) 10 MHz (0.2 µs)

3.0 to 5.5 V 5 MHz (0.4 µs) 6 MHz (0.33 µs)

2.7 to 5.5 V 5 MHz (0.4 µs) 5 MHz (0.4 µs)

1.8 to 5.5 V 1.25 MHz (1.6 µs) 1.25 MHz (1.6 µs)

Remark The values in parentheses indicate the minimum instruction execution time.

User’s Manual U14186EJ6V0UD

19

1.2 Features

• ROM and RAM capacity

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

Item

Product Name

µ

PD789166, 789176, 789166(A), 789176(A), 789166(A1),

789176(A1), 789166(A2), 789176(A2)

µ

PD789167, 789177, 789167(A), 789177(A), 789167(A1),

789177(A1), 789167(A2), 789177(A2)

µ

PD78F9177, 78F9177A, 78F9177A(A), 78F9177A(A1) Flash memory 24 KB

Program Memory

Mask ROM

(ROM)

16 KB

24 KB

Data Memory

(Internal High-Speed RAM)

512 bytes

• Minimum instruction execution time changeable from high-speed (0.2 µs: Main system clock 10.0 MHz

operation

Note

) to ultra-low speed (122 µs: Subsystem clock 32.768 kHz operation)

• I/O port: 31

• Serial interface: 1 channel

• 3-wire serial I/O mode/UART mode: 1 channel

• 8-bit resolution A/D converter: 8 channels (

• 10-bit resolution A/D converter: 8 channels (

µ

PD789167 Subseries)

µ

PD789177 Subseries)

• Timer: 6 channels

• 16-bit timer: 1 channel

• 8-bit timer/event counter: 2 channels

• 8-bit timer: 1 channel

• Watch timer: 1 channel

• Watchdog timer: 1 channel

• Vectored interrupt sources: 15

• Power supply voltage

• VDD = 1.8 to 5.5 V (

• VDD = 4.5 to 5.5 V (

µ

PD78916x, 78917x, 78916x(A), 78917x(A), 78F9177A, 78F9177A(A))

µ

PD78916x(A1), 78917x(A1), 78916x(A2), 78917x(A2))

• Operating ambient temperature

• TA = −40 to 85°C (

• TA = −40 to 110°C (

• TA = −40 to 125°C (

µ

PD78916x, 78917x, 78916x(A), 78917x(A), 78F9177A, 78F9177A(A))

µ

PD78916x(A1), 78917x(A1), 789177A(A1))

µ

PD78916x(A2), 78917x(A2))

Note When V

DD = 4.5 to 5.5 V and the product is an expanded-specification product

1.3 Applications

Power windows, keyless entry, battery management units, side air bags, etc.

20

User’s Manual U14186EJ6V0UD

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

1.4 Ordering Information

Part Number Package Internal ROM

µ

PD789166GB-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789166GA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789167GB-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789167GA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789176GB-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789176GA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789177GB-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789177GA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789166GB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789166GA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789167GB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789167GA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789176GB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789176GA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789177GB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789177GA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789166GB(A)-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789167GB(A)-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789176GB(A)-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789177GB(A)-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789166GB(A1)-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789167GB(A1)-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789176GB(A1)-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789177GB(A1)-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789166GB(A2)-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789167GB(A2)-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789176GB(A2)-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789177GB(A2)-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD78F9177GB-8ES 44-pin plastic LQFP (10 × 10) Flash memory

µ

PD78F9177AGB-8ES 44-pin plastic LQFP (10 × 10) Flash memory

µ

PD78F9177AGA-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Flash memory

µ

PD78F9177GB-8ES-A 44-pin plastic LQFP (10 × 10) Flash memory

µ

PD78F9177AGB-8ES-A 44-pin plastic LQFP (10 × 10) Flash memory

µ

PD78F9177AGA-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Flash memory

µ

PD78F9177AGB(A)-8ES 44-pin plastic LQFP (10 × 10) Flash memory

µ

PD78F9177AGB(A1)-8ES 44-pin plastic LQFP (10 × 10) Flash memory

Remarks 1. ××× indicates ROM code suffix.

2. Products with additional order code “-A” are lead-free products.

User’s Manual U14186EJ6V0UD

21

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

1.5 Quality Grades

Part Number Package Quality Grade

µ

PD789166GB-×××-8ES 44-pin plastic LQFP (10 × 10) Standard

µ

PD789166GA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789167GB-×××-8ES 44-pin plastic LQFP (10 × 10) Standard

µ

PD789167GA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789176GB-×××-8ES 44-pin plastic LQFP (10 × 10) Standard

µ

PD789176GA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789177GB-×××-8ES 44-pin plastic LQFP (10 × 10) Standard

µ

PD789177GA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789166GB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Standard

µ

PD789166GA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789167GB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Standard

µ

PD789167GA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789176GB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Standard

µ

PD789176GA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789177GB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Standard

µ

PD789177GA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789166GB(A)-×××-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD789167GB(A)-×××-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD789176GB(A)-×××-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD789177GB(A)-×××-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD789166GB(A1)-×××-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD789167GB(A1)-×××-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD789176GB(A1)-×××-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD789177GB(A1)-×××-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD789166GB(A2)-×××-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD789167GB(A2)-×××-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD789176GB(A2)-×××-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD789177GB(A2)-×××-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD78F9177GB-8ES 44-pin plastic LQFP (10 × 10) Standard

µ

PD78F9177AGB-8ES 44-pin plastic LQFP (10 × 10) Standard

µ

PD78F9177AGA-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD78F9177GB-8ES-A 44-pin plastic LQFP (10 × 10) Standard

µ

PD78F9177AGB-8ES-A 44-pin plastic LQFP (10 × 10) Standard

µ

PD78F9177AGA-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD78F9177AGB(A)-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD78F9177AGB(A1)-8ES 44-pin plastic LQFP (10 × 10) Special

Remarks 1. ××× indicates ROM code suffix.

2. Products with additional order code “-A” are lead-free products.

Please refer to Quality Grades on NEC Semiconductor Devices (C11531E) published by NEC Electronics

Corporation to know the specification of the quality grade on the devices and its recommended applications.

22

User’s Manual U14186EJ6V0UD

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

1.6 Pin Configuration (Top View)

• 44-pin plastic LQFP (10 × 10)

µ

PD789166GB-×××-8ES

µ

PD789167GB-×××-8ES

µ

PD789176GB-×××-8ES

µ

PD789177GB-×××-8ES

µ

PD789166GB-×××-8ES-A

µ

PD789167GB-×××-8ES-A

µ

PD789176GB-×××-8ES-A

µ

PD789177GB-×××-8ES-A

µ

PD789166GB(A)-×××-8ES

µ

PD789167GB(A)-×××-8ES

µ

PD789176GB(A)-×××-8ES

µ

PD789177GB(A)-×××-8ES

µ

PD789166GB(A1)-×××-8ES

µ

PD789167GB(A1)-×××-8ES

µ

PD789176GB(A1)-×××-8ES

µ

PD789177GB(A1)-×××-8ES

REFAVDD

AV

P53

P52

P51

P50

P05

SS1

V

µ

PD789166GB(A2)-×××-8ES

µ

PD789167GB(A2)-×××-8ES

µ

PD789176GB(A2)-×××-8ES

µ

PD789177GB(A2)-×××-8ES

µ

PD78F9177GB-8ES

µ

PD78F9177AGB-8ES

µ

PD78F9177GB-8ES-A

µ

PD78F9177AGB-8ES-A

µ

PD78F9177AGB(A)-8ES

µ

PD78F9177AGB(A1)-8ES

P04

P03

P02

P60/ANI0

P61/ANI1

P62/ANI2

P63/ANI3

P64/ANI4

P65/ANI5

P66/ANI6

P67/ANI7

AV

P10

P11

SS

44 43 42 41 40 39 38 37 36 35 34

1

2

3

4

5

6

7

8

9

10

11

12 13 14 15 16 17 18 19 20 21 22

DD1

V

P31/INTP1/TO81

P32/INTP2/TO90

P20/SCK20/ASCK20

P30/INTP0/TI81/CPT90

P33/INTP3/TO82/BZO90

P23

D20

D20

X

X

P22/SI20/R

P21/SO20/T

P24

33

32

31

30

29

28

27

26

25

24

23

)

PP

IC0 (V

Cautions 1. Connect the IC0 (internally connected) pin directly to the V

2. Connect the AV

3. Connect the AV

DD pin to the VDD0 pin.

SS pin to the VSS0 pin.

Remark Pin connections in parentheses are intended for the

µ

PD78F9177, 78F9177A, 78F9177A(A), and

78F9177A(A1).

P01

P00

P26/TO80

P25/TI80/SS20

DD0

V

V

SS0

X1

X2

RESET

XT1

XT2

SS0 or VSS1 pin.

User’s Manual U14186EJ6V0UD

23

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

• 48-pin plastic TQFP (fine pitch) (7 × 7)

µ

PD789166GA-×××-9EU

µ

PD789167GA-×××-9EU

µ

PD789176GA-×××-9EU

µ

PD789177GA-×××-9EU

P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
P64/ANI4
P65/ANI5
P66/ANI6
P67/ANI7

AV

SS

P10
P11

IC3

µ

PD789166GA-×××-9EU-A

µ

PD789167GA-×××-9EU-A

µ

PD789176GA-×××-9EU-A

µ

PD789177GA-×××-9EU-A

REFAVDD

AV

P53

P52

IC3

P51

48 47 46 45 44 43 4241 40 39 38 37

1
2
3
4
5
6
7
8

9
10
11
12

13 14 15 16 17 18 1920 21 22 23 24

P50

P05

SS1

V

P04

µ

PD78F9177AGA-9EU

µ

PD78F9177AGA-9EU-A

P03

P02

36
35
34
33
32
31
30
29
28
27
26
25

P01
P00
P26/TO80
P25/Tl80/SS20
V

DD0

IC3
V

SS0

X1
X2
RESET
XT1
XT2

)

DD1

IC3

V

P31/INTP1/TO81

P32/INTP2/TO90

P30/INTP0/Tl81/CPT90

P20/SCK20/ASCK20

P33/INTP3/TO82/BZO90

P21/SO20/TxD20

P22/Sl20/RxD20

P23

P24

PP

IC0 (V

Cautions 1. Connect the IC0 (internally connected) pin directly to the V

SS0 or VSS1 pin.

2. Leave the IC3 pin open.

3. Connect the AV

4. Connect the AV

DD pin to the VDD0 pin.

SS pin to the VSS0 pin.

5. The pin configuration of the 48-pin package for (A), (A1), and (A2) products is undefined.

Remark Pin connections in parentheses are intended for the

µ

PD78F9177A.

24

User’s Manual U14186EJ6V0UD

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

ANI0 to ANI7: Analog input RESET: Reset

ASCK20: Asynchronous serial input RxD20: Receive data

AV

DD: Analog power supply SCK20: Serial clock

REF: Analog reference voltage SI20: Serial input

AV

AV

SS: Analog ground SO20: Serial output

BZO90: Buzzer output SS20: Chip select input

CPT90: Capture trigger input TI80, TI81: Timer input

IC0, IC3: Internally connected TO80 to TO82, TO90: Timer output

INTP0 to INTP3: Interrupt from peripherals TxD20: Transmit data

P00 to P05: Port 0 VDD0, VDD1: Power supply

P10, P11: Port 1 VPP: Programming power supply

P20 to P26: Port 2 VSS0, VSS1: Ground

P30 to P33: Port 3 X1, X2: Crystal (main system clock)

P50 to P53: Port 5 XT1, XT2: Crystal (subsystem clock)

P60 to P67: Port 6

User’s Manual U14186EJ6V0UD

25

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

1.7 78K/0S Series Lineup

The 78K/0S Series products are shown below. The subseries names are indicated in frames.

Products under development

µ

µ

µ

µ

78K/0S

Series

44-pin
42-/44-pin
30-pin
30-pin
20-pin
20-pin

44-pin
44-pin
30-pin
30-pin
30-pin
30-pin

144-pin

88-pin

80-pin

80-pin
80-pin

80-pin
64-pin
64-pin
64-pin
64-pin

64-pin
64-pin

52-pin

52-pin

44-pin

44-pin

44-pin
30-pin

30-pin
20-pin

20-pin

Products in mass production

Y Subseries products support SMB.

Small-scale package, general-purpose applications

PD789074 with added subsystem clock

PD789046

µ

µ

PD789026

µ

PD789088

µ

PD789074
PD789062

µ

µ

PD789052

Small-scale package, general-purpose applications and A/D converter

µ

PD789177

µ

µ

PD789167

µ

PD789134A

µ

PD789124A

µ

PD789114A

µ

PD789104A

LCD drive

µ

PD789835B

µ

PD789830

µ

PD789489

µ

PD789479

PD789417A

µ

PD789407A

µ

PD789456

µ
µ

PD789446

µ

PD789436
PD789426

µ
µ

PD789316
PD789306

µ

µ

PD789467

µ

PD789327

USB

µ

PD789800

Inverter control

µ

PD789842

On-chip bus controller

PD789852

µ

PD789850A

µ

Keyless entry

PD789862

µ

µ

PD789861

PD789860

µ

PD789177Y

PD789167Y

µ

µ

On-chip UART and capable of low voltage (1.8 V) operation

PD789074 with enhanced timer and increased ROM, RAM capacity

µ

PD789026 with enhanced timer

µ

RC oscillation version of the PD789052

PD789860 without EEPROM, POC, and LVI

µ

µ

PD789167 with enhanced A/D converter (10 bits)

PD789104A with enhanced timer

µ

PD789124A with enhanced A/D converter (10 bits)

µ

RC oscillation version of the PD789104A

µ

PD789104A with enhanced A/D converter (10 bits)

µ

PD789026 with added 8-bit A/D converter and multiplier

UART, 8-bit A/D, and dot LCD (Total display output pins: 96)
UART and dot LCD (40 × 16)

SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 × 4)
SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)

PD789407A with enhanced A/D converter (10 bits)

µ

SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)
PD789446 with enhanced A/D converter (10 bits)

µ

SIO, 8-bit A/D, and on-chip voltage booster type LCD (15 × 4)

PD789426 with enhanced A/D converter (10 bits)

µ

SIO, 8-bit A/D, and on-chip voltage booster type LCD (5 × 4)
RC oscillation version of the PD789306

SIO and on-chip voltage booster type LCD (24 × 4)

8-bit A/D and on-chip voltage booster type LCD (23 × 4)
SIO and resistance division type LCD (24 × 4)

For PC keyboard and on-chip USB function

On-chip inverter controller and UART

µ

PD789850A with enhanced functions such as timer and A/D converter

On-chip CAN controller

PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity

µ

RC oscillation version of the PD789860

On-chip POC and key return circuit

Sensor

µ

20-pin

20-pin

52-pin

64-pin

PD789864

PD789863

µ

VFD drive

µ

PD789871

Meter control

PD789881

µ

Remark VFD (Vacuum Fluorescent Display) is referred to as FIP

documents, but the functions of the two are the same.

26

User’s Manual U14186EJ6V0UD

On-chip analog macro for sensor

RC oscillation version of the PD789864

On-chip VFD controller (Total display output pins: 25)

UART and resistance division type LCD (26 × 4)

µ

TM

(Fluorescent Indicator Panel) in some

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

The major functional differences between the subseries are listed below.

Series for General-purpose applications and LCD drive

ROM

Subseries Name

Small-scale

package,

general-

purpose

applications

µ

µ

µ

µ

µ

µ

Small-scale

package,

general-

purpose

applications

and A/D

converter

µ

µ

µ

µ

µ

µ

LCD drive

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

PD789046 16 KB 1 ch

PD789026 4 KB to 16 KB

PD789088 16 KB to

PD789074 2 KB to 8 KB 1 ch

PD789062 RC oscillation

PD789052

PD789177

PD789167

PD789134A

PD789124A 4 ch

PD789114A

PD789104A

PD789835B 24 KB to

PD789830 24 KB 1 ch

PD789489 32 KB to

PD789479 24 KB to

PD789417A

PD789407A

PD789456

PD789446 6 ch

PD789436

PD789426

PD789316 RC oscillation

PD789306

PD789467 1 ch

PD789327

Capacity

32 KB

4 KB 2 ch

16 KB to

24 KB

2 KB to 8 KB 1 ch

60 KB

48 KB

48 KB

12 KB to

24 KB

12 KB to

16 KB

8 KB to 16 KB

4 KB to 24 KB

Note Flash memory version: 3.0 V

8-Bit

Timer V

8-Bit 16-Bit Watch WDT

1 ch 1 ch

1 ch 34

3 ch

−

3 ch 1 ch

1 ch

6 ch

−

1 ch

3 ch

2 ch

−

1 ch

−

1 ch

−

1 ch 1 ch

10-Bit

A/D

A/D

− −

8 ch

−

8 ch

4 ch

3 ch 37 1.8 V

8 ch

7 ch

6 ch

−

4 ch

−

−

4 ch

−

−

−

−

8 ch

−

7 ch

−

−

6 ch

−

−

6 ch

−

−

−

−

Serial

Interface

(UART: 1 ch)

−

1 ch

(UART: 1 ch)

1 ch

(UART: 1 ch)

2 ch

(UART: 1 ch)

1 ch

(UART: 1 ch)

2 ch

(UART: 1 ch)

−

1 ch 21

I/O

24

14

31

20

30 2.7 V

45

43

30

40

23

18

DD Function

MIN.

Value

1.8 V

1.8 V

1.8 V

Remarks

version

RC oscillation

version

Note

Dot LCD

supported

version

−

−

−

−

−

−

User’s Manual U14186EJ6V0UD

27

Series for ASSP

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

Subseries Name

USB

Inverter

control

µ

µ

µ

controller

µ

µ

entry

µ

µ

Sensor

µ

µ

ROM

Capacity

PD789800 8 KB 2 ch

PD789842 8 KB to 16 KB 3 ch

PD789852 24 KB to

32 KB

PD789850A 16 KB 1 ch

PD789861

PD789860

PD789862 16 KB 1 ch 2 ch

PD789864

PD789863

4 KB 2 ch

4 KB 1 ch

8-Bit 16-Bit Watch WDT

− −

Note 1

3 ch

1 ch

− −

Note 2

Timer V

1 ch 1 ch 8 ch

−

−

−

1 ch

1 ch

1 ch

1 ch

8-Bit

A/D

− −

−

4 ch

− −

−

10-Bit

A/D

2 ch

(USB: 1 ch)

1 ch

−

(UART: 1 ch)

8 ch 3 ch

(UART: 2 ch)

2 ch

−

(UART: 1 ch)

1 ch

(UART: 1 ch)

4 ch

Serial

Interface

−

I/O

Value

31 4.0 V

30 4.0 V

31 On-chip bus

4.0 V

18

1.8 V

14 Keyless

22

5 1.9 V

DD Function

MIN.

Remarks

−

−

−

RC oscillation

version, on-

chip EEPROM

On-chip

EEPROM

On-chip

EEPROM

RC oscillation

version, on-

chip EEPROM

VFD drive µPD789871 4 KB to 8 KB 3 ch

Meter

control

µ

PD789881 16 KB 2 ch 1 ch

Notes 1. 10-bit timer: 1 channel

2. 12-bit timer: 1 channel

3. Flash memory version: 3.0 V

−

1 ch 1 ch

1 ch

−

− −

− −

1 ch 33 2.7 V

1 ch

(UART: 1 ch)

28 2.7 V

Note 3

−

−

28

User’s Manual U14186EJ6V0UD

1.8 Block Diagram

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

TI80/SS20/P25

TO80/P26

TI81/INTP0/CPT90/P30

TO81/INTP1/P31

TO82/INTP3/BZO90/P33

CPT90/INTP0/TI81/P30

TO90/INTP2/P32

BZO90/INTP3/TO82/P33

SCK20/ASCK20/P20

X

D20/P21

SO20/T

SI20/RXD20/P22

SS20/TI80/P25

ANI0/P60 to

ANI7/P67

AV
AV

AV

REF

DD

SS

8-bit timer/
event counter 80

8-bit timer/
event counter 81

8-bit timer 82

16-bit timer 90

Watch timer

Watchdog timer

SIO20

A/D

converter

78K/0S

CPU core

RAM

ROM

(flash

memory)

Port 0

Port 1

Port 2

Port 3

Port 5

Port 6

System

control

Interrupt

control

P00 to P05

P10, P11

P20 to P26

P30 to P33

P50 to P53

P60 to P67

RESET
X1
X2
XT1
XT2

INTP0/TI81/CPT90/P30
INTP1/TO81/P31
INTP2/TO90/P32
INTP3/TO82/BZO90/P33

Multiplier

V

DD0

V

SS0

IC0

V

SS1

PP

)

V

DD1

(V

Remarks 1. The size of the internal ROM varies depending on the product.

2. Pin connections in parentheses are intended for the

µ

PD78F9177, 78F9177A, 78F9177A(A), and

78F9177A(A1).

User’s Manual U14186EJ6V0UD

29

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

1.9 Outline of Functions

Part Number

Item

Internal memory

µ

PD789166, 789176,

789166(A), 789176(A),

789166(A1), 789176(A1),

789166(A2), 789176(A2)

Mask ROM Flash memory ROM

µ

PD789167, 789177,

789167(A), 789177(A),

789167(A1), 789177(A1),

789167(A2), 789177(A2)

µ

PD78F9177,

78F9177A,
78F9177A(A),
78F9177A(A1)

16 KB 24 KB 24 KB

High-speed RAM 512 bytes

Minimum instruction execution time Expanded-specification products of µPD78916x, 78917x, 78916x(A), 78917x(A),

78F9177A, 78F9177A(A)

0.2/0.8

µ

s (operation with main system clock operating at 10.0 MHz, VDD = 4.5 to 5.5

V)

• 122

µ

s (operation with subsystem clock operating at 32.768 kHz)

Other than above products

• 0.4/1.6

• 122

µ

s (operation with main system clock operating at 5.0 MHz)

µ

s (operation with subsystem clock operating at 32.768 kHz)

General-purpose registers 8 bits × 8 registers

Instruction set • 16-bit operations

• Bit manipulations (such as set, reset, and test)

Multiplier 8 bits × 8 bits = 16 bits

I/O ports Total: 31

• CMOS input: 8

• CMOS I/O: 17

• N-ch open-drain: 6

A/D converter • 8-bit resolution × 8 channels (µPD789167 Subseries)

• 10-bit resolution × 8 channels (

µ

PD789177 Subseries)

Serial interface • Switchable between 3-wire serial I/O and UART modes: 1 channel

Timers • 16-bit timer: 1 channel

• 8-bit timer/event counter: 2 channels

• 8-bit timer: 1 channel

• Watch timer: 1 channel

• Watchdog timer: 1 channel

Timer output Four outputs

Buzzer output One output

Maskable Internal: 10, external: 4 Vectored interrupt

sources

Non-maskable Internal: 1

Power supply voltage VDD = 1.8 to 5.5 V (µPD78916x, 78917x, 78916x(A), 78917x(A), 78F9177,

78F9177A, 78F9177A(A)
V

DD = 4.5 to 5.5 V (

µ

PD78916x(A1), 78917x(A1), 78916x(A2), 78917x(A2),

78F9177A(A1)

Operating ambient temperature TA = −40°C to +85°C (µPD78916x, 78917x, 78916x(A), 78917x(A), 78F9177,

78F9177A, 78F9177A(A)
T

A = −40°C to +110°C (

T

A = −40°C to +125°C (

Package • 44-pin plastic LQFP (10 × 10)

• 48-pin plastic TQFP (fine pitch) (7 × 7)

µ

PD78916x(A1), 78917x(A1), 78F9177A(A1)

µ

PD78916x(A2), 78917x(A2)

Note

µ

Note

PD789166, 789167, 789176, 789177, and 78F9177A only

30

User’s Manual U14186EJ6V0UD

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

The timers are outlined below.

16-Bit

Timer 90

mode

Function

Interval timer

External event counter

Timer output 1 output 1 output 1 output 1 output

PWM output

Square-wave output

Buzzer output 1 output

Capture 1 input

Interrupt sources 1 1 1 1 2 2

−

−

−

−

Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.

2. The watchdog timer provides a watchdog timer function and an interval timer function. Use either of

the functions.

8-Bit

Timer/Event

Counter 80

1 channel 1 channel 1 channel 1 channel

1 channel 1 channel

1 output 1 output 1 output

1 output 1 output 1 output

− − − − −

− − − − −

8-Bit

Timer/Event

Counter 81

8-Bit Timer

82

− − −

Watch Timer Watchdog

Note 1

− −

− −

− −

Timer

1 channel

Note 2

Operating

User’s Manual U14186EJ6V0UD

31

CHAPTER 1 GENERAL (µPD789167 AND 789177 SUBSERIES)

1.10 Differences Between Standard Quality Grade Products and (A) Products, (A1) Products, and (A2) Products

Standard quality grade products, (A) products, (A1) products, and (A2) products indicate the following products

respectively.

Standard quality grade products...

(A) products...

(A1) products...

(A2) products...

µ

PD789166(A), 789167(A), 789176(A), 789177(A), 78F9177A(A)

µ

PD789166(A1), 789167(A1), 789176(A1), 789177(A1), 78F9177A(A1)

µ

PD789166(A2), 789167(A2), 789176(A2), 789177(A2)

Table 1-2 shows the differences between the standard quality grade products and (A) products, (A1) products,

and (A2) products.

Table 1-2. Differences Between Standard Quality Grade Products and (A) Products, (A1) Products, and

(A2) Products

Part Number

Item

Standard Quality Grade

Products

µ

PD789166, 789167, 789176, 789177, 78F9177, 78F9177A

(A) Products (A1) Products (A2) Products

Quality grade Standard Special

Power supply voltage VDD = 1.8 to 5.5 V VDD = 4.5 to 5.5 V

Operating ambient

temperature

Minimum instruction

execution time

Electrical specifications Refer to the ELECTRICAL SPECIFICATIONS chapters.

TA = −40 to 85°C TA = −40 to 110°C TA = −40 to 125°C

Expanded-specification product

µ

0.2

Conventional product

0.4

s (at 10.0 MHz operation)

µ

s (at 5.0 MHz operation)

Note

:

Note

:

0.4

µ

s (at 5.0 MHz operation)

Note Refer to 1.1 Expanded-Specification Products and Conventional Products

32

User’s Manual U14186EJ6V0UD

µ

k

CHAPTER 2 GENERAL (

PD789167Y AND 789177Y SUBSERIES)

2.1

Expanded-Specification Products and Conventional Products

The expanded-specification products and conventional products refer to the following products.

Expanded-specification product... Products with a rank

• Mask ROM versions for which orders were received after December 1, 2001.

•

µ

PD78F9177AY, 78F9177AY(A)

Conventional product... Products with rank

Note

K

• Products other than the above expanded-specification products.

Note The rank is indicated by the 5th digit from the left in the lot number marked on the package.

Lot number

Year
code

Week
code

Expanded-specification products and conventional products differ in operating frequency ratings. The differences

are shown in Table 2-1.

Table 2-1. Differences Between Expanded-Specification Products and Conventional Products

Guaranteed Operating Speed (Operating Frequency) Power Supply Voltage (VDD)

Conventional Products Expanded-Specification Products

Note

× × × ×

NEC Electronics
control code

Ran

other than K

4.5 to 5.5 V 5 MHz (0.4 µs) 10 MHz (0.2 µs)

3.0 to 5.5 V 5 MHz (0.4 µs) 6 MHz (0.33 µs)

2.7 to 5.5 V 5 MHz (0.4 µs) 5 MHz (0.4 µs)

1.8 to 5.5 V 1.25 MHz (1.6 µs) 1.25 MHz (1.6 µs)

Remark The values in parentheses indicate the minimum instruction execution time.

User’s Manual U14186EJ6V0UD

33

2.2 Features

• ROM and RAM capacity

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES)

Item

Product Name

µ

PD789166Y, 789176Y, 789166Y(A), 789176Y(A) 16 KB

µ

PD789167Y, 789177Y, 789167Y(A), 789177Y(A)

µ

PD78F9177Y, 78F9177AY, 78F9177AY(A) Flash memory 24 KB

Program Memory

Mask ROM

(ROM)

Data Memory

(Internal High-Speed RAM)

512 bytes

24 KB

• Minimum instruction execution time changeable from high-speed (0.2 µs: Main system clock 10.0 MHz

operation

Note

) to ultra-low speed (122 µs: Subsystem clock 32.768 kHz operation)

• I/O port: 31

• Serial interface: 2 channels

• 3-wire serial I/O mode/UART mode: 1 channel

• SMB: 1 channel

• 8-bit resolution A/D converter: 8 channels (

• 10-bit resolution A/D converter: 8 channels (

µ

PD789167Y Subseries)

µ

PD789177Y Subseries)

• Timer: 6 channels

• 16-bit timer: 1 channel

• 8-bit timer/event counter: 2 channels

• 8-bit timer: 1 channel

• Watch timer: 1 channel

• Watchdog timer: 1 channel

• Vectored interrupt sources: 17

• Supply voltage: V

• Operating ambient temperature: T

DD = 1.8 to 5.5 V

A = –40 to +85°C

Note When VDD = 4.5 to 5.5 V and the product is an expanded-specification product.

2.3 Applications

Power windows, keyless entry, battery management units, side air bags, etc.

34

User’s Manual U14186EJ6V0UD

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES)

2.4 Ordering Information

Part Number Package Internal ROM

µ

PD789166YGB-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789166YGA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789167YGB-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789167YGA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789176YGB-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789176YGA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789177YGB-×××-8ES 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789177YGA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789166YGB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789166YGA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789167YGB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789167YGA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789176YGB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789176YGA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789177YGB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Mask ROM

µ

PD789177YGA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789166YGA(A)-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789167YGA(A)-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789176YGA(A)-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD789177YGA(A)-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Mask ROM

µ

PD78F9177YGB-8ES 44-pin plastic LQFP (10 × 10) Flash memory

µ

PD78F9177YGA-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Flash memory

µ

PD78F9177AYGB-8ES 44-pin plastic LQFP (10 × 10) Flash memory

µ

PD78F9177AYGA-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Flash memory

µ

PD78F9177YGB-8ES-A 44-pin plastic LQFP (10 × 10) Flash memory

µ

PD78F9177YGA-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Flash memory

µ

PD78F9177AYGB-8ES-A 44-pin plastic LQFP (10 × 10) Flash memory

µ

PD78F9177AYGA-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Flash memory

µ

PD78F9177AYGB(A)-8ES 44-pin plastic LQFP (10 × 10) Flash memory

µ

PD78F9177AYGA(A)-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Flash memory

Remark ××× indicates ROM code suffix.

User’s Manual U14186EJ6V0UD

35

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES)

2.5 Quality Grades

Part Number Package

µ

PD789166YGB-×××-8ES 44-pin plastic LQFP (10 × 10) Standard

µ

PD789166YGA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789167YGB-×××-8ES 44-pin plastic LQFP (10 × 10) Standard

µ

PD789167YGA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789176YGB-×××-8ES 44-pin plastic LQFP (10 × 10) Standard

µ

PD789176YGA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789177YGB-×××-8ES 44-pin plastic LQFP (10 × 10) Standard

µ

PD789177YGA-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789166YGB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Standard

µ

PD789166YGA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789167YGB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Standard

µ

PD789167YGA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789176YGB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Standard

µ

PD789176YGA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789177YGB-×××-8ES-A 44-pin plastic LQFP (10 × 10) Standard

µ

PD789177YGA-×××-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD789166YGA(A)-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Special

µ

PD789167YGA(A)-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Special

µ

PD789176YGA(A)-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Special

µ

PD789177YGA(A)-×××-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Special

µ

PD78F9177YGB-8ES 44-pin plastic LQFP (10 × 10) Standard

µ

PD78F9177YGA-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD78F9177AYGB-8ES 44-pin plastic LQFP (10 × 10) Standard

µ

PD78F9177AYGA-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD78F9177YGB-8ES-A 44-pin plastic LQFP (10 × 10) Standard

µ

PD78F9177YGA-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD78F9177AYGB-8ES-A 44-pin plastic LQFP (10 × 10) Standard

µ

PD78F9177AYGA-9EU-A 48-pin plastic TQFP (fine pitch) (7 × 7) Standard

µ

PD78F9177AYGB(A)-8ES 44-pin plastic LQFP (10 × 10) Special

µ

PD78F9177AYGA(A)-9EU 48-pin plastic TQFP (fine pitch) (7 × 7) Special

Remark ××× indicates ROM code suffix.

Please refer to Quality Grades on NEC Semiconductor Devices (C11531E) published by NEC Electronics

Corporation to know the specification of the quality grade on the device and its recommended applications.

Quality Grade

36

User’s Manual U14186EJ6V0UD

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES)

2.6 Pin Configuration (Top View)

• 44-pin plastic LQFP (10 × 10)

µ

PD789166YGB-×××-8ES

µ

PD789167YGB-×××-8ES

µ

PD789176YGB -×××-8ES

µ

PD789177YGB -×××-8ES

µ

PD789166YGB-×××-8ES-A

µ

PD789167YGB-×××-8ES-A

µ

PD789176YGB -×××-8ES-A

µ

PD789177YGB -×××-8ES-A

REFAVDD

AV

P53

P52

P51

P50

P05

SS1

V

P04

µ

PD78F9177YGB-8ES

µ

PD78F9177AYGB-8ES

µ

PD78F9177YGB-8ES-A

µ

PD78F9177AYGB-8ES-A

µ

PD78F9177AYGB(A)-8ES

P03

P02

P60/ANI0

P61/ANI1

P62/ANI2

P63/ANI3

P64/ANI4

P65/ANI5

P66/ANI6

P67/ANI7

AV

P10

P11

SS

44 43 42 41 40 39 38 37 36 35 34

1

2

3

4

5

6

7

8

9

10

11

12 13 14 15 16 17 18 19 20 21 22

DD1

D20

D20

V

X

X

P23/SCL0

P31/INTP1/TO81

P32/INTP2/TO90

P20/SCK20/ASCK20

P30/INTP0/TI81/CPT90

P33/INTP3/TO82/BZO90

P22/SI20/R

P21/SO20/T

33

32

31

30

29

28

27

26

25

24

23

)

PP

IC0 (V

P24/SDA0

Cautions 1. Connect the IC0 (internally connected) pin directly to the V

2. Connect the AV

3. Connect the AV

DD pin to the VDD0 pin.

SS pin to the VSS0 pin.

Remark Pin connections in parentheses are intended for the

78F9177AY(A).

P01

P00

P26/TO80

P25/TI80/SS20

V

DD0

V

SS0

X1

X2

RESET

XT1

XT2

SS0 or VSS1 pin.

µ

PD78F9177Y, 78F9177AY, and

User’s Manual U14186EJ6V0UD

37

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES)

• 48-pin plastic TQFP (fine pitch) (7 × 7)

µ

PD789166YGA-×××-9EU

µ

PD789167YGA-×××-9EU

µ

PD789176YGA-×××-9EU

µ

PD789177YGA-×××-9EU

µ

PD789166YGA-×××-9EU-A

µ

PD789167YGA-×××-9EU-A

µ

PD789176YGA-×××-9EU-A

µ

PD789177YGA-×××-9EU-A

µ

µ

µ

µ

P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
P64/ANI4
P65/ANI5
P66/ANI6
P67/ANI7

AV

P10
P11

IC2

SS

1
2
3
4
5
6
7
8

9
10
11
12

PD789166YGA(A)-×××-9EU µPD78F9177YGA-9EU

PD789167YGA(A)-×××-9EU µPD78F9177AYGA-9EU

PD789176YGA(A)-×××-9EU µPD78F9177YGA-9EU-A

PD789177YGA(A)-×××-9EU µPD78F9177AYGA-9EU-A

µ

PD78F9177AYGA(A)-9EU

REFAVDD

AV

P53

P52

IC0

P51

48 47 46 45 44 43 4241 40 39 38 37

13 14 15 16 17 18 1920 21 22 23 24

P50

P05

SS1

V

P04

P03

P02

36
35
34
33
32
31
30
29
28
27
26
25

P01
P00
P26/TO80
P25/Tl80/SS20
V

DD0

IC2
V

SS0

X1
X2
RESET
XT1
XT2

)

DD1

IC2

V

P31/INTP1/TO81

P32/INTP2/TO90

P30/INTP0/Tl81/CPT90

P20/SCK20/ASCK20

P33/INTP3/TO82/BZO90

P21/SO20/TxD20

P22/Sl20/RxD20

PP

IC0 (V

P23/SCL0

P24/SDA0

Cautions 1. Connect the IC0 (internally connected) pin directly to the VSS0 or VSS1 pin.

2. Leave the IC2 pin open.

3. Connect the AV

4. Connect the AV

DD pin to the VDD0 pin.

SS pin to the VSS0 pin.

Remark Pin connections in parentheses are intended for the

µ

PD78F9177Y, 78F9177AY, and

78F9177AY(A).

38

User’s Manual U14186EJ6V0UD

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES)

ANI0 to ANI7: Analog input RESET: Reset

ASCK20: Asynchronous serial input RxD20: Receive data

AV

DD: Analog power supply SCK20: Serial clock (for SIO20)

REF: Analog reference voltage SCL0: Serial clock (for SMB0)

AV

AV

SS: Analog ground SDA0: Serial data

BZO90: Buzzer output SI20: Serial input

CPT90: Capture trigger input SO20: Serial output

IC0, IC2: Internally connected SS20: Chip select input

INTP0 to INTP3: Interrupt from peripherals TI80, TI81: Timer input

P00 to P05: Port 0 TO80 to TO82, TO90: Timer output

P10, P11: Port 1 TxD20: Transmit data

P20 to P26: Port 2 VDD0, VDD1: Power supply

P30 to P33: Port 3 V

P50 to P53: Port 5 V

PP: Programming power supply

SS0, VSS1: Ground

P60 to P67: Port 6 X1, X2: Crystal (main system clock)

XT1, XT2: Crystal (subsystem clock)

User’s Manual U14186EJ6V0UD

39

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES)

2.7 78K/0S Series Lineup

The 78K/0S Series products are shown below. The subseries names are indicated in frames.

Products under development

µ

µ

µ

µ

78K/0S

Series

44-pin
42-/44-pin
30-pin
30-pin
20-pin
20-pin

44-pin
44-pin
30-pin
30-pin
30-pin
30-pin

144-pin

88-pin

80-pin

80-pin
80-pin

80-pin
64-pin
64-pin
64-pin
64-pin

64-pin
64-pin

52-pin

52-pin

44-pin

44-pin

44-pin
30-pin

30-pin
20-pin

20-pin

Products in mass production

Y Subseries products support SMB.

Small-scale package, general-purpose applications

PD789074 with added subsystem clock

PD789046

µ

µ

PD789026

µ

PD789088

µ

PD789074
PD789062

µ

µ

PD789052

Small-scale package, general-purpose applications and A/D converter

µ

PD789177

µ

µ

PD789167

µ

PD789134A

µ

PD789124A

µ

PD789114A

µ

PD789104A

LCD drive

µ

PD789835B

µ

PD789830

µ

PD789489

µ

PD789479

PD789417A

µ

PD789407A

µ

PD789456

µ
µ

PD789446

µ

PD789436
PD789426

µ
µ

PD789316
PD789306

µ

µ

PD789467

µ

PD789327

USB

µ

PD789800

Inverter control

µ

PD789842

On-chip bus controller

PD789852

µ

PD789850A

µ

Keyless entry

PD789862

µ

µ

PD789861

PD789860

µ

PD789177Y

PD789167Y

µ

µ

On-chip UART and capable of low voltage (1.8 V) operation

PD789074 with enhanced timer and increased ROM, RAM capacity

µ

PD789026 with enhanced timer

µ

RC oscillation version of the PD789052

PD789860 without EEPROM, POC, and LVI

µ

µ

PD789167 with enhanced A/D converter (10 bits)

PD789104A with enhanced timer

µ

PD789124A with enhanced A/D converter (10 bits)

µ

RC oscillation version of the PD789104A

µ

PD789104A with enhanced A/D converter (10 bits)

µ

PD789026 with added 8-bit A/D converter and multiplier

UART, 8-bit A/D, and dot LCD (Total display output pins: 96)
UART and dot LCD (40 × 16)

SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 × 4)
SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)

PD789407A with enhanced A/D converter (10 bits)

µ

SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)
PD789446 with enhanced A/D converter (10 bits)

µ

SIO, 8-bit A/D, and on-chip voltage booster type LCD (15 × 4)

PD789426 with enhanced A/D converter (10 bits)

µ

SIO, 8-bit A/D, and on-chip voltage booster type LCD (5 × 4)
RC oscillation version of the PD789306

SIO and on-chip voltage booster type LCD (24 × 4)

8-bit A/D and on-chip voltage booster type LCD (23 × 4)
SIO and resistance division type LCD (24 × 4)

For PC keyboard and on-chip USB function

On-chip inverter controller and UART

µ

PD789850A with enhanced functions such as timer and A/D converter

On-chip CAN controller

PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity

µ

RC oscillation version of the PD789860

On-chip POC and key return circuit

Sensor

µ

20-pin

20-pin

52-pin

64-pin

PD789864

PD789863

µ

VFD drive

µ

PD789871

Meter control

PD789881

µ

Remark VFD (Vacuum Fluorescent Display) is referred to as FIP

documents, but the functions of the two are the same.

40

User’s Manual U14186EJ6V0UD

On-chip analog macro for sensor

RC oscillation version of the PD789864

On-chip VFD controller (Total display output pins: 25)

UART and resistance division type LCD (26 × 4)

µ

TM

(Fluorescent Indicator Panel) in some

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES)

The functions of the Y Subseries are listed below.

Function

Subseries Name

ROM Capacity Serial Interface Configuration I/O

(pins)

VDD

MIN. Value

Remark

Small-scale

package,

general-

purpose

application

+ A/D

converter

µ

PD789177Y

µ

PD789167Y

16 KB to 24 KB 3-wire/UART: 1 ch

SMB: 1 ch

31 1.8 V

−

User’s Manual U14186EJ6V0UD

41

2.8 Block Diagram

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES)

TI80/SS20/P25

TO80/P26

TI81/INTP0/CPT90/P30

TO81/INTP1/P31

TO82/INTP3/BZO90/P33

CPT90/INTP0/TI81/P30

TO90/INTP2/P32

BZO90/INTP3/TO82/P33

SCK20/ASCK20/P20

X

D20/P21

SO20/T

SI20/RXD20/P22

SS20/TI80/P25

SCL0/P23

SDA0/P24

ANI0/P60 to

ANI7/P67

AV

AV

AV

REF

DD

SS

8-bit timer/
event counter 80

8-bit timer/
event counter 81

8-bit timer 82

16-bit timer 90

Watch timer

Watchdog timer

SIO20

SMB

A/D

converter

78K/0S

CPU core

RAM

ROM
(flash

memory)

Port 0

Port 1

Port 2

Port 3

Port 5

Port 6

System
control

Interrupt

control

P00 to P05

P10, P11

P20 to P26

P30 to P33

P50 to P53

P60 to P67

RESET
X1
X2
XT1
XT2

INTP0/TI81/CPT90/P30
INTP1/TO81/P31
INTP2/TO90/P32
INTP3/TO82/BZO90/P33

Multiplier

V

DD0

V

SS0

IC0

(V

V

SS1

PP

V

DD1

)

Remarks 1. The size of the internal ROM varies depending on the model.

2. Pin connections in parentheses are intended for the

78F9177AY(A).

µ

PD78F9177Y, 78F9177AY, and

42

User’s Manual U14186EJ6V0UD

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES)

2.9 Outline of Function

Part Number

Item

Internal memory

High-speed RAM 512 bytes

Minimum instruction execution time Expanded-specification products of µPD78916xY, 78917xY, 78916xY(A), 78917xY(A),

General-purpose registers 8 bits × 8 registers

Instruction set • 16-bit operations

Multiplier 8 bits × 8 bits = 16 bits

I/O ports Total: 31

A/D converter • 8-bit resolution × 8 channels (µPD789167Y Subseries)

Serial interface • Switchable between 3-wire serial I/O and UART modes: 1 channel

Timers • 16-bit timer: 1 channel

Timer output Four outputs

Buzzer output One output

Maskable Internal: 12, external: 4 Vectored interrupt

sources

Power supply voltage VDD = 1.8 to 5.5 V

Operating ambient temperature TA = −40 to +85°C

Package • 44-pin plastic LQFP (10 × 10)

Nonmaskable Internal: 1

µ

PD789166Y, 789176Y

789166Y(A), 789176Y(A)

Mask ROM Flash Memory ROM

16 KB 24 KB 24 KB

78F9177AY, 78F9177AY(A)

µ

• 0.2/0.8

V

• 122

Other than above products

• 0.4/1.6

• 122

• Bit manipulations (such as set, reset, and test)

• CMOS input: 8

• CMOS I/O: 17

• N-ch open-drain: 6

• 10-bit resolution × 8 channels (

• SMB (System Management Bus): 1 channel

• 8-bit timer/event counter: 2 channels

• 8-bit timer: 1 channel

• Watch timer: 1 channel

• Watchdog timer: 1 channel

• 48-pin plastic TQFP (fine pitch) (7 × 7)

s (operation with main system clock operating at 10.0 MHz,

DD = 4.5 to 5.5 V)

µ

s (operation with subsystem clock operating at 32.768 kHz)

µ

s (operation with main system clock operating at 5.0 MHz)

µ

s (operation with subsystem clock operating at 32.768 kHz)

µ

PD789167Y, 789177Y

789167Y(A), 789177Y(A)

µ

PD789177Y Subseries)

Note

µ

PD78F9177Y, 78F9177AY

78F9177AY(A)

Note

µ

PD789166Y, 789167Y, 789176Y, 789177Y, 78F9177Y, 78F9177AY, and 78F9177AY(A) only

User’s Manual U14186EJ6V0UD

43

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES)

The timers are outlined below.

16-Bit

Timer 90

mode

Function

Interval timer

External event counter

Timer output 1 output 1 output 1 output 1 output

PWM output

Square-wave output

−

−

−

−

Buzzer output 1 output

Capture 1 input

8-Bit

Timer/Event

Counter 80

1 channel 1 channel 1 channel 1 channel

1 channel 1 channel

8-Bit

Timer/Event

Counter 81

8-Bit Timer

Watch Timer Watchdog

82

Note 1

− − −

− −

1 output 1 output 1 output

1 output 1 output 1 output

− −

− −

− − − − −

− − − − −

Timer

1 channel

Interrupt sources 1 1 1 1 2 2

Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.

2. The watchdog timer provides a watchdog timer function and an interval timer function. Use either of

the functions.

Note 2

Operating

44

User’s Manual U14186EJ6V0UD

CHAPTER 2 GENERAL (µPD789167Y AND 789177Y SUBSERIES)

2.10 Differences Between Standard Quality Grade Products and (A) Products

Standard quality grade products and (A) products indicate the following products.

Standard quality grade products...

(A) products...

µ

PD789166Y(A), 789167Y(A), 789176Y(A), 789177Y(A), 78F9177AY(A)

Table 2-2 shows the differences between the standard quality grade products and (A) products

Table 2-2. Differences Between Standard Quality Grade Products and (A) Products

Part Number

Item

Quality grade Standard Special

Power supply voltage VDD = 1.8 to 5.5 V

Operating ambient temperature TA = −40 to 85°C

Minimum instruction execution

time

Electrical specifications Refer to the ELECTRICAL SPECIFICATIONS chapters.

µ

PD789166Y, 789167Y, 789176Y, 789177Y, 78F9177Y, 78F9177AY

Standard Quality Grade Products (A) Products

Expanded-specification product

Conventional product

Note

Note

: 0.2 µs (at 10.0 MHz operation)

: 0.4 µs (at 5.0 MHz operation)

Note Refer to 2.1 Expanded-Specification Products and Conventional Products.

User’s Manual U14186EJ6V0UD

45

µ

CHAPTER 3 PIN FUNCTIONS (

PD789167 AND 789177 SUBSERIES)

3.1 Pin Function List

(1) Port pins

Pin Name I/O Function After Reset Alternate Function

P00 to P05 I/O Port 0

6-bit I/O port

I/O mode can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can

be specified by means of pull-up resistor option register 0

(PU0).

P10, P11 I/O Port 1

2-bit I/O port

I/O mode can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can

be specified by means of pull-up resistor option register 0

(PU0).

P20 SCK20/ASCK20

P21 SO20/TxD20

P22 SI20/RxD20

P23

P24

P25 TI80/SS20

P26

P30 INTP0/TI81/CPT90

P31 INTP1/TO81

P32 INTP2/TO90

P33

P50 to P53 I/O Port 5

P60 to P67 Input Port 6

I/O Port 2

7-bit I/O port

I/O mode can be specified in 1-bit units.

For P20 to P22, P25, and P26, an on-chip pull-up resistor

can be specified by means of pull-up resistor option register

B2 (PUB2).

Only P23 and P24 can be used as N-ch open-drain I/O port

pins.

I/O Port 3

4-bit I/O port

I/O mode can be specified in 1-bit units.

An on-chip pull-up resistor can be specified by means of pull-

up resistor option register B3 (PUB3).

4-bit N-ch open-drain I/O port

I/O mode can be specified in 1-bit units.

For a mask ROM version, an on-chip pull-up resistor can be

specified by the mask option.

8-bit input-only port

Input

Input

Input

TO80

Input

INTP3/TO82/BZO90

Input

Input ANI0 to ANI7

−

−

−

−

−

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CHAPTER 3 PIN FUNCTIONS (µPD789167 AND 789177 SUBSERIES)

(2) Non-port pins

Pin Name I/O Function After Reset Alternate Function

INTP0 P30/TI81/CPT90

INTP1 P31/TO81

INTP2 P32/TO90

INTP3

SI20 Input Serial data input to serial interface Input P22/RxD20

SO20 Output Serial data output from serial interface Input P21/TxD20

SCK20 I/O Serial clock I/O for serial interface Input P20/ASCK20

SS20 Input Chip select input to serial interface Input P25/TI80

ASCK20 Input Serial clock input for asynchronous serial interface Input P20/SCK20

RxD20 Input Serial data input for asynchronous serial interface Input P22/SI20

TxD20 Output Serial data output for asynchronous serial interface Input P21/SO20

TI80 Input External count clock input to 8-bit timer/event counter (TM80) Input P25/SS20

TI81 Input External count clock input to 8-bit timer/event counter (TM81) Input P30/INTP0/CPT90

TO80 Output 8-bit timer/event counter (TM80) output Input P26

TO81 Output 8-bit timer/event counter (TM81) output Input P31/INTP1

TO82 Output 8-bit timer (TM82) output Input P33/INTP3/BZO90

TO90 Output 16-bit timer (TM90) output Input P32/INTP2

CPT90 Input Capture edge input Input P30/INTP0/TI81

BZO90 Output Buzzer output Input P33/INTP3/TO82

ANI0 to ANI7 Input A/D converter analog input Input P60 to P67

AVREF

AVSS

AVDD

X1 Input

X2

XT1 Input

XT2

RESET Input System reset input Input

VDD0

VDD1

VSS0

VSS1

IC0

IC3

VPP

Input External interrupt input for which the valid edge (rising edge,

falling edge, or both rising and falling edges) can be specified

A/D converter reference voltage

−

A/D converter ground potential

−

A/D converter analog power supply

−

Connecting crystal resonator for main system clock oscillation

−

Connecting crystal resonator for subsystem clock oscillation

−

Positive power supply

−

Positive power supply (other than ports)

−

Ground potential

−

Ground potential (other than ports)

−

Internally connected. Connect this pin directly to the VSS0 or

−
V

SS1 pin.

Internally connected. Leave open.

−

This pin is used to set flash memory programming mode and

−
applies a high voltage when a program is written or verified.

Input

P33/TO82/BZO90

− −

− −

− −

− −

− −

− −

− −

−

− −

− −

− −

− −

− −

− −

− −

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CHAPTER 3 PIN FUNCTIONS (µPD789167 AND 789177 SUBSERIES)

3.2 Description of Pin Functions

3.2.1 P00 to P05 (Port 0)

These pins constitute a 6-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode

register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-

up resistor option register 0 (PU0).

3.2.2 P10, P11 (Port 1)

These pins constitute a 2-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode

register 1 (PM1). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-

up resistor option register 0 (PU0).

3.2.3 P20 to P26 (Port 2)

These pins constitute a 7-bit I/O port. In addition, these pins provide a function to perform I/O to/from the timer

and to I/O the data and clock of the serial interface.

Port 2 can be set to the following operation modes in 1-bit units.

(1) Port mode

In port mode, P20 to P26 function as a 7-bit I/O port. Port 2 can be set to input or output mode in 1-bit units

by using port mode register 2 (PM2). For P20 to P22, P25, and P26, whether to use on-chip pull-up resistors

can be specified in 1-bit units by using pull-up resistor option register B2 (PUB2), regardless of the setting of

port mode register 2 (PM2). P23 and P24 are N-ch open-drain I/O ports.

(2) Control mode

In this mode, P20 to P26 function as the timer I/O, the data I/O and the clock I/O of the serial interface.

(a) TI80

This is the external clock input pin for 8-bit timer/event counter 80.

(b) TO80

This is the timer output pin of 8-bit timer/event counter 80.

(c) SI20, SO20

These are the serial data I/O pins of the serial interface.

(d) SCK20

This is the serial clock I/O pin of the serial interface.

(e) SS20

This is the chip select input pin of the serial interface.

(f) RxD20, TxD20

These are the serial data I/O pins of the asynchronous serial interface.

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CHAPTER 3 PIN FUNCTIONS (µPD789167 AND 789177 SUBSERIES)

(g) ASCK20

This is the serial clock input pin of the asynchronous serial interface.

Caution When using P20 to P26 as serial interface pins, the I/O mode and output latch must be

set according to the function to be used. For details of the setting, see Table 14-2

Operating Mode Settings of Serial Interface 20.

3.2.4 P30 to P33 (Port 3)

These pins constitute a 4-bit I/O port. In addition, these pins function as the timer I/O and the external interrupt

input.

Port 3 can be set to the following operation modes in 1-bit units.

(1) Port mode

In port mode, P30 to P33 function as a 4-bit I/O port. Port 3 can be set to input or output mode in 1-bit units

by using port mode register 3 (PM3). Whether to use the on-chip pull-up resistor can be specified in 1-bit

units by using pull-up resistor option register B3 (PUB3), regardless of the setting of port mode register 3

(PM3).

(2) Control mode

In this mode, P30 to P33 function as the timer I/O and the external interrupt input.

(a) TI81

This is the external clock input pin for 8-bit timer/event counter 81.

(b) TO90, TO81, TO82

These are the output pins of 16-bit timer 90, 8-bit timer/event counter 81, and 8-bit timer 82.

(c) CPT90

This is the capture edge input pin of 16-bit timer 90.

(d) BZO90

This is the buzzer output pin of 16-bit timer 90.

(e) INTP0 to INTP3

These are external interrupt input pins for which the valid edge (rising edge, falling edge, and both the

rising and falling edges) can be specified.

3.2.5 P50 to P53 (Port 5)

These pins constitute a 4-bit N-ch open-drain I/O port. Port 5 can be set to input or output mode in 1-bit units by

using port mode register 5 (PM5). For a mask ROM version, whether a pull-up resistor is to be incorporated can be

specified by a mask option.

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CHAPTER 3 PIN FUNCTIONS (µPD789167 AND 789177 SUBSERIES)

3.2.6 P60 to P67 (Port 6)

These pins constitute an 8-bit input-only port. They can function as A/D converter input pins as well as a general-

purpose input port.

(1) Port mode

In port mode, P60 to P67 function as an 8-bit input-only port.

(2) Control mode

In control mode, P60 to P67 function as A/D converter analog inputs (ANI0 to ANI7).

3.2.7 RESET

A low-level active system reset signal is input to this pin.

3.2.8 X1, X2

These pins are used to connect a crystal resonator for main system clock oscillation.

To supply an external clock, input the clock to X1 and input the inverted signal to X2.

3.2.9 XT1, XT2

These pins are used to connect a crystal resonator for subsystem clock oscillation.

To supply an external clock, input the clock to XT1 and input the inverted signal to XT2.

3.2.10 AV

DD

Analog power supply pin of the A/D converter. Always use the same potential as that of the V

DD0 pin even when

the A/D converter is not used.

3.2.11 AV

SS

This is a ground potential pin of the A/D converter. Always use the same potential as that of the V

SS0 pin even

when the A/D converter is not used.

3.2.12 AV

REF

This is the A/D converter reference voltage input pin. When the A/D converter is not used, connect this pin to

V

DD0 or VSS0.

3.2.13 V

DD0, VDD1

V

DD0 is a positive power supply pin for ports.

V

DD1 is a positive power supply pin for other than ports.

3.2.14 V

SS0, VSS1

V

SS0 is a ground potential for ports pin.

V

SS1 is a ground potential pin for other than ports.

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CHAPTER 3 PIN FUNCTIONS (µPD789167 AND 789177 SUBSERIES)

3.2.15 VPP (flash memory version only)

High voltage application pin for flash memory programming mode setting and program write/verify.

Connect this pin in either of the following ways.

• Independently connect to a 10 kΩ pull-down resistor.

• By using a jumper on the board, connect directly to the dedicated flash programmer in the programming mode

or to V

SS in the normal operation mode.

If the wiring between the V

PP pin and VSS pin is very long or external noise is superimposed on the VPP pin, the

user program may not run correctly.

3.2.16 IC0 (mask ROM version only)

The IC0 (internally connected) pin is used to set the

shipment. In normal operation mode, directly connect this pin to the V

µ

PD789167 and 789177 Subseries to test mode before

SS0 or VSS1 pin with as short a wiring length as

possible.

If a potential difference is generated between the IC0 pin and V

SS0 or VSS1 pin due to a long wiring length or

external noise superimposed on the IC0 pin, the user program may not run correctly.

• Directly connect the IC0 pin to the V

SS0 or VSS1 pin.

3.2.17 IC3

The IC3 pin is internally connected. Leave this pin open.

V

SS0

,

IC0

SS1

V

Keep short

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CHAPTER 3 PIN FUNCTIONS (µPD789167 AND 789177 SUBSERIES)

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.

For the I/O circuit configuration of each type, refer to Figure 3-1.

Table 3-1. Types of I/O Circuits for Each Pin and Recommended Connection of Unused Pins

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins

Input: Independently connect to V

P00 to P05

5-H

P10, P11

P20/SCK20/ASCK20

8-C

P21/SO20/TxD20

P22/SI20/RxD20

P23

13-X Input: Independently connect to V

P24

P25/TI80/SS20

8-C

P26/TO80

P30/INTP0/TI81/CPT90

P31/INTP1/TO81

P32/INTP2/TO90

P33/INTP3/TO82/BZO90

P50 to P53 (mask ROM version) 13-U

P50 to P53 (flash memory version) 13-T

P60/ANI0 to P67/ANI7 9-C Input Connect directly to VDD0, VDD1, VSS0, or VSS1.

XT1 Input Connect directly to VSS0 or VSS1.

−

XT2

RESET 2 Input

IC0 (mask ROM version) Connect directly to VSS0 or VSS1.

− −

IC3 Leave open.

VPP (flash memory version)

I/O

DD0, VDD1 VSS0, or VSS1

via a resistor.

Output: Leave open.

DD0 or VDD1 via a resistor.

Output: Leave open.

Input: Independently connect to V

DD0, VDD1, VSS0, or VSS1

via a resistor.

Output: Leave open.

Input: Independently connect to V

SS0 or VSS1 via a resistor.

Output: Leave open.

Input: Connect to V

SS0 or VSS1.

Output: Leave open.

Leave open.

−

−

Independently connect via a 10 kΩ pull-down resistor, or

connect directly to V

SS0 or VSS1.

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CHAPTER 3 PIN FUNCTIONS (µPD789167 AND 789177 SUBSERIES)

Figure 3-1. Pin I/O Circuits

Type 2

IN

Schmitt-triggered input with hysteresis characteristics

Type 13-T

Output data

Output disable

N-ch

V

SS0

Input enable

Input buffer with intermediate withstanding voltage

IN/OUT

Type 5-H

Pull-up
enable

Data

Output
disable

Input
enable

Type 8-C

Pull-up
enable

Data

Output
disable

DD0

V

P-ch

DD0

V

P-ch

IN/OUT

N-ch

V

SS0

Type 13-U

Output data

Output disable

Input enable

Pull-up resistor

(mask option)

V

SS0

V

N-ch

DD0

IN/OUT

Input buffer with intermediate withstanding voltage

DD0

V

Type 13-X

P-ch

IN/OUT

DD0

V

P-ch

Output data

Output disable

N-ch

V

SS0

IN/OUT

N-ch

V

SS0

Input buffer with 5 V
withstanding voltage

Comparator

Type 9-C

IN

P-ch
N-ch

AV

SS

V

REF

(Threshold voltage)

Comparator

+

−

Input
enable

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53

µ

CHAPTER 4 PIN FUNCTIONS (

PD789167Y AND 789177Y SUBSERIES)

4.1 Pin Function List

(1) Port pins

Pin Name I/O Function After Reset Alternate Function

P00 to P05 I/O Port 0

6-bit I/O port

I/O mode can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can

be specified by means of pull-up resistor option register 0

(PU0).

P10, P11 I/O Port 1

2-bit I/O port

I/O mode can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can

be specified by means of pull-up resistor option register 0

(PU0).

P20 SCK20/ASCK20

P21 SO20/TxD20

P22 SI20/RxD20

P23 SCL0

P24 SDA0

P25 TI80/SS20

P26

P30 INTP0/TI81/CPT90

P31 INTP1/TO81

P32 INTP2/TO90

P33

P50 to P53 I/O Port 5

P60 to P67 Input Port 6

I/O Port 2

7-bit I/O port

I/O mode can be specified in 1-bit units.

For P20 to P22, P25, and P26, an on-chip pull-up resistor

can be specified by means of pull-up resistor option register

B2 (PUB2).

Only P23 and P24 can be used as N-ch open-drain I/O port

pins.

I/O Port 3

4-bit I/O port

I/O mode can be specified in 1-bit units.

An on-chip pull-up resistor can be specified by means of pull-

up resistor option register B3 (PUB3).

4-bit N-ch open-drain I/O port

I/O mode can be specified in 1-bit units.

For a mask ROM version, an on-chip pull-up resistor can be

specified by the mask option.

8-bit input-only port

Input

Input

Input

TO80

Input

INTP3/TO82/BZO90

Input

Input ANI0 to ANI7

−

−

−

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CHAPTER 4 PIN FUNCTIONS (µPD789167Y AND 789177Y SUBSERIES)

(2) Non-port pins

Pin Name I/O Function After Reset Alternate Function

INTP0 P30/TI81/CPT90

INTP1 P31/TO81

INTP2 P32/TO90

INTP3

SI20 Input Serial data input to serial interface Input P22/RxD20

SO20 Output Serial data output from serial interface Input P21/TxD20

SCK20 I/O Serial clock I/O for serial interface Input P20/ASCK20

SS20 Input Chip select input to serial interface Input P25/TI80

ASCK20 Input Serial clock input for asynchronous serial interface Input P20/SCK20

RxD20 Input Serial data input for asynchronous serial interface Input P22/SI20

TxD20 Output Serial data output for asynchronous serial interface Input P21/SO20

SCL0 I/O SMB0 clock I/O Input P23

SDA0 I/O SMB0 data I/O Input P24

TI80 Input External count clock input to 8-bit timer/event counter (TM80) Input P25/SS20

TI81 Input External count clock input to 8-bit timer/event counter (TM81) Input P30/INTP0/CPT90

TO80 Output 8-bit timer/event counter (TM80) output Input P26

TO81 Output 8-bit timer/event counter (TM81) output Input P31/INTP1

TO82 Output 8-bit timer (TM82) output Input P33/INTP3/BZO90

TO90 Output 16-bit timer (TM90) output Input P32/INTP2

CPT90 Input Capture edge input Input P30/INTP0/TI81

BZO90 Output Buzzer output Input P33/INTP3/TO82

ANI0 to ANI7 Input A/D converter analog input Input P60 to P67

AVREF

AVSS

AVDD

X1 Input

X2

XT1 Input

XT2

RESET Input System reset input Input

VDD0

VDD1

VSS0

VSS1

IC0

IC2

VPP

Input External interrupt input for which the valid edge (rising edge,

falling edge, or both rising and falling edges) can be specified

A/D converter reference voltage

−

A/D converter ground potential

−

A/D converter analog power supply

−

Connecting crystal resonator for main system clock oscillation

−

Connecting crystal resonator for subsystem clock oscillation

−

Positive power supply

−

Positive power supply (other than ports)

−

Ground potential

−

Ground potential (other than ports)

−

Internally connected. Connect this pin directly to the VSS0 or

−
V

SS1 pin.

Internally connected. Leave this pin open.

−

This pin is used to set flash memory programming mode and

−
applies a high voltage when a program is written or verified.

Input

P33/TO82/BZO90

− −

− −

− −

− −

− −

− −

− −

−

− −

− −

− −

− −

− −

− −

− −

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CHAPTER 4 PIN FUNCTIONS (µPD789167Y AND 789177Y SUBSERIES)

4.2 Description of Pin Functions

4.2.1 P00 to P05 (Port 0)

These pins constitute a 6-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode

register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-

up resistor option register 0 (PU0).

4.2.2 P10, P11 (Port 1)

These pins constitute a 2-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode

register 1 (PM1). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-

up resistor option register 0 (PU0).

4.2.3 P20 to P26 (Port 2)

These pins constitute a 7-bit I/O port. In addition, these pins provide a function to perform I/O to/from the timer

and to I/O the data and clock of the serial interface.

Port 2 can be set to the following operation modes in 1-bit units.

(1) Port mode

In port mode, P20 to P26 function as a 7-bit I/O port. Port 2 can be set to input or output mode in 1-bit units

by using port mode register 2 (PM2). For P20 to P22, P25, and P26, whether to use on-chip pull-up resistors

can be specified in 1-bit units by using pull-up resistor option register B2 (PUB2), regardless of the setting of

port mode register 2 (PM2). P23 and P24 are N-ch open-drain I/O ports.

(2) Control mode

In this mode, P20 to P26 function as the timer I/O, the data I/O and the clock I/O of the serial interface.

(a) TI80

This is the external clock input pin for 8-bit timer/event counter 80.

(b) TO80

This is the timer output pin of 8-bit timer/event counter 80.

(c) SI20, SO20

These are the serial data I/O pins of the serial interface.

(d) SCK20

This is the serial clock I/O pin of the serial interface.

(e) SS20

This is the chip select input pin of the serial interface.

(f) RxD20, TxD20

These are the serial data I/O pins of the asynchronous serial interface.

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CHAPTER 4 PIN FUNCTIONS (µPD789167Y AND 789177Y SUBSERIES)

(g) ASCK20

This is the serial clock input pin of the asynchronous serial interface.

(h) SCL0

This is the clock I/O pin of SMB0.

(i) SDA0

This is the data I/O pin of SMB0.

Caution When using P20 to P26 as serial interface pins, the I/O mode and output latch must be

set according to the function to be used. For details of the setting, see Table 14-2

Operating Mode Setting of Serial Interface 20.

4.2.4 P30 to P33 (Port 3)

These pins constitute a 4-bit I/O port. In addition, these pins function as the timer I/O and the external interrupt

input.

Port 3 can be set to the following operation modes in 1-bit units.

(1) Port mode

In port mode, P30 to P33 function as a 4-bit I/O port. Port 3 can be set to input or output mode in 1-bit units

by using port mode register 3 (PM3). Whether to use the on-chip pull-up resistor can be specified in 1-bit

units by using pull-up resistor option register B3 (PUB3), regardless of the setting of port mode register 3

(PM3).

(2) Control mode

In this mode, P30 to P33 function as the timer I/O and the external interrupt input.

(a) TI81

This is the external clock input pin for 8-bit timer/event counter 81.

(b) TO90, TO81, TO82

These are the output pins of 16-bit timer 90, 8-bit timer/event counter 81, and 8-bit timer 82.

(c) CPT90

This is the capture edge input pin of 16-bit timer 90.

(d) BZO90

This is the buzzer output pin of 16-bit timer 90.

(e) INTP0 to INTP3

These are external interrupt input pins for which the valid edge (rising edge, falling edge, and both the

rising and falling edges) can be specified.

4.2.5 P50 to P53 (Port 5)

These pins constitute a 4-bit N-ch open-drain I/O port. Port 5 can be set to input or output mode in 1-bit units by

using port mode register 5 (PM5). For a mask ROM version, whether a pull-up resistor is to be incorporated can be

specified by a mask option.

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CHAPTER 4 PIN FUNCTIONS (µPD789167Y AND 789177Y SUBSERIES)

4.2.6 P60 to P67 (Port 6)

These pins constitute an 8-bit input-only port. They can function as A/D converter input pins as well as a general-

purpose input port.

(1) Port mode

In port mode, P60 to P67 function as an 8-bit input-only port.

(2) Control mode

In control mode, P60 to P67 function as A/D converter analog inputs (ANI0 to ANI7).

4.2.7 RESET

A low-level active system reset signal is input to this pin.

4.2.8 X1, X2

These pins are used to connect a crystal resonator for main system clock oscillation.

To supply an external clock, input the clock to X1 and input the inverted signal to X2.

4.2.9 XT1, XT2

These pins are used to connect a crystal resonator for subsystem clock oscillation.

To supply an external clock, input the clock to XT1 and input the inverted signal to XT2.

4.2.10 AV

DD

Analog power supply pin of the A/D converter. Always use the same potential as that of the V

DD0 pin even when

the A/D converter is not used.

4.2.11 AV

SS

This is a ground potential pin of the A/D converter. Always use the same potential as that of the V

SS0 pin even

when the A/D converter is not used.

4.2.12 AV

REF

This is the A/D converter reference voltage input pin. When the A/D converter is not used, connect this pin to

V

DD0 or VSS0.

4.2.13 V

DD0, VDD1

V

DD0 is a positive power supply pin for ports.

V

DD1 is a positive power supply pin for other than ports.

4.2.14 V

SS0, VSS1

V

SS0 is a ground potential pin for ports.

V

SS1 is a ground potential pin for other than ports.

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4.2.15 VPP (flash memory version only)

High voltage apply pin for flash memory programming mode setting and program write/verify.

Connect this pin in either of the following ways.

• Independently connect to a 10 kΩ pull-down resistor.

• By using a jumper on the board, connect directly to the dedicated flash programmer in the programming mode

or to V

SS in the normal operation mode.

If the wiring between the V

PP pin and VSS pin is very long or external noise is superimposed on the VPP pin, the

user program may not run correctly.

4.2.16 IC0 (mask ROM version only)

The IC0 (internally connected) pin is used to set the

shipment. In normal operation mode, directly connect this pin to the V

µ

PD789167Y and 789177Y Subseries to test mode before

SS0 or VSS1 pin with as short a wiring length as

possible.

If a potential difference is generated between the IC0 pin and V

SS0 or VSS1 pin due to a long wiring length or

external noise superimposed on the IC0 pin, the user program may not run correctly.

• Directly connect the IC0 pin to the V

SS0 or VSS1 pin.

4.2.17 IC2

The IC2 pin is internally connected. Leave this pin open.

V

SS0

,

SS1

V

IC0

Keep short

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CHAPTER 4 PIN FUNCTIONS (µPD789167Y AND 789177Y SUBSERIES)

4.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 4-1.

For the I/O circuit configuration of each type, refer to Figure 4-1.

Table 4-1. Types of I/O Circuits for Each Pin and Recommended Connection of Unused Pins

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins

I/O

P00 to P05

5-H

P10, P11

P20/SCK20/ASCK20

8-C

P21/SO20/TxD20

P22/SI20/RxD20

P23/SCL0

13-X Input: Independently connect to V

P24/SDA0

P25/TI80/SS20

8-C

P26/TO80

P30/INTP0/TI81/CPT90

P31/INTP1/TO81

P32/INTP2/TO90

P33/INTP3/TO82/BZO90

P50 to P53 (mask ROM version) 13-U

P50 to P53 (flash memory version) 13-T

P60/ANI0 to P67/ANI7 9-C Input Connect directly to VDD0, VDD1, VSS0, or VSS1.

XT1 Input Connect directly to VSS0 or VSS1.

−

XT2

RESET 2 Input

IC0 (mask ROM version) Connect directly to VSS0 or VSS1.

− −

IC2 Leave open.

VPP (flash memory version)

Input: Independently connect to V

DD0, VDD1, VSS0, or VSS1

via a resistor.

Output: Leave open.

DD0 or VDD1 via a resistor.

Output: Leave open.

Input: Independently connect to V

DD0, VDD1, VSS0, or VSS1

via a resistor.

Output: Leave open.

Input: Independently connect to V

SS0 or VSS1 via a resistor.

Output: Leave open.

Input: Connect to V

SS0 or VSS1.

Output: Leave open.

Leave open.

−

−

Independently connect via a 10 kΩ pull-down resistor, or

connect directly to V

SS0 or VSS1.

60

User’s Manual U14186EJ6V0UD

CHAPTER 4 PIN FUNCTIONS (µPD789167Y AND 789177Y SUBSERIES)

Figure 4-1. Pin I/O Circuits

Type 2

IN

Schmitt-triggered input with hysteresis characteristics

Type 5-H

Pull-up
enable

Data

DD0

V

P-ch

DD0

V

P-ch

IN/OUT

Output
disable

N-ch

VSS0

Input
enable

Type 13-T

Output data

Output disable

N-ch

V

SS0

Input enable

Input buffer with intermediate withstanding voltage

Type 13-U

V

DD0

Pull-up resistor

(mask option)

Output data

Output disable

N-ch

VSS0

Input enable

Input buffer with intermediate withstanding voltage

IN/OUT

IN/OUT

Type 8-C

Pull-up
enable

Data

Output
disable

Type 9-C

IN

P-ch
N-ch

V

VSS0

AV

SS

VREF

(Threshold voltage)

DD0

V

P-ch

DD0

P-ch

N-ch

Comparator

+

−

Input
enable

IN/OUT

Type 13-X

Output data

Output disable

Input buffer with 5 V
withstanding voltage

Comparator

IN/OUT

N-ch

VSS0

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CHAPTER 5 CPU ARCHITECTURE

5.1 Memory Space

Products in the µPD789167, 789177, 789167Y, and 789177Y Subseries can each access up to 64 KB of memory

space. Figures 5-1 through 5-3 show the memory maps.

Figure 5-1. Memory Map (

FFFFH

FF00H
FEFFH

FD00H
FCFFH

µ

PD789166, µPD789176, µPD789166Y, and µPD789176Y)

Special-function registers

256 × 8 bits

Internal high-speed RAM

512 × 8 bits

Data memory space

4000H
3FFFH

Program memory
space

0000H

Reserved

Internal ROM

16,384 × 8 bits

3FFFH

0080H
007FH

0040H
003FH

0024H
0023H

0000H

Program area

CALLT table area

Program area

Vector table area

62

User’s Manual U14186EJ6V0UD

Data memory space

CHAPTER 5 CPU ARCHITECTURE

Figure 5-2. Memory Map (µPD789167, µPD789177, µPD789167Y, and µPD789177Y)

FFFFH

Special-function registers

256 × 8 bits

FF00H
FEFFH

Internal high-speed RAM

512 × 8 bits

FD00H
FCFFH

Reserved

5FFFH

6000H
5FFFH

Program area

Program memory
space

0000H

Internal ROM

24,576 × 8 bits

0080H
007FH

0040H
003FH

0024H
0023H

0000H

CALLT table area

Program area

Vector table area

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63

Figure 5-3. Memory Map (µPD78F9177, µPD78F9177Y, µPD78F9177A, and µPD78F9177AY)

Data memory space

CHAPTER 5 CPU ARCHITECTURE

FFFFH

Special-function registers

256 × 8 bits

FF00H
FEFFH

Internal high-speed RAM

512 × 8 bits

FD00H
FCFFH

Reserved

5FFFH

6000H
5FFFH

Program area

Program memory
space

0000H

Internal flash memory

24,576 × 8 bits

0080H
007FH

0040H
003FH

0024H
0023H

0000H

CALLT table area

Program area

Vector table area

64

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CHAPTER 5 CPU ARCHITECTURE

5.1.1 Internal program memory space

The internal program memory space stores programs and table data. This space is usually addressed by the

program counter (PC).

The

µ

PD789167, 789177, 789167Y, and 789177Y Subseries provide the following internal ROM (or flash

memory) containing the following capacities.

Table 5-1. Internal ROM Capacity

Internal ROM Part Number

Structure Capacity

µ

PD789166, µPD789176, µPD789166Y, µPD789176Y 16,384 × 8 bits

µ

PD789167, µPD789177, µPD789167Y, µPD789177Y

µ

PD78F9177, µPD78F9177Y, µPD78F9177A, µPD

78F9177AY

Mask ROM

24,576 × 8 bits

Flash memory 24,576 × 8 bits

The following areas are allocated to the internal program memory space.

(1) Vector table area

A 36-byte area of addresses 0000H to 0023H is reserved as a vector table area. This area stores program

start addresses to be used when branching by RESET input or interrupt request generation. Of a

16-bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an

odd address.

Table 5-2. Vector Table

Vector Table Address Interrupt Request Vector Table Address Interrupt Request

0000H RESET input 0014H INTWTI

0004H INTWDT 0016H INTTM80

0006H INTP0 0018H INTTM81

0008H INTP1 001AH INTTM82

000AH INTP2 001CH INTTM90

000CH INTP3 001EH INTSMB0

000EH INTSR20/INTCSI20 0020H INTSMBOV0

0010H INTST20 0022H INTAD0

Note

Note

0012H INTWT

Note For the

µ

PD789167Y and 789177Y Subseries only

(2) CALLT instruction table area

The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in a 64-byte area of

addresses 0040H to 007FH.

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CHAPTER 5 CPU ARCHITECTURE

5.1.2 Internal data memory (internal high-speed RAM) space

The

µ

PD789167, 789177, 789167Y, and 789177Y Subseries provide a 512-byte internal high-speed RAM.

The internal high-speed RAM can also be used as a stack memory.

5.1.3 Special-function register (SFR) area

Special-function registers (SFRs) of on-chip peripheral hardware are allocated to an area of FF00H to FFFFH

(see Table 5-3).

5.1.4 Data memory addressing

Each of the

µ

PD789167, 789177, 789167Y, 789177Y Subseries is provided with a wide range of addressing

modes to make memory manipulation as efficient as possible. A data memory area (FD00H to FFFFH) can be

accessed using a unique addressing mode according to its use, such as a special-function register (SFR). Figures 5-

4 through 5-6 illustrate the data memory addressing modes.

Figure 5-4. Data Memory Addressing Modes (

µ

PD789166, µPD789176, µPD789166Y, and µPD789176Y)

FFFFH

Special-function registers (SFR)

256 × 8 bits

FF20H
FF1FH

SFR addressing

FF00H
FEFFH

FE20H
FE1FH

FD00H
FCFFH

4000H
3FFFH

Internal high-speed RAM

512 × 8 bits

Reserved

Short direct addressing

Direct addressing

Register indirect addressing

Based addressing

66

0000H

Internal ROM

16,384 × 8 bits

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CHAPTER 5 CPU ARCHITECTURE

Figure 5-5. Data Memory Addressing Modes (µPD789167, µPD789177, µPD789167Y, and µPD789177Y)

FFFFH

Special-function registers (SFR)

256 × 8 bits

FF20H
FF1FH

FF00H
FEFFH

SFR addressing

FE20H
FE1FH

FD00H
FCFFH

6000H
5FFFH

Internal high-speed RAM

512 × 8 bits

Reserved

Internal ROM

24,576 × 8 bits

Short direct addressing

Direct addressing

Register indirect addressing

Based addressing

0000H

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67

CHAPTER 5 CPU ARCHITECTURE

Figure 5-6. Data Memory Addressing Modes (µPD78F9177, µPD78F9177Y, µPD78F9177A, and

µ

PD78F9177AY)

FFFFH

Special-function registers (SFR)

256 × 8 bits

FF20H
FF1FH

FF00H
FEFFH

SFR addressing

FE20H
FE1FH

FD00H
FCFFH

6000H
5FFFH

Internal high-speed RAM

512 × 8 bits

Reserved

Internal flash memory

24,576 × 8 bits

Short direct addressing

Direct addressing

Register indirect addressing

Based addressing

68

0000H

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CHAPTER 5 CPU ARCHITECTURE

5.2 Processor Registers

The µPD789167, 789177, 789167Y, and 789177Y Subseries provide the following on-chip processor registers.

5.2.1 Control registers

The control registers have special functions to control the program sequence statuses and stack memory. The

control registers include a program counter, a program status word, and a stack pointer.

(1) Program counter (PC)

The program counter is a 16-bit register which holds the address information of the next program to be

executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction

to be fetched. When a branch instruction is executed, immediate data or register contents are set.

RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 5-7. Program Counter Configuration

015

PC14PC15PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruction

execution.

Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW

instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions.

RESET input sets the PSW to 02H.

Figure 5-8. Program Status Word Configuration

70

PSW

IE

Z 0 AC 0 0 1 CY

User’s Manual U14186EJ6V0UD

69

(a) Interrupt enable flag (IE)

This flag controls interrupt request acknowledgment operations of the CPU.

When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests except non-maskable interrupt

are disabled.

When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with

an interrupt mask flag for various interrupt sources.

This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI

instruction execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.

(c) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all

other cases.

(d) Carry flag (CY)

This flag stores an overflow or underflow that occurs upon add/subtract instruction execution. It stores the

shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation

instruction execution.

CHAPTER 5 CPU ARCHITECTURE

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User’s Manual U14186EJ6V0UD

(3) Stack pointer (SP)

This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high-

speed RAM area can be set as the stack area.

SP14SP15SP SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of writing (saving) to the stack memory and is incremented after reading

(restoring) from the stack memory.

Each stack operation saves/restores data as shown in Figures 5-10 and 5-11.

Caution Since RESET input makes SP contents undefined, be sure to initialize the SP before using

the stack.

CHAPTER 5 CPU ARCHITECTURE

Figure 5-9. Stack Pointer Configuration

015

Figure 5-10. Data to Be Saved to Stack Memory

SP SP _ 2

SP _ 2

SP _ 1

SP

SP

SP + 1

PUSH rp
instruction

Register pair
lower

Register pair
higher

SP SP _ 2

SP _ 2

SP _ 1

SP

CALL, CALLT
instructions

PC7 to PC0

PC15 to PC8

Figure 5-11. Data to Be Restored from Stack Memory

instruction

Register pair
lower

Register pair
higher

SP

SP + 1

RET instructionPOP rp

PC7 to PC0

PC15 to PC8

SP SP _ 3

SP _ 3

SP _ 2

SP _ 1

SP

SP

SP + 1

Interrupt

PC7 to PC0

PC15 to PC8

PSW

RETI instruction

PC7 to PC0

PC15 to PC8

SP SP + 2

SP SP + 2

User’s Manual U14186EJ6V0UD

SP + 2

SP SP + 3

PSW

71

CHAPTER 5 CPU ARCHITECTURE

5.2.2 General-purpose registers

The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).

In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit

register (AX, BC, DE, and HL).

They can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute

names (R0 to R7 and RP0 to RP3).

Figure 5-12. General-Purpose Register Configuration

(a) Absolute names

16-bit processing 8-bit processing

R7

RP3

R6

R5

RP2

RP1

RP0

15 0 7 0

R4

R3

R2

R1

R0

(b) Functional names

16-bit processing 8-bit processing

H

HL

L

72

D

DE

E

B

BC

C

A

AX

X

15 0 7 0

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CHAPTER 5 CPU ARCHITECTURE

5.2.3 Special-function registers (SFR)

Unlike a general-purpose register, each special-function register has a special function.

They are allocated to the 256-byte area FF00H to FFFFH.

The special-function registers can be manipulated, like the general-purpose registers, with operation, transfer, and

bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special-function register

type.

Each manipulation bit unit can be specified as follows.

• 1-bit manipulation

Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This

manipulation can also be specified with an address.

• 8-bit manipulation

Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This

manipulation can also be specified with an address.

• 16-bit manipulation

Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifying

an address, describe an even address.

Table 5-3 lists the special-function registers. The meanings of the symbols in this table are as follows.

• Symbol

Indicates the addresses of the implemented special-function registers. The symbols shown in this column are

reserved words in the assembler, and have already been defined as sfr variables by the #pragma sfr directive in

the C compiler. Therefore, these symbols can be used as instruction operands if an assembler or integrated

debugger is used.

• R/W

Indicates whether the special-function register can be read or written.

R/W: Read/write

R: Read only

W: Write only

• Bit units for manipulation

Indicates the bit units (1, 8, and 16) in which the special-function register can be manipulated.

• After reset

Indicates the status of the special-function register when the RESET signal is input.

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CHAPTER 5 CPU ARCHITECTURE

Table 5-3. Special-Function Registers (1/2)

Symbol R/W

Name

FF00H Port 0 P0

FF01H Port 1 P1

FF02H Port 2 P2

FF03H Port 3 P3

FF05H Port 5 P5

FF06H Port 6 P6

FF10H

FF11H

FF14H

FF15H

FF16H

FF17H

FF18H

FF19H

FF1AH

FF1BH

FF20H Port mode register 0 PM0

FF21H Port mode register 1 PM1

FF22H Port mode register 2 PM2

FF23H Port mode register 3 PM3

FF25H Port mode register 5 PM5

FF32H Pull-up resistor option register B2 PUB2

FF33H Pull-up resistor option register B3 PUB3

FF42H Timer clock selection register 2 TCL2

FF48H 16-bit timer mode control register 90 TMC90

FF49H Buzzer output control register 90 BZC90

FF4AH Watch timer mode control register WTM

FF50H 8-bit compare register 80 CR80 W

FF51H 8-bit timer counter 80 TM80 R

FF53H 8-bit timer mode control register 80 TMC80 R/W

16-bit multiplication result storage
register 0

A/D conversion result register 0 ADCR0

16-bit compare register 90

16-bit timer counter 90

16-bit capture register 90

MUL0L

MUL0H

CR90L

CR90H

TM90L

TM90H

TCP90L

TCP90H

MUL0

CR90

TM90

TCP90

R/W

R

W

R

R/W

Bit Units for Manipulation Address Special-Function Register (SFR)

1 Bit 8 Bits 16 Bits

√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −

− −

−

− −

− −

− −

√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −

− √ −
√ √ −
√ √ −
√ √ −

− √ −

− √ −

√ √ −

√

Note 1

√

Notes 2, 3

√

Note 2

Notes 2, 3

√

Notes 2, 3

√

Notes 2, 3

√

After Reset

00H

Undefined

FFFFH

0000H

Undefined

FFH

00H

Undefined

00H

Notes 1. When using this register with an 8-bit A/D converter (µPD789167 or 789167Y Subseries), the register

can be accessed in 8-bit units. At this time, the address is FF15H.

When using this register with a 10-bit A/D converter (

can be accessed only in 16-bit units. When the

counterpart of the

µ

PD789166 or µPD789167, is used, the register can be accessed in 8-bit units.

However, only an object file assembled with the

also true for the

or

µ

PD789167Y. When the µPD78F9177Y or µPD78F9177AY is used, the register can be accessed in

µ

PD78F9177Y or µPD78F9177AY, the flash memory counterpart of the µPD789166Y

8-bit units. However, only an object file assembled with the

µ

PD789177 or 789177Y Subseries), the register

µ

PD78F9177 or µPD78F9177A, the flash memory

µ

PD789166 or µPD789167 can be used. The same is

µ

PD789166Y and µPD789167Y can be

used.

2. 16-bit access is allowed only with short direct addressing.

3. MUL0, CR90, TM90, and TCP90 are designed only for 16-bit access. With direct addressing, however,

they can also be accessed in 8-bit mode.

74

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CHAPTER 5 CPU ARCHITECTURE

Table 5-3. Special-Function Registers (2/2)

Symbol R/W

Name

FF54H 8-bit compare register 81 CR81 W

FF55H 8-bit timer counter 81 TM81 R

FF57H 8-bit timer mode control register 81 TMC81 R/W

FF58H 8-bit compare register 82 CR82 W

FF59H 8-bit timer counter 82 TM82 R

FF5BH 8-bit timer mode control register 82 TMC82

FF70H Asynchronous serial interface mode

ASIM20

R/W

register 20

FF71H Asynchronous serial interface status

ASIS20 R

register 20

FF72H Serial operation mode register 20 CSIM20

FF73H Baud rate generator control register

BRGC20

R/W

20

Transmission shift register 20

Reception buffer register 20

FF78H SMB control register 0

FF79H SMB status register 0

FF7AH SMB clock selection register 0

FF7BH SMB slave address register 0

FF7CH SMB mode register 0

Note

SMBC0 R/W

Note

SMBS0 R

Note

Note

Note

SMBM0

FF7DH SMB input level setting register 0

FF7EH SMB shift register 0

Note

SMB0

SMBCL0

SMBSVA0

Note

SMBVI0

TXS20

RXB2

0

SIO20

R/W

FF80H A/D converter mode register 0 ADM0

FF84H A/D input selection register 0 ADS0

FFD0H Multiplication data register A0 MRA0

FFD1H Multiplication data register B0 MRB0

FFD2H Multiplier control register 0 MULC0

R/W

FFE0H Interrupt request flag register 0 IF0

FFE1H Interrupt request flag register 1 IF1

FFE4H Interrupt mask flag register 0 MK0

FFE5H Interrupt mask flag register 1 MK1

FFECH External interrupt mode register 0 INTM0

FFEDH External interrupt mode register 1 INTM1

FFF0H Suboscillation mode register SCKM

FFF2H Subclock control register CSS

FFF7H Pull-up resistor option register 0 PU0

FFF9H Watchdog timer mode register WDTM

FFFAH Oscillation stabilization time

OSTS

selection register

FFFBH Processor clock control register PCC

Note For the

µ

PD789167Y and 789177Y Subseries only

W

R

W

Bit Units for Manipulation Address Special-Function Register (SFR)

1 Bit 8 Bits 16 Bits

− √ −

− √ −
√ √ −

− √ −

− √ −
√ √ −
√ √ −

√ √ −

√ √ −

− √ −

− √ −

− √ −

√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −

− √ −

− √ −
√ √ −
√ √ −
√ √ −
√ √ −

− √ −

√ √ −

After Reset

Undefined

00H

Undefined

00H

FFH FF74H

Undefined

00H

20H

00H

Undefined

00H

FFH

00H

04H

02H

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CHAPTER 5 CPU ARCHITECTURE

5.3 Instruction Address Addressing

An instruction address is determined by the program counter (PC) contents. The PC contents are normally

incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each

time another instruction is executed. When a branch instruction is executed, the branch destination information is set

to the PC and branched by the following addressing (for details of each instruction, refer to 78K/0S Series

Instruction User’s Manual (U11047E)).

5.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the

start address of the following instruction is transferred to the program counter (PC) and branched. The

displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign bit. In

other words, the range of branch in relative addressing is between –128 and +127 of the start address of the

following instruction.

This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15 0

PC

+

15 0

α

15 0

PC

When S = 0, α indicates all bits "0".
When S = 1, α indicates all bits "1".

876

S

jdisp8

...

PC is the start address of
the next instruction of
a BR instruction.

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CHAPTER 5 CPU ARCHITECTURE

5.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched.

This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed.

CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces.

[Illustration]

In case of CALL !addr16 and BR !addr16 instructions

70

CALL or BR

Low Addr.

High Addr.

15 0

PC

87

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CHAPTER 5 CPU ARCHITECTURE

5.3.3 Table indirect addressing

[Function]

Table contents (branch destination address) of the particular location to be addressed by the immediate data of

an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.

Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can be

used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH.

[Illustration]

765 10

Instruction code

Effective address

ta4−0

15 1

00000000

01

001

87

65 0

0

Memory (table)

70

Lower addr.

Effective address + 1

15 0

PC

Higher addr.

87

5.3.4 Register addressing

[Function]

Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)

and branched.

This function is carried out when the BR AX instruction is executed.

[Illustration]

70

rp

AX

07

78

15 0

PC

87

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CHAPTER 5 CPU ARCHITECTURE

5.4 Operand Address Addressing

The following methods are available to specify the register and memory (addressing) which undergo manipulation

during instruction execution.

5.4.1 Direct addressing

[Function]

The memory indicated by immediate data in an instruction word is directly addressed.

[Operand format]

Identifier Description

addr16 Label or 16-bit immediate data

[Description example]

MOV A, !FE00H; When setting !addr16 to FE00H

Instruction code 0 0 1 0 1 0 0 1 OP code

0 0 0 0 0 0 0 0 00H

1 1 1 1 1 1 1 0 FEH

[Illustration]

70

OP code

addr16 (lower)

addr16 (higher)

Memory

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CHAPTER 5 CPU ARCHITECTURE

5.4.2 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.

The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal high-

speed RAM and special-function registers (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH,

respectively.

The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area. In

this area, ports which are frequently accessed in a program and a compare register of the timer counter are

mapped, and these SFRs can be manipulated with a small number of bytes and clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,

bit 8 is set to 1. See [Illustration] below.

[Operand format]

Identifier Description

saddr Label or FE20H to FF1FH immediate data

saddrp Label or FE20H to FF1FH immediate data (even address only)

[Description example]

MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H

Instruction code 1 1 1 1 0 1 0 1 OP code

1 0 0 1 0 0 0 0 90H (saddr-offset)

0 1 0 1 0 0 0 0 50H (immediate data)

[Illustration]

07

OP code

saddr-offset

8

α

0
Effective
address

15

1

111111

Short direct memory

80

When 8-bit immediate data is 20H to FFH, = 0.
When 8-bit immediate data is 00H to 1FH, = 1.

α
α

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CHAPTER 5 CPU ARCHITECTURE

5.4.3 Special-function register (SFR) addressing

[Function]

The memory-mapped special-function registers (SFR) are addressed with 8-bit immediate data in an instruction

word.

This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to

FF1FH can also be accessed with short direct addressing.

[Operand format]

Identifier Description

sfr Special-function register name

[Description example]

MOV PM0, A; When selecting PM0 for sfr

Instruction code 1 1 1 0 0 1 1 1

0 0 1 0 0 0 0 0

[Illustration]

Effective
address

OP code

sfr-offset

15

1

111111

07

87

1

SFR

0

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CHAPTER 5 CPU ARCHITECTURE

5.4.4 Register addressing

[Function]

The general-purpose registers are accessed as operands. The general-purpose register to be accessed is

specified by the register specification code and functional name in the instruction code.

Register addressing is carried out when an instruction with the following operand format is executed. When an

8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.

[Operand format]

Identifier Description

r X, A, C, B, E, D, L, H

rp AX, BC, DE, HL

‘r’ and ‘rp’ can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A,

C, B, E, D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; When selecting the C register for r

Instruction code 0 0 0 0 1 0 1 0

0 0 1 0 0 1 0 1

Register specify code

INCW DE; When selecting the DE register pair for rp

Instruction code 1 0 0 0 1 0 0 0

Register specify code

82

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CHAPTER 5 CPU ARCHITECTURE

5.4.5 Register indirect addressing

[Function]

The memory is addressed with the contents of the register pair specified as an operand. The register pair to be

accessed is specified with the register pair specify code in the instruction code. This addressing can be carried

out for all the memory spaces.

[Operand format]

Identifier Description

−

[DE], [HL]

[Description example]

MOV A, [DE]; When selecting register pair [DE]

Instruction code 0 0 1 0 1 0 1 1

[Illustration]

15 08D7

DE

The contents of addressed
memory are transferred

7 0

A

E

07

Memory address specified
by register pair DE

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CHAPTER 5 CPU ARCHITECTURE

5.4.6 Based addressing

[Function]

8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is

used to address the memory. Addition is performed by expanding the offset data as a positive number to 16

bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier Description

−

[HL+byte]

[Description example]

MOV A, [HL+10H]; When setting byte to 10H

Instruction code 0 0 1 0 1 1 0 1

0 0 0 1 0 0 0 0

5.4.7 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN

instructions are executed or the register is saved/reset upon generation of an interrupt request.

Stack addressing can be used to access the internal high-speed RAM area only.

[Description example]

In the case of PUSH DE

Instruction code 1 0 1 0 1 0 1 0

84

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CHAPTER 6 PORT FUNCTIONS

6.1 Port Functions

The µPD789167, 789177, 789167Y, and 789177Y Subseries are provided with the ports shown in Figure 6-1.

These ports are used to enable several types of control. Table 6-1 lists the functions of each port.

These ports, while originally designed as digital I/O ports, have alternate functions, as summarized in 3.1 Pin

Function List (

Subseries).

µ

PD789167 and 789177 Subseries) and 4.1 Pin Function List (µPD789167Y and 789177Y

Figure 6-1. Port Types

P30

Port 3

P33

P50

Port 5

P53

P60

Port 6

P67

P00

P05

P10
P11

P20

P26

Port 0

Port 1

Port 2

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CHAPTER 6 PORT FUNCTIONS

Table 6-1. Port Functions

Pin Name I/O Function After Reset Alternate Function

P00 to P05 I/O Port 0

Input

−

6-bit I/O port

I/O mode can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can

be specified by means of pull-up resistor option register 0

(PU0).

P10, P11 I/O Port 1

Input

−

2-bit I/O port

I/O mode can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can

be specified by means of pull-up resistor option register 0

(PU0).

P20 SCK20/ASCK20

P21 SO20/TxD20

P22 SI20/RxD20

P23 SCL0

P24 SDA0

P25 TI80/SS20

P26

P30 INTP0/TI81/CPT90

P31 INTP1/TO81

P32 INTP2/TO90

P33

P50 to P53 I/O Port 5

I/O Port 2

7-bit I/O port

I/O mode can be specified in 1-bit units.

For P20 to P22, P25, and P26, an on-chip pull-up resistor

can be specified by means of pull-up resistor option register

B2 (PUB2).

Only P23 and P24 can be used as N-ch open-drain I/O port

pins.

I/O Port 3

4-bit I/O port

I/O mode can be specified in 1-bit units.

An on-chip pull-up resistor can be specified by means of pull-

up resistor option register B3 (PUB3).

Input

Input

Input

Note

Note

TO80

INTP3/TO82/BZO90

−

4-bit N-ch open-drain I/O port

I/O mode can be specified in 1-bit units.

For a mask ROM version, an on-chip pull-up resistor can be

specified by a mask option.

P60 to P67 Input Port 6

Input ANI0 to ANI7

8-bit input-only port

Note For the

86

µ

PD789167Y and 789177Y Subseries only

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CHAPTER 6 PORT FUNCTIONS

6.2 Port Configuration

Ports have the following hardware configuration.

Table 6-2. Configuration of Port

Parameter Configuration

Control registers Port mode registers (PMm: m = 0 to 3, 5)

Pull-up resistor option register 0 (PU0)

Pull-up resistor option registers B2, B3 (PUB2, PUB3)

Ports Total: 31 (CMOS I/O: 17, CMOS input: 8, N-ch open-drain I/O: 6)

Pull-up resistors • Mask ROM versions

Total: 21 (software control: 17, mask option control: 4)

• Flash memory versions

Total: 17 (software control only)

6.2.1 Port 0

This is a 6-bit I/O port with output latches. Port 0 can be set to input or output mode in 1-bit units by using port

mode register 0 (PM0). When the P00 to P05 pins are used as input port pins, on-chip pull-up resistors can be

connected in 6-bit units by using pull-up resistor option register 0 (PU0).

RESET input sets port 0 to input mode.

Figure 6-2 shows a block diagram of port 0.

Figure 6-2. Block Diagram of P00 to P05

WR

PU0

PU00

RD

WR

PORT

Internal bus

Output latch

(P00 to P05)

WR

PM

PM00 to PM05

PU0: Pull-up resistor option register 0

PM: Port mode register

RD: Port 0 read signal

WR: Port 0 write signal

Selector

DD0

V

P-ch

P00 to P05

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CHAPTER 6 PORT FUNCTIONS

6.2.2 Port 1

This is a 2-bit I/O port with output latches. Port 1 can be set to input or output mode in 1-bit units by using the port

mode register 1 (PM1). When the P10 and P11 pins are used as input port pins, on-chip pull-up resistors can be

connected in 2-bit units by using pull-up resistor option register 0 (PU0).

RESET input sets port 1 to input mode.

Figure 6-3 shows a block diagram of port 1.

Figure 6-3. Block Diagram of P10 and P11

WR

PU0

PU01

RD

WR

PORT

Internal bus

WR

PM

Output latch

(P10, P11)

PM10, PM11

PU0: Pull-up resistor option register 0

PM: Port mode register

RD: Port 1 read signal

WR: Port 1 write signal

Selector

DD0

V

P-ch

P10, P11

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CHAPTER 6 PORT FUNCTIONS

6.2.3 Port 2

This is a 7-bit I/O port with output latches. Port 2 can be set to input or output mode in 1-bit units by using port

mode register 2 (PM2). For the P20 to P22, P25, and P26 pins, on-chip pull-up resistors can be connected in 1-bit

units by using pull-up resistor option register B2 (PUB2).

The port is also used as a data I/O and clock I/O to and from the serial interface, and as the timer I/O.

RESET input sets port 2 to input mode.

Figures 6-4 through 6-8 show block diagrams of port 2.

Caution When using the pins of port 2 as the serial interface, the I/O and output latches must be set

according to the function to be used. For details of the settings, see Table 14-2 Operating Mode

Settings of Serial Interface 20.

Figure 6-4. Block Diagram of P20

V

DD0

WR

PUB2

PUB20

Alternate

function

RD

WR

PORT

Internal bus

WR

PM

Output latch

(P20)

PM20

Alternate

function

PUB2: Pull-up resistor option register B2

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

P-ch

Selector

P20/ASCK20/
SCK20

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CHAPTER 6 PORT FUNCTIONS

Figure 6-5. Block Diagram of P21

VDD0

PUB2

WR

PUB21

RD

PORT

WR

Internal bus

WRPM

Output latch

(P21)

PM21

Alternate

function

PUB2: Pull-up resistor option register B2

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

P-ch

Selector

P21/TxD20/
SO20

90

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CHAPTER 6 PORT FUNCTIONS

Figure 6-6. Block Diagram of P22 and P25

V

DD0

WR

PUB2

PUB22, PUB25

Alternate

function

RD

PORT

WR

Internal bus

Output latch

(P22, P25)

WR

PM

PM22, PM25

PUB2: Pull-up resistor option register B2

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

P-ch

Selector

P22/RxD20/SI20
P25/TI80/SS20

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CHAPTER 6 PORT FUNCTIONS

Figure 6-7. Block Diagram of P23 and P24

Comparator

reference signal

Input switch signal

Alternate

Note

function

RD

Selector

+

WR

PORT

Internal bus

WR

PM

Output latch

(P23, P24)

PM23, PM24

Alternate

Note

function

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

Note This function is provided for the

789177 Subseries, P23 and P24 cannot be used as alternate-function pins.

P23/SCL0
P24/SDA0

Note

Note

N-ch

µ

PD789167Y and 789177Y Subseries only. For the µPD789167 and

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CHAPTER 6 PORT FUNCTIONS

Figure 6-8. Block Diagram of P26

V

DD0

WR

PUB2

PUB26

RD

PORT

WR

Internal bus

Output latch

(P26)

WR

PM

PM26

Alternate

function

PUB2: Pull-up resistor option register B2

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

P-ch

Selector

P26/TO80

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CHAPTER 6 PORT FUNCTIONS

6.2.4 Port 3

This is a 4-bit I/O port with output latches. Port 3 can be set to input or output mode in 1-bit units by using port

mode register 3 (PM3). For the P30 to P33 pins, on-chip pull-up resistors can be connected in 1-bit units by using

pull-up resistor option register B3 (PUB3).

The port is also used as an external interrupt input, capture input, timer output, and buzzer output.

RESET input sets port 3 to input mode.

Figures 6-9 through 6-11 show block diagrams of port 3.

Figure 6-9. Block Diagram of P30

V

DD0

WR

PUB3

PUB30

Alternate

RD

WR

PORT

Internal bus

WR

PM

function

Output latch

(P30)

PM30

PUB3: Pull-up resistor option register B3

PM: Port mode register

RD: Port 3 read signal

WR: Port 3 write signal

P-ch

Selector

P30/INTP0/
TI81/CPT90

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CHAPTER 6 PORT FUNCTIONS

Figure 6-10. Block Diagram of P31 and P32

V

DD0

WR

PUB3

PUB31, PUB32

Alternate

function

RD

PORT

WR

Internal bus

Output latch

(P31, P32)

WR

PM

PM31, PM32

Alternate

function

PUB3: Pull-up resistor option register B3

PM: Port mode register

RD: Port 3 read signal

WR: Port 3 write signal

P-ch

Selector

P31/INTP1/TO81
P32/INTP2/TO90

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CHAPTER 6 PORT FUNCTIONS

Figure 6-11. Block Diagram of P33

VDD0

PUB3

WR

PUB33

Alternate

RD

PORT

WR

Internal bus

WRPM

function

Output latch

(P33)

PM33

Alternate

function

Alternate

function

PUB3: Pull-up resistor option register B3

PM: Port mode register

RD: Port 3 read signal

WR: Port 3 write signal

P-ch

Selector

P33/INTP3/
TO82/BZO90

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CHAPTER 6 PORT FUNCTIONS

6.2.5 Port 5

This is a 4-bit N-ch open-drain I/O port with output latches. Port 5 can be set to input or output mode in 1-bit units

by using port mode register 5 (PM5). For a mask ROM version, whether a pull-up resistor is to be incorporated can

be specified by the mask option.

RESET input sets port 5 to input mode.

Figure 6-12 shows a block diagram of port 5.

Figure 6-12. Block Diagram of P50 to P53

V

RD

DD0

Mask option resistor
Mask ROM version only.
For flash memory version,
a pull-up resistor is not
incorporated.

Selector

WR

PORT

Internal bus

WR

PM

Output latch

(P50 to P53)

PM50 to PM53

PM: Port mode register

RD: Port 5 read signal

WR: Port 5 write signal

Caution When using port 5 of the

µ

PD78F9177 and 78F9177Y as an input port, be sure to observe the

restrictions listed below.

• When V

Use within the range of T

• When T

Use within the range of V

• When T

DD = 1.8 to 5.5 V

A = 25 to 85°C

A = −40 to 85°C

DD = 2.7 to 5.5 V

A = −40 to 85°C and VDD = 1.8 to 5.5 V

Issue three consecutive read instructions when reading port 5.

If the above restrictions are not observed, the input value may be read incorrectly.

Note, however, that these restrictions do not apply when port 5 pins are used as output pins, or

when the product is other than the

µ

PD78F9177 or 78F9177Y.

P50 to P53

N-ch

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CHAPTER 6 PORT FUNCTIONS

6.2.6 Port 6

This is an 8-bit input port.

The port is also used as an analog input to the A/D converter.

Figure 6-13 shows a block diagram of port 6.

Figure 6-13. Block Diagram of P60 to P67

RD

Internal bus

A/D converter

+

–

V

REF

P60/ANI0 to P67/ANI7

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CHAPTER 6 PORT FUNCTIONS

6.3 Port Function Control Registers

The following two types of registers are used to control the ports.

• Port mode registers (PM0 to PM3, and PM5)

• Pull-up resistor option registers (PU0, PUB2, and PUB3)

(1) Port mode registers (PM0 to PM3, and PM5)

The port mode registers separately set each port bit to either input or output.

Each port mode register is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input writes FFH into the port mode registers.

When port pins are used for alternate functions, the corresponding port mode register and output latch must

be set or reset as described in Table 6-3.

Caution When port 3 is acting as an output port and its output level is changed, an interrupt

request flag is set, because this port is also used as the input for an external interrupt. To

use port 3 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.

Figure 6-14. Format of Port Mode Register

76 54Symbol Address After reset R/W

1 1 PM05 PM04 PM03 PM02 PM01 PM00PM0

3210

FF20H FFH R/W

1 1 1 1 1 1 PM11 PM10PM1 FF21H FFH R/W

1 PM26 PM25 PM24 PM23 PM22 PM21 PM20PM2 FF22H FFH R/W

1 1 1 1 PM33 PM32 PM31 PM30PM3 FF23H FFH R/W

1 1 1 1 PM53 PM52 PM51 PM50PM5 FF25H FFH R/W

PMmn

0 Output mode (output buffer on)

Input mode (output buffer off) 1

Pmn pin I/O mode selection
m = 0 : n = 0 to 5, m = 1 : n = 0, 1
m = 2 : n = 0 to 6, m = 3 : n = 0 to 3
m = 5 : n = 0 to 3

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CHAPTER 6 PORT FUNCTIONS

Table 6-3. Port Mode Register and Output Latch Settings for Using Alternate Functions

Alternate Function Pin Name

Name I/O

P25 TI80 Input 1

P26 TO80 Output 0 0

P30

P31

P32

P33

INTP0 Input 1

TI81 Input 1

CPT90 Input 1

INTP1 Input 1

TO81 Output 0 0

INTP2 Input 1

TO90 Output 0 0

INTP3 Input 1

TO82 Output 0 0

BZO90 Output 0 0

Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set

according to the function to be used. For details of the settings, see Table 14-2 Operating

Mode Settings of Serial Interface 20.

Remark ×: don’t care

PM××: Port mode register

P××: Port output latch

(2) Pull-up resistor option register 0 (PU0)

Pull-up resistor option register 0 (PU0) sets whether an on-chip pull-up resistor on each port is used. On the

port which is specified to use the on-chip pull-up resistor in PU0, the pull-up resistor can be internally used

only for the bits set to input mode. No on-chip pull-up resistors can be used for the bits set to output mode

regardless of the setting of PU0. On-chip pull-up resistors cannot be used even when the pins are used as

the alternate-function output pins.

PU0 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears PU0 to 00H.

Figure 6-15. Format of Pull-up Resistor Option Register 0

PM×× P××

×

×

×

×

×

×

×

100

76 54Symbol Address After reset R/W

0 0 0 0 0 0 PU01 PU00PU0

PU0m

On-chip pull-up resistor not used

0

On-chip pull-up resistor used

1

3 2 <1> <0>

FFF7H 00H R/W

Pm on-chip pull-up resistor selection (m = 0, 1)

Caution Bits 2 to 7 must all be set to 0.

User’s Manual U14186EJ6V0UD