How it Works
Renesas
Loading...
TPS-1
User Manual
91 pgs1.73 Mb0
Table of contents
Loading...

Renesas TPS-1 User Manual

All information contained in these materials, including products and product specifications,
website (http://www.renesas.com).
: Hardware
Rev.1.07 Jul 2018
RENESAS ASSP Ethernet Controller
User’s Manual
www.renesas.com
User’s Manual
for PROFINET IO Devices
represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Notice
on of
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operati semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and i nformation i n the desi gn of your produc t or syste m. Renesa s Electr onics discla ims any and al l liabilit y for any loss es and damages incurred by you or third parti es arising from the use of these circuits, software, or infor ma tion.
2. Renesas Elec tronics hereby expressly disclai ms any warranties against and liabi lity for infringeme nt or any other claims involving patents, copyrights, or other intellectual prop erty rights of third part ies, by or arising from the use of Renesas Electronics pr oducts or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application examples.
3. No license, expr ess, impli ed or otherwi se, is gra nted hereb y under an y patents , copyright s or other intell ectual prop erty rights of Renesas Electronics or others.
4. You shall not alter , modify, copy, or revers e engineer any Renes as Electr onics product , whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or reverse engineering.
5. Renesas Electroni cs products are cla ssified accordi ng to the following two qua lity grades: “Sta ndard” and “High Quali ty”. The intended applications for each Renesas Electronics product depends on the product’s quality grade, a s indicated below. “Standard”: Computers; office equipment; communications equipment; test and measurement equi pment; audio and visual equipment;
home electronic appliances; machine tools; personal electronic eq uipment; industria l robots; etc.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication
equipment; key financial terminal systems; safety control equipment; etc. Unless expressl y designated a s a high reli abilit y product or a product for ha rsh environ ments in a Renes as Elec tronics data sheet or ot her Renesas Electr onic s docum ent, Ren esa s El ectr onic s pr oduc ts a re not i ntended or a uthor i z ed for us e in produc t s or systems tha t may pose a direct threat to huma n life or bodily injury (ar tificial life supp ort devices or systems; s urgical implantations ; etc.), or may cause ser ious property damage (s pace system; unders ea repeaters ; nuclear power cont rol systems; a ircraft control systems; key pla nt systems; milit ary equipment; etc. ). Renesa s El ectroni cs dis claims a ny and al l liab ilit y for any damages or los ses i ncurred b y you or any thi rd parties arising from the use of any Renes as Electronics product that is inconsistent with any Renesa s Electronics data sheet, us er’s manual or other Renesas Electronics document.
6. When using Renesas Elect roni cs product s, r efer to t he lates t product informa tion ( data sheet s, user ’s manu als, applica tion not es, “Genera l Notes for Handling a nd Using Semic onductor Devices ” in the relia bility handbook, etc.), and ens ure that usage c onditions are w ithin the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characterist ics, insta llation, etc. Renesa s Electr onics dis claims any and a ll liabi lity for any ma lfunct ions, fa ilure or acc ident aris ing out of the use of Renesas Electronics products outside of such specified ranges.
7. Although Renesa s Electroni cs endeavors to imp rove the qual ity and relia bility of Renes as Electroni cs products, semiconductor products have specific cha racteristics, such as the occurrenc e of failure at a certain rate and malf unctions under certain use conditi ons. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesa s Elect ronics produc ts are not s ubject t o radiation res istance des ign. You are r esponsib le for implement ing safety measures to gua rd aga ins t the pos sibi lity of b odil y injur y, injur y or da mage c aus ed by fir e, a nd/or d anger t o the p ublic in the e vent of a failure or malf unction of Renesas Elec tronics pr oducts, s uch as safety design for ha rdware a nd software, including b ut not limited t o redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the e valuat ion of mic roc omputer s oft ware a lone is very dif fi cult and imp ract ical, you are res pons ibl e for eval uat ing the s afet y of the final products or systems manufactured by you.
8. Please contact a Renesas El ectronics sa les office f or details as to environmenta l matters such as the en vironmental compatibility of each Renesas Elec tronic s produc t. Y ou are r esp onsibl e for c aref ully and s uff icient ly inves ti gati ng appl icab le laws and r egulat ions that regula te the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compl iance with all these applicab le laws and regul ations. Renesa s Electr onics disclai ms any and all liab ility for damages or losses occurring as a result of your noncompliance wit h applicable laws and regulations.
9. Renesas Electr oni cs pr oduc ts and t echnol ogi es s ha ll not be us ed f or or incorp or ated i nt o any pr oduc ts or s ystems whos e manuf act ur e, us e, or sale is pr ohibited under a ny applica ble domestic or foreign laws or regulati ons. You shall comply with an y applicabl e export contr ol laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions.
10. It is the respons ibility of the buyer or distributor of Renesas Electronics products, or any other party who distr ibutes, disposes of, or otherwise sell s or tr ansf er s the p r oduct to a thi rd pa r ty, t o noti f y such t hir d p ar ty in a dvanc e of the c ont ent s a nd condi t ions s et f orth i n t his document.
11. This document sha ll not be repri nted, rep roduced or dup licated i n any form, in whole or in part, wit hout prior wr itten consent of Renesa s Electronics.
12. Please contact a Renesas Electronics sales of fice if you have an y questions r egarding the information conta ined in this document or Renesas Electronics products.
(Note 1) “Renesas Elect ronics” as used in t his document m eans Renesas Electronics Corporation a nd also incl udes its direc tly or indirect ly
controlled subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
- The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in
the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.
- The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are
undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.
- The reserved addresses are provided for the possible future expansion of functions. Do not access these
addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching
the clock signal during program execution, wait until the target clock signal has stabilized.
- When the clock signal is generated with an external resonator (or from an external oscillator) during a reset,
ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable.
Instructions for the use of product
In this section, the precautions are described for over whole of CMOS device. Please refer to this manual about individual precaution. When there is a mention unlike the text of this manual, a mention of the text takes first priority
Particular attention should be paid to the precautionary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to the text of the manual for details.
Document
Type
Description
Document Title
Document No.
Data Sheet
Hardware overview and electrical characteristics
TPS-1 Datasheet
R19DS0069EJ
User’s manual for Hardware
Hardware specifications (pin assignments, memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation descriptiont
TPS-1 User’s Manual: Hardware
This User’s manual
User’s manual
User Manual TPS-1
Note
Driver Manual
TPS-1 API functions
Driver Interface TPS-1
Note
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes.
The following documents apply to the TPS-1. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Electronics Web site.
Note: These documents are available from Phoenix Contact Software.
2. Notation of Numbers and Symbols
Note : Explanation of (Note) in the text Caution : Item deserving extra attention Remark : Supplementary explanation to the text
Numeric notation : Binary XXXb
Decimal XXXX Hexadecimal XXXXH or 0x XXXX
Prefixes representing powers of 2 (address space, memory capacity)
k (kilo): 210 = 1024 M (mega): 220 = 10242 = 1.048.576 G (giga): 230 = 10243 = 1.073.741.824
Data Type : Word 32 bits
Halfword 16 bits Byte 8 bits
Abbreviation
Full Form
CSI
Clocked Serial Interface
FO
Fiber Optic
FPBGA
Fine Pitch Ball Grid Array
GND
Ground Potential
GPIO
General Purpose Input /Output
I
Input
I/O or IO
Input/Output
MISO
Master in Slave out (SPI signal)
MOSI
Master out Slave in (SPI signal)
MRP
Media Redundancy Protocol (IEC 61158)
O
Output
PCB
Printed Circuit Board
PCF
Photonic Crystal Fiber
PECL
Positive-Emitter-Coupled Logic
PLL
Phase Locked Loop
POF
Plastic Optical Fiber
POR
Power On Reset
RJ-45
Ethernet connection (copper wire)
SC-RJ
Ethernet connection (fiber optic)
SPI
Serial Peripheral Interface
UART
Universal Asynchronous Receiver/Transmitter
n.c.
Not connected
ppm
Parts per Million
Abbreviation
Full Form
AR
Application Relation (PROFINET terms)
CR
Communication Relation (PROFINET terms)
I&M
Identification & Maintenance
IRT
Isochronous Real-Time (PROFINET operating mode)
NRT
Non Real Time (PRFINET terms)
PNIO
PROFINET IO
RT
Real-Time
3. List of Abbreviations and Acronyms
All trademarks and registered trademarks are the property of their respective owners.
Table of Contents
1. OVERVIEW ............................................................................................................................................................................ 8
1.1. FEATURES ................................................................................................................................................................................. 8
1.2. ABSTRACT ................................................................................................................................................................................. 9
1.3. BLOCK DIAGRAM ..................................................................................................................................................................... 10
2. PIN FUNCTION.................................................................................................................................................................... 11
2.1. SIGNAL OVERVIEW AND DESCRIPTION ..................................................................................................................................... 11
2.2. GPIO MULTIPLEXING .............................................................................................................................................................. 14
2.3. SUPPLY VOLTAGE CIRCUITRY ................................................................................................................................................. 15
2.4. SIGNALS FOR IRT COMMUNICATION ....................................................................................................................................... 16
3. HOST INTERFACE............................................................................................................................................................... 17
3.1. TESTING DPRAM INTERFACE ................................................................................................................................................. 17
3.2. PARALLEL INTERFACE ............................................................................................................................................................ 17
3.2.1. Operating modes of the parallel interface .................................................................................................................... 17
3.2.2. Signal description of the parallel interface .................................................................................................................. 18
3.2.3. Memory Segmentation at 4 kByte and 16 kByte page size .......................................................................................... 20
3.2.4. Connection example for a 8bit data bus ....................................................................................................................... 22
3.2.5. Connection example for a 16-bit data bus .................................................................................................................... 23
3.3. SPI SLAVE INTERFACE ............................................................................................................................................................ 24
3.3.1. Serial access to the shared memory ............................................................................................................................. 25
3.3.2. SPI Slave Interface Timing .......................................................................................................................................... 28
3.3.3. SPI Slave Interface Reset Timing ................................................................................................................................ 33
4. SHARED MEMORY STRUCTURE........................................................................................................................................ 34
4.1. EVENT COMMUNICATION WITH THE TPS-1 FIRMWARE............................................................................................................ 36
4.2. EVENTS FROM THE TPS-1 FIRMWARE TO THE HOST ................................................................................................................ 37
4.3. EVENTS FROM THE HOST TO THE TPS-1 FIRMWARE ................................................................................................................ 38
4.4. INTERRUPT COMMUNICATION WITH THE TPS-1 ...................................................................................................................... 39
4.4.1. How to generate an interrupt by an event ................................................................................................................... 39
5. TPS-1 BOOT SUBSYSTEM ................................................................................................................................................... 43
5.1. HARDWARE STRUCTURE FOR THE BOOT OPERATION............................................................................................................... 43
5.2. LOADING AND UPDATE OF THE FIRMWARE DURING THE MANUFACTURING PROCESS ............................................................... 44
5.2.1. UART interface (UART boot) ........................................................................................................................................ 44
5.2.2. SPI master interface (Boot Flash) ................................................................................................................................ 45
6. IO LOCAL GPIO INTERFACE .............................................................................................................................................. 47
6.1. GPIO (DIGITAL INPUT AND OUTPUT) ....................................................................................................................................... 47
6.2. STATUS LEDS OF THETPS-1 ................................................................................................................................................... 48
6.3. I2C-BUS – LWL DIAGNOSTIC .................................................................................................................................................. 48
7. TPS-1 WATCHDOG .............................................................................................................................................................. 49
7.1. SIGNAL WD_OUT (PIN B12) ................................................................................................................................................... 49
7.2. SIGNAL WD_IN (PIN A11) ....................................................................................................................................................... 50
8. PROFINET IO SWITCH ........................................................................................................................................................ 51
8.1. 100BASE-TX INTERFACE ......................................................................................................................................................... 52
8.1.1. 100Base-TX interface (Port 1) ...................................................................................................................................... 52
8.1.2. 100Base-TX interface (Port 2) ...................................................................................................................................... 52
8.2. 100BASE-FX INTERFACE (FIBER OPTIC) ................................................................................................................................. 52
8.2.1. 100Base-FX interface (Port 1) ...................................................................................................................................... 53
8.2.2. 100Base-FX interface (Port 2) ...................................................................................................................................... 53
8.3. I2C-BUS – LWC DIAGNOSTIC ................................................................................................................................................. 53
8.4. ADDITIONAL TPS-1 PINS ......................................................................................................................................................... 54
page 6 of 86
INTEGRATED VOLTAGE REGULATOR 1.5 V ............................................................................................................................... 54
8.5.
9. CLOCK CIRCUIT .................................................................................................................................................................. 56
9.1. USING THE INTERNAL CLOCK OSCILLATOR .............................................................................................................................. 56
9.2. EXTERNAL CLOCK SOURCE ...................................................................................................................................................... 57
10. RESET OF THE TPS-1 ..................................................................................................................................................... 58
11. BOUNDARY SCAN INTERFACE (JTAG) ......................................................................................................................... 59
11.1. CIRCUIT RECOMMENDATION OF THE JTAG INTERFACE .......................................................................................................... 60
SETTING OF OPERATING MODES ................................................................................................................ 61
HOST INTERFACE .................................................................................................................................................................... 62
Host Parallel Interface ................................................................................................................................................. 62
Host Serial Interface ..................................................................................................................................................... 63
LOCAL I/O-CONFIGURATION ................................................................................................................................................... 64
IO Parallel ..................................................................................................................................................................... 64
IO Serial Interface ........................................................................................................................................................ 67
IO Local Interface ......................................................................................................................................................... 69
IO Local parallel Interface ............................................................................................................................................ 69
Configuration of the IO Local Parallel Interface.......................................................................................................... 69
Configuration of the IO Local Serial interface (SPI Master) ....................................................................................... 70
I&M0 Configuration (I&M0 data) “Deleted” OK? ................................................................................................ 71
ETHERNET INTERFACE CONFIGURATION ................................................................................................................................ 72
COPYING THE CONFIGURATION DATA INTO THE BOOT FLASH .................................................................................................. 73
GENERATING A COMPLETE SERIAL BOOT FLASH IMAGE........................................................................................................... 74
BOARD DESIGN INFORMATION ................................................................................................................... 75
VOLTAGE SUPPLY .................................................................................................................................................................... 75
SWITCHING REGULATOR ......................................................................................................................................................... 75
Wiring for the Switching Regulator ............................................................................................................................. 76
Layout Example for Switching Regulator .................................................................................................................... 77
BOARD DESIGN RECOMMENDATIONS FOR ETHERNET PHY ..................................................................................................... 78
Supply Voltage Circuitry .............................................................................................................................................. 78
100BASE-TX Mode Circuitry ....................................................................................................................................... 80
Unused 100Base-TX Interface ...................................................................................................................................... 81
100BASE-FX Mode Circuitry ....................................................................................................................................... 82
Unused 100Base-FX interface ...................................................................................................................................... 85
FAST START UP REQUIREMENTS ................................................................................................................ 86
page 7 of 86
TPS-1
R19UH0081ED0107 Rev. 1.07
Jul 30, 2018

1. Overview

1.1. Features

PROFINET Device Chip
• Integrated PROFINET CPU
• Host CPU interface (SPI-Slave o r 8/16 bit parallel)
• SPI Master-Interface for direct connection of SPI-Slaves (to exchange process data)
• 48 GPIO for direct connection of digital peripheral signals (digital I/Os)
• Serial Flash interface
• Support of PROFINET IO communication channels NRT, RT, and IRT
• Watchdog support for connected host CPUs
• Compliance with PROFINET Conformance Class C
• Hardware support for time-critical PROFINET protocols, including PTCP with LLDP
• Firmware download during the manufacturing process via JTAG Boundary Scan interface, Ethernet or UART
interface
• Firmware update via Ethernet interface with BOOTP/TFTP
• Easy configuration of host interfaces and GPIOs
• 2 Fast Ethernet Ports w ith inte gr ated PHY s 100 Mbit full duplex data transmission IRT Bridge Delay < 3 μsec Auto Negotiation Auto Cross-Over Auto Polarity Support for 100Base-TX and 100Base-FX ports
2
Monitoring of fiber optic transmission links with integrated I
• Power dissipation around < 1 W
Host Interface
• Serial (SPI up to 25 MHz) and parallel (8 or 16 bit) interface for use with an external host CPU
• Data exchange (cyclic and acyclic) with external host via integrated Shared Memory Area (event and interrupt
controlled)
• 1016 Byte maximum data for cyclic exchange, dy nam ically distr ib uted to tw o ARs (payload inclusive IOxS data)
• Two application relations available (from stack version V1.2 onwards)
• The TPS-1 firmware allows a up to 64 Slot/Subslots (e.g. 1 Slot with up to 64 Subslots)
• Configuration of all host interfaces wit h softw ar e tool; con figuration data are stored in a boot Flash
C interfaces
Note: A maximum data size of 1016 Byte is po ssibl e with stack version 1.4.0.14 or newer. This data size can be f lexibly
distributed over 2 PROFINET application relations (example: one AR uses 256 Bytes, the other AR use s 760 Bytes). With stack versi ons ear lier th an 1.4. 0.14 t he max imum data siz e is li mited to 340 Byte s for e ach of th e two configurable application relations.
R19UH0081ED0107 Rev. 1.07 page 8 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 1. Overview
Med ia Dependent
Interface
Port 1
SC-RJRJ45
Med ia Dependent
Interface
Port 2
SC-RJ
RJ45
Application
CPU
TPS-1
PROFINET
Device Chip
Flash
SPI-Slave

1.2. Abstract

The PROFINET Devic e Chip TPS-1 is designed for easy and cost-efficien t im pl ementation of PROFINET interfaces for automation devices. It is a highly integrated s ingle chip solution that meets all requirements of th e PROFINET protocols. The configurable host interf aces facili tate the flexible realization of differen t use cases like direct connec tion of an external host CPU or digital I/Os without additional circuitry. The TPS-1 com plies with PROFINET Conformance Class C. The integrated components realize the complete interface functionality. The internal structure is designed to fulfill the requirements of the IRT protocol. Special synchronous signals are available to realize all synchroniza tion tasks. To support line topologies in PROFINET networks, the TPS-1 is equipped with two integrated PHYs and an integrated IRT switch. Time-critical PROFINET protocols are supported by hardware. For the complete implemen tation of a PROFINET device interface, only the TPS-1, a serial Flash device, an oscillator, and the physical adaptations for the Ethernet interface (transformers and connectors) are needed. The serial Flash component contains the individual chip configuration and firmware for the PROFINET CPU. Due to the low space requirement and low power dissipation of the TPS-1, a PROFINET interface can also be integrated into automation devices with special requirements regarding housing size and protection classes. Conductor routing between the balls is still possible in order to keep down PCB cost.
Figure 1-1: TPS-1 Overview
R19UH0081ED0107 Rev. 1.07 page 9 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 1. Overview
Shared Memory
I/O Int e rfa c e
PHY 2PHY 1
SPI
Slave
Parallel Interface 8 / 16 Bit
Host Interface
M U X
PROFINET CPU
Boot­ROM
ARM Core
RAM
PROFINET Core
Time Sync
IRT Switch
Protocol Handlin g
LAN signals
(I2C-bus, link and
Activity), Test Sync
Clock Signals T1 to T6
Clock
Unit
25 MHz
MDI MDI
Link1, Act1, Link2, Act2
Test Sync
JTAG / Debug
Serial Flash
(SPI Slave)
Host Interface / Parallel - Serial
48 GPIO
Status Info
LEDs
Control Signals
Power Supply
Swit ching Regulator
3.3 V
1.5 V

1.3. Block Diagram

The block diagram shows the internal structure and main components of the TPS-1. The additional serial boot Flash component, the oscilla tor and the physical adaptat ion for the Ethernet interfaces ar e not listed.
Figure 1-2: TPS-1 Block Diagram
The TPS-1 contains the PROFINET CPU, the PROFINET core, the I/O interface, and the Host Interface for connecting a host CPU. The PROFINET c o re processes the PROFINET communication. All time-critical services are implemented in hardware to realize high perform ance. The communication between an externa l host CPU and other PROFINET components is processed by the PROFINET CPU (connection establishment, administration and management of Application Relations, contr olling of Ethernet connections, setup and monitoring of RT and IRT channels, etc.). Simple IO in terfaces can be realized wit h the I/O inter face only (e.g. digital I/Os )
R19UH0081ED0107 Rev. 1.07 page 10 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 2. Pin function
Pin
Designation
Typ
Function
Remark
M12
CS_FLASH_OUT
O
SPI Master Interface Firmware Flash: Chip Select
(active low)
M13
SPI3_SRXD_IN
I
SPI Master Interface Firmware Flash: Receive Data
Synchronization signals
J11
T1 O Clock signal 1 (isochronous mode, IRT)
G11
T3 O Clock signal 3 (isochronous mode, IRT)
E11
T5 O Clock signal 5 (isochronous mode, IRT)
LED signals device status PROFINET
B11
LED_SF_OUT
O
Control LED „System Fail“
(active low)
B10
LED_MT_OUT
O
Control LED „Maintenance“
(active low)
C9
I2C_1_D_INOUT
I/O
Fiber Optic Port 1: I2C-Bus “Data”
e.g. SC-RJ
C12
LINK_PHY1
O
LINK indication ETHERNET Port 1 (up or down)
(active high)
F13
P1_TX_P
O
ETHERNET Port 1 transmit data (positive)
e.g. RJ45
E13
P1_RX_P
I
ETHERNET Port 1 Receive Data (positive)
e.g. RJ45
B8
P1_SD_P
I
Fiber Optic Port 1: Signal Detect (positive)
e.g. SC-RJ
B9
P1_RD_P
I
Fiber Optic Port 1: Receive Data (positive)
e.g. SC-RJ
B6
P1_TD_OUT_P
O
Fiber Optic Port 1: Transmit Data (negative)
e.g. SC-RJ
A5
P1_FX_EN_OUT
O
Fiber Optic Port 1: Transmitter enable (active high)
e.g. SC-RJ
PHY Port 2
M11
I2C_2_D_INOUT
I/O
Fiber Optic Port 2: I2C-Bus “Data”
e.g. SC-RJ

2. Pin function

2.1. Signal overview and description

Table 2-1 contains an overview about all signals of the TPS-1.
Table 2-1: TPS-1 signal overview and description
e
SPI Master for Boot Flash ROM
(TPS-1)
N13 SPI3_SCLK_OUT O SPI Master Interface Firmware Flash: CLOCK (TPS-1)
(TPS-1) -MISO
M14 SPI3_STXD_OUT O SPI Master Interface Firmware Flash: Send Data
(TPS-1) - MOSI
N12 TEST_SYNC O Clock signal for certification Note 2)
H11 T2 O Clock signal 2 (isochronous mode, IRT)
F11 T4 O Clock signal 4 (isochronous mode, IRT)
D11 T6 O Clock signal 6 (isochronous mode, IRT)
B13 LED_BF_OUT O Control LED „Bus Failure“ (active low)
C10 LED_READY_OUT O Control LED „Device Ready“ (active low)
PHY Port 1
C6 SCLK_1_INOUT O Fiber Optic Port 1: I2C-Bus “Clock” e.g. SC-RJ
D10 ACT_PHY1 O Activity ETHERNET Port 1 (active high)
F14 P1_TX_N O ETHERNET Port 1 transmit data (negative) e.g. RJ45
E14 P1_RX_N I ETHERNET Port 1 Receive Data (negative) e.g. RJ45
A8 P1_SD_N I Fiber Optic Port 1: Signal Detect (negative) e.g. SC-RJ
A9 P1_RD_N I Fiber Optic Port 1: Receive Data (negative) e.g. SC-RJ
A6 P1_TD_OUT_N O Fiber Optic Port 1: Transmit Data (positive) e.g. SC-RJ
R19UH0081ED0107 Rev. 1.07 page 11 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 2. Pin function
C11
LINK_PHY2
O
LINK indication ETHERNET Port 2 (up or down)
(active high)
J13
P2_TX_P
O
ETHERNET Port 2 Transmit Data (positive)
e.g. RJ45
K14
P2_RX_N
I
ETHERNET Port 2 Receive Data (negative)
e.g. RJ45
N8
P2_SD_P
I
Fiber Optic Port 2: Signal Detect (positive)
e.g. SC-RJ
N9
P2_RD_P
I
Fiber Optic Port 2: Receive Data (positive)
e.g. SC-RJ
P6
P2_TD_OUT_N
O
Fiber Optic Port 2: Transmit Data (positive)
e.g. SC-RJ
P5
P2_FX_EN_OUT
O
Fiber Optic Port 2: Transmitter enable (active high)
e.g. SC-RJ
N11
XCLK1
I
Connection external oscillator (1), 25 MHz
JTAG – Interface
J10
TM1
I
Test Input 1 (Chip Test - 10k to GND)
(pull down external)
L6
TMS
I
JTAG-Interface: “Test Mode Select”
(pull-up external)
L5
TDI I JTAG-Interface: “Test Data Input”
(pull-up external)
Reset / Test
H12
ATP
I
Test pin for production test (n.c.)
E10
TMC1
I
Test Mode Control 1 (production test)
(pull down external
D6
TEST_1_IN
I
Test Pin 1 for hardware test of the TPS-1
(pull down external D8
TESTDOUT5
O
Test Data Output 5 (High Speed Signals for PHY)
D9
TESTDOUT6
O
Test Data Output 6 (High Speed Signals for PHY)
L8
TESTDOUT7
O
Test Data Output 7 (High Speed Signals for PHY)
A11
WD_IN
I
Watchdog input (from the Host) (the rising edge resets
(active high) K11
INT_OUT
O
Interrupt output (to the Host)
(active high)
L11 SCLK_2_INOUT O Fiber Optic Port 2: I2C-Bus “Clock” e.g. SC-RJ
A10 ACT_PHY2 O Activity ETHERNET Port 2 (active high)
J14 P2_TX_N O ETHERNET Port 2 Transmit Data (negative) e.g. RJ45 K13 P2_RX_P I ETHERNET Port 2 Receive Data (positive) e.g. RJ45
P8 P2_SD_N I Fiber Optic Port 2: Signal Detect (negative) e.g. SC-RJ
P9 P2_RD_N I Fiber Optic Port 2: Receive Data (negative) e.g. SC-RJ N6 P2_TD_OUT_P O Fiber Optic Port 2: Transmit Data (negative) e.g. SC-RJ
Oscillator
P11 XCLK2 O Connection external oscillator (2), 25 MHz
L4 TM0 I Test Input 0 (Chip Test - 10k to GND) (pull down external)
K5 TRSTN I JTAG-Interface: “Test Reset” (pull down external)
L7 TDO O JTAG-Interface: “Test Data Output” J5 TCK I JTAG-Interface: “Test Clock” (pull-up external)
A12 RESETN I TPS-1 Reset (Global Reset) (active low)
H13 EXTRES O External reference resistor (12.4 kΩ,1 %), connect to
analog GND
recommended)
K10 TMC2 I Test Mode Control 2 (production test) (pull down external
recommended)
recommended)
D7 TEST_2_IN I Test Pin 2 for hardware test of the TPS-1 (pull down external
recommended)
Host interface
the watchdog counter of the TPS-1)
B12 WD_OUT O Watchdog output (to the Host) (active low)
Boot interface (serial)
R19UH0081ED0107 Rev. 1.07 page 12 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 2. Pin function
C13
UART6_RX
I
Boot UART “Receive Data“
Test signals for switching regulator
G3
TEST2
I
Test Pin switching regulator (in combination with
PHY supply voltages
C8
VDDQ_PECL_B1
I
PECL buffer power supply 3.3 V (Port 1)
L9
PLL_AGND
PLL analog GND
Pins for switching regulator
G1
BGND
GND for switching regulator (please place bypass G2
AGND_REG
Analog GND switching regulator
F1
FB I Feedback (regulator)
GPIO_00 -
I/O
(see table “Alternate use of the GPIO”)
C14 UART6_TX O Boot UART “Transmit Data“
P12 BOOT_1 I Forced Boot
H3 TEST1 I Test Pin switching regulator (in combination with
Test2, Test3)
Test1, Test3)
E1 TEST3 I Test Pin switching regulator (in combination with
Test1, Test2)
E12 VDD33ESD Analog test supply, 3.3 V
M8 VDDQ_PECL_B2 I PECL buffer power supply 3.3 V (Port 2) D14 P1VDDARXTX I Analog Rx/Tx port power supply
Analog 1.5 V V
(must be generated via a filter from
DD
digital 1.5 V power supply) – Port 1
L14 P2VDDARXTX I Analog Rx/Tx port power supply
Analog 1.5 V VDD (must be generated via a filter from digital 1,5 V power supply) – Port 2
H14 VDDACB I Analog 3.3 V VDD (must be generated via a filter from
digital 3.3 V power supply) G13 VSSAPLLCB Analog central GND G14 VDDAPLL Analog central power supply for PHYs, 1.5 V
Pins for core PLL power supply
(core PLL)
L10 PLL_AVDD PLL analog 1.0 V (core PLL)
J1 BVDD I Supply voltage for the switching regulator (3.3 V
supply for the switching transistor)
capacitor between analog power supply and GND). F2 AVDD_REG Analog VDD for regulator (3.3 V supply),
smoothed voltage to feed the internal POR.
H1 LX O 1.5 V output of the internal switching regulator
Configurable GPIOs
GPIO_47
After reset the GPIO pin are configured as Inputs (no
pull up or down)
Notes:
1. Pin F2 must be always connected to VDD33 (refer Figure 8-2: Internal voltage regulator).
2. The signal TEST_SYNC must be available for certification test (a reachable pad is enou g h) .
Note 1)
R19UH0081ED0107 Rev. 1.07 page 13 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 2. Pin function
Pin
Designation
Alternate Use
Description
D5
GPIO 0
LBU WR EN IN
Write Enable
B5
GPIO 1
LBU READ EN IN
Read Enable
C5
GPIO 2
LBU CS IN
Chip Select
C4
GPIO 3
LBU BE 1 IN
Byte Selection (low)
A4
GPIO 4
LBU BE 2 IN
Byte Selection (high)
B4
GPIO 5
LBU READY OUT
Ready Signal TPS-1 (Note 1), (N ote 2)
C3
GPIO 6
LBU DATA0
Data Bit
A3
GPIO 7
LBU DATA1
Data Bit
B3
GPIO 8
LBU DATA2
Data Bit
B2
GPIO 9
LBU DATA3
Data Bit
D3
GPIO 10
LBU DATA4
Data Bit
D4
GPIO 11
LBU DATA5
Data Bit
C1
GPIO 12
LBU DATA6
Data Bit
C2
GPIO 13
LBU DATA7
Data Bit
D2
GPIO 14
LBU DATA8
Data Bit
D1
GPIO 15
LBU DATA9
Data Bit
E2
GPIO 16
LBU DATA10
Data Bit
E3
GPIO 17
LBU DATA11
Data Bit
E4
GPIO 18
LBU DATA12
Data Bit
E5
GPIO 19
LBU DATA13
Data Bit
F5
GPIO 20
LBU DATA14
Data Bit
F4
GPIO 21
LBU DATA15
Data Bit
F3
GPIO 22
LBU A0 IN
Address Bit
G5
GPIO 23
LBU A1 IN
Address Bit
G4
GPIO 24
LBU A2 IN
Address Bit
H5
GPIO 25
LBU A3 IN
Address Bit
H4
GPIO 26
LBU A4 IN
Address Bit
J4
GPIO 27
LBU A5 IN
Address Bit
J3
GPIO 28
LBU A6 IN
Address Bit
K3
GPIO 29
LBU A7 IN
Address Bit
K4
GPIO 30
LBU A8 IN
Address Bit
K2
GPIO 31
LBU A9 IN
Address Bit
L2
GPIO 32
LBU A10 IN
Address Bit
L3
GPIO 33
LBU A11 IN
Address Bit
L1
GPIO 34
LBU A12 IN
Address Bit
M2
GPIO 35
LBU A13 IN
Address Bit
M1
GPIO 36
LBU SEG0 IN
Segment choice 1
M3
GPIO 37
LBU SEG1 IN
Segment choice 2
P3
GPIO 38
HOST RESET IN
Reset Host SPI Interface
N3
GPIO 39
HOST SFRN IN
Start new SPI Transfer (Note 3)
N2
GPIO 40
HOST SRXD IN
SPI receive data
N4
GPIO 41
HOST SCLK IN
SPI Clock
M4
GPIO 42
HOST STXD OUT
SPI transmit data
P4
GPIO 43
HOST SHDR OUT
Header recognized
N5
GPIO 44
LOCAL SCLK OUT
SPI Clock (SPI master IO interface)
M5
GPIO 45
LOCAL SFRN OUT
SPI Chip Select (SPI master IO interface)
M6
GPIO 46
LOCAL SRXD IN
SPI receive date (SPI master IO interface)
M7
GPIO 47
LOCAL STXD OUT
SPI transmit data (SPI master IO interface)

2.2. GPIO multiplexing

Table 2-2: Alternate use of the GPIOs
Note: You can only use one interface exclusively. It is not allowed to use e.g. the parallel and serial host interface at the same time.
Note 1): The “LBU_READY_OUT” is designed to connect only to one microcontroller. If you want to connect additional devices you must add circuitry to realize the high-impedance state.
Note 2): If your processor does not have a READY Input, you can choose a wait time of 260 ns during each transfer cycle. Note 3): As soon as the signal HOST_SFRN_IN is set to “1”, no more data is received on the RxD interface. Setting the signal is not a llowed
during an ongoing transfer.
R19UH0081ED0107 Rev. 1.07 page 14 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 2. Pin function
Pin
Pin Name
Function
Supply Voltage Generation
G14
VDDAPLL
Analog central power
E12
VDD33ESD
Analog test power
C8,
VDDQ_PECL_B1
PECL buffer power
L10
PLL_AVDD
Power supply for the D12, D13, L12, L13
AGND
Analog Ground for
A2, A7, A13, F12, K1, K12, M9,
VDD15
Voltage Supply 1.5 V
form Switching Regulator or

2.3. Supply Voltage Circuitry

The TPS-1 works with three operating voltages: VDD15 (1.5 V), VDD33 (3.3 V, IO) and VDD10 (1.0 V, core). Additionally, the on-chip PLL for the device clock generation requires a sup ply called PLL_AVDD (1.0 V), which is typically a filtered version of VDD10. The integrated PHYs of the TPS-1 require additional filtered operating voltages.
Table 2-3: Supply Voltage Circuitry
D14, L14
P1VDDARXTX P2VDDARXTX
Analog port RX/TX power supply, 1.5 V (PHY port 1 and port
2)
supply, 1.5 V (PHY)
H14 VDDACB Analog central power
supply, 3.3 V (PHY)
supply, 3.3 V (PHY)
G13 VSSAPLLCB Analog central GND
(PHY)
M8
VDDQ_PECL_B2
supply 3.3 V (port 1 and port 2)
L9 PLL_AGND Analog Ground for the
internal CPU clock generation
internal CPU clock generation (1.0V)
A1, A14, B7, F7, F8, F9, G6, G7,
GND Digital GND G8, G9, G10, G12, H6, H7, H8, H9, H10, J2, J6, J7, J8, J9, J12, M10, N7, N10, P1, P14
PHYs
B1, B14, C7, F6, F10, H2, N1,
VDD33 Voltage Supply 3.3 V External N14, P7, P10
Must be generated from VDD15 via a filter.
Must be generated from VDD33 via a filter.
Must be generated from GND Core/IO via a filter or connected to GND Core/IO at the far end from TPS-1.
P2, P13 E6, E7, E8, E9, K6, K7, K8, K9 VDD10 Voltage Supply 1.0 V External
R19UH0081ED0107 Rev. 1.07 page 15 of 86 Jul 30, 2018
external
TPS-1 User’s Manual: Hardware 2. Pin function
T1
J11
Ti (T_IO_Input)
Time at which the input data must be read from
T4
F11
T_IO_OutputValid
This signal indicates when the data for output are
T6
D11
-for further use

2.4. Signals for IRT Communication

The TPS-1 synchronizes the IO device to the PROFINET controller and generates trigger signals that are used for application synchronization. T_IO_Input relates peripheral inputs and T_IO_Output relates peripheral outputs to the data cycle.
Table 2-4: IRT Communication Signals
Signal Pin Function Comment
TEST_SYNC N12 Start of bus cycle A signal on this pin signalizes a new cycle event. It is
used as well to test the synchronization during the
certification. The signal should be made accessible for
measurement purposes.
process.
T2 H11 To (T_IO_Output) Data can be used by the application at this configured
time.
T3 G11 T_IO_InputValid Time at which the input data must be in the transfer
buffer.
available.
T5 E11 -for further use
R19UH0081ED0107 Rev. 1.07 page 16 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 3. Host Interface
TPS
-1
0x8000 0x8004
0x0000
0xFFFF
Magic Number NRT Area Size
ARM CPU
Application CPU
The application CPU read
the Magic Number to
recognize the start up of
the TPS-1
Operating mode Separate Read / Write signal (Intel Mode)
Polarity of ready signal Ready Signal “active low”
Data bus width 8 bit

3. Host Interface

The host interface is designed to connect external mic r o processors. These processors access the internal sh ared memory of the TPS-1 in order to exchange cyclic or acyclic data with the PROFINET IO interface. The shared memory has an address space of 64 Kbyte. The data exchange is processed with the help of an “Event Unit”. Another way to inform the external host CPU about a new PROFINET status is the integrated interrupt system. The parallel interface can be switched to Motorola or Intel mode. It is only possible to use the Host parallel interface or the Host serial interface. It is not possible to use both at the same time.

3.1. Testing DPRAM Interface

For testing the DPRAM Interface it is useful to have addresses with defined values. After start of the TPS-1 firmware the TPS-1 writes the magic number and the NRT Area Size into the addresses 0x8000 and 0x8004.
Figure 3-1: TPS-1 with address page 16 Kbyte

3.2. Parallel Interface

3.2.1. Operating modes of the parallel interface

The parallel interface can be used with an 8-bit or 16-bit data bus.
Table 3-1: Operating Modes of the parallel interface
Setting Description
Read-/Write-Control (Motorola Mode)
Ready Signal “active high”
The configuration of the parallel interface is also done with “TPS Configurator”.
16 bit
R19UH0081ED0107 Rev. 1.07 page 17 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 3. Host Interface
LBU
_
Ax_
IN
(13
:
0)
A
(
15
:
0
)
A
(13
:0
)
A(15:14)
Ext
. Host CPU
LBU
_Ax_IN(15:14)
LBU_Ax_IN(11:0)
A(13:0)
A(11:0)
A(13:12)
Ext. Host CPU
TPS-1
Host Interface
LBU_SEG(1:0)_IN
Host Interface

3.2.2. Signal description of the parallel interface

The shared memory has an address space of 64 Kbyte (refer to chapter “Shared memory structure”). The typical pag e size is 16 KByte. For a correct alignment you have to connect the highest address bits to the signals LBU_SEG0_IN and LBU_SEG1_IN (see Table 3-2, Figure 3-2 and Figure 3-3).
TPS-1
LBU_SEG(1:0)_IN
You can also choose a pa ge size of 4 Kbyte. When you choose 4 Kbyte pages you have less space inside the NRT area for configuration slots and subslots.
LBU_Ax_IN(13:12)
Figure 3-2: TPS-1 with address page 16 Kbyte
Figure 3-3: TPS-1 with address page 4 Kbyte
R19UH0081ED0107 Rev. 1.07 page 18 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 3. Host Interface
0: write; 1: read no function (Motorola-Mode)
LBU_BE_1_IN
Byte Selection 1
LBU_READY_OUT
Ready Signal
polarity changeable
LBU_A0_IN – LBU_A13_IN
Address lines 0 - 13
LBU_SEG1_IN
High Bit of the segment
page selection
0
1
8-Bit HIGH
Other combinations
Not allowed
01 1 0
8-Bit access
11 1 0
8-Bit access
Table 3-2 describes all signals of the parallel Host interfac e.
Table 3-2: Parallel Host Interface Layout
Signal designation Function Remarks
LBU_WR_EN_IN Write Control active low (Intel mode)
(Motorola mode)
LBU_READ_EN_IN Read Control active low (Intel-mode)
LBU_CS_IN Chip Select
LBU_BE_2_IN Byte Selection 2
LBU_DATA0 – LBU_DATA15 data line 0 – 15
LBU_SEG0_IN Low Bit of the segment page selection
During a memory access, the TPS-1 behaves like a „16-bit Little Endian“ device with an 8-bit or 16-bit memory. The possible access types are listed in Table 3-3.
Table 3-3: 16-Bit External Host Databus
LBU_BE_2_IN LBU_BE_1_IN Access type
1 0 8-Bit LOW
0 0 16-Bit
Table 3-4: 8-Bit External Host Databus
LBU_A[1:0] LBU_BE_2_IN LBU_BE_1_IN Access type
00 1 0 8-Bit access
10 1 0 8-Bit access
Other combinations Not allowed
An illegal access results in an „Error-IRQ“ from the event u nit.
R19UH0081ED0107 Rev. 1.07 page 19 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 3. Host Interface
LBU_SEG(1:0)
Selected Page
0 0
Page 00
0 1
Page 01
1 0
Page 02
1 1
Page 03
0x
0000
0x
2000
0x
8000
0xFFFF
NRT
-Area
IO
-RAM
Event
-Unit
16 K Page Size
0x4000
0xC000
Page 00
Page 02
Page 01
Page 03

3.2.3. Memory Segmentation at 4 kByte and 16 kByte page size

You decide the page size with the TPS Configurator. A connected Host CPU selected the pages with the LBU_SEGx_IN signals. Table 3-5 shows the page decoding.
Table 3-5: Page selection with LBU_SEGx_IN signals
The segmentation with 16 Kbyte pages is shown in Figure 3-4. With 16 address lines you can reach the whole 64 kByte address space.
Figure 3-4: 16 kByte page size
R19UH0081ED0107 Rev. 1.07 page 20 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 3. Host Interface
0x0000
0x
2000
0x
8000
0xFFFF
NRT
-Area
IO
-RAM
Event-Unit
4 K Page Size
0x3000
0x9000
Page 00
Page 02
Page 01
Page 03
0x1000
0x9FFF
Using the 4 kByte address pages limits the available a d dress space of the NRT area. Figure 3-5 shows the pages. You can reach the complete Event­Unit and th e complete IO-RAM. Out of the NRT area you can only use the address space between 0x8000 and 0x9FFF.
Figure 3-5: 4 kByte page size
Because of the page size, i t is not possible to use the max. Possible number of slots and subslots. Other page sizes than 16 kByte and 4 kByte are not possible.
R19UH0081ED0107 Rev. 1.07 page 21 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 3. Host Interface
TPS-1
HOST-CPU
RDN
A0 – A15
CSN
AD0 – AD7
A14 A15
WR0N
LBU_CS_IN
LBU_BE_1_IN
LBU_BE_2_IN
LBU_READ_EN_IN
LBU_SEG0_IN LBU_SEG1_IN
LBU_WR_EN_IN
LBU_A0_IN – LBU_A13_IN
LBU_DATA0 – LBU_DATA7
WR0N (byte)
RDN
AD0 – AD7
A0 – A15
&
0
0
0
INTN
INT_OUT
INT Port
READYN
LBU_READY_OUT
WAITN
„1"
CSN

3.2.4. Connection example for an 8bit data bus

Figure 3-6 shows a connection example of an 8-bi t data bus to the TPS -1.
Figure 3-6: Connection example for an 8-bit data bus
R19UH0081ED0107 Rev. 1.07 page 22 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 3. Host Interface
TPS
-
1
HOST
-
CPU
RDN
A1 – A15
CSN
AD
0
– AD15
A14
A15
WR
0N
WR1N
LBU
_
CS_
IN
LBU_BE_1_IN
LBU_BE_2_IN
LBU_READ_EN_IN
LBU
_
SEG
0
_IN
LBU_
SEG
1
_IN
LBU_WR_EN
_IN
LBU_A1_IN – LBU
_
A13
_
IN
LBU_DATA0 – LBU_DATA
15
WR0N
WR
1N
RDN
AD0 – AD15
A1 – A15
&
0
0
0
INTN
INT
_
OUT
INT Port
READYN
LBU_
READY
_
OUT
WAITN
&
0
0
0
&
0
0
0
CSN
LBU_
A0
_IN
10
K

3.2.5. Connection example for a 16-bit data bus

Figure 3-7 shows the connection of a 16-bit CPU to the TPS-1. The connection uses a 16-bit data bus and an address bus of 16 bit. Thus, it is possible to access the entire addr ess space of 64 KByte. Address line A0 should not be connected using the 16-bit data bus. The Address line LBU_A0_IN should be connected to a pull down.
Figure 3-7: Connection of a V850 CPU with a 16-bit data bus
R19UH0081ED0107 Rev. 1.07 page 23 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 3. Host Interface
Pin
GPIO Pin
N3
GPIO_39
HOST_SFRN_IN
Serial Frame
The start of a new SPI
N4
GPIO_41
HOST_SCLK_IN
Serial Clock Input
Serial Clock driven by the P4
GPIO_43
HOST_SHDR_OUT
Serial Header Information
header information available
TPS-1
SPI-SLAVE
HOST-CPU (V850ES/JG2)
MOSI MISO
SCLK
CSIBx-Master SOBx SIBx SCKBx
HOST_STXD_OUT
HOST_SRXD_IN
HOST_SCLK_IN
SPI-Reset
SFRN_IN
SHDR_OUT
HOST_RESET_IN
HOST_SFRN_IN
HOST_SHDR_OUT
P02 (Output)
P03 (Output)
P04 (Input)

3.3. SPI Slave Interface

Another way to connect a host CPU is the SPI interface. The maximum speed for s er ial access to the shared m emory is 25 MHz. The tr ansmission clock frequency should range between 1 MHz and 25 MHz. A control unit for processing the SPI Master commands is implemented into the TPS-1. The SPI Master commands are described in this chapter.
Table 3-6: SPI host interface signals
Signal designation Function Remarks
P3 GPIO_38 HOST_RESET_IN Serial Reset The SPI Slave interface can
be reset by using this signal (signal is active high).
transfer is signalized.
N2 GPIO_40 HOST_SRXD_IN Serial Data Input MOSI (Master out Slave in)
SPI Master
M4 GPIO_42 HOST_STXD_OUT Serial Data Output MISO (Master in Slave out)
An unknown or wrong SPI access causes an „Error-IRQ“ that is reported to the host CPU by the event unit. The clock phase and the CPOL (clock polarity) is adjustable (active low, active high). The following figure shows the connection of a host CPU (V850ES/JG2) to the SPI Slave interface of the TPS-1. The “chip select” line is not connected. The data transfer is cont rolled by the status of the “clock line” (CSI-Master). The pins HOST_RESET_IN, HOST_SFRN_IN and HOST_SHDR_OUT are not supported directly by the HOST-CPU. They have to be simulated by the pins P02, P03 and P04.
R19UH0081ED0107 Rev. 1.07 page 24 of 86 Jul 30, 2018
Figure 3-8: Connection of a V850 CPU to the SPI interface
TPS-1 User’s Manual: Hardware 3. Host Interface
Command
Address
Address
Length
Length

3.3.1. Serial access to the shared memory

The access to the shared memory is processed with command bytes that are part of the SPI-Header. The command structure depends on the device.
Generally, an SPI interface works like a shift register. The clock is driven by the SPI master. After processing the SPI command, the SPI slave sends th e requested data to the host CPU (or data is only sent to the SPI slave). As long as the chip select signal is active, data are exc hanged between the devices (master – slave).
3.3.1.1. Header structure
The content and meaning of SPI data is defined by the implementation of the SPI slave. The following chapter describes the structure of the SPI slave commands.
Table 3-7: SPI header structure
Header Data
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 – max.
1 Byte 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte .. max. length Shared Memory
An indirect command contains the length information in byte 3 and 4. A direct command contains the length information in the bits 0 to 3 of the command byte. The maximum ad dress access is limited t o 15 byte.
R19UH0081ED0107 Rev. 1.07 page 25 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 3. Host Interface
b7 b6
b
5 b
4
b3
b2
b
1 b0
Access Area
Direct IO Length
b6 = 1 (write) b7 = 1 (read)
3.3.1.2. Structure of a comm and byte
Figure 3-9 shows the format of a command byte. A command byte can be followed by an address area, length area and data.
Figure 3-9: Command b yte for SPI slaves (host interface)
The bits of the command byte have the following meaning:
• b7 indicates a read command,
• b6 indicates a write command,
• b5 and b4 describe the addressing range:
„00“: MEM ac cess to the complete shared m emory (64 Kbyte) „01“: IO access to the input/output area „10“: access to a multicast provider CR (only write) „11“: fractional access to an I-CR (b6 = 1) or MC-CR (b6 = 0)
• b3 .. b0 contain the length for an optimized direct data access
„= 0000“: no d irect acces s. „≠ 0000“: direct access length information (maximum of 15 byte)
R19UH0081ED0107 Rev. 1.07 page 26 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 3. Host Interface
This gives the external host CPU access to the complete address space of 64 Kbyte.
Read MEM Direct
Reads from the transferred
0b1000_nnnn
2 0 1 - 15
With this command, the external host CPU can read from and write to the complete 64
Read MEM
Reads from the transferred
0b1000_0000
2 2 1 – 32K
3.3.1.3. Command overview
The SPI commands are optimized for the use with PROFINET. The following table describes the implemented commands.
Table 3-8: Implemented SPI commands
DirectMEM-
Access
Each access transfers not more than 15 byte. The length is coded in the command byte.
Command Description
address. The length is coded in the command byte.
Write MEM Direct Writes to the transferred
address. The length is coded in the command byte.
MEM-Access
Kbyte address space with a maximum data length of 64 Kbyte (access to cyclic and acyclic data).
Command Description
address. The length is coded in the length byte.
Write MEM Writes to the transferred
address. The length is coded in the length byte.
Command
code
(0x8n)
0b0100_nnnn (0x4n)
Command
code
(0x80)
0b0100_0000 (0x40)
Number of
address
bytes
Number of
length
bytes
Number
of data
bytes
2 0 1 - 15
Number of
address
bytes
Number of
length
bytes
Number
of
data
bytes
(64K)
2 2 1 – 32K
(64K)
R19UH0081ED0107 Rev. 1.07 page 27 of 86 Jul 30, 2018
TPS-1 User’s Manual: Hardware 3. Host Interface
B7 B6 B5
B4 B3 B1B2 B0 B15 B14 B13 B12 B11 B9B10 B8 B7 B6 B5 B4
HOST_SCLK_IN
SPI-Header
SPI-Data
B7 B6 B5 B4 B3 B1B2 B0
B15 B14 B13 B12 B11 B9B10 B8
DummyDummyDummyDumm
y
MSBit
LSBit LSBit
MSBit
HOST_SFRN_IN
HOST_SRXD_IN
HOST_STXD_IN
HOST_SHDR_OUT
Motorola SPI format: SPO = 0 SPH = 0

3.3.2. SPI Slave Interface Timing

The SPI transfer is controlled by the signal HOST_SFRN_IN. A chip select signal is not used.
3.3.2.1. SPI Slave Interface Typical Timing
The following figure shows a typical SPI-Slave Timing (Motorola Mode). Each transfer (a transmission of 8 bit) starts with a falling edge of the HOST_SFRN_IN signal. The transmission is controlled by the clock signal. All receive and transmit da ta is processed in the Little-Endian format by the serial host interface. When connecting a Big-Endian Host System, the format has to be changed into the correct order. There is a maximum clock frequency of 25 MHz possible using t his interface .
Figure 3-10: SPI Slave Timing
The signal HOST_SHDR_OUT is used to inform the SPI master, that header information has been received (HOST_SHDR_OUT = 0). When the signal goes to high level (HOST_SHDR_OUT = 1), payload data is expected.
R19UH0081ED0107 Rev. 1.07 page 28 of 86 Jul 30, 2018
Loading...
+ 63 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use