Renesas SH7781 User Manual
REJ09B0261-0100
SH7785
32
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH™ RISC Engine Family
SH7780 Series
Rev.1.00
Revision Date: Jan. 10, 2008
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
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products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev.1.00 Jan. 10, 2008 Page ii of xxx
REJ09B0261-0100
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in
the manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in
the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions
may occur due to the false recognition of the pin state as an input signal. Unused pins
should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register settings
and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the
states of pins are not guaranteed from the moment when power is supplied until the
reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on
reset function are not guaranteed from the moment when power is supplied until the
power reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do not
access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has
become stable. When switching the clock signal during program execution, wait until the
target clock signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization
of the clock signal. Moreover, when switching to a clock signal produced with an
external resonator (or by an external oscillator) while program execution is in progress,
wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number,
confirm that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different type numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different type numbers, implement a system-evaluation test for
each of the products.
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REJ09B0261-0100
Rev.1.00 Jan. 10, 2008 Page iv of xxx
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Preface
This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas
Technology-original RISC CPU (SH-4A) and various peripheral functions required to configure a
system.
Target Users: This manual was written for users who will be using this LSI in the design of
application systems. Users of this manual are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the above users.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual consists of parts on the CPU, system
control functions, peripheral functions and electrical characteristics.
• In order to understand individual instructions in detail
Read the separate manuals SH-4A Extended Functions Software Manual and SH-4A Software
Manual.
Rules: Bit order: The MSB is on the left and the LSB is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to active-low signals: xxxx
Rev.1.00 Jan. 10, 2008 Page v of xxx
REJ09B0261-0100
Abbreviations
ALU Arithmetic Logic Unit
ASID Address Space Identifier
BGA Ball Grid Array
CMT Timer/Counter (Compare Match Timer)
CPG Clock Pulse Generator
CPU Central Processing Unit
DDR Double Data Rate
DDRIF DDR-SDRAM Interface
DMA Direct Memory Access
DMAC Direct Memory Access Controller
FIFO First-In First-Out
FPU Floating-point Unit
HAC Audio Codec
H-UDI User Debugging Interface
INTC Interrupt Controller
JTAG Joint Test Action Group
LBSC Local Bus State Controller
LRAM L Memory
LRU Least Recently Used
LSB Least Significant Bit
MMCIF Multimedia Card Interface
MMU Memory Management Unit
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MSB Most Significant Bit
PC Program Counter
PCI Peripheral Component Interconnect
PCIC PCI (local bus) Controller
PFC Pin Function Controller
RISC Reduced Instruction Set Computer
RTC Realtime Clock
SCIF Serial Communication Interface with FIFO
SIOF Serial Interface with FIFO
SSI Serial Sound Interface
TAP Test Access Port
TLB Translation Lookaside Buffer
TMU Timer Unit
UART Universal Asynchronous Receiver/Transmitter
UBC User Break Controller
WDT Watchdog Timer
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REJ09B0261-0100
All trademarks and registered trademarks are the property of their respective owners.
Rev.1.00 Jan. 10, 2008 Page viii of xxx
REJ09B0261-0100
Contents
Section 1 Overview.................................................................................................................. 1
1.1 Features of the SH7785..........................................................................................................1
1.2 Block Diagram ..................................................................................................................... 13
1.3 Pin Arrangement Table ........................................................................................................ 14
1.4 Pin Arrangement .................................................................................................................. 22
1.5 Physical Memory Address Map ........................................................................................... 24
Section 2 Programming Model........................................................................................... 25
2.1
Data Formats ........................................................................................................................ 25
2.2 Register Descriptions ...........................................................................................................26
2.2.1 Privileged Mode and Banks.................................................................................. 26
2.2.2 General Registers.................................................................................................. 30
2.2.3 Floating-Point Registers ....................................................................................... 31
2.2.4 Control Registers .................................................................................................. 33
2.2.5 System Registers................................................................................................... 35
2.3 Memory-Mapped Registers.................................................................................................. 39
2.4 Data Formats in Registers .................................................................................................... 40
2.5 Data Formats in Memory ..................................................................................................... 40
2.6 Processing States.................................................................................................................. 41
2.7 Usage Notes .........................................................................................................................43
2.7.1 Notes on Self-Modifying Code............................................................................. 43
Section 3 Instruction Set....................................................................................................... 45
3.1 Execution Environment ....................................................................................................... 45
3.2 Addressing Modes ............................................................................................................... 47
3.3 Instruction Set ...................................................................................................................... 52
Section 4 Pipelining
4.1 Pipelines............................................................................................................................... 65
4.2 Parallel-Executability........................................................................................................... 76
4.3 Issue Rates and Execution Cycles........................................................................................ 79
Section 5 Exception Handling
5.1
Summary of Exception Handling......................................................................................... 89
5.2 Register Descriptions ...........................................................................................................89
5.2.1 TRAPA Exception Register (TRA) ...................................................................... 90
............................................................................................................... 65
............................................................................................ 89
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5.2.2 Exception Event Register (EXPEVT)................................................................... 91
5.2.3 Interrupt Event Register (INTEVT)...................................................................... 92
5.2.4 Non-Support Detection Exception Register (EXPMASK)................................... 93
5.3 Exception Handling Functions............................................................................................. 95
5.3.1 Exception Handling Flow ..................................................................................... 95
5.3.2 Exception Handling Vector Addresses................................................................. 95
5.4 Exception Types and Priorities ............................................................................................ 96
5.5 Exception Flow .................................................................................................................... 98
5.5.1 Exception Flow..................................................................................................... 98
5.5.2 Exception Source Acceptance ............................................................................ 100
5.5.3 Exception Requests and BL Bit.......................................................................... 101
5.5.4 Return from Exception Handling........................................................................ 101
5.6 Description of Exceptions.................................................................................................. 102
5.6.1 Resets.................................................................................................................. 102
5.6.2 General Exceptions............................................................................................. 104
5.6.3 Interrupts............................................................................................................. 120
5.6.4 Priority Order with Multiple Exceptions ............................................................ 121
5.7 Usage Notes ....................................................................................................................... 123
Section 6 Floating-Point Unit (FPU) .............................................................................. 125
6.1
Features.............................................................................................................................. 125
6.2 Data Formats...................................................................................................................... 126
6.2.1 Floating-Point Format......................................................................................... 126
6.2.2 Non-Numbers (NaN) .......................................................................................... 129
6.2.3 Denormalized Numbers...................................................................................... 130
6.3 Register Descriptions ......................................................................................................... 131
6.3.1 Floating-Point Registers ..................................................................................... 131
6.3.2 Floating-Point Status/Control Register (FPSCR) ............................................... 133
6.3.3 Floating-Point Communication Register (FPUL)............................................... 136
6.4 Rounding............................................................................................................................ 137
6.5 Floating-Point Exceptions.................................................................................................. 138
6.5.1 General FPU Disable Exceptions and Slot FPU Disable Exceptions ................. 138
6.5.2 FPU Exception Sources ...................................................................................... 138
6.5.3 FPU Exception Handling.................................................................................... 139
6.6 Graphics Support Functions............................................................................................... 140
6.6.1 Geometric Operation Instructions....................................................................... 140
6.6.2 Pair Single-Precision Data Transfer.................................................................... 141
Section 7 Memory Management Unit (MMU)
7.1 Overview of MMU ............................................................................................................ 144
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............................................................ 143
7.1.1 Address Spaces ................................................................................................... 146
7.2 Register Descriptions ......................................................................................................... 152
7.2.1 Page Table Entry High Register (PTEH)............................................................ 153
7.2.2 Page Table Entry Low Register (PTEL)............................................................. 154
7.2.3 Translation Table Base Register (TTB).............................................................. 155
7.2.4 TLB Exception Address Register (TEA)............................................................ 156
7.2.5 MMU Control Register (MMUCR).................................................................... 156
7.2.6 Page Table Entry Assistance Register (PTEA)................................................... 159
7.2.7 Physical Address Space Control Register (PASCR)........................................... 160
7.2.8 Instruction Re-Fetch Inhibit Control Register (IRMCR).................................... 162
7.3 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0)............................................ 164
7.3.1 Unified TLB (UTLB) Configuration .................................................................. 164
7.3.2 Instruction TLB (ITLB) Configuration............................................................... 167
7.3.3 Address Translation Method............................................................................... 167
7.4 TLB Functions (TLB Extended Mode; MMUCR.ME = 1) ............................................... 170
7.4.1 Unified TLB (UTLB) Configuration .................................................................. 170
7.4.2 Instruction TLB (ITLB) Configuration............................................................... 173
7.4.3 Address Translation Method............................................................................... 174
7.5 MMU Functions................................................................................................................. 177
7.5.1 MMU Hardware Management............................................................................ 177
7.5.2 MMU Software Management ............................................................................. 177
7.5.3 MMU Instruction (LDTLB)................................................................................ 178
7.5.4 Hardware ITLB Miss Handling .......................................................................... 180
7.5.5 Avoiding Synonym Problems............................................................................. 181
7.6 MMU Exceptions............................................................................................................... 182
7.6.1 Instruction TLB Multiple Hit Exception............................................................. 182
7.6.2 Instruction TLB Miss Exception......................................................................... 183
7.6.3 Instruction TLB Protection Violation Exception................................................ 184
7.6.4 Data TLB Multiple Hit Exception ......................................................................185
7.6.5 Data TLB Miss Exception ..................................................................................185
7.6.6 Data TLB Protection Violation Exception.......................................................... 187
7.6.7 Initial Page Write Exception............................................................................... 188
7.7 Memory-Mapped TLB Configuration................................................................................ 190
7.7.1 ITLB Address Array ........................................................................................... 191
7.7.2 ITLB Data Array (TLB Compatible Mode)........................................................ 192
7.7.3 ITLB Data Array (TLB Extended Mode) ........................................................... 193
7.7.4 UTLB Address Array.......................................................................................... 195
7.7.5 UTLB Data Array (TLB Compatible Mode) ...................................................... 196
7.7.6 UTLB Data Array (TLB Extended Mode).......................................................... 197
7.8 32-Bit Address Extended Mode......................................................................................... 199
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7.8.1 Overview of 32-Bit Address Extended Mode..................................................... 199
7.8.2 Transition to 32-Bit Address Extended Mode .................................................... 200
7.8.3 Privileged Space Mapping Buffer (PMB) Configuration ................................... 200
7.8.4 PMB Function..................................................................................................... 202
7.8.5 Memory-Mapped PMB Configuration ............................................................... 203
7.8.6 Notes on Using 32-Bit Address Extended Mode................................................ 204
7.9 32-Bit Boot Function ......................................................................................................... 207
7.9.1 Initial Entries to PMB......................................................................................... 207
7.9.2 Notes on 32-Bit Boot.......................................................................................... 207
7.10 Usage Notes ....................................................................................................................... 209
7.10.1 Note on Using LDTLB Instruction..................................................................... 209
Section 8 Caches................................................................................................................... 211
8.1
Features.............................................................................................................................. 211
8.2 Register Descriptions ......................................................................................................... 215
8.2.1 Cache Control Register (CCR) ........................................................................... 216
8.2.2 Queue Address Control Register 0 (QACR0)..................................................... 218
8.2.3 Queue Address Control Register 1 (QACR1)..................................................... 219
8.2.4 On-Chip Memory Control Register (RAMCR).................................................. 220
8.3 Operand Cache Operation.................................................................................................. 222
8.3.1 Read Operation ................................................................................................... 222
8.3.2 Prefetch Operation.............................................................................................. 223
8.3.3 Write Operation .................................................................................................. 224
8.3.4 Write-Back Buffer .............................................................................................. 225
8.3.5 Write-Through Buffer......................................................................................... 225
8.3.6 OC Two-Way Mode ........................................................................................... 226
8.4 Instruction Cache Operation .............................................................................................. 227
8.4.1 Read Operation ................................................................................................... 227
8.4.2 Prefetch Operation.............................................................................................. 227
8.4.3 IC Two-Way Mode............................................................................................. 228
8.4.4 Instruction Cache Way Prediction Operation ..................................................... 228
8.5 Cache Operation Instruction .............................................................................................. 229
8.5.1 Coherency between Cache and External Memory.............................................. 229
8.5.2 Prefetch Operation.............................................................................................. 231
8.6 Memory-Mapped Cache Configuration ............................................................................. 232
8.6.1 IC Address Array................................................................................................ 232
8.6.2 IC Data Array ..................................................................................................... 234
8.6.3 OC Address Array .............................................................................................. 234
8.6.4 OC Data Array.................................................................................................... 236
8.6.5 Memory-Mapped Cache Associative Write Operation....................................... 237
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8.7 Store Queues ...................................................................................................................... 238
8.7.1 SQ Configuration................................................................................................ 238
8.7.2 Writing to SQ...................................................................................................... 238
8.7.3 Transfer to External Memory.............................................................................. 239
8.7.4 Determination of SQ Access Exception.............................................................. 240
8.7.5 Reading from SQ ................................................................................................ 240
8.8 Notes on Using 32-Bit Address Extended Mode ............................................................... 241
Section 9 On-Chip Memory .............................................................................................. 243
9.1
Features .............................................................................................................................. 243
9.2 Register Descriptions ......................................................................................................... 246
9.2.1 On-Chip Memory Control Register (RAMCR) .................................................. 247
9.2.2 OL memory Transfer Source Address Register 0 (LSA0).................................. 248
9.2.3 OL memory Transfer Source Address Register 1 (LSA1).................................. 250
9.2.4 OL memory Transfer Destination Address Register 0 (LDA0).......................... 252
9.2.5 OL memory Transfer Destination Address Register 1 (LDA1).......................... 254
9.3 Operation ........................................................................................................................... 256
9.3.1 Instruction Fetch Access from the CPU.............................................................. 256
9.3.2 Operand Access from the CPU and Access from the FPU ................................. 256
9.3.3 Access from the SuperHyway Bus Master Module............................................ 257
9.3.4 OL Memory Block Transfer ............................................................................... 257
9.4 On-Chip Memory Protective Functions ............................................................................. 260
9.5 Usage Notes ....................................................................................................................... 261
9.5.1 Page Conflict ...................................................................................................... 261
9.5.2 Access Across Different Pages........................................................................... 261
9.5.3 On-Chip Memory Coherency ............................................................................. 261
9.5.4 Sleep Mode ......................................................................................................... 262
9.6 Note on Using 32-Bit Address Extended Mode................................................................. 262
Section 10 Interrupt Controller (INTC) ......................................................................... 263
10.1
Features.............................................................................................................................. 263
10.1.1 Interrupt Method................................................................................................. 266
10.1.2 Interrupt Sources................................................................................................. 267
10.2 Input/Output Pins...............................................................................................................272
10.3 Register Descriptions......................................................................................................... 273
10.3.1 External Interrupt Request Registers .................................................................. 277
10.3.2 User Mode Interrupt Disable Function ............................................................... 298
10.3.3 On-chip Module Interrupt Priority Registers...................................................... 300
10.3.4 Individual On-Chip Module Interrupt Source Registers (INT2B0 to INT2B7).. 314
10.3.5 GPIO Interrupt Set Register (INT2GPIC) .......................................................... 322
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10.4 Interrupt Sources................................................................................................................ 324
10.4.1 NMI Interrupts.................................................................................................... 324
10.4.2 IRQ Interrupts..................................................................................................... 324
10.4.3 IRL Interrupts ..................................................................................................... 325
10.4.4 On-Chip Peripheral Module Interrupts ............................................................... 327
10.4.5 Priority of On-Chip Peripheral Module Interrupts.............................................. 328
10.4.6 Interrupt Exception Handling and Priority ......................................................... 329
10.5 Operation ........................................................................................................................... 337
10.5.1 Interrupt Sequence.............................................................................................. 337
10.5.2 Multiple Interrupts.............................................................................................. 339
10.5.3 Interrupt Masking by MAI Bit............................................................................ 339
10.6 Interrupt Response Time.................................................................................................... 340
10.7 Usage Notes ....................................................................................................................... 343
10.7.1 Example of Handing Routine of IRL Interrupts and Level Detection
IRQ Interrupts when ICR0.LVLMODE = 0....................................................... 343
10.7.2 Notes on Setting IRQ/IRL[7:0] Pin Function ..................................................... 344
10.7.3 Clearing IRQ and IRL Interrupt Requests .......................................................... 345
Section 11 Local Bus State Controller (LBSC)........................................................... 347
11.1 Features.............................................................................................................................. 347
11.2 Input/Output Pins...............................................................................................................350
11.3 Overview of Areas............................................................................................................. 354
11.3.1 Space Divisions .................................................................................................. 354
11.3.2 Memory Bus Width ............................................................................................ 357
11.3.3 PCMCIA Support ............................................................................................... 358
11.4 Register Descriptions......................................................................................................... 362
11.4.1 Memory Address Map Select Register (MMSELR)........................................... 364
11.4.2 Bus Control Register (BCR)............................................................................... 367
11.4.3 CSn Bus Control Register (CSnBCR) ................................................................ 371
11.4.4 CSn Wait Control Register (CSnWCR).............................................................. 377
11.4.5 CSn PCMCIA Control Register (CSnPCR)........................................................ 382
11.5 Operation ........................................................................................................................... 387
11.5.1 Endian/Access Size and Data Alignment ........................................................... 387
11.5.2 Areas................................................................................................................... 398
11.5.3 SRAM interface.................................................................................................. 403
11.5.4 Burst ROM Interface .......................................................................................... 412
11.5.5 PCMCIA Interface.............................................................................................. 416
11.5.6 MPX Interface .................................................................................................... 427
11.5.7 Byte Control SRAM Interface ............................................................................ 441
11.5.8 Wait Cycles between Access Cycles .................................................................. 446
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11.5.9 Bus Arbitration ................................................................................................... 448
11.5.10 Master Mode....................................................................................................... 450
11.5.11 Slave Mode ......................................................................................................... 451
11.5.12 Cooperation between Master and Slave.............................................................. 451
11.5.13 Power-Down Mode and Bus Arbitration ............................................................ 451
11.5.14 Mode Pin Settings and General Input Output Port Settings about
Data Bus Width................................................................................................... 452
11.5.15 Pins Multiplexed with Other Modules Functions ...............................................452
11.5.16 Register Settings for Divided-Up DACKn Output ............................................. 452
Section 12 DDR2-SDRAM Interface (DBSC2).......................................................... 457
12.1
Features.............................................................................................................................. 457
12.2 Input/Output Pins...............................................................................................................460
12.3 Data Alignment..................................................................................................................465
12.4 Register Descriptions......................................................................................................... 479
12.4.1 DBSC2 Status Register (DBSTATE) ................................................................. 482
12.4.2 SDRAM Operation Enable Register (DBEN)..................................................... 483
12.4.3 SDRAM Command Control Register (DBCMDCNT)....................................... 484
12.4.4 SDRAM Configuration Setting Register (DBCONF)......................................... 486
12.4.5 SDRAM Timing Register 0 (DBTR0)................................................................ 488
12.4.6 SDRAM Timing Register 1 (DBTR1)................................................................ 492
12.4.7 SDRAM Timing Register 2 (DBTR2)................................................................ 495
12.4.8 SDRAM Refresh Control Register 0 (DBRFCNT0) .......................................... 499
12.4.9 SDRAM Refresh Control Register 1 (DBRFCNT1) .......................................... 500
12.4.10 SDRAM Refresh Control Register 2 (DBRFCNT2) ..........................................502
12.4.11 SDRAM Refresh Status Register (DBRFSTS)................................................... 504
12.4.12 DDRPAD Frequency Setting Register (DBFREQ) ............................................ 505
12.4.13 DDRPAD DIC, ODT, OCD Setting Register (DBDICODTOCD)..................... 507
12.4.14 SDRAM Mode Setting Register (DBMRCNT).................................................. 510
12.5 DBSC2 Operation .............................................................................................................. 512
12.5.1 Supported SDRAM Commands.......................................................................... 512
12.5.2 SDRAM Command Issue ...................................................................................513
12.5.3 Initialization Sequence........................................................................................ 516
12.5.4 Self-Refresh Operation .......................................................................................517
12.5.5 Auto-Refresh Operation...................................................................................... 520
12.5.6 Regarding Address Multiplexing........................................................................ 521
12.5.7 Regarding SDRAM Access and Timing Constraints.......................................... 530
12.5.8 Important Information Regarding Use of 8-Bank DDR2-SDRAM Products ..... 544
12.5.9 Important Information Regarding ODT Control Signal Output to SDRAM ...... 544
12.5.10 DDR2-SDRAM Power Supply Backup Function............................................... 546
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12.5.11 Method for Securing Time Required for Initialization, Self-Refresh
Cancellation, etc. ................................................................................................ 549
12.5.12 Regarding the Supported Clock Ratio ................................................................ 549
12.5.13 Regarding MCKE Signal Operation ................................................................... 550
Section 13 PCI Controller (PCIC)................................................................................... 551
13.1
Features.............................................................................................................................. 551
13.2 Input/Output Pins...............................................................................................................554
13.3 Register Descriptions......................................................................................................... 557
13.3.1 PCIC Enable Control Register (PCIECR) .......................................................... 562
13.3.2 Configuration Registers ...................................................................................... 563
13.3.3 PCI Local Registers ............................................................................................ 590
13.4 Operation ........................................................................................................................... 630
13.4.1 Supported PCI Commands ................................................................................. 630
13.4.2 PCIC Initialization .............................................................................................. 631
13.4.3 Master Access..................................................................................................... 632
13.4.4 Target Access ..................................................................................................... 640
13.4.5 Host Mode .......................................................................................................... 648
13.4.6 Normal Mode...................................................................................................... 651
13.4.7 Power Management ............................................................................................ 651
13.4.8 PCI Local Bus Basic Interface............................................................................ 653
Section 14 Direct Memory Access Controller (DMAC)........................................... 665
14.1 Features.............................................................................................................................. 665
14.2 Input/Output Pins...............................................................................................................667
14.3 Register Descriptions......................................................................................................... 668
14.3.1 DMA Source Address Registers 0 to 11 (SAR0 to SAR11)............................... 675
14.3.2 DMA Source Address Registers B0 to B3, B6 to B9
(SARB0 to SARB3, SARB6 to SARB9)............................................................ 676
14.3.3 DMA Destination Address Registers 0 to 11 (DAR0 to DAR11) ...................... 677
14.3.4 DMA Destination Address Registers B0 to B3, B6 to B9
(DARB0 to DARB3, DARB6 to DARB9) ......................................................... 678
14.3.5 DMA Transfer Count Registers 0 to 11 (TCR0 to TCR11)................................ 679
14.3.6 DMA Transfer Count Registers B0 to B3, B6 to B9
(TCRB0 to TCRB3, TCRB6 to TCRB9)............................................................ 680
14.3.7 DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11) ....................... 681
14.3.8 DMA Operation Register 0, 1 (DMAOR0 and DMAOR1)................................ 689
14.3.9 DMA Extended Resource Selectors 0 to 5 (DMARS0 to DMARS5)................. 693
14.4 Operation ........................................................................................................................... 701
14.4.1 DMA Transfer Requests ..................................................................................... 701
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14.4.2 Channel Priority.................................................................................................. 706
14.4.3 DMA Transfer Types.......................................................................................... 709
14.4.4 DMA Transfer Flow ........................................................................................... 717
14.4.5 Repeat Mode Transfer ........................................................................................ 719
14.4.6 Reload Mode Transfer ........................................................................................ 720
14.4.7 DREQ Pin Sampling Timing .............................................................................. 721
14.5 DMAC Interrupt Sources................................................................................................... 729
14.6 Usage Notes ....................................................................................................................... 730
14.6.1 Stopping Modules and Changing Frequency...................................................... 730
14.6.2 Address Error...................................................................................................... 730
14.6.3 NMI Interrupt...................................................................................................... 730
14.6.4 Burst Mode Transfer........................................................................................... 730
14.6.5 Divided-Up DACK Output................................................................................. 730
14.6.6 DACK/DREQ Setting......................................................................................... 731
Section 15 Clock Pulse Generator (CPG) ..................................................................... 733
15.1
Features.............................................................................................................................. 733
15.2 Input/Output Pins...............................................................................................................736
15.3 Clock Operating Modes ..................................................................................................... 737
15.4 Register Descriptions......................................................................................................... 739
15.4.1 Frequency Control Register 0 (FRQCR0) ..........................................................741
15.4.2 Frequency Control Register 1 (FRQCR1) ..........................................................742
15.4.3 Frequency Display Register 1 (FRQMR1) .........................................................745
15.4.4 PLL Control Register (PLLCR).......................................................................... 747
15.5 Calculating the Frequency .................................................................................................748
15.6 How to Change the Frequency........................................................................................... 749
15.6.1 Changing the Frequency of Clocks Other than the Bus Clock ........................... 749
15.6.2 Changing the Bus Clock Frequency ................................................................... 749
15.7 Notes on Designing Board................................................................................................. 756
Section 16 Watchdog Timer and Reset (WDT)
16.1
Features.............................................................................................................................. 759
16.2 Input/Output Pins...............................................................................................................761
16.3 Register Descriptions......................................................................................................... 762
16.3.1 Watchdog Timer Stop Time Register (WDTST)................................................ 763
16.3.2 Watchdog Timer Control/Status Register (WDTCSR)....................................... 764
16.3.3 Watchdog Timer Base Stop Time Register (WDTBST)..................................... 766
16.3.4 Watchdog Timer Counter (WDTCNT)............................................................... 767
16.3.5 Watchdog Timer Base Counter (WDTBCNT) ................................................... 768
16.4 Operation ........................................................................................................................... 769
........................................................... 759
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16.4.1 Reset Request ..................................................................................................... 769
16.4.2 Using Watchdog Timer Mode ............................................................................ 771
16.4.3 Using Interval Timer Mode ................................................................................ 771
16.4.4 Time until WDT Counters Overflow.................................................................. 772
16.4.5 Clearing WDT Counters ..................................................................................... 773
16.5 Status Pin Change Timing during Reset ............................................................................ 774
16.5.1 Power-On Reset by PRESET Pin ....................................................................... 774
16.5.2 Power-On Reset by Watchdog Timer Overflow................................................. 777
16.5.3 Manual Reset by Watchdog Timer Overflow..................................................... 779
Section 17 Power-Down Mode ........................................................................................ 781
17.1
Features.............................................................................................................................. 781
17.1.1 Types of Power-Down Modes............................................................................ 781
17.2 Input/Output Pins...............................................................................................................783
17.3 Register Descriptions......................................................................................................... 783
17.3.1 Sleep Control Register (SLPCR) ........................................................................ 785
17.3.2 Standby Control Register 0 (MSTPCR0) ........................................................... 786
17.3.3 Standby Control Register 1 (MSTPCR1) ........................................................... 789
17.3.4 Standby Display Register (MSTPMR) ............................................................... 791
17.4 Sleep Mode ........................................................................................................................ 793
17.4.1 Transition to Sleep Mode.................................................................................... 793
17.4.2 Releasing Sleep Mode ........................................................................................ 793
17.5 Deep Sleep Mode............................................................................................................... 794
17.5.1 Transition to Deep Sleep Mode .......................................................................... 794
17.5.2 Releasing Deep Sleep Mode............................................................................... 795
17.6 Module Standby Functions ................................................................................................ 796
17.6.1 Transition to Module Standby Mode .................................................................. 796
17.6.2 Releasing Module Standby Functions ................................................................ 796
17.7 Timing of the Changes on the STATUS Pins .................................................................... 797
17.7.1 Reset ................................................................................................................... 797
17.7.2 Releasing Sleep Mode ........................................................................................ 797
17.8 DDR-SDRAM Power Supply Backup............................................................................... 797
Section 18 Timer Unit (TMU)
18.1
Features.............................................................................................................................. 799
18.2 Input/Output Pins...............................................................................................................801
18.3 Register Descriptions......................................................................................................... 802
18.3.1 Timer Start Registers (TSTRn) (n = 0, 1)........................................................... 804
18.3.2 Timer Constant Registers (TCORn) (n = 0 to 5) ................................................ 806
18.3.3 Timer Counters (TCNTn) (n = 0 to 5)................................................................ 806
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.......................................................................................... 799
18.3.4 Timer Control Registers (TCRn) (n = 0 to 5) ..................................................... 807
18.3.5 Input Capture Register 2 (TCPR2) ..................................................................... 809
18.4 Operation ........................................................................................................................... 810
18.4.1 Counter Operation .............................................................................................. 810
18.4.2 Input Capture Function ....................................................................................... 813
18.5 Interrupts............................................................................................................................ 814
18.6 Usage Notes ....................................................................................................................... 815
18.6.1 Register Writes ................................................................................................... 815
18.6.2 Reading from TCNT........................................................................................... 815
18.6.3 External Clock Frequency .................................................................................. 815
Section 19 Display Unit (DU) .......................................................................................... 817
19.1
Features.............................................................................................................................. 817
19.2 Input/Output Pins...............................................................................................................820
19.3 Register Descriptions......................................................................................................... 821
19.3.1 Display Unit System Control Register................................................................ 841
19.3.2 Display Mode Register (DSMR) ........................................................................ 845
19.3.3 Display Status Register (DSSR) ......................................................................... 849
19.3.4 Display Unit Status Register Clear Register (DSRCR) ...................................... 853
19.3.5 Display Unit Interrupt Enable Register (DIER).................................................. 854
19.3.6 Color Palette Control Register (CPCR) .............................................................. 857
19.3.7 Display Plane Priority Register (DPPR) ............................................................. 859
19.3.8 Display Unit Extensional Function Enable Register (DEFR)............................. 862
19.3.9 Horizontal Display Start Register (HDSR)......................................................... 864
19.3.10 Horizontal Display End Register (HDER).......................................................... 865
19.3.11 Vertical Display Start Register (VDSR)............................................................. 866
19.3.12 Vertical Display End Register (VDER).............................................................. 867
19.3.13 Horizontal Cycle Register (HCR)....................................................................... 868
19.3.14 Horizontal Sync Width Register (HSWR).......................................................... 869
19.3.15 Vertical Cycle Register (VCR) ........................................................................... 870
19.3.16 Vertical Sync Point Register (VSPR) ................................................................. 871
19.3.17 Equal Pulse Width Register (EQWR)................................................................. 872
19.3.18 Separation Width Register (SPWR).................................................................... 873
19.3.19 CLAMP Signal Start Register (CLAMPSR) ...................................................... 874
19.3.20 CLAMP Signal Width Register (CLAMPWR)................................................... 875
19.3.21 DE Signal Start Register (DESR) ....................................................................... 876
19.3.22 DE Signal Width Register (DEWR) ................................................................... 877
19.3.23 Color Palette 1 Transparent Color Register (CP1TR)......................................... 878
19.3.24 Color Palette 2 Transparent Color Register (CP2TR)......................................... 881
19.3.25 Color Palette 3 Transparent Color Register (CP3TR)......................................... 884
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19.3.26 Color Palette 4 Transparent Color Register (CP4TR) ........................................ 887
19.3.27 Display Off Mode Output Register (DOOR)...................................................... 890
19.3.28 Color Detection Register (CDER) ...................................................................... 891
19.3.29 Background Plane Output Register (BPOR)....................................................... 892
19.3.30 Raster Interrupt Offset Register (RINTOFSR)................................................... 894
19.3.31 Plane n Mode Register (PnMR) (n = 1 to 6)....................................................... 895
19.3.32 Plane n Memory Width Register (PnMWR) (n = 1 to 6).................................... 898
19.3.33 Plane n Blending Ratio Register (PnALPHAR) (n = 1 to 6) .............................. 899
19.3.34 Plane n Display Size X Register (PnDSXR) (n = 1 to 6).................................... 901
19.3.35 Plane n Display Size Y Register (PnDSYR) (n = 1 to 6).................................... 902
19.3.36 Plane n Display Position X Register (PnDPXR) (n = 1 to 6).............................. 903
19.3.37 Plane n Display Position Y Register (PnDPYR) (n = 1 to 6).............................. 904
19.3.38 Plane n Display Area Start Address 0 Register (PnDSA0R) (n = 1 to 6) ........... 905
19.3.39 Plane n Display Area Start Address 1 Register (PnDSA1R) (n = 1 to 6) ........... 906
19.3.40 Plane n Start Position X Register (PnSPXR) (n = 1 to 6) ................................... 907
19.3.41 Plane n Start Position Y Register (PnSPYR) (n = 1 to 6) ................................... 908
19.3.42 Plane n Wrap Around Start Position Register (PnWASPR) (n = 1 to 6) ............ 909
19.3.43 Plane n Wrap Around Memory Width Register (PnWAMWR) (n = 1 to 6) ...... 910
19.3.44 Plane n Blinking Time Register (PnBTR) (n = 1 to 6) ....................................... 911
19.3.45 Plane n Transparent Color 1 Register (PnTC1R) (n = 1 to 6)............................. 912
19.3.46 Plane n Transparent Color 2 Register (PnTC2R) (n = 1 to 6)............................. 913
19.3.47 Plane n Memory Length Register (PnMLR) (n = 1 to 6).................................... 914
19.3.48 Color Palette 1 Register 000 to 255 (CP1_000R to CP1_255R) ........................ 915
19.3.49 Color Palette 2 Register 000 to 255 (CP2_000R to CP2_255R) ........................ 916
19.3.50 Color Palette 3 Register 000 to 255 (CP3_000R to CP3_255R) ........................ 918
19.3.51 Color Palette 4 Register 000 to 255 (CP4_000R to CP4_255R) ........................ 919
19.3.52 External Synchronization Control Register (ESCR)........................................... 921
19.3.53 Output Signal Timing Adjustment Register (OTAR)......................................... 923
19.4 Operation ........................................................................................................................... 930
19.4.1 Configuration of Output Screen.......................................................................... 930
19.4.2 Display On/Off ................................................................................................... 933
19.4.3 Plane Parameter .................................................................................................. 934
19.4.4 Memory Allocation............................................................................................. 936
19.4.5 Input Display Data Format ................................................................................. 937
19.4.6 Output Data Format ............................................................................................ 940
19.4.7 Endian Conversion.............................................................................................. 940
19.4.8 Color Palettes...................................................................................................... 942
19.4.9 Superpositioning of Planes ................................................................................. 943
19.4.10 Display Contention ............................................................................................. 947
19.4.11 Blinking .............................................................................................................. 949
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19.4.12 Scroll Display .....................................................................................................950
19.4.13 Wraparound Display........................................................................................... 951
19.4.14 Upper-Left Overflow Display............................................................................. 952
19.4.15 Double Buffer Control........................................................................................ 953
19.4.16 Sync Mode.......................................................................................................... 954
19.5 Display Control.................................................................................................................. 956
19.5.1 Display Timing Generation ................................................................................ 956
19.5.2 CSYNC............................................................................................................... 959
19.5.3 Scan Method ....................................................................................................... 961
19.5.4 Color Detection................................................................................................... 965
19.5.5 Output Signal Timing Adjustment...................................................................... 966
19.5.6 CLAMP Signal and DE Signal ........................................................................... 967
19.6 Power-Down Sequence...................................................................................................... 968
19.6.1 Procedures before Executing the Power-Down Sequence.................................. 968
19.6.2 Resetting the Power-Down Sequence................................................................. 968
Section 20 Graphics Data Translation Accelerator (GDTA)................................... 969
20.1
Features.............................................................................................................................. 969
20.2 GDTA Address Space........................................................................................................ 973
20.3 Register Descriptions......................................................................................................... 974
20.3.1 GA Mask Register (GACMR) ............................................................................ 979
20.3.2 GA Enable Register (GACER) ........................................................................... 980
20.3.3 GA Interrupt Source Indicating Register (GACISR) .......................................... 981
20.3.4 GA Interrupt Source Indication Clear Register (GACICR)................................ 982
20.3.5 GA Interrupt Enable Register (GACIER)........................................................... 983
20.3.6 GA CL Input Data Alignment Register (DRCL_CTL)....................................... 984
20.3.7 GA CL Output Data Alignment Register (DWCL_CTL)................................... 985
20.3.8 GA MC Input Data Alignment Register (DRMC_CTL) ....................................986
20.3.9 GA MC Output Data Alignment Register (DWMC_CTL)................................. 987
20.3.10 GA Buffer RAM 0 Data Alignment Register (DCP_CTL)................................. 988
20.3.11 GA Buffer RAM 1 Data Alignment Register (DID_CTL) ................................. 989
20.3.12 CL Command FIFO (CLCF) .............................................................................. 990
20.3.13 CL Control Register (CLCR).............................................................................. 991
20.3.14 CL Status Register (CLSR)................................................................................. 993
20.3.15 CL Frame Width Setting Register (CLWR) ....................................................... 994
20.3.16 CL Frame Height Setting Register (CLHR) ....................................................... 995
20.3.17 CL Input Y Padding Size Setting Register (CLIYPR)........................................ 996
20.3.18 CL Input UV Padding Size Setting Register (CLIUVPR).................................. 997
20.3.19 CL Output Padding Size Setting Register (CLOPR) .......................................... 998
20.3.20 CL Palette Pointer Register (CLPLPR) .............................................................. 999
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20.3.21 MC Command FIFO (MCCF) .......................................................................... 1000
20.3.22 MC Status Register (MCSR) ............................................................................ 1003
20.3.23 MC Frame Width Setting Register (MCWR)................................................... 1004
20.3.24 MC Frame Height Setting Register (MCHR) ................................................... 1005
20.3.25 MC Y Padding Size Setting Register (MCYPR) .............................................. 1006
20.3.26 MC UV Padding Size Setting Register (MCUVPR) ........................................ 1007
20.3.27 MC Output Frame Y Pointer Register (MCOYPR).......................................... 1008
20.3.28 MC Output Frame U Pointer Register (MCOUPR).......................................... 1008
20.3.29 MC Output Frame V Pointer Register (MCOVPR).......................................... 1009
20.3.30 MC Past Frame Y Pointer Register (MCPYPR)............................................... 1009
20.3.31 MC Past Frame U Pointer Register (MCPUPR)............................................... 1010
20.3.32 MC Past Frame V Pointer Register (MCPVPR)............................................... 1010
20.3.33 MC Future Frame Y Pointer Register (MCFYPR) ........................................... 1011
20.3.34 MC Future Frame U Pointer Register (MCFUPR) ........................................... 1011
20.3.35 MC Future Frame V Pointer Register (MCFVPR) ........................................... 1012
20.4 GDTA Operation ............................................................................................................. 1013
20.4.1 Explanation of CL Operation............................................................................ 1013
20.4.2 Explanation of MC Operation........................................................................... 1019
20.5 Interrupt Processing ......................................................................................................... 1029
20.6 Data Alignment................................................................................................................ 1029
20.7 Usage Notes ..................................................................................................................... 1031
20.7.1 Regarding Module Stoppage ............................................................................ 1031
20.7.2 Regarding Deep Sleep Modes........................................................................... 1031
20.7.3 Regarding Frequency Changes ......................................................................... 1032
Section 21 Serial Communication Interface with FIFO (SCIF) ........................... 1033
21.1
Features............................................................................................................................ 1033
21.2 Input/Output Pins............................................................................................................. 1039
21.3 Register Descriptions....................................................................................................... 1040
21.3.1 Receive Shift Register (SCRSR) ...................................................................... 1046
21.3.2 Receive FIFO Data Register (SCFRDR) .......................................................... 1046
21.3.3 Transmit Shift Register (SCTSR) ..................................................................... 1047
21.3.4 Transmit FIFO Data Register (SCFTDR)......................................................... 1047
21.3.5 Serial Mode Register (SCSMR) ....................................................................... 1048
21.3.6 Serial Control Register (SCSCR) ..................................................................... 1051
21.3.7 Serial Status Register n (SCFSR) ..................................................................... 1055
21.3.8 Bit Rate Register n (SCBRR) ........................................................................... 1061
21.3.9 FIFO Control Register n (SCFCR) ................................................................... 1062
21.3.10 Transmit FIFO Data Count Register n (SCTFDR) ........................................... 1064
21.3.11 Receive FIFO Data Count Register n (SCRFDR) ............................................ 1065
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21.3.12 Serial Port Register n (SCSPTR) ...................................................................... 1066
21.3.13 Line Status Register n (SCLSR) ....................................................................... 1069
21.3.14 Serial Error Register n (SCRER) ...................................................................... 1070
21.4 Operation ......................................................................................................................... 1071
21.4.1 Overview .......................................................................................................... 1071
21.4.2 Operation in Asynchronous Mode .................................................................... 1074
21.4.3 Operation in Clocked Synchronous Mode........................................................ 1085
21.5 SCIF Interrupt Sources and the DMAC........................................................................... 1094
21.6 Usage Notes ..................................................................................................................... 1096
Section 22 Serial I/O with FIFO (SIOF)...................................................................... 1099
22.1
Features............................................................................................................................ 1099
22.2 Input/Output Pins............................................................................................................. 1101
22.3 Register Descriptions....................................................................................................... 1102
22.3.1 Mode Register (SIMDR) .................................................................................. 1104
22.3.2 Control Register (SICTR)................................................................................. 1106
22.3.3 Transmit Data Register (SITDR) ...................................................................... 1108
22.3.4 Receive Data Register (SIRDR) ....................................................................... 1109
22.3.5 Transmit Control Data Register (SITCR) ......................................................... 1110
22.3.6 Receive Control Data Register (SIRCR) .......................................................... 1111
22.3.7 Status Register (SISTR).................................................................................... 1112
22.3.8 Interrupt Enable Register (SIIER) .................................................................... 1118
22.3.9 FIFO Control Register (SIFCTR) ..................................................................... 1120
22.3.10 Clock Select Register (SISCR) ......................................................................... 1122
22.3.11 Transmit Data Assign Register (SITDAR) ....................................................... 1123
22.3.12 Receive Data Assign Register (SIRDAR) ........................................................ 1125
22.3.13 Control Data Assign Register (SICDAR) ......................................................... 1126
22.4 Operation ......................................................................................................................... 1128
22.4.1 Serial Clocks..................................................................................................... 1128
22.4.2 Serial Timing .................................................................................................... 1129
22.4.3 Transfer Data Format........................................................................................ 1131
22.4.4 Register Allocation of Transfer Data................................................................ 1133
22.4.5 Control Data Interface ...................................................................................... 1135
22.4.6 FIFO.................................................................................................................. 1137
22.4.7 Transmit and Receive Procedures..................................................................... 1139
22.4.8 Interrupts........................................................................................................... 1144
22.4.9 Transmit and Receive Timing........................................................................... 1146
Section 23 Serial Peripheral Interface (HSPI)
23.1
Features............................................................................................................................ 1151
............................................................ 1151
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23.2 Input/Output Pins............................................................................................................. 1153
23.3 Register Descriptions....................................................................................................... 1153
23.3.1 Control Register (SPCR) .................................................................................. 1155
23.3.2 Status Register (SPSR) ..................................................................................... 1158
23.3.3 System Control Register (SPSCR) ................................................................... 1161
23.3.4 Transmit Buffer Register (SPTBR) .................................................................. 1163
23.3.5 Receive Buffer Register (SPRBR).................................................................... 1164
23.4 Operation ......................................................................................................................... 1165
23.4.1 Operation Overview with FIFO Mode Disabled............................................... 1165
23.4.2 Operation with FIFO Mode Enabled ................................................................ 1166
23.4.3 Timing Diagrams.............................................................................................. 1167
23.4.4 HSPI Software Reset ........................................................................................ 1169
23.4.5 Clock Polarity and Transmit Control................................................................ 1169
23.4.6 Transmit and Receive Routines ........................................................................ 1169
23.4.7 Flags and Interrupt Timing ............................................................................... 1170
23.4.8 Low-Power Consumption and Clock Synchronization..................................... 1170
Section 24 Multimedia Card Interface (MMCIF)..................................................... 1171
24.1
Features............................................................................................................................ 1171
24.2 Input/Output Pins............................................................................................................. 1172
24.3 Register Descriptions....................................................................................................... 1173
24.3.1 Command Registers 0 to 5 (CMDR0 to CMDR5)............................................ 1177
24.3.2 Command Start Register (CMDSTRT) ............................................................ 1178
24.3.3 Operation Control Register (OPCR)................................................................. 1179
24.3.4 Card Status Register (CSTR)............................................................................ 1181
24.3.5 Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2)................................. 1183
24.3.6 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2) ............................... 1187
24.3.7 Transfer Clock Control Register (CLKON) ..................................................... 1193
24.3.8 Command Timeout Control Register (CTOCR)............................................... 1194
24.3.9 Transfer Byte Number Count Register (TBCR) ............................................... 1195
24.3.10 Mode Register (MODER)................................................................................. 1196
24.3.11 Command Type Register (CMDTYR).............................................................. 1197
24.3.12 Response Type Register (RSPTYR)................................................................. 1198
24.3.13 Transfer Block Number Counter (TBNCR) ..................................................... 1202
24.3.14 Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD).......................... 1203
24.3.15 Data Timeout Register (DTOUTR) .................................................................. 1205
24.3.16 Data Register (DR) ........................................................................................... 1206
24.3.17 FIFO Pointer Clear Register (FIFOCLR) ......................................................... 1207
24.3.18 DMA Control Register (DMACR) ................................................................... 1208
24.4 Operation ......................................................................................................................... 1209
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24.4.1 Operations in MMC Mode................................................................................ 1209
24.5 MMCIF Interrupt Sources................................................................................................ 1239
24.6 Operations when Using DMA.......................................................................................... 1240
24.6.1 Operation in Read Sequence............................................................................. 1240
24.6.2 Operation in Write Sequence............................................................................ 1250
24.7 Register Accesses with Little Endian Specification......................................................... 1261
Section 25 Audio Codec Interface (HAC) .................................................................. 1263
25.1
Features............................................................................................................................ 1263
25.2 Input/Output Pins............................................................................................................. 1265
25.3 Register Descriptions....................................................................................................... 1266
25.3.1 Control and Status Register (HACCR) ............................................................. 1269
25.3.2 Command/Status Address Register (HACCSAR) ............................................ 1271
25.3.3 Command/Status Data Register (HACCSDR).................................................. 1273
25.3.4 PCM Left Channel Register (HACPCML)....................................................... 1275
25.3.5 PCM Right Channel Register (HACPCMR) .................................................... 1277
25.3.6 TX Interrupt Enable Register (HACTIER)....................................................... 1278
25.3.7 TX Status Register (HACTSR)......................................................................... 1279
25.3.8 RX Interrupt Enable Register (HACRIER) ...................................................... 1281
25.3.9 RX Status Register (HACRSR) ........................................................................ 1282
25.3.10 HAC Control Register (HACACR) .................................................................. 1284
25.4 AC 97 Frame Slot Structure............................................................................................. 1286
25.5 Operation ......................................................................................................................... 1288
25.5.1 Receiver ............................................................................................................ 1288
25.5.2 Transmitter........................................................................................................ 1288
25.5.3 DMA................................................................................................................. 1289
25.5.4 Interrupts........................................................................................................... 1289
25.5.5 Initialization Sequence...................................................................................... 1290
25.5.6 Power-Down Mode........................................................................................... 1295
25.5.7 Notes................................................................................................................. 1295
25.5.8 Reference .......................................................................................................... 1295
Section 26 Serial Sound Interface (SSI) Module ...................................................... 1297
26.1
Features............................................................................................................................ 1297
26.2 Input/Output Pins............................................................................................................. 1299
26.3 Register Descriptions....................................................................................................... 1300
26.3.1 Control Register (SSICR) ................................................................................. 1301
26.3.2 Status Register (SSISR).................................................................................... 1308
26.3.3 Transmit Data Register (SSITDR).................................................................... 1313
26.3.4 Receive Data Register (SSIRDR) ..................................................................... 1313
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26.4 Operation ......................................................................................................................... 1314
26.4.1 Bus Format ....................................................................................................... 1314
26.4.2 Non-Compressed Modes .................................................................................. 1315
26.4.3 Compressed Modes........................................................................................... 1324
26.4.4 Operation Modes .............................................................................................. 1327
26.4.5 Transmit Operation........................................................................................... 1328
26.4.6 Receive Operation ............................................................................................ 1331
26.4.7 Serial Clock Control ......................................................................................... 1334
26.5 Usage Note....................................................................................................................... 1335
26.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation ........ 1335
26.5.2 Pin Function Setting for the SSI Module.......................................................... 1335
26.5.3 Usage Note in Slave Mode ............................................................................... 1335
Section 27 NAND Flash Memory Controller (FLCTL).......................................... 1337
27.1
Features............................................................................................................................ 1337
27.2 Input/Output Pins............................................................................................................. 1340
27.3 Register Descriptions....................................................................................................... 1342
27.3.1 Common Control Register (FLCMNCR) ......................................................... 1344
27.3.2 Command Control Register (FLCMDCR)........................................................ 1346
27.3.3 Command Code Register (FLCMCDR) ........................................................... 1348
27.3.4 Address Register (FLADR) .............................................................................. 1349
27.3.5 Address Register 2 (FLADR2) ......................................................................... 1351
27.3.6 Data Counter Register (FLDTCNTR) .............................................................. 1352
27.3.7 Data Register (FLDATAR) .............................................................................. 1353
27.3.8 Interrupt DMA Control Register (FLINTDMACR) ......................................... 1354
27.3.9 Ready Busy Timeout Setting Register (FLBSYTMR) ..................................... 1359
27.3.10 Ready Busy Timeout Counter (FLBSYCNT)................................................... 1360
27.3.11 Data FIFO Register (FLDTFIFO)..................................................................... 1361
27.3.12 Control Code FIFO Register (FLECFIFO)....................................................... 1362
27.3.13 Transfer Control Register (FLTRCR)............................................................... 1363
27.4 Operation ......................................................................................................................... 1364
27.4.1 Operating Modes .............................................................................................. 1364
27.4.2 Command Access Mode ................................................................................... 1364
27.4.3 Sector Access Mode ......................................................................................... 1368
27.4.4 Status Read ....................................................................................................... 1371
27.5 Example of Register Setting ............................................................................................ 1373
27.6 Interrupt Processing ......................................................................................................... 1376
27.7 DMA Transfer Settings.................................................................................................... 1376
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Section 28 General Purpose I/O Ports (GPIO)........................................................... 1377
28.1
Features............................................................................................................................ 1377
28.2 Register Descriptions....................................................................................................... 1382
28.2.1 Port A Control Register (PACR) ...................................................................... 1386
28.2.2 Port B Control Register (PBCR)....................................................................... 1389
28.2.3 Port C Control Register (PCCR)....................................................................... 1391
28.2.4 Port D Control Register (PDCR) ...................................................................... 1393
28.2.5 Port E Control Register (PECR) ....................................................................... 1395
28.2.6 Port F Control Register (PFCR)........................................................................ 1397
28.2.7 Port G Control Register (PGCR) ...................................................................... 1399
28.2.8 Port H Control Register (PHCR) ...................................................................... 1401
28.2.9 Port J Control Register (PJCR)......................................................................... 1403
28.2.10 Port K Control Register (PKCR) ...................................................................... 1405
28.2.11 Port L Control Register (PLCR) ....................................................................... 1407
28.2.12 Port M Control Register (PMCR)..................................................................... 1409
28.2.13 Port N Control Register (PNCR) ...................................................................... 1410
28.2.14 Port P Control Register (PPCR)........................................................................ 1412
28.2.15 Port Q Control Register (PQCR) ...................................................................... 1414
28.2.16 Port R Control Register (PRCR)....................................................................... 1416
28.2.17 Port A Data Register (PADR)........................................................................... 1418
28.2.18 Port B Data Register (PBDR) ........................................................................... 1419
28.2.19 Port C Data Register (PCDR) ........................................................................... 1420
28.2.20 Port D Data Register (PDDR)........................................................................... 1421
28.2.21 Port E Data Register (PEDR)............................................................................ 1422
28.2.22 Port F Data Register (PFDR)............................................................................ 1423
28.2.23 Port G Data Register (PGDR)........................................................................... 1424
28.2.24 Port H Data Register (PHDR)........................................................................... 1425
28.2.25 Port J Data Register (PJDR) ............................................................................. 1426
28.2.26 Port K Data Register (PKDR)........................................................................... 1427
28.2.27 Port L Data Register (PLDR)............................................................................ 1428
28.2.28 Port M Data Register (PMDR) ......................................................................... 1429
28.2.29 Port N Data Register (PNDR)........................................................................... 1430
28.2.30 Port P Data Register (PPDR)............................................................................ 1431
28.2.31 Port Q Data Register (PQDR)........................................................................... 1432
28.2.32 Port R Data Register (PRDR) ........................................................................... 1433
28.2.33 Port E Pull-Up Control Register (PEPUPR)..................................................... 1434
28.2.34 Port H Pull-Up Control Register (PHPUPR) .................................................... 1435
28.2.35 Port J Pull-Up Control Register (PJPUPR)....................................................... 1436
28.2.36 Port K Pull-Up Control Register (PKPUPR) .................................................... 1437
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28.2.37 Port L Pull-Up Control Register (PLPUPR)..................................................... 1438
28.2.38 Port M Pull-Up Control Register (PMPUPR)................................................... 1439
28.2.39 Port N Pull-Up Control Register (PNPUPR) .................................................... 1440
28.2.40 Input-Pin Pull-Up Control Register 1 (PPUPR1) ............................................. 1441
28.2.41 Input-Pin Pull-Up Control Register 2 (PPUPR2) ............................................. 1441
28.2.42 Peripheral Module Select Register 1 (P1MSELR) ........................................... 1443
28.2.43 Peripheral Module Select Register 2 (P2MSELR) ........................................... 1447
28.3 Usage Example ................................................................................................................ 1449
28.3.1 Port Output Function ........................................................................................ 1449
28.3.2 Port Input function............................................................................................ 1450
28.3.3 Peripheral Module Function ............................................................................. 1451
Section 29 User Break Controller (UBC).................................................................... 1453
29.1 Features............................................................................................................................ 1453
29.2 Register Descriptions....................................................................................................... 1455
29.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1) ....................... 1457
29.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1) ....................... 1463
29.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1).......................... 1465
29.2.4 Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)......... 1466
29.2.5 Match Data Setting Register 1 (CDR1) ............................................................ 1468
29.2.6 Match Data Mask Setting Register 1 (CDMR1)............................................... 1469
29.2.7 Execution Count Break Register 1 (CETR1).................................................... 1470
29.2.8 Channel Match Flag Register (CCMFR) .......................................................... 1471
29.2.9 Break Control Register (CBCR)....................................................................... 1472
29.3 Operation Description...................................................................................................... 1473
29.3.1 Definition of Words Related to Accesses ......................................................... 1473
29.3.2 User Break Operation Sequence....................................................................... 1474
29.3.3 Instruction Fetch Cycle Break .......................................................................... 1475
29.3.4 Operand Access Cycle Break ........................................................................... 1476
29.3.5 Sequential Break............................................................................................... 1477
29.3.6 Program Counter Value to be Saved................................................................. 1479
29.4 User Break Debugging Support Function........................................................................ 1480
29.5 User Break Examples....................................................................................................... 1481
29.6 Usage Notes ..................................................................................................................... 1485
Section 30 User Debugging Interface (H-UDI)
30.1
Features............................................................................................................................ 1487
30.2 Input/Output Pins............................................................................................................. 1489
30.3 Register Description ........................................................................................................ 1491
30.3.1 Instruction Register (SDIR).............................................................................. 1492
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......................................................... 1487
30.3.2 Interrupt Source Register (SDINT)................................................................... 1492
30.3.3 Bypass Register (SDBPR) ................................................................................ 1493
30.3.4 Boundary Scan Register (SDBSR) ................................................................... 1493
30.4 Operation ......................................................................................................................... 1503
30.4.1 Boundary-Scan TAP Controller (IDCODE, EXTEST, SAMPLE/PRELOAD,
and BYPASS) ................................................................................................... 1503
30.4.2 TAP Control...................................................................................................... 1505
30.4.3 H-UDI Reset ..................................................................................................... 1506
30.4.4 H-UDI Interrupt ................................................................................................ 1507
30.5 Usage Notes ..................................................................................................................... 1507
Section 31 Register List.................................................................................................... 1509
31.1
Register Address List....................................................................................................... 1509
31.2 States of the Registers in the Individual Operating Modes.............................................. 1533
Section 32 Electrical Characteristics ............................................................................ 1561
32.1
Absolute Maximum Ratings ............................................................................................1561
32.2 DC Characteristics ........................................................................................................... 1562
32.3 AC Characteristics ........................................................................................................... 1567
32.3.1 Clock and Control Signal Timing..................................................................... 1568
32.3.2 Control Signal Timing ...................................................................................... 1572
32.3.3 Bus Timing ....................................................................................................... 1574
32.3.4 DBSC2 Signal Timing ...................................................................................... 1592
32.3.5 INTC Module Signal Timing............................................................................ 1597
32.3.6 PCIC Module Signal Timing ............................................................................ 1599
32.3.7 DMAC Module Signal Timing ......................................................................... 1601
32.3.8 TMU Module Signal Timing ............................................................................ 1602
32.3.9 SCIF Module Signal Timing............................................................................. 1603
32.3.10 H-UDI Module Signal Timing.......................................................................... 1605
32.3.11 GPIO Signal Timing......................................................................................... 1607
32.3.12 HSPI Module Signal Timing ............................................................................ 1608
32.3.13 SIOF Module Signal Timing ............................................................................ 1609
32.3.14 MMCIF Module Signal Timing........................................................................ 1613
32.3.15 HAC Interface Module Signal Timing.............................................................. 1614
32.3.16 SSI Interface Module Signal Timing ................................................................ 1616
32.3.17 FLCTL Module Signal Timing......................................................................... 1618
32.3.18 Display Unit Signal Timing.............................................................................. 1622
32.4 AC Characteristic Test Conditions................................................................................... 1625
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Appendix ............................................................................................................................ 1627
A.
Package Dimensions........................................................................................................ 1627
B. Mode Pin Settings ............................................................................................................ 1628
C. Pin Functions ................................................................................................................... 1631
C.1 Pin States .......................................................................................................... 1631
C.2 Handling of Unused Pins .................................................................................. 1642
D. Turning On and Off Power Supply.................................................................................. 1653
D.1 Turning On and Off Between Each Power Supply Series ................................ 1653
D.2 Power-On and Power-Off Sequences for Power Supplies with Different
Potentials in DDR2-SDRAM Power Supply Backup Mode............................. 1654
D.3 Turning On and Off Between the Same Power Supply Series.......................... 1655
E. Version Registers (PVR, PRR) ........................................................................................ 1656
F. Product Lineup................................................................................................................. 1657
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