Renesas SH7751 Group, SH7751R Group User Manual

32

The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.

SH7751 Group, SH7751R Group

User’s Manual: Hardware

Renesas 32-Bit RISC Microcomputer
SuperH™ RISC engine Family / SH7750 Series

Rev.3.01 Sep 2013

Page ii of liv R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

Notice

semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.

3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of
third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of
Renesas Electronics or others.

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Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration,
modification, copy or otherwise misappropriation of Renesas Electronics product.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The
recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems;

Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to
human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property
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by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas
Electronics.

6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.

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specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
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malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems
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8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility
of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and
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manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use
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regulations and follow the procedures required by such laws and regulations.

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places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this
document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of
unauthorized use of Renesas Electronics products.

11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas
Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document
or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its

(Note 2) “Renesas Electronics product(s)” means any product develope d or manufactured by or for Renesas Electronics.

equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.

anti-crime systems; and safety equipment etc.

majority-owned subsidiaries.

(2012.4)

R01UH0457EJ0301 Rev. 3.01 Page iii of liv

Sep 24, 2013

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
they are used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.

5. Reading from/Writing to Reserved Bit of Each Register

Note: Treat the reserved bit of register used in each module as follows except in cases where the

specifications for values which are read from or written to the bit are provided in the
description.
The bit is always read as 0. The write value should be 0 or one, which has been read
immediately before writing.
Writing the value, which has been read immediately before writing has the advantage of
preventing the bit from being affected on its extended function when the function is
assigned.

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Preface

The SH-4 (SH7751 Group (SH7751, SH7751R)) microprocessor incorporates the 32-bit SH-4
CPU and is also equipped with peripheral functions necessary for configuring a user system.

The SH7751 Group is built in with a variety of peripheral functions such as cache memory,
memory management unit (MMU), interrupt controller, floating-point unit (FPU), timers, two
serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC),
bus state controller (BSC) and PCI controller (PCIC). This series can be used in a wide range of
multimedia equipment. The bus controller is compatible with ROM, SRAM, DRAM, synchronous
DRAM and PCMCIA.

Target Readers: This manual is designed for use by people who design application systems using
the SH7751 or SH7751R.
To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is
required.

This hardware manual contains revisions related to the addition of R-mask functionality. Be sure
to check the text for the updated content.

Purpose: This manual provides the information of the hardware functions and electrical
characteristics of the SH7751 and SH7751R.
The SH-4 Software Manual contains detailed information of executable instructions. Please read
the Software Manual together with this manual.

How to Use the Book:

• To understand general functions

→ Read the manual from the beginning.

The manual explains the CPU, system control functions, peripheral functions and electrical

characteristics in that order.

• To understanding CPU functions

→ Refer to the separate SH-4 Software Manual.

Explanatory Note: Bit sequence: upper bit at left, and lower bit at right

List of Related Documents: The latest documents are available on our Web site. Please make

sure that you have the latest version.
(http://www.renesas.com/)

R01UH0457EJ0301 Rev. 3.01 Page v of liv

Sep 24, 2013

• User manuals for SH7751 and SH7751R

Name of Document Document No.

SH7751 Group, SH7751R Group Hardware Manual This manual

SH-4 Software Manual REJ09B0318-0600

• User manuals for development tools

Name of Document Document No.

SuperH™ C/C++ Compiler, Assembler, Optimizing Linkage Editor User's

Manual

SuperH™ RISC engine Simulator/Debugger User's Manual REJ10B0210-0300

High-performance Embedded Workshop User's Manual REJ10J1554-0100

REJ10B0047-0100H

Page vi of liv R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

Main Revisions for This Edition

Item Page Revision (See Manual for Details)

All ⎯ Added ONPAC-BGA products (HD6417750SBA200V)

1.1 SH7751/SH7751R
Group Features

Table 1.1
SH7751/SH7751R Group
Features

2 Table amended

Item Features

CPU

8

Item Features

Product lineup

SH7751 1.8 V 167 MHz HD6417751BP167 256-pin BGA

HD6417751F167 256-pin QFP

SH7751R 1.5 V 240 MHz HD6417751RBP240 256-pin BGA

HD6417751RBA240H

HD6417751RF240 256-pin QFP

HD6417751RBG240 292-pin BGA

•

Renesas Electronics original SuperH architecture

Abbreviation Voltage

Operating
Frequency Model No.

Package

22.2.1 PCI Configuration
Register 0 (PCICONF0)

22.12.5 Notes on Parity
Error Detection during
Master Access

23.1 Absolute Maximum
Ratings

Table 23.1 Absolute
Maximum Ratings

857 Note amended

Note: * The vendor ID H'1054 specifies Hitachi, Ltd., but

the SH7751 and SH7751R are now products of
Renesas Electronics Corp. For information on
these products, contact Renesas Electronics
Corp.

980,

Newly added

981

983 Table amended and note added

Item Symbol Value Unit

I/O, RTC, CPG power supply voltage V

Internal power supply voltage VDD, V

Input voltage Vin –0.3 to V

Operating temperature T

Storage temperature T

,

DDQ

V

DD-RTC

V

DD-CPG

–20 to 75, –40 to 85*2 °C

opr

–55 to 125 °C

stg

Notes: 1. HD6417751R only.

2. HD6417751RBA240HV only.

,

–0.3 to 2.5

DD-PLL1/2

–0.3 to 4.2

–0.3 to 4.6*

–0.3 to 2.1*

1

1

+0.3 V

DDQ

V

V

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Item Page Revision (See Manual for Details)

23.2 DC Characteristics

Table 23.2 DC

982,
983

Table title amended and note added

Notes: 3. Ta = –40 to 85°C for the HD6417751RBA240HV.
Characteristics
(HD6417751RBP240 (V),
HD6417751RBG240 (V),
HD6417751RBA240HV)

Ta = –20 to +75°C*3

Table 23.4 DC
Characteristics
(HD6417751RBP200 (V),
HD6417751RBG200 (V),
HD6417751RBA240HV*3)

988,.
989

Table title amended and note added

Notes: 3. This is the case when the device in use is an

HD6417751RBA240HV running at 200 MHz.

4. Ta = –40 to 85°C for the HD6417751RBA240HV.

Ta = –20 to +75°C*4

23.3 AC Characteristics

996 Table title amended

Table 23.9 Clock Timing
(HD6417751RBP240 (V),
HD6417751RBG240 (V),
HD6417751RBA240HV)

Table 23.11 Clock
Timing
(HD6417751RBP200 (V),
HD6417751RBG200 (V),

997 Table title amended and note added

Note: * This is the case when the device in use is an

HD6417751RBA240HV running at 200 MHz.

HD6417751RBA240HV*)

23.3.1 Clock and Control
Signal Timing

Table 23.14 Clock and
Control Signal Timing
(HD6417751RBP240 (V),
HD6417751RBG240 (V),
HD6417751RBA240HV)

= 3.0 to 3.6 V, VDD =

V

DDQ

998,
999

Table title and table amended and note added

Item Symbol Min Max Unit Figure

Standby return oscillation settling time 1*

Standby return oscillation settling time 2*

Standby return oscillation settling time 3*1 t

1

t

2 — ms

OSC2

1

t

2 — ms

OSC3

2 — ms

OSC4

Notes: 1. When the oscillation settling time of the crystal

resonator is 1 ms or less.

2. Ta = –40 to 85°C for the HD6417751RBA240HV.

1.5 V, Ta = –20 to 75°C*2,
C

= 30 pF

L

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Sep 24, 2013

Item Page Revision (See Manual for Details)

23.3.1 Clock and Control
Signal Timing

Table 23.16 Clock and
Control Signal Timing
(HD6417751RBP200 (V),
HD6417751RBG200 (V),
HD6417751RBA240HV*2)

V

= 3.0 to 3.6 V, VDD =

DDQ

1.5 V, Ta = –20 to 75°C*3,
C

= 30 pF

L

23.3.2 Control Signal
Timing

Table 23.19 Control
Signal Timing

1002,
1003

Table title and table amended and note added

Item Symbol Min Max Unit Figure

Standby return oscillation settling time 1*

Standby return oscillation settling time 2*

Standby return oscillation settling time 3*1 t

1

t

2 — ms

OSC2

1

t

2 — ms

OSC3

2 — ms

OSC4

Notes: 1. When the oscillation settling time of the crystal

resonator is 1 ms or less.

2. This is the case when the device in use is an
HD6417751RBA240HV running at 200 MHz.

3. Ta = –40 to 85°C for the HD6417751RBA240HV.

1012 Table amended and note added

HD6417751
RBP240 (V)
HD6417751
RBG240 (V)
HD6417751
RBA240HV

Item Symbol Min Max Min Max Min Max Min Max Unit Figure

Notes: 1. V

= 3.0 to 3.6 V, VDD = 1.5 V, Ta= –20 to

DDQ

HD6417751
RBP200 (V)
HD6417751
RBG200 (V)
HD6417751
RBA240HV

1

*

*1 *

2

*

75°C*3, CL = 30 pF, PLL2 on

2. This is the case when the device in use is an
HD6417751RBA240HV running at 200 MHz.

3. Ta = –40 to 85°C for the HD6417751RBA240HV.

23.3.3 Bus Timing

Table 23.21 Bus Timing
(1)

1016,
1017

Table amended and note added

HD6417751
RBP240 (V)
HD6417751
RBG240 (V)

*

Item Symbol Min Max Min Max Min Max Min Max Unit Notes

Notes: 1. V

HD6417751
RBA240HV

= 3.0 to 3.6 V, VDD = 1.5 V, Ta= –20 to

DDQ

HD6417751
RBP200 (V)
HD6417751
RBG200 (V)
HD6417751
RBA240HV

1

*

2

*

1

75°C*3, CL = 30 pF, PLL2 on

2. This is the case when the device in use is an
HD6417751RBA240HV running at 200 MHz.

3. Ta = –40 to 85°C for the HD6417751RBA240HV.

HD6417751
RF240 (V)

1

HD6417751
RF240 (V)

1

*

HD6417751
RF200 (V)

*1

HD6417751
RF200 (V)

*1

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Item Page Revision (See Manual for Details)

23.3.4 Peripheral
Module Signal Timing

Table 23.23 Peripheral
Module Signal Timing (1)

1067
to
1069

Table amended and note added

HD6417751
RBP240 (V)
HD6417751
RBG240 (V)
HD6417751

*

Module Item Symbol Min Max Min Max Min Max Min Max Unit Figure Notes

Notes: 1. V

RBA240HV

= 3.0 to 3.6 V, VDD = 1.5 V, Ta= –20 to

DDQ

HD6417751
RBP200 (V)
HD6417751
RBG200 (V)
HD6417751
RBA240HV

2

*2 *2 *2

3

*

HD6417751
RF240 (V)

75°C*4, CL = 30 pF, PLL2 on

3. This is the case when the device in use is an
HD6417751RBA240HV running at 200 MHz.

4. Ta = –40 to 85°C for the HD6417751RBA240HV.

Table 23.25 PCIC Signal
Timing (in
PCIREQ/PCIGNT Non­Port Mode) (1)

1076

Table title amended and note added

Notes: 1. HD6417751RF240 (V), HD6417751RF200 (V)

2. Ta = –40 to 85°C for the HD6417751RBA240HV.

HD6417751RBP240 (V),
HD6417751RBP200 (V),
HD6417751RBG240 (V),
HD6417751RBG200 (V),
HD6417751RBA240HV,
HD6417751RF240 (V),
HD6417751RF200 (V):

= 3.0 to 3.6 V, VDD =

V

DDQ

Asterisk "*" in table changed to "*1"

"3.0 (3.5*)" → "3.0 (3.5*1)"

1.5 V, Ta = –20 to 75°C*2,
= 30 pF

C

L

Table 23.27 PCIC Signal
Timing (With
PCIREQ/PCIGNT Port

1079 Table title amended and note added

Note: * Ta = –40 to 85°C for the HD6417751RBA240HV.

Settings in Non-Host
Mode) (1)

HD6417751RBP240 (V),
HD6417751RBP200 (V),
HD6417751RBG240 (V),
HD6417751RBG200 (V),
HD6417751RBA240HV,
HD6417751RF240 (V),
HD6417751RF200 (V):

= 3.0 to 3.6 V, VDD =

V

DDQ

1.5 V, Ta = –20 to 75°C*,
= 30 pF

C

L

HD6417751
RF200 (V)

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Item Page Revision (See Manual for Details)

Appendix B Package

1092 Figure title amended

Dimensions

Figure B.2 Package
Dimensions (256-pin
BGA: Devices Other than
HD6417751RBA240HV)

Figure B.4 Package

1094 Figure newly added

Dimensions

(256-Pin BGA:
HD6417750RBA240HV)

D.2 Handling of Unused
Pins

Table D.4 Handling of

1105 Table amended

Pin Name I/O Handling

AD31–AD0 I/O Pull up to 3.3 V*

Pins When PCI Is Not
Used

Appendix H Product
Lineup

Table H.1
SH7751/SH7751R
Product Lineup

1125 Table note amended

Notes: 1. Contact a Renesas sales office regarding

product versions with specifications for a wider
temperature range (−40 to +85°C). The wide
temperature range (−40 to +85°C) is the
standard specification for the
HD6417751RBA240HV.

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All trademarks and registered trademarks are the property of their respective owners.

Page xii of liv R01UH0457EJ0301 Rev. 3.01

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Contents

Section 1 Overview................................................................................................1

1.1 SH7751/SH7751R Group Features ........................................................................................ 1

1.2 Block Diagram ....................................................................................................................... 9

1.3 Pin Arrangement ..................................................................................................................10

1.4 Pin Functions ....................................................................................................................... 13

1.4.1 Pin Functions (256-Pin QFP).................................................................................. 13

1.4.2 Pin Functions (256-Pin BGA)................................................................................. 24

1.4.3 Pin Functions (292-Pin BGA)................................................................................. 35

Section 2 Programming Model ............................................................................47

2.1 Data Formats ........................................................................................................................ 47

2.2 Register Configuration ......................................................................................................... 48

2.2.1 Privileged Mode and Banks.................................................................................... 48

2.2.2 General Registers.................................................................................................... 51

2.2.3 Floating-Point Registers.......................................................................................... 53

2.2.4 Control Registers ....................................................................................................55

2.2.5 System Registers..................................................................................................... 56

2.3 Memory-Mapped Registers.................................................................................................. 58

2.4 Data Format in Registers...................................................................................................... 59

2.5 Data Formats in Memory ..................................................................................................... 59

2.6 Processor States ................................................................................................................... 60

2.7 Processor Modes .................................................................................................................. 62

Section 3 Memory Management Unit (MMU) ....................................................63

3.1 Overview.............................................................................................................................. 63

3.1.1 Features................................................................................................................... 63

3.1.2 Role of the MMU.................................................................................................... 63

3.1.3 Register Configuration............................................................................................ 66

3.1.4 Caution.................................................................................................................... 66

3.2 Register Descriptions ...........................................................................................................67

3.3 Address Space ...................................................................................................................... 71

3.3.1 Physical Address Space .......................................................................................... 71

3.3.2 External Memory Space.......................................................................................... 74

3.3.3 Virtual Address Space............................................................................................. 75

3.3.4 On-Chip RAM Space.............................................................................................. 76

3.3.5 Address Translation ................................................................................................ 76

3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode ......................77

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3.3.7 Address Space Identifier (ASID)............................................................................ 77

3.4 TLB Functions ..................................................................................................................... 78

3.4.1 Unified TLB (UTLB) Configuration ...................................................................... 78

3.4.2 Instruction TLB (ITLB) Configuration................................................................... 82

3.4.3 Address Translation Method................................................................................... 82

3.5 MMU Functions...................................................................................................................85

3.5.1 MMU Hardware Management................................................................................ 85

3.5.2 MMU Software Management ................................................................................. 85

3.5.3 MMU Instruction (LDTLB).................................................................................... 85

3.5.4 Hardware ITLB Miss Handling .............................................................................. 86

3.5.5 Avoiding Synonym Problems................................................................................. 87

3.6 MMU Exceptions................................................................................................................. 88

3.6.1 Instruction TLB Multiple Hit Exception................................................................. 88

3.6.2 Instruction TLB Miss Exception............................................................................. 88

3.6.3 Instruction TLB Protection Violation Exception.................................................... 89

3.6.4 Data TLB Multiple Hit Exception .......................................................................... 90

3.6.5 Data TLB Miss Exception ...................................................................................... 91

3.6.6 Data TLB Protection Violation Exception.............................................................. 92

3.6.7 Initial Page Write Exception................................................................................... 93

3.7 Memory-Mapped TLB Configuration ................................................................................. 94

3.7.1 ITLB Address Array ............................................................................................... 94

3.7.2 ITLB Data Array 1.................................................................................................. 95

3.7.3 ITLB Data Array 2.................................................................................................. 96

3.7.4 UTLB Address Array.............................................................................................. 97

3.7.5 UTLB Data Array 1 ................................................................................................ 98

3.7.6 UTLB Data Array 2 ................................................................................................ 99

3.8 Usage Notes ....................................................................................................................... 100

Section 4 Caches................................................................................................101

4.1 Overview............................................................................................................................ 101

4.1.1 Features................................................................................................................. 101

4.1.2 Register Configuration.......................................................................................... 102

4.2 Register Descriptions ......................................................................................................... 103

4.3 Operand Cache (OC) ......................................................................................................... 105

4.3.1 Configuration........................................................................................................ 105

4.3.2 Read Operation ..................................................................................................... 108

4.3.3 Write Operation .................................................................................................... 109

4.3.4 Write-Back Buffer ................................................................................................ 111

4.3.5 Write-Through Buffer........................................................................................... 111

4.3.6 RAM Mode........................................................................................................... 111

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4.3.7 OC Index Mode .................................................................................................... 113

4.3.8 Coherency between Cache and External Memory................................................ 113

4.3.9 Prefetch Operation ................................................................................................ 113

4.3.10 Notes on Using OC RAM Mode (SH7751R Only) when in Cache Enhanced

Mode..................................................................................................................... 114

4.4 Instruction Cache (IC)........................................................................................................ 116

4.4.1 Configuration........................................................................................................ 116

4.4.2 Read Operation ..................................................................................................... 119

4.4.3 IC Index Mode...................................................................................................... 120

4.5 Memory-Mapped Cache Configuration (SH7751)............................................................. 120

4.5.1 IC Address Array.................................................................................................. 120

4.5.2 IC Data Array........................................................................................................ 122

4.5.3 OC Address Array ................................................................................................ 123

4.5.4 OC Data Array...................................................................................................... 124

4.6 Memory-Mapped Cache Configuration (SH7751R) .......................................................... 125

4.6.1 IC Address Array.................................................................................................. 125

4.6.2 IC Data Array........................................................................................................ 127

4.6.3 OC Address Array ................................................................................................ 128

4.6.4 OC Data Array...................................................................................................... 129

4.6.5 Summary of Memory-Mapped OC Addresses...................................................... 130

4.7 Store Queues ...................................................................................................................... 131

4.7.1 SQ Configuration.................................................................................................. 131

4.7.2 SQ Writes.............................................................................................................. 131

4.7.3 Transfer to External Memory................................................................................ 132

4.7.4 Determination of SQ Access Exception................................................................ 133

4.7.5 SQ Read (SH7751R only)..................................................................................... 133

4.7.6 SQ Usage Notes (SH7751 Only) .......................................................................... 134

Section 5 Exceptions..........................................................................................137

5.1 Overview............................................................................................................................ 137

5.1.1 Features................................................................................................................. 137

5.1.2 Register Configuration.......................................................................................... 137

5.2 Register Descriptions ......................................................................................................... 138

5.3 Exception Handling Functions ........................................................................................... 139

5.3.1 Exception Handling Flow ..................................................................................... 139

5.3.2 Exception Handling Vector Addresses ................................................................. 139

5.4 Exception Types and Priorities .......................................................................................... 140

5.5 Exception Flow ..................................................................................................................143

5.5.1 Exception Flow..................................................................................................... 143

5.5.2 Exception Source Acceptance............................................................................... 144

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5.5.3 Exception Requests and BL Bit ............................................................................ 146

5.5.4 Return from Exception Handling.......................................................................... 146

5.6 Description of Exceptions.................................................................................................. 146

5.6.1 Resets.................................................................................................................... 147

5.6.2 General Exceptions............................................................................................... 152

5.6.3 Interrupts............................................................................................................... 166

5.6.4 Priority Order with Multiple Exceptions .............................................................. 169

5.7 Usage Notes ....................................................................................................................... 170

5.8 Restrictions ........................................................................................................................ 171

Section 6 Floating-Point Unit............................................................................173

6.1 Overview............................................................................................................................ 173

6.2 Data Formats...................................................................................................................... 173

6.2.1 Floating-Point Format........................................................................................... 173

6.2.2 Non-Numbers (NaN) ............................................................................................ 175

6.2.3 Denormalized Numbers ........................................................................................ 176

6.3 Registers ............................................................................................................................ 177

6.3.1 Floating-Point Registers ....................................................................................... 177

6.3.2 Floating-Point Status/Control Register (FPSCR) ................................................. 179

6.3.3 Floating-Point Communication Register (FPUL)................................................. 180

6.4 Rounding............................................................................................................................ 181

6.5 Floating-Point Exceptions.................................................................................................. 181

6.6 Graphics Support Functions............................................................................................... 183

6.6.1 Geometric Operation Instructions......................................................................... 183

6.6.2 Pair Single-Precision Data Transfer...................................................................... 184

6.7 Usage Notes ....................................................................................................................... 185

6.7.1 Rounding Mode and Underflow Flag ................................................................... 185

6.7.2 Setting of Overflow Flag by FIPR or FTRV Instruction ...................................... 186

6.7.3 Sign of Operation Result when Using FIPR or FTRV Instruction ....................... 187

6.7.4 Notes on Double-Precision FADD and FSUB Instructions.................................. 187

Section 7 Instruction Set.................................................................................... 189

7.1 Execution Environment ..................................................................................................... 189

7.2 Addressing Modes ............................................................................................................. 191

7.3 Instruction Set .................................................................................................................... 195

7.4 Usage Notes ....................................................................................................................... 207

7.4.1 Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction

(H'FFFD) .............................................................................................................. 207

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Section 8 Pipelining ...........................................................................................211

8.1 Pipelines............................................................................................................................. 211

8.2 Parallel-Executability ......................................................................................................... 218

8.3 Execution Cycles and Pipeline Stalling ............................................................................. 222

8.4 Usage Notes ....................................................................................................................... 238

Section 9 Power-Down Modes ..........................................................................239

9.1 Overview............................................................................................................................ 239

9.1.1 Types of Power-Down Modes .............................................................................. 239

9.1.2 Register Configuration.......................................................................................... 241

9.1.3 Pin Configuration.................................................................................................. 241

9.2 Register Descriptions ......................................................................................................... 242

9.2.1 Standby Control Register (STBCR)...................................................................... 242

9.2.2 Peripheral Module Pin High Impedance Control.................................................. 244

9.2.3 Peripheral Module Pin Pull-Up Control................................................................ 244

9.2.4 Standby Control Register 2 (STBCR2)................................................................. 245

9.2.5 Clock Stop Register 00 (CLKSTP00)................................................................... 246

9.2.6 Clock Stop Clear Register 00 (CLKSTPCLR00).................................................. 247

9.3 Sleep Mode ........................................................................................................................ 248

9.3.1 Transition to Sleep Mode...................................................................................... 248

9.3.2 Exit from Sleep Mode........................................................................................... 248

9.4 Deep Sleep Mode ............................................................................................................... 248

9.4.1 Transition to Deep Sleep Mode ............................................................................248

9.4.2 Exit from Deep Sleep Mode ................................................................................. 249

9.5 Pin Sleep Mode ..................................................................................................................249

9.5.1 Transition to Pin Sleep Mode ............................................................................... 249

9.5.2 Exit from Pin Sleep Mode..................................................................................... 249

9.6 Standby Mode ....................................................................................................................249

9.6.1 Transition to Standby Mode.................................................................................. 249

9.6.2 Exit from Standby Mode....................................................................................... 250

9.6.3 Clock Pause Function ........................................................................................... 251

9.7 Module Standby Function .................................................................................................. 251

9.7.1 Transition to Module Standby Function ............................................................... 251

9.7.2 Exit from Module Standby Function .................................................................... 252

9.8 Hardware Standby Mode ................................................................................................... 253

9.8.1 Transition to Hardware Standby Mode................................................................. 253

9.8.2 Exit from Hardware Standby Mode...................................................................... 253

9.8.3 Usage Notes .......................................................................................................... 254

9.9 STATUS Pin Change Timing ............................................................................................ 254

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9.9.1 In Reset ................................................................................................................. 255

9.9.2 In Exit from Standby Mode .................................................................................. 256

9.9.3 In Exit from Sleep Mode ...................................................................................... 257

9.9.4 In Exit from Deep Sleep Mode ............................................................................. 260

9.9.5 Hardware Standby Mode Timing.......................................................................... 262

9.10 Usage Notes ....................................................................................................................... 264

9.10.1 Note on Current Consumption .............................................................................. 264

Section 10 Clock Oscillation Circuits ...............................................................267

10.1 Overview............................................................................................................................ 267

10.1.1 Features................................................................................................................. 267

10.2 Overview of CPG............................................................................................................... 269

10.2.1 Block Diagram of CPG......................................................................................... 269

10.2.2 CPG Pin Configuration ......................................................................................... 272

10.2.3 CPG Register Configuration ................................................................................. 272

10.3 Clock Operating Modes ..................................................................................................... 273

10.4 CPG Register Description.................................................................................................. 275

10.4.1 Frequency Control Register (FRQCR) ................................................................. 275

10.5 Changing the Frequency .................................................................................................... 278

10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off) ............ 278

10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)............. 278

10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On) ....................... 279

10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off) ...................... 279

10.5.5 Changing CPU or Peripheral Module Clock Division Ratio ................................ 279

10.6 Output Clock Control......................................................................................................... 280

10.7 Overview of Watchdog Timer ........................................................................................... 280

10.7.1 Block Diagram...................................................................................................... 280

10.7.2 Register Configuration.......................................................................................... 281

10.8 WDT Register Descriptions............................................................................................... 281

10.8.1 Watchdog Timer Counter (WTCNT).................................................................... 281

10.8.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 282

10.8.3 Notes on Register Access ..................................................................................... 284

10.9 Using the WDT.................................................................................................................. 285

10.9.1 Standby Clearing Procedure ................................................................................. 285

10.9.2 Frequency Changing Procedure............................................................................ 285

10.9.3 Using Watchdog Timer Mode .............................................................................. 286

10.9.4 Using Interval Timer Mode .................................................................................. 286

10.10 Notes on Board Design ...................................................................................................... 287

10.11 Usage Notes ....................................................................................................................... 289

10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7751 Only)................. 289

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Section 11 Realtime Clock (RTC) .....................................................................291

11.1 Overview............................................................................................................................ 291

11.1.1 Features................................................................................................................. 291

11.1.2 Block Diagram ...................................................................................................... 292

11.1.3 Pin Configuration.................................................................................................. 293

11.1.4 11.1.4 Register Configuration ............................................................................... 293

11.2 Register Descriptions......................................................................................................... 295

11.2.1 64 Hz Counter (R64CNT)..................................................................................... 295

11.2.2 Second Counter (RSECCNT) ............................................................................... 296

11.2.3 Minute Counter (RMINCNT) ............................................................................... 296

11.2.4 Hour Counter (RHRCNT)..................................................................................... 297

11.2.5 Day-of-Week Counter (RWKCNT)...................................................................... 297

11.2.6 Day Counter (RDAYCNT) ................................................................................... 298

11.2.7 Month Counter (RMONCNT) .............................................................................. 298

11.2.8 Year Counter (RYRCNT) ..................................................................................... 299

11.2.9 Second Alarm Register (RSECAR) ...................................................................... 300

11.2.10 Minute Alarm Register (RMINAR)...................................................................... 300

11.2.11 Hour Alarm Register (RHRAR) ........................................................................... 301

11.2.12 Day-of-Week Alarm Register (RWKAR)............................................................. 301

11.2.13 Day Alarm Register (RDAYAR).......................................................................... 302

11.2.14 Month Alarm Register (RMONAR) ..................................................................... 303

11.2.15 RTC Control Register 1 (RCR1)........................................................................... 303

11.2.16 RTC Control Register 2 (RCR2)........................................................................... 305

11.2.17 RTC Control Register (RCR3) and Year-Alarm Register (RYRAR)

(SH7751R Only)................................................................................................... 308

11.3 Operation ........................................................................................................................... 309

11.3.1 Time Setting Procedures ....................................................................................... 309

11.3.2 Time Reading Procedures ..................................................................................... 311

11.3.3 Alarm Function ..................................................................................................... 312

11.4 Interrupts............................................................................................................................ 313

11.5 Usage Notes ....................................................................................................................... 313

11.5.1 Register Initialization............................................................................................ 313

11.5.2 Carry Flag and Interrupt Flag in Standby Mode ...................................................313

11.5.3 Crystal Oscillation Circuit .................................................................................... 313

Section 12 Timer Unit (TMU) ...........................................................................315

12.1 Overview............................................................................................................................ 315

12.1.1 Features................................................................................................................. 315

12.1.2 Block Diagram ...................................................................................................... 316

12.1.3 Pin Configuration.................................................................................................. 316

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12.1.4 Register Configuration.......................................................................................... 317

12.2 Register Descriptions......................................................................................................... 318

12.2.1 Timer Output Control Register (TOCR) ............................................................... 318

12.2.2 Timer Start Register (TSTR) ................................................................................ 319

12.2.3 Timer Start Register 2 (TSTR2) ........................................................................... 320

12.2.4 Timer Constant Registers (TCOR) ....................................................................... 321

12.2.5 Timer Counters (TCNT) ....................................................................................... 321

12.2.6 Timer Control Registers (TCR) ............................................................................ 322

12.2.7 Input Capture Register 2 (TCPR2) ....................................................................... 326

12.3 Operation ........................................................................................................................... 327

12.3.1 Counter Operation ................................................................................................ 327

12.3.2 Input Capture Function ......................................................................................... 330

12.4 Interrupts............................................................................................................................ 332

12.5 Usage Notes ....................................................................................................................... 332

12.5.1 Register Writes ..................................................................................................... 332

12.5.2 TCNT Register Reads ........................................................................................... 333

12.5.3 Resetting the RTC Frequency Divider.................................................................. 333

12.5.4 External Clock Frequency .................................................................................... 333

Section 13 Bus State Controller (BSC) ............................................................. 335

13.1 Overview............................................................................................................................ 335

13.1.1 Features................................................................................................................. 335

13.1.2 Block Diagram...................................................................................................... 337

13.1.3 Pin Configuration.................................................................................................. 338

13.1.4 Register Configuration.......................................................................................... 340

13.1.5 Overview of Areas ................................................................................................ 341

13.1.6 PCMCIA Support ................................................................................................. 344

13.2 Register Descriptions......................................................................................................... 348

13.2.1 Bus Control Register 1 (BCR1) ............................................................................ 348

13.2.2 Bus Control Register 2 (BCR2) ............................................................................ 357

13.2.3 Bus Control Register 3 (BCR3) (SH7751R Only)................................................ 359

13.2.4 Bus Control Register 4 (BCR4) (SH7751R Only)................................................ 361

13.2.5 Wait Control Register 1 (WCR1) ......................................................................... 363

13.2.6 Wait Control Register 2 (WCR2) ......................................................................... 366

13.2.7 Wait Control Register 3 (WCR3) ......................................................................... 374

13.2.8 Memory Control Register (MCR)......................................................................... 376

13.2.9 PCMCIA Control Register (PCR) ........................................................................ 383

13.2.10 Synchronous DRAM Mode Register (SDMR) ..................................................... 386

13.2.11 Refresh Timer Control/Status Register (RTCSR)................................................. 388

13.2.12 Refresh Timer Counter (RTCNT)......................................................................... 390

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13.2.13 Refresh Time Constant Register (RTCOR) .......................................................... 391

13.2.14 Refresh Count Register (RFCR) ........................................................................... 392

13.2.15 Notes on Accessing Refresh Control Registers .................................................... 392

13.3 Operation ........................................................................................................................... 393

13.3.1 Endian/Access Size and Data Alignment.............................................................. 393

13.3.2 Areas ..................................................................................................................... 400

13.3.3 SRAM Interface .................................................................................................... 405

13.3.4 DRAM Interface ................................................................................................... 413

13.3.5 Synchronous DRAM Interface ............................................................................. 427

13.3.6 Burst ROM Interface ............................................................................................ 457

13.3.7 PCMCIA Interface ................................................................................................ 460

13.3.8 MPX Interface....................................................................................................... 471

13.3.9 Byte Control SRAM Interface .............................................................................. 485

13.3.10 Waits between Access Cycles............................................................................... 489

13.3.11 Bus Arbitration ..................................................................................................... 490

13.3.12 Master Mode......................................................................................................... 493

13.3.13 Slave Mode ........................................................................................................... 494

13.3.14 Cooperation between Master and Slave................................................................ 495

13.3.15 Notes on Usage ..................................................................................................... 495

Section 14 Direct Memory Access Controller (DMAC) ...................................497

14.1 Overview............................................................................................................................ 497

14.1.1 Features................................................................................................................. 497

14.1.2 Block Diagram (SH7751) ..................................................................................... 500

14.1.3 Pin Configuration (SH7751) ................................................................................. 501

14.1.4 Register Configuration (SH7751) .........................................................................502

14.2 Register Descriptions......................................................................................................... 504

14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) ........................................... 504

14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)................................... 505

14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3).......................... 506

14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3).................................... 507

14.2.5 DMA Operation Register (DMAOR) ................................................................... 515

14.3 Operation ........................................................................................................................... 517

14.3.1 DMA Transfer Procedure ..................................................................................... 517

14.3.2 DMA Transfer Requests ....................................................................................... 520

14.3.3 Channel Priorities ................................................................................................. 523

14.3.4 Types of DMA Transfer........................................................................................ 526

14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 535

14.3.6 Ending DMA Transfer .......................................................................................... 549

14.4 Examples of Use ................................................................................................................ 552

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14.4.1 Examples of Transfer between External Memory and an External Device

with DACK........................................................................................................... 552

14.5 On-Demand Data Transfer Mode (DDT Mode) ................................................................ 553

14.5.1 Operation .............................................................................................................. 553

14.5.2 Pins in DDT Mode................................................................................................ 555

14.5.3 Transfer Request Acceptance on Each Channel ................................................... 558

14.5.4 Notes on Use of DDT Module .............................................................................. 580

14.6 Configuration of the DMAC (SH7751R)........................................................................... 583

14.6.1 Block Diagram of the DMAC............................................................................... 583

14.6.2 Pin Configuration (SH7751R) .............................................................................. 584

14.6.3 Register Configuration (SH7751R) ...................................................................... 585

14.7 Register Descriptions (SH7751R)...................................................................................... 588

14.7.1 DMA Source Address Registers 0−7 (SAR0−SAR7)........................................... 588

14.7.2 DMA Destination Address Registers 0−7 (DAR0−DAR7) .................................. 588

14.7.3 DMA Transfer Count Registers 0−7 (DMATCR0−DMATCR7) ......................... 589

14.7.4 DMA Channel Control Registers 0−7 (CHCR0−CHCR7) ................................... 589

14.7.5 DMA Operation Register (DMAOR) ................................................................... 593

14.8 Operation (SH7751R) ........................................................................................................ 595

14.8.1 Channel Specification for a Normal DMA Transfer............................................. 595

14.8.2 Channel Specification for DDT-Mode DMA Transfer ......................................... 595

14.8.3 Transfer Channel Notification in DDT Mode....................................................... 596

14.8.4 Clearing Request Queues by DTR Format ........................................................... 597

14.8.5 Interrupt-Request Codes ....................................................................................... 597

14.9 Usage Notes ....................................................................................................................... 600

Section 15 Serial Communication Interface (SCI)............................................603

15.1 Overview............................................................................................................................ 603

15.1.1 Features................................................................................................................. 603

15.1.2 Block Diagram...................................................................................................... 605

15.1.3 Pin Configuration.................................................................................................. 606

15.1.4 Register Configuration.......................................................................................... 606

15.2 Register Descriptions......................................................................................................... 607

15.2.1 Receive Shift Register (SCRSR1) ........................................................................ 607

15.2.2 Receive Data Register (SCRDR1) ........................................................................ 607

15.2.3 Transmit Shift Register (SCTSR1) ....................................................................... 608

15.2.4 Transmit Data Register (SCTDR1)....................................................................... 608

15.2.5 Serial Mode Register (SCSMR1).......................................................................... 609

15.2.6 Serial Control Register (SCSCR1)........................................................................ 611

15.2.7 Serial Status Register (SCSSR1) .......................................................................... 615

15.2.8 Serial Port Register (SCSPTR1) ........................................................................... 619

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15.2.9 Bit Rate Register (SCBRR1) ................................................................................ 623

15.3 Operation ........................................................................................................................... 631

15.3.1 Overview............................................................................................................... 631

15.3.2 Operation in Asynchronous Mode ........................................................................633

15.3.3 Multiprocessor Communication Function............................................................. 644

15.3.4 Operation in Synchronous Mode .......................................................................... 655

15.4 SCI Interrupt Sources and DMAC ..................................................................................... 665

15.5 Usage Notes ....................................................................................................................... 666

Section 16 Serial Communication Interface with FIFO (SCIF) ........................671

16.1 Overview............................................................................................................................ 671

16.1.1 Features................................................................................................................. 671

16.1.2 Block Diagram ...................................................................................................... 673

16.1.3 Pin Configuration.................................................................................................. 674

16.1.4 Register Configuration.......................................................................................... 674

16.2 Register Descriptions......................................................................................................... 675

16.2.1 Receive Shift Register (SCRSR2)......................................................................... 675

16.2.2 Receive FIFO Data Register (SCFRDR2) ............................................................ 675

16.2.3 Transmit Shift Register (SCTSR2) ....................................................................... 676

16.2.4 Transmit FIFO Data Register (SCFTDR2) ........................................................... 676

16.2.5 Serial Mode Register (SCSMR2).......................................................................... 677

16.2.6 Serial Control Register (SCSCR2)........................................................................ 679

16.2.7 Serial Status Register (SCFSR2) .......................................................................... 682

16.2.8 Bit Rate Register (SCBRR2) ................................................................................ 688

16.2.9 FIFO Control Register (SCFCR2) ........................................................................ 689

16.2.10 FIFO Data Count Register (SCFDR2).................................................................. 692

16.2.11 Serial Port Register (SCSPTR2) ........................................................................... 693

16.2.12 Line Status Register (SCLSR2) ............................................................................ 700

16.3 Operation ........................................................................................................................... 701

16.3.1 Overview............................................................................................................... 701

16.3.2 Serial Operation ....................................................................................................703

16.4 SCIF Interrupt Sources and the DMAC............................................................................. 713

16.5 Usage Notes ....................................................................................................................... 714

Section 17 Smart Card Interface........................................................................719

17.1 Overview............................................................................................................................ 719

17.1.1 Features................................................................................................................. 719

17.1.2 Block Diagram ...................................................................................................... 720

17.1.3 Pin Configuration.................................................................................................. 721

17.1.4 Register Configuration.......................................................................................... 721

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17.2 Register Descriptions......................................................................................................... 722

17.2.1 Smart Card Mode Register (SCSCMR1) .............................................................. 722

17.2.2 Serial Mode Register (SCSMR1).......................................................................... 723

17.2.3 Serial Control Register (SCSCR1)........................................................................ 724

17.2.4 Serial Status Register (SCSSR1) .......................................................................... 725

17.3 Operation ........................................................................................................................... 726

17.3.1 Overview .............................................................................................................. 726

17.3.2 Pin Connections .................................................................................................... 727

17.3.3 Data Format .......................................................................................................... 728

17.3.4 Register Settings ................................................................................................... 729

17.3.5 Clock..................................................................................................................... 731

17.3.6 Data Transfer Operations...................................................................................... 734

17.4 Usage Notes ....................................................................................................................... 741

Section 18 I/O Ports...........................................................................................747

18.1 Overview............................................................................................................................ 747

18.1.1 Features................................................................................................................. 747

18.1.2 Block Diagrams .................................................................................................... 748

18.1.3 Pin Configuration.................................................................................................. 755

18.1.4 Register Configuration.......................................................................................... 758

18.2 Register Descriptions......................................................................................................... 759

18.2.1 Port Control Register A (PCTRA) ........................................................................ 759

18.2.2 Port Data Register A (PDTRA) ............................................................................ 760

18.2.3 Port Control Register B (PCTRB) ........................................................................ 761

18.2.4 Port Data Register B (PDTRB)............................................................................. 762

18.2.5 GPIO Interrupt Control Register (GPIOIC).......................................................... 763

18.2.6 Serial Port Register (SCSPTR1) ........................................................................... 764

18.2.7 Serial Port Register (SCSPTR2) ........................................................................... 766

Section 19 Interrupt Controller (INTC)............................................................. 769

19.1 Overview............................................................................................................................ 769

19.1.1 Features................................................................................................................. 769

19.1.2 Block Diagram...................................................................................................... 769

19.1.3 Pin Configuration.................................................................................................. 771

19.1.4 Register Configuration.......................................................................................... 771

19.2 Interrupt Sources................................................................................................................ 772

19.2.1 NMI Interrupt........................................................................................................ 772

19.2.2 IRL Interrupts ....................................................................................................... 773

19.2.3 On-Chip Peripheral Module Interrupts ................................................................. 775

19.2.4 Interrupt Exception Handling and Priority............................................................ 776

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19.3 Register Descriptions......................................................................................................... 780

19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) ................................................ 780

19.3.2 Interrupt Control Register (ICR)........................................................................... 781

19.3.3 Interrupt Priority Level Settting Register 00 (INTPRI00) .................................... 783

19.3.4 Interrupt Factor Register 00 (INTREQ00)............................................................ 784

19.3.5 Interrupt Mask Register 00 (INTMSK00)............................................................. 784

19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) ...........................................785

19.3.7 INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation ........................... 786

19.4 INTC Operation ................................................................................................................. 787

19.4.1 Interrupt Operation Sequence ............................................................................... 787

19.4.2 Multiple Interrupts ................................................................................................789

19.4.3 Interrupt Masking with MAI Bit........................................................................... 789

19.5 Interrupt Response Time.................................................................................................... 790

19.6 Usage Notes ....................................................................................................................... 791

19.6.1 NMI Interrupts (SH7751 Only)............................................................................. 791

Section 20 User Break Controller (UBC) ..........................................................795

20.1 Overview............................................................................................................................ 795

20.1.1 Features................................................................................................................. 795

20.1.2 Block Diagram ...................................................................................................... 796

20.2 Register Descriptions......................................................................................................... 798

20.2.1 Access to UBC Registers ...................................................................................... 798

20.2.2 Break Address Register A (BARA) ...................................................................... 799

20.2.3 Break ASID Register A (BASRA)........................................................................ 800

20.2.4 Break Address Mask Register A (BAMRA)......................................................... 800

20.2.5 Break Bus Cycle Register A (BBRA)................................................................... 801

20.2.6 Break Address Register B (BARB) ...................................................................... 803

20.2.7 Break ASID Register B (BASRB) ........................................................................ 803

20.2.8 Break Address Mask Register B (BAMRB) ......................................................... 803

20.2.9 Break Data Register B (BDRB) ............................................................................ 803

20.2.10 Break Data Mask Register B (BDMRB)............................................................... 804

20.2.11 Break Bus Cycle Register B (BBRB) ................................................................... 805

20.2.12 Break Control Register (BRCR) ........................................................................... 805

20.3 Operation ........................................................................................................................... 808

20.3.1 Explanation of Terms Relating to Accesses.......................................................... 808

20.3.2 Explanation of Terms Relating to Instruction Intervals ........................................ 808

20.3.3 User Break Operation Sequence ...........................................................................809

20.3.4 Instruction Access Cycle Break ............................................................................ 810

20.3.5 Operand Access Cycle Break................................................................................ 811

20.3.6 Condition Match Flag Setting ............................................................................... 812

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20.3.7 Program Counter (PC) Value Saved ..................................................................... 812

20.3.8 Contiguous A and B Settings for Sequential Conditions ...................................... 813

20.3.9 Usage Notes .......................................................................................................... 814

20.4 User Break Debug Support Function................................................................................. 816

20.5 Examples of Use ................................................................................................................ 818

20.6 User Break Controller Stop Function................................................................................. 820

20.6.1 Transition to User Break Controller Stopped State............................................... 820

20.6.2 Cancelling the User Break Controller Stopped State............................................ 820

20.6.3 Examples of Stopping and Restarting the User Break Controller......................... 821

Section 21 High-performance User Debug Interface (H-UDI) ........................823

21.1 Overview............................................................................................................................ 823

21.1.1 Features................................................................................................................. 823

21.1.2 Block Diagram...................................................................................................... 823

21.1.3 Pin Configuration.................................................................................................. 825

21.1.4 Register Configuration.......................................................................................... 826

21.2 Register Descriptions......................................................................................................... 827

21.2.1 Instruction Register (SDIR) .................................................................................. 827

21.2.2 Data Register (SDDR) .......................................................................................... 828

21.2.3 Bypass Register (SDBPR) .................................................................................... 828

21.2.4 Interrupt Factor Register (SDINT)........................................................................ 829

21.2.5 Boundary Scan Register (SDBSR) ....................................................................... 829

21.3 Operation ........................................................................................................................... 843

21.3.1 TAP Control ......................................................................................................... 843

21.3.2 H-UDI Reset ......................................................................................................... 844

21.3.3 H-UDI Interrupt .................................................................................................... 844

21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) ............................. 845

21.4 Usage Notes ....................................................................................................................... 845

Section 22 PCI Controller (PCIC)..................................................................... 847

22.1 Overview............................................................................................................................ 847

22.1.1 Features................................................................................................................. 847

22.1.2 Block Diagram...................................................................................................... 848

22.1.3 Pin Configuration.................................................................................................. 849

22.1.4 Register Configuration.......................................................................................... 850

22.2 PCIC Register Descriptions ............................................................................................... 856

22.2.1 PCI Configuration Register 0 (PCICONF0) ......................................................... 856

22.2.2 PCI Configuration Register 1 (PCICONF1) ......................................................... 857

22.2.3 PCI Configuration Register 2 (PCICONF2) ......................................................... 863

22.2.4 PCI Configuration Register 3 (PCICONF3) ......................................................... 865

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22.2.5 PCI Configuration Register 4 (PCICONF4) ......................................................... 867

22.2.6 PCI Configuration Register 5 (PCICONF5) ......................................................... 869

22.2.7 PCI Configuration Register 6 (PCICONF6) ......................................................... 871

22.2.8 PCI Configuration Register 7 (PCICONF7) to PCI Configuration Register 10

(PCICONF10)....................................................................................................... 873

22.2.9 PCI Configuration Register 11 (PCICONF11) ..................................................... 874

22.2.10 PCI Configuration Register 12 (PCICONF12) ..................................................... 875

22.2.11 PCI Configuration Register 13 (PCICONF13) ..................................................... 875

22.2.12 PCI Configuration Register 14 (PCICONF14) ..................................................... 876

22.2.13 PCI Configuration Register 15 (PCICONF15) ..................................................... 877

22.2.14 PCI Configuration Register 16 (PCICONF16) ..................................................... 879

22.2.15 PCI Configuration Register 17 (PCICONF17) ..................................................... 881

22.2.16 Reserved Area....................................................................................................... 883

22.2.17 PCI Control Register (PCICR).............................................................................. 884

22.2.18 PCI Local Space Register [1:0] (PCILSR [1:0])................................................... 888

22.2.19 PCI Local Address Register [1:0] (PCILAR [1:0])............................................... 890

22.2.20 PCI Interrupt Register (PCIINT)........................................................................... 892

22.2.21 PCI Interrupt Mask Register (PCIINTM) ............................................................. 895

22.2.22 PCI Address Data Register at Error (PCIALR) ....................................................897

22.2.23 PCI Command Data Register at Error (PCICLR)................................................. 898

22.2.24 PCI Arbiter Interrupt Register (PCIAINT) ........................................................... 900

22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM).............................................. 902

22.2.26 PCI Error Bus Master Data Register (PCIBMLR)................................................ 903

22.2.27 PCI DMA Transfer Arbitration Register (PCIDMABT) ...................................... 904

22.2.28 PCI DMA Transfer PCI Address Register [3:0] (PCIDPA [3:0])......................... 905

22.2.29 PCI DMA Transfer Local Bus Start Address Register [3:0] (PCIDLA [3:0]) ...... 907

22.2.30 PCI DMA Transfer Counter Register [3:0] (PCIDTC [3:0]) ................................ 908

22.2.31 PCI DMA Control Register [3:0] (PCIDCR [3:0])............................................... 910

22.2.32 PIO Address Register (PCIPAR).......................................................................... 913

22.2.33 Memory Space Base Register (PCIMBR)............................................................. 915

22.2.34 I/O Space Base Register (PCIIOBR) .................................................................... 917

22.2.35 PCI Power Management Interrupt Register (PCIPINT) .......................................918

22.2.36 PCI Power Management Interrupt Mask Register (PCIPINTM).......................... 919

22.2.37 PCI Clock Control Register (PCICLKR).............................................................. 920

22.2.38 PCIC-BSC Registers............................................................................................. 921

22.2.39 Port Control Register (PCIPCTR)......................................................................... 923

22.2.40 Port Data Register (PCIPDTR)............................................................................. 926

22.2.41 PIO Data Register (PCIPDR)................................................................................ 927

22.3 Description of Operation.................................................................................................... 928

22.3.1 Operating Modes................................................................................................... 928

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22.3.2 PCI Commands ..................................................................................................... 929

22.3.3 PCIC Initialization ................................................................................................ 930

22.3.4 Local Register Access........................................................................................... 931

22.3.5 Host Functions ...................................................................................................... 931

22.3.6 PCI Bus Arbitration in Non-host Mode ................................................................ 934

22.3.7 PIO Transfers........................................................................................................ 934

22.3.8 Target Transfers.................................................................................................... 937

22.3.9 DMA Transfers ..................................................................................................... 940

22.3.10 Transfer Contention within PCIC......................................................................... 946

22.3.11 PCI Bus Basic Interface........................................................................................ 947

22.4 Endians .............................................................................................................................. 959

22.4.1 Internal Bus (Peripheral Bus) Interface for Peripheral Modules........................... 959

22.4.2 Endian Control for Local Bus............................................................................... 961

22.4.3 Endian Control in DMA Transfers ....................................................................... 961

22.4.4 Endian Control in Target Transfers (Memory Read/Memory Write) ................... 963

22.4.5 Endian Control in Target Transfers (I/O Read/I/O Write).................................... 966

22.4.6 Endian Control in Target Transfers

(Configuration Read/Configuration Write)........................................................... 966

22.5 Resetting ............................................................................................................................ 968

22.6 Interrupts............................................................................................................................ 969

22.6.1 Interrupts from PCIC to CPU ............................................................................... 969

22.6.2 Interrupts from External PCI Devices................................................................... 970

22.6.3 INTA..................................................................................................................... 971

22.7 Error Detection .................................................................................................................. 971

22.8 PCIC Clock........................................................................................................................ 971

22.9 Power Management ........................................................................................................... 972

22.9.1 Power Management Overview.............................................................................. 972

22.9.2 Stopping the Clock ............................................................................................... 973

22.9.3 Compatibility with Standby and Sleep ................................................................. 976

22.10 Port Functions .................................................................................................................... 976

22.11 Version Management ......................................................................................................... 977

22.12 Usage Notes ....................................................................................................................... 977

22.12.1 Notes on Arbiter Interrupt Usage (SH7751 Only) ................................................ 977

22.12.2 Notes on I/O Read and I/O Write Commands (SH7751 Only)............................. 980

22.12.3 Notes on Configuration-Read and Configuration-Write Commands

(SH7751 Only)...................................................................................................... 980

22.12.4 Notes on Target Read/Write Cycle Timing (SH7751 Only)................................. 980

22.12.5 Notes on Parity Error Detection during Master Access........................................ 980

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Section 23 Electrical Characteristics .................................................................983

23.1 Absolute Maximum Ratings .............................................................................................. 983

23.2 DC Characteristics ............................................................................................................. 984

23.3 AC Characteristics ............................................................................................................. 996

23.3.1 Clock and Control Signal Timing ......................................................................... 998

23.3.2 Control Signal Timing ........................................................................................ 1012

23.3.3 Bus Timing ......................................................................................................... 1016

23.3.4 Peripheral Module Signal Timing....................................................................... 1067

23.3.5 AC Characteristic Test Conditions ..................................................................... 1081

23.3.6 Change in Delay Time Based on Load Capacitance ........................................... 1082

Appendix A Address List ................................................................................1083

Appendix B Package Dimensions....................................................................1091

Appendix C Mode Pin Settings .......................................................................1095

Appendix D Pin Functions...............................................................................1099

D.1 Pin States.......................................................................................................................... 1099

D.2 Handling of Unused Pins ................................................................................................. 1104

D.3 Note on Pin Processing .................................................................................................... 1105

Appendix E Synchronous DRAM Address Multiplexing Tables...................1107

Appendix F Instruction Prefetching and Its Side Effects.................................1119

Appendix G Power-On and Power-Off Procedures.........................................1121

G.1 Power-On Stipulations ..................................................................................................... 1121

G.2 Power-Off Stipulations .................................................................................................... 1121

G.3 Common Stipulations for Power-On and Power-Off....................................................... 1124

Appendix H Product Lineup ............................................................................1125

Appendix I Version Registers..........................................................................1127

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Figures

Section 1 Overview

Figure 1.1 Block Diagram of SH7751/SH7751R Group Functions ............................................. 9

Figure 1.2 Pin Arrangement (256-Pin QFP) ............................................................................... 10

Figure 1.3 Pin Arrangement (256-Pin BGA).............................................................................. 11

Figure 1.4 Pin Arrangement (292-Pin BGA).............................................................................. 12

Section 2 Programming Model

Figure 2.1 Data Formats ............................................................................................................. 47

Figure 2.2 CPU Register Configuration in Each Processor Mode.............................................. 50

Figure 2.3 General Registers ...................................................................................................... 52

Figure 2.4 Floating-Point Registers ............................................................................................ 54

Figure 2.5 Data Formats In Memory ..........................................................................................60

Figure 2.6 Processor State Transitions ....................................................................................... 61

Section 3 Memory Management Unit (MMU)

Figure 3.1 Role of the MMU ......................................................................................................65

Figure 3.2 MMU-Related Registers ........................................................................................... 67

Figure 3.3 Physical Address Space (MMUCR.AT = 0) ............................................................. 71

Figure 3.4 P4 Area...................................................................................................................... 72

Figure 3.5 External Memory Space ............................................................................................ 74

Figure 3.6 Virtual Address Space (MMUCR.AT = 1)................................................................ 75

Figure 3.7 UTLB Configuration ................................................................................................. 78

Figure 3.8 Relationship between Page Size and Address Format............................................... 79

Figure 3.9 ITLB Configuration...................................................................................................82

Figure 3.10 Flowchart of Memory Access Using UTLB ............................................................. 83

Figure 3.11 Flowchart of Memory Access Using ITLB............................................................... 84

Figure 3.12 Operation of LDTLB Instruction ..............................................................................86

Figure 3.13 Memory-Mapped ITLB Address Array..................................................................... 95

Figure 3.14 Memory-Mapped ITLB Data Array 1 ....................................................................... 96

Figure 3.15 Memory-Mapped ITLB Data Array 2 ....................................................................... 97

Figure 3.16 Memory-Mapped UTLB Address Array................................................................... 98

Figure 3.17 Memory-Mapped UTLB Data Array 1...................................................................... 99

Figure 3.18 Memory-Mapped UTLB Data Array 2.................................................................... 100

Section 4 Caches

Figure 4.1 Cache and Store Queue Control Registers (CCR)................................................... 103

Figure 4.2 Configuration of Operand Cache (SH7751)............................................................ 106

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Figure 4.3 Configuration of Operand Cache (SH7751R) ......................................................... 107

Figure 4.4 Configuration of Write-Back Buffer ....................................................................... 111

Figure 4.5 Configuration of Write-Through Buffer.................................................................. 111

Figure 4.6 Configuration of Instruction Cache (SH7751) ........................................................ 117

Figure 4.7 Configuration of Instruction Cache (SH7751R)...................................................... 118

Figure 4.8 Memory-Mapped IC Address Array ....................................................................... 121

Figure 4.9 Memory-Mapped IC Data Array ............................................................................. 122

Figure 4.10 Memory-Mapped OC Address Array...................................................................... 124

Figure 4.11 Memory-Mapped OC Data Array ........................................................................... 125

Figure 4.12 Memory-Mapped IC Address Array ....................................................................... 126

Figure 4.13 Memory-Mapped IC Data Array............................................................................. 127

Figure 4.14 Memory-Mapped OC Address Array...................................................................... 129

Figure 4.15 Memory-Mapped OC Data Array ........................................................................... 130

Figure 4.16 Store Queue Configuration...................................................................................... 131

Section 5 Exceptions

Figure 5.1 Register Bit Configurations..................................................................................... 138

Figure 5.2 Instruction Execution and Exception Handling....................................................... 143

Figure 5.3 Example of General Exception Acceptance Order.................................................. 145

Section 6 Floating-Point Unit

Figure 6.1 Format of Single-Precision Floating-Point Number................................................ 173

Figure 6.2 Format of Double-Precision Floating-Point Number .............................................. 174

Figure 6.3 Single-Precision NaN Bit Pattern............................................................................ 176

Figure 6.4 Floating-Point Registers .......................................................................................... 178

Section 8 Pipelining

Figure 8.1 Basic Pipelines ........................................................................................................ 212

Figure 8.2 Instruction Execution Patterns ................................................................................ 213

Figure 8.3 Examples of Pipelined Execution ........................................................................... 225

Section 9 Power-Down Modes

Figure 9.1 STATUS Output in Power-On Reset ...................................................................... 255

Figure 9.2 STATUS Output in Manual Reset .......................................................................... 255

Figure 9.3 STATUS Output in Standby → Interrupt Sequence ............................................... 256

Figure 9.4 STATUS Output in Standby → Power-On Reset Sequence................................... 256

Figure 9.5 STATUS Output in Standby → Manual Reset Sequence ....................................... 257

Figure 9.6 STATUS Output in Sleep → Interrupt Sequence.................................................... 257

Figure 9.7 STATUS Output in Sleep → Power-On Reset Sequence ....................................... 258

Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence............................................ 259

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Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence .......................................... 260

Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence .............................. 260

Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence .................................. 261

Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation)........... 262

Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation).............. 263

Figure 9.14 Timing When Power Other than VDD-RTC Is Off ................................................ 263

Figure 9.15 Timing When VDD-RTC Power Is Off → On........................................................ 264

Section 10 Clock Oscillation Circuits

Figure 10.1 (1) Block Diagram of CPG (SH7751) .................................................................... 269

Figure 10.1 (2) Block Diagram of CPG (SH7751R).................................................................. 270

Figure 10.2 Block Diagram of WDT.......................................................................................... 280

Figure 10.3 Writing to WTCNT and WTCSR............................................................................ 284

Figure 10.4 Points for Attention when Using Crystal Resonator ...............................................287

Figure 10.5 Points for Attention when Using PLL Oscillator Circuit ........................................ 288

Section 11 Realtime Clock (RTC)

Figure 11.1 Block Diagram of RTC ........................................................................................... 292

Figure 11.2 Examples of Time Setting Procedures .................................................................... 309

Figure 11.3 Examples of Time Reading Procedures .................................................................. 311

Figure 11.4 Example of Use of Alarm Function ........................................................................ 312

Figure 11.5 Example of Crystal Oscillation Circuit Connection................................................ 314

Section 12 Timer Unit (TMU)

Figure 12.1 Block Diagram of TMU.......................................................................................... 316

Figure 12.2 Example of Count Operation Setting Procedure ..................................................... 328

Figure 12.3 TCNT Auto-Reload Operation................................................................................ 329

Figure 12.4 Count Timing when Operating on Internal Clock................................................... 329

Figure 12.5 Count Timing when Operating on External Clock.................................................. 330

Figure 12.6 Count Timing when Operating on On-Chip RTC Output Clock............................. 330

Figure 12.7 Operation Timing when Using Input Capture Function.......................................... 331

Section 13 Bus State Controller (BSC)

Figure 13.1 Block Diagram of BSC ...........................................................................................337

Figure 13.2 Correspondence between Virtual Address Space and External Memory Space...... 341

Figure 13.3 External Memory Space Allocation ........................................................................ 343

Figure 13.4 Example of RDY Sampling Timing at which BCR4 Is Set

(Two Wait Cycles Are Inserted by WCR2) ............................................................ 362

Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR.................................................. 393

Figure 13.6 Basic Timing of SRAM Interface ...........................................................................406

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Figure 13.7 Example of 32-Bit Data Width SRAM Connection.............................................. 407

Figure 13.8 Example of 16-Bit Data Width SRAM Connection.............................................. 408

Figure 13.9 Example of 8-Bit Data Width SRAM Connection................................................ 409

Figure 13.10 SRAM Interface Wait Timing (Software Wait Only)........................................... 410

Figure 13.11 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal)......... 411

Figure 13.12 SRAM Interface Read Strobe Negate Timing

(AnS = 1, AnW = 4, and AnH = 2)....................................................................... 412

Figure 13.13 Example of DRAM Connection (32-Bit Data Width, Area 3).............................. 413

Figure 13.14 Basic DRAM Access Timing ............................................................................... 415

Figure 13.15 DRAM Wait State Timing.................................................................................... 416

Figure 13.16 DRAM Burst Access Timing................................................................................ 417

Figure 13.17 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1) .......................... 418

Figure 13.18 Burst Access Timing in DRAM EDO Mode ........................................................ 419

Figure 13.19 (1) DRAM Burst Bus Cycle, RAS Down Mode Start

(Fast Page Mode, RCD = 0, AnW = 0)................................................................. 420

Figure 13.19 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation

(Fast Page Mode, RCD = 0, AnW = 0)................................................................. 421

Figure 13.19 (3) DRAM Burst Bus Cycle, RAS Down Mode Start

(EDO Mode, RCD = 0, AnW = 0)........................................................................ 422

Figure 13.19 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation

(EDO Mode, RCD = 0, AnW = 0)........................................................................ 423

Figure 13.20 CAS-Before-RAS Refresh Operation................................................................... 424

Figure 13.21 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1) ............ 425

Figure 13.22 DRAM Self-Refresh Cycle Timing ...................................................................... 426

Figure 13.23 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3)......... 428

Figure 13.24 Basic Timing for Synchronous DRAM Burst Read.............................................. 431

Figure 13.25 Basic Timing for Synchronous DRAM Single Read............................................ 433

Figure 13.26 Basic Timing for Synchronous DRAM Burst Write............................................. 434

Figure 13.27 Basic Timing for Synchronous DRAM Single Write ........................................... 436

Figure 13.28 Burst Read Timing................................................................................................ 438

Figure 13.29 Burst Read Timing (RAS Down, Same Row Address) ........................................ 439

Figure 13.30 Burst Read Timing (RAS Down, Different Row Addresses) ............................... 440

Figure 13.31 Burst Write Timing............................................................................................... 441

Figure 13.32 Burst Write Timing (Same Row Address)............................................................ 442

Figure 13.33 Burst Write Timing (Different Row Addresses)................................................... 443

Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding

Burst Read Cycle.................................................................................................. 446

Figure 13.35 Auto-Refresh Operation........................................................................................ 448

Figure 13.36 Synchronous DRAM Auto-Refresh Timing ......................................................... 448

Figure 13.37 Synchronous DRAM Self-Refresh Timing........................................................... 450

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Figure 13.38 (1) Synchronous DRAM Mode Write Timing (PALL).......................................... 452

Figure 13.38 (2) Synchronous DRAM Mode Write Timing (Mode Register Setting) ................ 453

Figure 13.39 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8)..... 455

Figure 13.40 Basic Timing of a Burst Write to Synchronous DRAM ....................................... 456

Figure 13.41 Burst ROM Basic Access Timing......................................................................... 458

Figure 13.42 Burst ROM Wait Access Timing.......................................................................... 459

Figure 13.43 Burst ROM Wait Access Timing.......................................................................... 460

Figure 13.44 Example of PCMCIA Interface............................................................................. 464

Figure 13.45 Basic Timing for PCMCIA Memory Card Interface ............................................465

Figure 13.46 Wait Timing for PCMCIA Memory Card Interface.............................................. 466

Figure 13.47 PCMCIA Space Allocation................................................................................... 467

Figure 13.48 Basic Timing for PCMCIA I/O Card Interface..................................................... 468

Figure 13.49 Wait Timing for PCMCIA I/O Card Interface...................................................... 469

Figure 13.50 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface............................. 470

Figure 13.51 Example of 32-Bit Data Width MPX Connection ................................................ 472

Figure 13.52 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait)....... 473

Figure 13.53 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted).. 474

Figure 13.54 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No External Wait)...... 475

Figure 13.55 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted) 476

Figure 13.56 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait) ........ 477

Figure 13.57 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control). 478

Figure 13.58 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait)........ 479

Figure 13.59 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control)480

Figure 13.60 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait,

Bus Width: 32 Bits, Transfer Data Size: 64 Bits) ................................................ 481

Figure 13.61 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait

Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) ................................. 482

Figure 13.62 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait,

Bus Width: 32 Bits, Transfer Data Size: 64 Bits) ................................................ 483

Figure 13.63 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait

Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) ................................. 484

Figure 13.64 Example of 32-Bit Data Width Byte Control SRAM ........................................... 485

Figure 13.65 Byte Control SRAM Basic Read Cycle (No Wait)............................................... 486

Figure 13.66 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle)...................... 487

Figure 13.67 Byte Control SRAM Basic Read Cycle

(One Internal Wait + One External Wait)............................................................. 488

Figure 13.68 Waits between Access Cycles............................................................................... 490

Figure 13.69 Arbitration Sequence ............................................................................................ 492

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Section 14 Direct Memory Access Controller (DMAC)

Figure 14.1 Block Diagram of DMAC..................................................................................... 500

Figure 14.2 DMAC Transfer Flowchart................................................................................... 519

Figure 14.3 Round Robin Mode............................................................................................... 524

Figure 14.4 Example of Changes in Priority Order in Round Robin Mode............................. 525

Figure 14.5 Data Flow in Single Address Mode ...................................................................... 527

Figure 14.6 DMA Transfer Timing in Single Address Mode .................................................. 528

Figure 14.7 Operation in Dual Address Mode ......................................................................... 529

Figure 14.8 Example of Transfer Timing in Dual Address Mode............................................ 530

Figure 14.9 Example of DMA Transfer in Cycle Steal Mode.................................................. 531

Figure 14.10 Example of DMA Transfer in Burst Mode........................................................... 531

Figure 14.11 Bus Handling with Two DMAC Channels Operating .......................................... 535

Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ

(Level Detection), DACK (Read Cycle)............................................................... 538

Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ

(Edge Detection), DACK (Read Cycle)................................................................ 539

Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ

(Level Detection), DACK (Read Cycle)............................................................... 540

Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ

(Edge Detection), DACK (Read Cycle)................................................................ 541

Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection)

→ External Bus..................................................................................................... 542

Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI

(Level Detection) .................................................................................................. 543

Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ

(Level Detection) .................................................................................................. 544

Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ

(Edge Detection)................................................................................................... 545

Figure 14.20 Single Address Mode/Burst Mode External Bus → External Bus/DREQ

(Level Detection) .................................................................................................. 546

Figure 14.21 Single Address Mode/Burst Mode External Bus → External Bus/DREQ

(Edge Detection)................................................................................................... 547

Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/DREQ
(Level Detection)/32-Byte Block Transfer (Bus Width: 32 Bits, SDRAM:

Row Hit Write) ..................................................................................................... 548

Figure 14.23 On-Demand Transfer Mode Block Diagram ........................................................ 553

Figure 14.24 System Configuration in On-Demand Data Transfer Mode ................................. 555

Figure 14.25 Data Transfer Request Format.............................................................................. 556

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Figure 14.26 Single Address Mode/Synchronous DRAM → External Device Longword
Transfer SDRAM Auto-Precharge Read Bus Cycle, Burst

(RCD = 1, CAS latency = 3, TPC = 3) ................................................................. 559

Figure 14.27 Single Address Mode/External Device → Synchronous DRAM Longword
Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst

(RCD = 1, TRWL = 2, TPC = 1) ..........................................................................560

Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer ..........561

Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte

Block Transfer/Channel 0 On-Demand Data Transfer ......................................... 562

Figure 14.30 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte

Block Transfer/Channel 0 On-Demand Data Transfer ......................................... 562

Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit

Transfer/Channel 0 On-Demand Data Transfer.................................................... 563

Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit

Transfer/Channel 0 On-Demand Data Transfer.................................................... 564

Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer).... 565

Figure 14.34 Handshake Protocol without Use of Data Bus

(Channel 0 On-Demand Data Transfer)................................................................ 566

Figure 14.35 Read from Synchronous DRAM Precharge Bank................................................. 567

Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss)..................... 567

Figure 14.37 Read from Synchronous DRAM (Row Hit).......................................................... 568

Figure 14.38 Write to Synchronous DRAM Precharge Bank ....................................................568

Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss) ........................ 569

Figure 14.40 Write to Synchronous DRAM (Row Hit) ............................................................. 569

Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte

Block Transfer/Channel 0 On-Demand Data Transfer ......................................... 570

Figure 14.42 DDT Mode Setting................................................................................................ 571

Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device

→ External Bus Data Transfer.............................................................................. 571

Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus

→ External Device Data Transfer......................................................................... 572

Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,

Quadword/External Bus → External Device Data Transfer ................................. 572

Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,

Quadword/External Device → External Bus Data Transfer ................................. 573

Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer

Request to Channels 1–3 Using Data Bus.............................................................574

Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus
→ External Device Data Transfer/ Direct Data Transfer Request to Channel 2

without Using Data Bus........................................................................................ 575

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Figure 14.49 Single Address Mode/Burst Mode/External Bus → External Device Data

Transfer/Direct Data Transfer Request to Channel 2............................................ 576

Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data

Transfer/Direct Data Transfer Request to Channel 2............................................ 577

Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data

Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2...... 578

Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data

Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2...... 579

Figure 14.53 Block Diagram of the DMAC............................................................................... 583

Figure 14.54 DTR Format (Transfer Request Format) (SH7751R)........................................... 594

Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte

Block Transfer/Channel 0 On-Demand Data Transfer ......................................... 598

Figure 14.56 Single Address Mode/Cycle Steal Mode/External Bus → External Device/

32-Byte Block Transfer/On-Demand Data Transfer on Channel 4....................... 599

Section 15 Serial Communication Interface (SCI)

Figure 15.1 Block Diagram of SCI .......................................................................................... 605

Figure 15.2 SCK Pin................................................................................................................ 621

Figure 15.3 TxD Pin................................................................................................................. 622

Figure 15.4 RxD Pin ................................................................................................................ 622

Figure 15.5 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits) ............................................... 634

Figure 15.6 Relation between Output Clock and Transfer Data Phase

(Asynchronous Mode) .......................................................................................... 636

Figure 15.7 Sample SCI Initialization Flowchart..................................................................... 637

Figure 15.8 Sample Serial Transmission Flowchart ................................................................ 638

Figure 15.9 Example of Transmit Operation in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit).................................................. 640

Figure 15.10 Sample Serial Reception Flowchart (1) ................................................................ 641

Figure 15.11 Example of SCI Receive Operation

(Example with 8-Bit Data, Parity, One Stop Bit).................................................. 644

Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A).......................................... 645

Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart ....................................... 647

Figure 15.14 Example of SCI Transmit Operation

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................. 649

Figure 15.15 Sample Flowchart of Multiprocessor Serial Reception with Interrupt

Generation ............................................................................................................ 651

Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (1) ....................................... 652

Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (2) ....................................... 653

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Figure 15.17 Example of SCI Receive Operation (Example with 8-Bit Data,

Multiprocessor Bit, One Stop Bit) ........................................................................ 654

Figure 15.18 Data Format in Synchronous Communication...................................................... 655

Figure 15.19 Sample SCI Initialization Flowchart..................................................................... 657

Figure 15.20 Sample Serial Transmission Flowchart................................................................. 658

Figure 15.21 Example of SCI Transmit Operation .................................................................... 660

Figure 15.22 Sample Serial Reception Flowchart (1) ................................................................ 661

Figure 15.23 Example of SCI Receive Operation ...................................................................... 663

Figure 15.24 Sample Flowchart for Serial Data Transmission and Reception........................... 664

Figure 15.25 Receive Data Sampling Timing in Asynchronous Mode...................................... 668

Figure 15.26 Example of Synchronous Transmission by DMAC.............................................. 669

Section 16 Serial Communication Interface with FIFO (SCIF)

Figure 16.1 Block Diagram of SCIF ........................................................................................673

Figure 16.2 MD8/RTS2 Pin ..................................................................................................... 696

Figure 16.3 MD7/CTS2 Pin ..................................................................................................... 697

Figure 16.4 MD1/TxD2 Pin ..................................................................................................... 698

Figure 16.5 MD2/RxD2 Pin ..................................................................................................... 698

Figure 16.6 MD0/SCK2 Pin..................................................................................................... 699

Figure 16.7 Sample SCIF Initialization Flowchart................................................................... 705

Figure 16.8 Sample Serial Transmission Flowchart................................................................. 706

Figure 16.9 Example of Transmit Operation

(Example with 8-Bit Data, Parity, One Stop Bit).................................................. 708

Figure 16.10 Example of Operation Using Modem Control (CTS2) ......................................... 708

Figure 16.11 Sample Serial Reception Flowchart (1) ................................................................ 709

Figure 16.11 Sample Serial Reception Flowchart (2) ................................................................ 710

Figure 16.12 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity,

One Stop Bit) ........................................................................................................ 712

Figure 16.13 Example of Operation Using Modem Control (RTS2) ......................................... 712

Figure 16.14 Receive Data Sampling Timing in Asynchronous Mode...................................... 716

Section 17 Smart Card Interface

Figure 17.1 Block Diagram of Smart Card Interface ............................................................... 720

Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections ............................. 727

Figure 17.3 Smart Card Interface Data Format........................................................................ 728

Figure 17.4 TEND Generation Timing .................................................................................... 730

Figure 17.5 Sample Start Character Waveforms...................................................................... 731

Figure 17.6 Difference in Clock Output According to GM Bit Setting ................................... 734

Figure 17.7 Sample Initialization Flowchart............................................................................ 735

Figure 17.8 Sample Transmission Processing Flowchart......................................................... 737

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Figure 17.9 Sample Reception Processing Flowchart.............................................................. 739

Figure 17.10 Receive Data Sampling Timing in Smart Card Mode .......................................... 741

Figure 17.11 Retransfer Operation in SCI Receive Mode ......................................................... 743

Figure 17.12 Retransfer Operation in SCI Transmit Mode........................................................ 743

Figure 17.13 Procedure for Stopping and Restarting the Clock................................................. 744

Section 18 I/O Ports

Figure 18.1 16-Bit Port A......................................................................................................... 748

Figure 18.2 16-Bit Port B......................................................................................................... 749

Figure 18.3 SCK Pin................................................................................................................ 750

Figure 18.4 TxD Pin................................................................................................................. 751

Figure 18.5 RxD Pin ................................................................................................................ 751

Figure 18.6 MD1/TxD2 Pin ..................................................................................................... 752

Figure 18.7 MD2/RxD2 Pin ..................................................................................................... 752

Figure 18.8 MD0/SCK2 Pin..................................................................................................... 753

Figure 18.9 MD7/CTS2 Pin ..................................................................................................... 754

Figure 18.10 MD8/RTS2 Pin ..................................................................................................... 755

Section 19 Interrupt Controller (INTC)

Figure 19.1 Block Diagram of INTC ....................................................................................... 770

Figure 19.2 Example of IRL Interrupt Connection .................................................................. 773

Figure 19.3 Interrupt Operation Flowchart .............................................................................. 788

Section 20 User Break Controller (UBC)

Figure 20.1 Block Diagram of User Break Controller ............................................................. 796

Figure 20.2 User Break Debug Support Function Flowchart................................................... 817

Section 21 High-performance User Debug Interface (H-UDI)

Figure 21.1 Block Diagram of H-UDI Circuit ......................................................................... 824

Figure 21.2 TAP Control State Transition Diagram ................................................................ 843

Figure 21.3 H-UDI Reset .........................................................................................................844

Section 22 PCI Controller (PCIC)

Figure 22.1 PCIC Block Diagram ............................................................................................ 848

Figure 22.2 PIO Memory Space Access .................................................................................. 936

Figure 22.3 PIO I/O Space Access........................................................................................... 937

Figure 22.4 Local Address Space Accessing Method.............................................................. 938

Figure 22.5 Example of DMA Transfer Control Register Settings .......................................... 942

Figure 22.6 Example of DMA Transfer Flowchart .................................................................. 944

Figure 22.7 Master Write Cycle in Host Mode (Single) .......................................................... 948

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Figure 22.8 Master Read Cycle in Host Mode (Single) ........................................................... 949

Figure 22.9 Master Memory Write Cycle in Non-Host Mode (Burst) ..................................... 950

Figure 22.10 Master Memory Read Cycle in Non-Host Mode (Burst)...................................... 951

Figure 22.11 Target Read Cycle in Non-Host Mode (Single).................................................... 953

Figure 22.12 Target Write Cycle in Non-Host Mode (Single)................................................... 954

Figure 22.13 Target Memory Read Cycle in Host Mode (Burst)............................................... 955

Figure 22.14 Target Memory Write Cycle in Host Mode (Burst).............................................. 956

Figure 22.15 Master Memory Write Cycle in Host Mode (Burst, With Stepping) .................... 957

Figure 22.16 Target Memory Read Cycle in Host Mode (Burst, With Stepping)...................... 958

Figure 22.17 Endian Conversion Modes for Peripheral Bus...................................................... 959

Figure 22.18 Peripheral Bus ↔ PCI Bus Data Alignment......................................................... 960

Figure 22.19 Endian Control for Local Bus............................................................................... 961

Figure 22.20 Data Alignment at DMA Transfer ........................................................................ 962

Figure 22.21 (1) Data Alignment at Target Memory Transfer (Big-Endian Local Bus) ............. 964

Figure 22.21 (2) Data Alignment at Target Memory Transfer (Little-Endian Local Bus) .......... 965

Figure 22.22 Data Alignment at Target I/O Transfer (Both Big Endian and Little Endian)...... 966

Figure 22.23 Data Alignment at Target Configuration Transfer

(Both Big Endian and Little Endian) .................................................................... 967

Figure 22.24 Target Bus Timeout Interrupt Generation Example 1
(Example in which the Target Device Asserts STOP at the Sixteenth Clock

Cycle after FRAME Was Asserted)...................................................................... 978

Figure 22.25 Target Bus Timeout Interrupt Generation Example 2 (Example in which

the Target Device Takes 8 Clock Cycles to Prepare for the Third Data

Transfer) ............................................................................................................... 979

Figure 22.26 Master Bus Timeout Interrupt Generation Example 1 (Example in which
the Master Device Prepares the Data and Asserts IRDY at the Eighth Clock

Cycle after FRAME Was Asserted)...................................................................... 979

Figure 22.27 Master Bus Timeout Interrupt Generation Example 2 (Example in which
the Master Device Takes 8 Clock Cycles to Prepare for the Third Data

Transfer following the Second Data Phase).......................................................... 980

Section 23 Electrical Characteristics

Figure 23.1 EXTAL Clock Input Timing............................................................................... 1007

Figure 23.2 (1) CKIO Clock Output Timing ........................................................................... 1007

Figure 23.2 (2) CKIO Clock Output Timing ........................................................................... 1007

Figure 23.3 Power-On Oscillation Settling Time................................................................... 1008

Figure 23.4 Standby Return Oscillation Settling Time (Return by RESET or MRESET) ..... 1008

Figure 23.5 Power-On Oscillation Settling Time................................................................... 1009

Figure 23.6 Standby Return Oscillation Settling Time (Return by RESET or MRESET) ..... 1009

Figure 23.7 Standby Return Oscillation Settling Time (Return by NMI).............................. 1010

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Figure 23.8 Standby Return Oscillation Settling Time (Return by IRL3–IRL0) ................... 1010

Figure 23.9 PLL Synchronization Settling Time in Case of RESET, MRESET or

NMI Interrupt...................................................................................................... 1011

Figure 23.10 PLL Synchronization Settling Time in Case of IRL Interrupt............................ 1011

Figure 23.11 Control Signal Timing ........................................................................................ 1014

Figure 23.12 (1) Pin Drive Timing for Reset or Sleep Mode .................................................... 1014

Figure 23.12 (2) Pin Drive Timing for Software Standby Mode............................................... 1015

Figure 23.13 SRAM Bus Cycle: Basic Bus Cycle (No Wait).................................................. 1020

Figure 23.14 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)................................... 1021

Figure 23.15 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) . 1022

Figure 23.16 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/

Hold Time Insertion, AnS = 1, AnH = 1) ........................................................... 1023

Figure 23.17 Burst ROM Bus Cycle (No Wait)....................................................................... 1024

Figure 23.18 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait;

2nd/3rd/4th Data: One Internal Wait)................................................................. 1025

Figure 23.19 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion,

AnS = 1, AnH = 1).............................................................................................. 1026

Figure 23.20 Burst ROM Bus Cycle (One Internal Wait + One External Wait)...................... 1027

Figure 23.21 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single

(RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011)....................................... 1028

Figure 23.22 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst

(RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011)....................................... 1029

Figure 23.23 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands,

Burst (RASD = 1, RCD [1:0] = 01, CAS Latency = 3) ...................................... 1030

Figure 23.24 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ
Commands, Burst (RASD = 1, RCD [1:0] = 01, TPC [2:0] = 001,

CAS Latency = 3) ............................................................................................... 1031

Figure 23.25 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst

(RASD = 1, CAS Latency = 3)........................................................................... 1032

Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single

(RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) .................................... 1033

Figure 23.27 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst

(RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) .................................... 1034

Figure 23.28 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands,

Burst (RASD = 1, RCD [1:0] = 01, TRWL [2:0] = 010).................................... 1035

Figure 23.29 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT +
WRITE Commands, Burst (RASD = 1, RCD [1:0] = 01, TPC [2:0] = 001,

TRWL [2:0] = 010)............................................................................................. 1036

Figure 23.30 Synchronous DRAM Normal Write Bus Cycle: WRITE Command,

Burst (RASD = 1, TRWL [2:0] = 010)............................................................... 1037

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Figure 23.31 Synchronous DRAM Bus Cycle: Precharge Command (TPC [2:0] = 001)........ 1038

Figure 23.32 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS = 1, TRC [2:0] = 001). 1039

Figure 23.33 Synchronous DRAM Bus Cycle: Self-Refresh (TRC [2:0] = 001)..................... 1040

Figure 23.34 (a) Synchronous DRAM Bus Cycle: Mode Register Setting (PALL).................. 1041

Figure 23.34 (b) Synchronous DRAM Bus Cycle: Mode Register Setting (SET)..................... 1042

Figure 23.35 DRAM Bus Cycles (1) RCD [1:0] = 00, AnW [2:0] = 000,

TPC [2:0] = 001 (2) RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 010......... 1043

Figure 23.36 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000,

TRC [2:0] = 001) ................................................................................................ 1044

Figure 23.37 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000,

TPC [2:0] = 001)................................................................................................. 1045

Figure 23.38 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001,

TPC [2:0] = 001)................................................................................................. 1046

Figure 23.39 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001,

TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width)......................................... 1047

Figure 23.40 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode,

RCD [1:0] = 00, AnW [2:0] = 000) .................................................................... 1048

Figure 23.41 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode,

RCD [1:0] = 00, AnW [2:0] = 000) .................................................................... 1049

Figure 23.42 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 00,

AnW [2:0] = 000, TPC [2:0] = 001) ................................................................... 1050

Figure 23.43 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01,

AnW [2:0] = 001, TPC [2:0] = 001) ................................................................... 1051

Figure 23.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01,

AnW [2:0] = 001, TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width) ........... 1052

Figure 23.45 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode,

RCD [1:0] = 00, AnW [2:0] = 000) .................................................................... 1053

Figure 23.46 DRAM Burst Bus Cycle: RAS Down Mode Continuation (Fast Page Mode,

RCD [1:0] = 00, AnW [2:0] = 000) .................................................................... 1054

Figure 23.47 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh

(TRAS [2:0] = 000, TRC [2:0] = 001)................................................................ 1055

Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS [2:0] = 001,

TRC [2:0] = 001) ................................................................................................ 1056

Figure 23.49 DRAM Bus Cycle: DRAM Self-Refresh (TRC [2:0] = 001).............................. 1057

Figure 23.50 PCMCIA Memory Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000,
No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait

+ One External Wait ........................................................................................... 1058

Figure 23.51 PCMCIA I/O Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000,
No Wait (2) TED [2:0] = 001, TEH [2:0] = 001,

One Internal Wait + One External Wait.............................................................. 1059

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Figure 23.52 PCMCIA I/O Bus Cycle (TED [2:0] = 001, TEH [2:0] = 001,

One Internal Wait, Bus Sizing)........................................................................... 1060

Figure 23.53 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2)

1st Data (One Internal Wait + One External Wait)............................................. 1061

Figure 23.54 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data

(One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait)....... 1062

Figure 23.55 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait),
2nd to 8th Data (No Internal Wait) (2) 1st Data (No Internal Wait),

2nd to 8th Data (No Internal Wait + External Wait Control).............................. 1063

Figure 23.56 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data
(One Internal Wait), 2nd to 8th Data (No Internal Wait +

External Wait Control)........................................................................................ 1064

Figure 23.57 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle
(No Wait) (2) Basic Read Cycle (One Internal Wait) (3)

Basic Read Cycle (One Internal Wait + One External Wait).............................. 1065

Figure 23.58 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle
(No Wait, Address Setup/Hold Time Insertion, AnS [0] = 1, AnH [1:0] = 01).. 1066

Figure 23.59 TCLK Input Timing............................................................................................ 1072

Figure 23.60 RTC Oscillation Settling Time at Power-On ...................................................... 1072

Figure 23.61 SCK Input Clock Timing.................................................................................... 1072

Figure 23.62 SCI I/O Synchronous Mode Clock Timing......................................................... 1073

Figure 23.63 I/O Port Input/Output Timing............................................................................. 1073

Figure 23.64 (a) DREQ/DRAK Timing .................................................................................... 1073

Figure 23.64 (b) DBREQ/TR Input Timing and BAVL Output Timing ................................... 1074

Figure 23.65 TCK Input Timing .............................................................................................. 1074

Figure 23.66 RESET Hold Timing .......................................................................................... 1075

Figure 23.67 H-UDI Data Transfer Timing ............................................................................. 1075

Figure 23.68 Pin Break Timing................................................................................................ 1075

Figure 23.69 NMI Input Timing .............................................................................................. 1075

Figure 23.70 PCI Clock Input Timing ..................................................................................... 1078

Figure 23.71 Output Signal Timing ......................................................................................... 1078

Figure 23.72 Output Signal Timing ......................................................................................... 1079

Figure 23.73 I/O Port Input/Output Timing............................................................................. 1080

Figure 23.74 Output Load Circuit............................................................................................ 1081

Figure 23.75 Load Capacitance−Delay Time........................................................................... 1082

Appendix B Package Dimensions

Figure B.1 Package Dimensions (256-pin QFP)..................................................................... 1091

Figure B.2 Package Dimensions (256-pin BGA: Devices Other than

HD6417751RBA240HV)...................................................................................... 1092

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Figure B.3 Package Dimensions (292-pin BGA).................................................................... 1093

Figure B.4 Package Dimensions (256-pin BGA: HD6417751RBA240HV).......................... 1094

Appendix F Instruction Prefetching and Its Side Effects

Figure F.1 Instruction Prefetch ............................................................................................... 1119

Appendix G Power-On and Power-Off Procedures

Figure G.1 Method for Temporarily Selecting Clock Operation Mode 6 ...............................1123

Figure G.2 Power-On Procedure 1 .......................................................................................... 1124

Figure G.3 Power-On Procedure 2 .......................................................................................... 1124

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Tables

Section 1 Overview

Table 1.1

Table 1.2 Pin Functions............................................................................................................. 13

Table 1.3 Pin Functions............................................................................................................. 24

Table 1.4 Pin Functions............................................................................................................. 35

Section 2 Programming Model

Table 2.1

Section 3 Memory Management Unit (MMU)

Table 3.1

Section 4 Caches

Table 4.1

Table 4.2 Cache Features (SH7751R)..................................................................................... 102

Table 4.3 Store Queue Features .............................................................................................. 102

Table 4.4 Cache Control Registers.......................................................................................... 102

SH7751/SH7751R Group Features ............................................................................. 2

Initial Register Values............................................................................................... 49

MMU Registers......................................................................................................... 66

Cache Features (SH7751)........................................................................................ 101

Section 5 Exceptions

Table 5.1

Table 5.2 Exceptions............................................................................................................... 140

Table 5.3 Types of Reset......................................................................................................... 148

Section 6 Floating-Point Unit

Table 6.1

Table 6.2 Floating-Point Ranges............................................................................................. 175

Section 7 Instruction Set

Table 7.1

Table 7.2 Notation Used in Instruction List ............................................................................ 195

Table 7.3 Fixed-Point Transfer Instructions............................................................................ 196

Table 7.4 Arithmetic Operation Instructions........................................................................... 198

Table 7.5 Logic Operation Instructions................................................................................... 200

Table 7.6 Shift Instructions ..................................................................................................... 201

Table 7.7 Branch Instructions ................................................................................................. 202

Table 7.8 System Control Instructions.................................................................................... 203

Table 7.9 Floating-Point Single-Precision Instructions........................................................... 205

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Exception-Related Registers ................................................................................... 137

Floating-Point Number Formats and Parameters .................................................... 174

Addressing Modes and Effective Addresses ........................................................... 191

Table 7.10 Floating-Point Double-Precision Instructions ......................................................... 206

Table 7.11 Floating-Point Control Instructions......................................................................... 206

Table 7.12 Floating-Point Graphics Acceleration Instructions ................................................. 207

Section 8 Pipelining

Table 8.1

Table 8.2 Parallel-Executability.............................................................................................. 222

Table 8.3 Execution Cycles..................................................................................................... 229

Section 9 Power-Down Modes

Table 9.1

Table 9.2 Power-Down Mode Registers ................................................................................. 241

Table 9.3 Power-Down Mode Pins ......................................................................................... 241

Table 9.4 State of Registers in Standby Mode ........................................................................ 250

Section 10 Clock Oscillation Circuits

Table 10.1

Table 10.2 CPG Register........................................................................................................... 272

Table 10.3 (1) Clock Operating Modes (SH7751) ................................................................... 273

Table 10.3 (2) Clock Operating Modes (SH7751R)................................................................. 273

Table 10.4 FRQCR Settings and Internal Clock Frequencies................................................... 274

Table 10.5 WDT Registers........................................................................................................ 281

Instruction Groups................................................................................................... 218

Status of CPU and Peripheral Modules in Power-Down Modes............................. 240

CPG Pins ................................................................................................................. 272

Section 11 Realtime Clock (RTC)

Table 11.1

Table 11.2 RTC Registers ......................................................................................................... 293

Table 11.3 Crystal Oscillation Circuit Constants (Recommended Values)............................... 313

Section 12 Timer Unit (TMU)

Table 12.1

Table 12.2 TMU Registers........................................................................................................ 317

Table 12.3 TMU Interrupt Sources ........................................................................................... 332

Section 13 Bus State Controller (BSC)

Table 13.1

Table 13.2 BSC Registers ......................................................................................................... 340

Table 13.3 External Memory Space Map.................................................................................. 342

Table 13.4 PCMCIA Interface Features.................................................................................... 344

Table 13.5 PCMCIA Support Interfaces ................................................................................... 345

Table 13.6 Idle Insertion between Accesses ............................................................................. 365

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RTC Pins ................................................................................................................. 293

TMU Pins................................................................................................................ 316

BSC Pins ................................................................................................................. 338

Table 13.7 When MPX Interface Is Set (Areas 0 to 6).............................................................. 373

Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment........................... 394

Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment........................... 395

Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment............................. 396

Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment ........................ 397

Table 13.12 16-Bit External Device/Little-Endian Access and Data Alignment ........................ 398

Table 13.13 8-Bit External Device/Little-Endian Access and Data Alignment.......................... 399

Table 13.14 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing.... 414

Table 13.15 Example of Correspondence between LSI and Synchronous DRAM Address

Pins (32-Bit Bus Width, AMX2–AMX0 = 000, AMXEXT = 0)............................ 429

Table 13.16 Cycles in Which Pipelined Access Can Be Used.................................................... 445

Table 13.17 Relationship between Address and CE When Using PCMCIA Interface ............... 462

Section 14 Direct Memory Access Controller (DMAC)

Table 14.1

Table 14.2 DMAC Pins in DDT Mode ..................................................................................... 502

Table 14.3 DMAC Registers..................................................................................................... 503

Table 14.4 Selecting External Request Mode with RS Bits ...................................................... 521

Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits....................... 522

Table 14.6 Supported DMA Transfers ...................................................................................... 526

Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode .......... 532

Table 14.8 External Request Transfer Sources and Destinations in Normal DMA Mode ........ 533

Table 14.9 External Request Transfer Sources and Destinations in DDT Mode ...................... 534

Table 14.10 Conditions for Transfer between External Memory and an External Device

with DACK, and Corresponding Register Settings................................................. 552

Table 14.11 Usable SZ, ID, and MD Combination in DDT Mode .............................................557

Table 14.12 DMAC Pins............................................................................................................. 584

Table 14.13 DMAC Pins in DDT Mode .....................................................................................585

Table 14.14 Register Configuration ............................................................................................ 586

Table 14.15 Channel Selection by DTR Format (DMAOR.DBL = 1)........................................ 594

Table 14.16 Notification of Transfer Channel in Eight-Channel DDT Mode............................. 596

Table 14.17 Function of BAVL .................................................................................................. 596

Table 14.18 DTR Format for Clearing Request Queues ............................................................. 597

Table 14.19 DMAC Interrupt-Request Codes............................................................................. 598

DMAC Pins............................................................................................................. 501

Section 15 Serial Communication Interface (SCI)

Table 15.1

Table 15.2 SCI Registers........................................................................................................... 606

Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ..................625

Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode..................... 628

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SCI Pins................................................................................................................... 606

Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator

(Asynchronous Mode)............................................................................................. 629

Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)................... 630

Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)..................... 630

Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection......................................... 632

Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection .......................... 633

Table 15.10 Serial Transfer Formats (Asynchronous Mode)...................................................... 635

Table 15.11 Receive Error Conditions........................................................................................ 643

Table 15.12 SCI Interrupt Sources.............................................................................................. 666

Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data............................................... 667

Section 16 Serial Communication Interface with FIFO (SCIF)

Table 16.1

Table 16.2 SCIF Registers ........................................................................................................ 674

Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection......................................... 702

Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection ............................................... 702

Table 16.5 Serial Transfer Formats........................................................................................... 703

Table 16.6 SCIF Interrupt Sources............................................................................................ 714

Section 17 Smart Card Interface

Table 17.1

Table 17.2 Smart Card Interface Registers ............................................................................... 721

Table 17.3 Smart Card Interface Register Settings ................................................................... 729

Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings..................................... 732

Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0)........ 732

Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) ..................... 732

Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)............. 733

Table 17.8 Register Settings and SCK Pin State....................................................................... 733

Table 17.9 Smart Card Mode Operating States and Interrupt Sources...................................... 740

SCIF Pins ................................................................................................................ 674

Smart Card Interface Pins ....................................................................................... 721

Section 18 I/O Ports

Table 18.1

Table 18.2 SCI I/O Port Pins..................................................................................................... 757

Table 18.3 SCIF I/O Port Pins .................................................................................................. 757

Table 18.4 I/O Port Registers.................................................................................................... 758

Section 19 Interrupt Controller (INTC)

Table 19.1

Table 19.2 INTC Registers ....................................................................................................... 771

Table 19.3 IRL3–IRL0 Pins and Interrupt Levels..................................................................... 774

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32-Bit General-Purpose I/O Port Pins..................................................................... 755

INTC Pins ............................................................................................................... 771

Table 19.4 Interrupt Exception Handling Sources and Priority Order ...................................... 777

Table 19.5 Interrupt Request Sources and IPRA–IPRD Registers............................................ 781

Table 19.6 Interrupt Request Sources and INTPRI00 Register................................................. 783

Table 19.7 Bit Allocation .......................................................................................................... 786

Table 19.8 Interrupt Response Time ......................................................................................... 790

Section 20 User Break Controller (UBC)

Table 20.1

UBC Registers......................................................................................................... 797

Section 21 High-performance User Debug Interface (H-UDI)

Table 21.1

H-UDI Pins.............................................................................................................. 825

Table 21.2 H-UDI Registers...................................................................................................... 826

Table 21.3 Structure of Boundary Scan Register ...................................................................... 830

Section 22 PCI Controller (PCIC)

Table 22.1

Pin Configuration .................................................................................................... 849

Table 22.2 List of PCI Configuration Registers........................................................................ 851

Table 22.3 PCI Configuration Register Configuration............................................................. 852

Table 22.4 List of PCIC Local Registers................................................................................... 853

Table 22.5 List of CLASS23 to 16 Base Class Codes (CLASS23 to 16).................................. 864

Table 22.6 Memory Space Base Address Register (BASE0).................................................... 870

Table 22.7 Memory Space Base Address Register (BASE1).................................................... 872

Table 22.8 Operating Modes..................................................................................................... 928

Table 22.9 PCI Command Support ...........................................................................................929

Table 22.10 Access Size.............................................................................................................. 960

Table 22.11 DMA Transfer Access Size and Endian Conversion Mode .................................... 962

Table 22.12 Target Transfer Access Size and Endian Conversion Mode ................................... 963

Table 22.13 Interrupts ................................................................................................................. 969

Table 22.14 Method of Stopping Clock per Operating Mode..................................................... 974

Section 23 Electrical Characteristics

Table 23.1

Absolute Maximum Ratings.................................................................................... 983

Table 23.2 DC Characteristics (HD6417751RBP240 (V), HD6417751RBG240 (V),

HD6417751RBA240HV)........................................................................................ 984

Table 23.3 DC Characteristics (HD6417751RF240 (V)).......................................................... 986

Table 23.4 DC Characteristics (HD6417751RBP200 (V), HD6417751RBG200 (V),

HD6417751RBA240HV*

3

)..................................................................................... 988

Table 23.5 DC Characteristics (HD6417751RF200 (V)).......................................................... 990

Table 23.6 DC Characteristics (HD6417751BP167 (V)).......................................................... 992

Table 23.7 DC Characteristics (HD6417751F167 (V))............................................................. 994

R01UH0457EJ0301 Rev. 3.01 Page li of liv

Sep 24, 2013

Table 23.8 Permissible Output Currents ................................................................................... 996

Table 23.9 Clock Timing (HD6417751RBP240 (V), HD6417751RBG240 (V),

HD6417751RBA240HV)........................................................................................ 996

Table 23.10 Clock Timing (HD6417751RF240 (V)).................................................................. 996

Table 23.11 Clock Timing (HD6417751RBP200 (V), HD6417751RBG200 (V),

HD6417751RBA240HV*)...................................................................................... 997

Table 23.12 Clock Timing (HD6417751RF200 (V)).................................................................. 997

Table 23.13 Clock Timing (HD6417751BP167 (V), HD6417751F167 (V)).............................. 997

Table 23.14 Clock and Control Signal Timing (HD6417751RBP240 (V),

HD6417751RBG240 (V), HD6417751RBA240HV).............................................. 998

Table 23.15 Clock and Control Signal Timing (HD6417751RF240 (V))................................. 1000

Table 23.16 Clock and Control Signal Timing (HD6417751RBP200 (V),

HD6417751RBG200 (V), HD6417751RBA240HV*

Table 23.17 Clock and Control Signal Timing (HD6417751RF200 (V))................................. 1004

Table 23.18 Clock and Control Signal Timing (HD6417751BP167 (V),

HD6417751F167 (V))........................................................................................... 1006

Table 23.19 Control Signal Timing........................................................................................... 1012

Table 23.20 Control Signal Timing........................................................................................... 1013

Table 23.21 Bus Timing (1)...................................................................................................... 1016

Table 23.22 Bus Timing (2)...................................................................................................... 1018

Table 23.23 Peripheral Module Signal Timing (1) ................................................................... 1067

Table 23.24 Peripheral Module Signal Timing (2) ................................................................... 1070

Table 23.25 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (1)......................... 1076

Table 23.26 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (2)......................... 1077

Table 23.27 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings

in Non-Host Mode) (1).......................................................................................... 1079

Table 23.28 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings

in Non-Host Mode) (2).......................................................................................... 1079

2

)......................................... 1002

Appendix A Address List

Table A.1

Appendix C Mode Pin Settings

Table C.1

Table C.2 Clock Operating Modes (SH7751R)..................................................................... 1096

Table C.3 Area 0 Memory Map and Bus Width.................................................................... 1096

Table C.4 Endian ................................................................................................................... 1096

Table C.5 Master/Slave.......................................................................................................... 1097

Table C.6 Clock Input............................................................................................................ 1097

Table C.7 PCI Mode.............................................................................................................. 1097

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Sep 24, 2013

Address List .......................................................................................................... 1083

Clock Operating Modes (SH7751)........................................................................ 1095

Appendix D Pin Functions

Table D.1

(PCI Enable, Disable Common) ............................................................................ 1099

Table D.2 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable).... 1101

Table D.3 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Disable) .. 1103

Table D.4 Handling of Pins When PCI Is Not Used .............................................................. 1105

Appendix H Product Lineup

Table H.1

Appendix I Version Registers

Table I.1

Pin States in Reset, Power-Down State, and Bus-Released State

SH7751/SH7751R Product Lineup ....................................................................... 1125

Register Configuration.......................................................................................... 1127

R01UH0457EJ0301 Rev. 3.01 Page liii of liv

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SH7751 Group, SH7751R Group Section 1 Overview

Section 1 Overview

1.1 SH7751/SH7751R Group Features

The SH7751/SH7751R Group microprocessor, featuring a built-in PCI bus controller compatible
with PCs and multimedia devices. The SuperH™* RISC engine is a Renesas original 32-bit RISC
(Reduced Instruction Set Computer) microcomputer. The SuperH™ RISC engine employs a fixed­length 16-bit instruction set, allowing an approximately 50% reduction in program size over a 32­bit instruction set.

The SH7751/SH7751R Group feature the SH-4 Core, which at the object code level is upwardly
compatible with the SH-1, SH-2, and SH-3 microcomputers. The SH7751/SH7751R Group have
an instruction cache, an operand cache that can be switched between copy-back and write-through
modes, a 4-entry full-associative instruction TLB (table look aside buffer), and MMU (memory
management unit) with 64-entry full-associative shared TLB.

The SH7751/SH7751R Group also feature a bus state controller (BSC) that can be coupled to
DRAM (page/EDO) and synchronous DRAM. Also, because of its built-in functions, such as PCI
bus controller, timers, and serial communications functions, required for multimedia and OA
equipment, use of the SH7751/SH7751R Group enable a dramatic reduction in system costs.

The features of the SH7751/SH7751R Group are summarized in table 1.1.

Note: * SuperH is a trademark of Renesas Electronics Corp.

R01UH0457EJ0301 Rev. 3.01 Page 1 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Table 1.1 SH7751/SH7751R Group Features

Item Features

LSI

CPU

• Superscalar architecture: Parallel execution of two instructions

• External buses (SH buses)
⎯ Separate 26-bit address and 32-bit data buses
⎯ External bus frequency of 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times internal

bus frequency

• External bus (PCI bus):
⎯ 32-bit address/data multiplexing
⎯ Selection of internal clock or external PCI-dedicated clock

• Renesas Electronics original SuperH architecture

• 32-bit internal data bus

• General register file:
⎯ Sixteen 32-bit general registers (and eight 32-bit shadow registers)
⎯ Seven 32-bit control registers
⎯ Four 32-bit system registers

• RISC-type instruction set (upward-compatible with SuperH Series)
⎯ Fixed 16-bit instruction length for improved code efficiency
⎯ Load-store architecture
⎯ Delayed branch instructions
⎯ Conditional execution
⎯ C-based instruction set

• Superscalar architecture (providing simultaneous execution of two

instructions) including FPU

• Instruction execution time: Maximum 2 instructions/cycle

• Virtual address space: 4 Gbytes (448-Mbyte external memory space)

• Space identifier ASIDs: 8 bits, 256 virtual address spaces

• On-chip multiplier

• Five-stage pipeline

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SH7751 Group, SH7751R Group Section 1 Overview

Item Features

FPU

• On-chip floating-point coprocessor

• Supports single-precision (32 bits) and double-precision (64 bits)

• Supports IEEE754-compliant data types and exceptions

• Two rounding modes: Round to Nearest and Round to Zero

• Handling of denormalized numbers: Truncation to zero or interrupt

generation for compliance with IEEE754

• Floating-point registers: 32 bits × 16 × 2 banks

(single-precision 32 bits × 16 or double-precision 64 bits × 8) × 2 banks

• 32-bit CPU-FPU floating-point communication register (FPUL)

• Supports FMAC (multiply-and-accumulate) instruction

• Supports FDIV (divide) and FSQRT (square root) instructions

• Supports FLDI0/FLDI1 (load constant 0/1) instructions

• Instruction execution times
⎯ Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8

cycles (double-precision)

⎯ Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles

(double-precision)

Note: FMAC is supported for single-precision only.

• 3-D graphics instructions (single-precision only):
⎯ 4-dimensional vector conversion and matrix operations (FTRV): 4

cycles (pitch), 7 cycles (latency)

⎯ 4-dimensional vector inner product (FIPR): 1 cycle (pitch), 4 cycles

(latency)

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Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Item Features

Clock pulse
generator (CPG)

• Choice of main clock
⎯ SH7751: 1/2, 1, 3, or 6 times EXTAL
⎯ SH7751R: 1, 6, or 12 times EXTAL

• Clock modes: (Maximum frequency: Varies with models)
⎯ CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
⎯ Bus frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
⎯ Peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock

• Power-down modes
⎯ Sleep mode
⎯ Deep sleep mode
⎯ Pin sleep mode
⎯ Standby mode
⎯ Hardware standby mode
⎯ Module standby function

• Single-channel watchdog timer

Memory
management
unit (MMU)

• 4-Gbyte address space, 256 address space identifiers (8-bit ASIDs)

• Single virtual mode and multiple virtual memory mode

• Supports multiple page sizes: 1 Kbyte, 4 Kbytes, 64 Kbytes, 1 Mbyte

• 4-entry fully-associative TLB for instructions

• 64-entry fully-associative TLB for instructions and operands

• Supports software-controlled replacement and random-counter

replacement algorithm

• TLB contents can be accessed directly by address mapping

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SH7751 Group, SH7751R Group Section 1 Overview

Item Features

Cache memory
[SH7751]

• Instruction cache (IC)
⎯ 8 Kbytes, direct mapping
⎯ 256 entries, 32-byte block length
⎯ Normal mode (8-Kbyte cache)
⎯ Index mode

• Operand cache (OC)
⎯ 16 Kbytes, direct mapping
⎯ 512 entries, 32-byte block length
⎯ Normal mode (16-Kbyte cache)
⎯ Index mode
⎯ RAM mode (8-Kbyte cache + 8-Kbyte RAM)
⎯ Choice of write method (copy-back or write-through)

• Single-stage copy-back buffer, single-stage write-through buffer

• Cache memory contents can be accessed directly by address mapping

(usable as on-chip memory)

• Store queue (32 bytes × 2 entries)

Cache memory
[SH7751R]

• Instruction cache (IC)
⎯ 16 Kbytes, 2-way set associative
⎯ 256 entries/way, 32-byte block length
⎯ Cache-double-mode (16-Kbyte cache)
⎯ Index mode
⎯ SH7751-compatible mode (8 Kbytes, direct mapping)

• Operand cache (OC)
⎯ 32 Kbytes, 2-way set associative
⎯ 512 entries/way, 32-byte block length
⎯ Cache-double-mode (32-Kbyte cache)
⎯ Index mode
⎯ RAM mode (16-Kbyte cache + 16-Kbyte RAM)
⎯ Choice of write method (copy-back or write-through)
⎯ SH7751-compatible mode (16 Kbytes, direct mapping)

• Single-stage copy-back buffer, single-stage write-through buffer

• Cache memory contents can be accessed directly by address mapping

(usable as on-chip memory)

• Store queue (32 bytes × 2 entries)

R01UH0457EJ0301 Rev. 3.01 Page 5 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Item Features

Interrupt controller
(INTC)

• Five independent external interrupts (NMI, IRL3 to IRL0)

• 15-level signed external interrupts: IRL3 to IRL0

• On-chip peripheral module interrupts: Priority level can be set for each

module

User break
controller (UBC)

• Supports debugging by means of user break interrupts

• Two break channels

• Address, data value, access type, and data size can all be set as break

conditions

• Supports sequential break function

Bus state
controller (BSC)

• Supports external memory access
⎯ 32/16/8-bit external data bus

• External memory space divided into seven areas, each of up to 64

Mbytes, with the following parameters settable for each area:

⎯ Bus size (8, 16, or 32 bits)
⎯ Number of wait cycles (hardware wait function also supported)
⎯ Direct connection of DRAM, synchronous DRAM, and burst ROM

possible by setting space type

⎯ Supports fast page mode and DRAM EDO
⎯ Supports PCMCIA interface
⎯ Chip select signals (CS0 to CS6) output for relevant areas

• DRAM/synchronous DRAM refresh functions
⎯ Programmable refresh interval
⎯ Supports CAS-before-RAS refresh mode and self-refresh mode

• DRAM/synchronous DRAM burst access function

• Big endian or little endian mode can be set

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Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Item Features

Direct memory
access controller
(DMAC)

• Physical address DMA controller
⎯ SH7751: 4-channel
⎯ SH7751R: 8-channel

• Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes

• Address modes:
⎯ Single address mode
⎯ Dual address mode

• Transfer requests: External, on-chip peripheral module, or auto-requests

• Bus modes: Cycle-steal or burst mode

• Supports on-demand data transfer mode (external bus 32 bit)

Timer unit (TMU)

• 5-channel auto-reload 32-bit timer

Input-capture function on one channel

• Selection from 7 counter input clocks in 3 of 5 channels and from 5

counter input clocks on remaining 2 of 5 channels

Realtime clock
(RTC)

• On-chip clock and calendar functions

• Built-in 32 kHz crystal oscillation circuit with maximum 1/256 second

resolution (cycle interrupts)

Serial
communication
interface
(SCI, SCIF)

• Two full-duplex communication channels (SCI, SCIF)

• Channel 1 (SCI):
⎯ Choice of asynchronous mode or synchronous mode
⎯ Supports smart card interface

• Channel 2 (SCIF):
⎯ Supports asynchronous mode
⎯ Separate 16-byte FIFOs provided for transmitter and receiver

R01UH0457EJ0301 Rev. 3.01 Page 7 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Item Features

PCI bus controller
(PCIC)

• PCI bus controller (supports a subset of PCI revision 2.1)*
⎯ 32-bit bus
⎯ 33 MHz/66 MHz support

• PCI master/slave support

• PCI host function support
⎯ Built-in bus arbiter

• 4 built-in PCI-dedicated DMAC (direct memory access controller)

channels

⎯ Each channel equipped with 64-byte FIFO

• Selection of built-in clock or external PCI-dedicated clock

• Interrupt requests can be sent to CPU

Product lineup

Abbreviation Voltage

Operating
Frequency Model No.

Package

SH7751 1.8 V 167 MHz HD6417751BP167 256-pin BGA

HD6417751F167 256-pin QFP

SH7751R 1.5 V 240 MHz HD6417751RBP240 256-pin BGA

HD6417751RBA240H

HD6417751RF240 256-pin QFP

HD6417751RBG240 292-pin BGA

200 MHz HD6417751RBP200 256-pin BGA

HD6417751RF200 256-pin QFP

HD6417751RBG200 292-pin BGA

Note: * Some items are not compatible with PCI 2.1.
For more information, see section 22.1.1, Features.

Page 8 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

1.2 Block Diagram

Figure 1.1 shows an internal block diagram of the SH7751/SH7751R Group.

CPU

32-bit data (store)

32-bit data (load)

32-bit address (data)

32-bit data (instructions)

32-bit address (instructions)

I cache O cacheITLB UTLB

CPG

INTC

SCI

(SCIF)

RTC

TMU

Peripheral data bus

UBC

Lower 32-bit data

Cache and

TLB

controller

29-bit address

BSC

Peripheral address bus

32-bit data

32-bit data

FPU

64-bit data (store)

Upper 32-bit data

DMAC

SH-4 Core

PCIC

(PCI)DMAC

32-bit
PCI
address/
data

26-bit
SH bus
address

32-bit data

Address

interface

32-bit data

32-bit
SH bus
data

Address

External (SH) bus

32-bit data

Legend:
BSC: Bus state controller
CPG: Clock pulse generator
DMAC: Direct memory access controller
FPU: Floating-point unit
INTC: Interrupt controller
ITLB: Instruction TLB (translation lookaside buffer)
UTLB: Unified TLB (translation lookaside buffer)
RTC: Realtime clock
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
TMU: Timer unit
UBC: User break controller
PCIC: PCI bus controller

Figure 1.1 Block Diagram of SH7751/SH7751R Group Functions

R01UH0457EJ0301 Rev. 3.01 Page 9 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

1.3 Pin Arrangement

IRL3

IRL2

IRL1

IRL0

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

C/BE0

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

C/BE1

PAR

PERR

PCILOCK

PCISTOP

DEVSEL

TRDY

IRDY

PCIFRAME

C/BE2

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

C/BE3

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

A9

129

128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

64

A10

A11

SERR
PCIREQ1/GNTIN
PCIGNT1/REQOUT

PCICLK

PCIRST
INTA

IDSEL

PCIREQ2/MD9

PCIREQ3/MD10
PCIREQ4
PCIGNT2
PCIGNT3
PCIGNT4
SLEEP

WE3/ICIOWR
WE2/ICIORD

A25
A24

A23
A22
A21
A20
A19
A18

D31
D30

D29
D28
D27
D26
D25
D24
D23
D22
D21
D20

D19
D18
D17
D16

CAS3/DQM3
CAS2/DQM2

A17
A16
A15
A14

A13
A12

193

XTAL2

194

EXTAL2

195

VDD-RTC

196

VSS-RTC

197

CA

198

RESET

199

TRST

200

MRESET

201

NMI

RDY

TXD

RXD

TCLK

SCK

AUDCK

AUDATA0
AUDATA1

AUDATA2
AUDATA3

Reserved

MD5

DACK0
DACK1
DRAK0
DRAK1

STATUS0
STATUS1

DREQ0
DREQ1

TDO

VSS-CPG

XTAL

EXTAL

202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263

D0D1D2D3D4D5D6D7D8

BS

TDI

CS0

CS1

CS4

CS5

TMS

TCK

CS6

WE1

WE0/REG

QFP256

(Top view)

VDD (internal)

VSS (internal)

VDDQ (IO)

VSSQ (IO)

D9

D10

D11

D12

D13

D14

D15

CAS0/DQM0

CAS1/DQM1

RD/WR

CKIO

Reserved

CKE

Reserved

RD/CASS/FRAME

RAS

CS2

CS3

A0A1A2A3A4A5A6A7A8

BACK/BSREQ
BREQ/BSACK

MD6/IOIS16

MD2/RXD2

MD8/RTS2

MD1/TXD2
MD0/SCK2
MD7/CTS2

AUDSYNC

MD3/CE2A
MD4/CE2B

ASEBRK/BRKACK

VDD-PLL2

VSS-PLL2

VDD-PLL1

VSS-PLL1
VDD-CPG

Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1,

VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL
circuits, crystal oscillation circuit, and RTC are used.

Figure 1.2 Pin Arrangement (256-Pin QFP)

Page 10 of 1128 R01UH0457EJ0301 Rev. 3.01

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SH7751 Group, SH7751R Group Section 1 Overview

1234567891011121314151617 192018

A

EXTAL VDD-PLL2

B

CS0

C

CS4

D

BS

E

D1

F

D3

G

D4

H

D8 D6

J

D12 D10

K

D15

CAS0/DQM0

L

M

CKIO

N

RAS

P

RD/CASS/

FRAME

R

A0

T

A4

U

A8

V

A10

W

A11

Y

CS1

CS6

D11

D14

CKE

VDD-PLL1

TMS

CS5

D0

WE0/REG

WE1

D2

D7

NC

CAS1/DQM1

RD/WR

NC

CS3

A3

A2

A7

A6

A9

A14

CAS2/DQM2

A13

A15

TDO

TCK

TDI

D5

D9

D13

CS2

A1

A5

A16

A17

DREQ1

ASEBRK/

BRKACK

CAS3/DQM3

D16

D17

D18 D21 D29 A19A12

DREQ0

STATUS1

STATUS0

D19

D20

DRAK1

DRAK0

DACK1

DACK0

MD5

MD4/CE2B

D22

D23

D24

D25

MD3/CE2A

AUDATA2

NC

AUDATA3

(Top view)

D26

D27

D28

AUDATA1XTAL

AUDCK

MD1/TXD2

AUDATA0

BGA256

A18

D30

D31

MD7/CTS2

AUDSYNC

MD0/SCK2

SCK

A21

A22

A23 SLEEP

VDDQ(IO)

VSSQ(IO)

VDD (internal)

MD8/RTS2

TCLK

RXD

MD2/RXD2

A24

A25

WE2/ICIORD

WE3/ICIOWR

TXD

BREQ/BSACK

MD6/IOIS16

PCIGNT4

PCIGNT3

VSS (internal)

VDD-PLL1/2

VSS-PLL1/2

BACK/BSREQ

RDY

MRESET

PCIGNT2

PCIREQ4

PCIREQ3/MD10

PCIREQ2/MD9

TRST

RESET

CA

NMI

IRL0

C/BE0

AD12

PERR

DEVSEL

AD16

AD25 AD21

IDSEL C/BE3

INTA

PCIRST

PCICLK SERR

EXTAL2

*

IRL2

AD0

AD1

AD4

AD8

AD10

AD13

AD14

C/BE1

PCILOCK

TRDY

IRDY

C/BE2

AD18

AD22

AD24

AD27

AD29

PCIGNT1/
REQOUT

PCIREQ1/

GNTIN

VDD-CPG/RTC

VSS-CPG/RTC

NC

XTAL2

IRL3

IRL1

AD2

AD5AD3

AD6AD7

AD9

AD11

AD15

PAR

PCISTOP

PCIFRAME

AD17

AD19

AD20

AD23

AD26A20

AD28

AD30

AD31

Notes: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-

PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC)
regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are
used.

* May be connected to V

SS

Q.

Figure 1.3 Pin Arrangement (256-Pin BGA)

R01UH0457EJ0301 Rev. 3.01 Page 11 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

1234567891011121314151617 192018

A

EXTAL VDD-PLL2

B

TMS

C

TDI

D

CS1

E

CS6

F

WE1

G

D2 C/BE0

H

D4 D6

J

D7 D9

K

D10 D12

L

CAS1/DQM1

M

CAS0/
DQM0

N

CKIO

P

RAS

R

CS3

T

A2

U

A5

V

A8 A10

W

A11

Y

VDD-PLL1

VSS-CPG

TCK

VDD-CPG

CS0

VSS-PLL1

CS4

CS5

BS

WE0/REG

D1 AD6

D5

D8

D11

D14

RD/WR

RD/CASS/

FRAME

CKE

CS2

A1 AD20

A3

A4

A6

A7

CAS3/DQM3

A9

CAS2/DQM2

A12 D20

A16

A14

A15

VSS-PLL2

TDO

A17

STATUS0

STATUS1

BRKACK

DREQ0

DREQ1

D21

D18

D17 D23

D19

D16 D22 D27 A18 A24A13

MD5

DRAK0

DACK0 AUDATA1

DRAK1ASEBRK/

DACK1

D26

D25

D24

MD1/TXD2

AUDATA0XTAL

AUDATA3

MD3/CE2A

MD4/CE2B

AUDSYNC

AUDCK

AUDATA2 CA

MD2/RXD2

TCLK

MD0/SCK2 RXD

MD8/RTS2

MD7/CTS2

SCK

MD6/IOIS16

BACK/BSREQ

RDY

BREQ/BSACK

TXD MRESET

BGA292

(Top view)

D29

D31

D28 A19

D30

A23

A20

WE2/ICIORD

A22

A21 PCICLKWE3/ICIOWR

VDDQ(IO)
VDD-PLL1/2

A25 AD29

PCIGNT2

SLEEP

PCIGNT3

PCIGNT4

VSS
VSS-CPG/RTC

PCIREQ2/MD9

PCIREQ3/MD10

PCIREQ4

NMI

VDD-RTC

RESET

VSS-RTC

TRST

AD12

AD15

DEVSEL

C/BE2

AD19A0

AD23

AD24

PCIREQ1/

GNTIN

PCIRST

PCIGNT1/
REQOUT

INTA

IDSEL

IRL0

AD9

EXTAL2

IRL2

AD0

AD3

AD10

AD13

C/BE1

PCILOCKD15D13

TRDY

PCIFRAME

AD17

AD22

AD25

AD27

SERR

XTAL2

IRL3

IRL1

AD1

AD4AD2

AD7AD5D0

AD8D3

AD11

AD14

PAR

PCISTOPPERR

IRDY

AD16

AD18

AD21

C/BE3

AD26

AD28

AD30

AD31

VDD-CPG/RTC

VDD (internal)

VSS-PLL1/2

Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2,

VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of
whether or not the PLL circuits, crystal oscillation circuit, and RTC are used.

Figure 1.4 Pin Arrangement (292-Pin BGA)

Page 12 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

1.4 Pin Functions

1.4.1 Pin Functions (256-Pin QFP)

Table 1.2 Pin Functions

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

1 TMS I Mode

(H-UDI)

2 TCK I Clock

(H-UDI)

3 VDDQ Power IO VDD

4 VSSQ Power IO GND

5 TDI I Data in

(H-UDI)

6 CS0 O Chip select 0 CS0 CS0

7 CS1 O Chip select 1 CS1 CS1

8 CS4 O Chip select 4 CS4 CS4

9 CS5 O Chip select 5 CS5 CE1A CS5

10 CS6 O Chip select 6 CS6 CE1B CS6

11 BS O Bus start (BS) (BS) (BS) (BS) (BS)

12 WE0/REG O D7–D0

select signal

13 WE1 O D15-D8

select signal

14 D0 I/O Data A0

15 VDDQ Power IO VDD

16 VSSQ Power IO GND

17 VDD Power Internal VDD

18 VSS Power Internal GND

19 D1 I/O Data A1

20 D2 I/O Data A2

21 D3 I/O Data A3

22 D4 I/O Data A4

23 D5 I/O Data A5

24 D6 I/O Data A6

25 D7 I/O Data A7

WE0 REG

WE1 WE1

R01UH0457EJ0301 Rev. 3.01 Page 13 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

26 D8 I/O Data A8

27 D9 I/O Data A9

28 D10 I/O Data A10

29 VDDQ Power IO VDD

30 VSSQ Power IO GND

31 D11 I/O Data A11

32 D12 I/O Data A12

33 D13 I/O Data A13

34 D14 I/O Data A14

35 D15 I/O Data A15

36 CAS0/

DQM0

37 CAS1/

DQM1

38 RD/WR O Read/write RD/WR RD/WR RD/WR RD/WR RD/WR

39 CKIO O Clock output CKIO CKIO CKIO CKIO

40 Reserved Do not

41 VDDQ Power IO VDD

42 VSSQ Power IO GND

43 Reserved Do not

44 RD/CASS/

FRAME

45 CKE O Clock output

46 RAS O RAS RAS RAS

47 VDD Power Internal VDD

48 VSS Power Internal GND

49 CS2 O Chip select 2 CS2 (CS2) CS2 CS2

50 CS3 O Chip select 3 CS3 (CS3) CS3 CS3

51 A0 O Address

52 A1 O Address

53 A2 O Address

54 A3 O Address

55 VDDQ Power IO VDD

O D7–D0

select signal

O D15–D8

select signal

connect

connect

O Read/CAS/

FRAME

enable

CAS0 DQM0

CAS1 DQM1

OE CAS OE FRAME

CKE

Page 14 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

56 VSSQ Power IO GND

57 A4 O Address

58 A5 O Address

59 A6 O Address

60 A7 O Address

61 A8 O Address

62 A9 O Address

63 A10 O Address

64 A11 O Address

65 A12 O Address

66 A13 O Address

67 VDDQ Power IO VDD

68 VSSQ Power IO GND

69 A14 O Address

70 A15 O Address

71 A16 O Address

72 A17 O Address

73 CAS2/

DQM2

74 CAS3/

DQM3

75 D16 I/O Data A16

76 D17 I/O Data A17

77 D18 I/O Data A18

78 D19 I/O Data A19

79 VDDQ Power IO VDD

80 VSSQ Power IO GND

81 VDD Power Internal VDD

82 VSS Power Internal GND

83 D20 I/O Data A20

84 D21 I/O Data A21

85 D22 I/O Data A22

86 D23 I/O Data A23

O D23–D16

select signal

O D31–D24

select signal

CAS2 DQM2

CAS3 DQM3

R01UH0457EJ0301 Rev. 3.01 Page 15 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

87 D24 I/O Data A24

88 D25 I/O Data A25

89 D26 I/O Data

90 D27 I/O Data

91 D28 I/O Data

92 D29 I/O Data ACCSIZE0

93 VDDQ Power IO VDD

94 VSSQ Power IO GND

95 D30 I/O Data ACCSIZE1

96 D31 I/O Data ACCSIZE2

97 VDD Power Internal VDD

98 VSS Power Internal GND

99 A18 O Address

100 A19 O Address

101 A20 O Address

102 A21 O Address

103 A22 O Address

104 A23 O Address

105 VDDQ Power IO VDD

106 VSSQ Power IO GND

107 A24 O Address

108 A25 O Address

109 WE2/

ICIORD

110 WE3/

ICIOWR

111 VDD Power Internal VDD

112 VSS Power Internal GND

113 SLEEP I Sleep

114 PCIGNT4 O Bus grant

115 PCIGNT3 O Bus grant

O D23–D16

select signal

O D31–D24

select signal

(host function)

(host function)

WE2 ICIORD

WE3 ICIOWR

Page 16 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

116 PCIGNT2 O Bus grant

(host function)

117 PCIREQ4 I* Bus request

(host function)

118 PCIREQ3/

MD10

I* Bus request

MD10

(host
function)/
mode

119 VDDQ Power IO VDD

120 VSSQ Power IO GND

121 PCIREQ2/

MD9

I* Bus request

MD9

(host
function)/
mode

122 IDSEL I Configuration

device select

123 INTA O Interrupt

(async)

124 PCIRST O Reset output

125 PCICLK I PCI input

clock

126 PCIGNT1/

REQOUT

O Bus grant

(host
function)/
bus request

127 PCIREQ1/

GNTIN

I Bus request

(host function)
/bus grant

128 SERR I/O System error

129 AD31 I/O PCI address/

(Port) (Port) (Port) (Port) (Port)

data/port

130 AD30 I/O PCI address/

(Port) (Port) (Port) (Port) (Port)

data/port

131 VDDQ Power IO VDD

132 VSSQ Power IO GND

133 AD29 I/O PCI address/

(Port) (Port) (Port) (Port) (Port)

data/port

R01UH0457EJ0301 Rev. 3.01 Page 17 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

134 AD28 I/O PCI address/

data/port

135 AD27 I/O PCI address/

data/port

136 AD26 I/O PCI address/

data/port

137 AD25 I/O PCI address/

data/port

138 AD24 I/O PCI address/

data/port

139 C/BE3 I/O Command/byt

e enable

140 AD23 I/O PCI address/

data/port

141 AD22 I/O PCI address/

data/port

142 AD21 I/O PCI address/

data/port

143 VDDQ Power IO VDD

144 VSSQ Power IO GND

145 VDD Power Internal VDD

146 VSS Power Internal GND

147 AD20 I/O PCI address/

data/port

148 AD19 I/O PCI address/

data/port

149 AD18 I/O PCI address/

data/port

150 AD17 I/O PCI address/

data/port

151 AD16 I/O PCI address/

data/port

152 C/BE2 I/O Command/

byte enable

153 PCIFRAME I/O Bus cycle

154 IRDY I/O Initiator ready

155 TRDY I/O Target ready

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

Page 18 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

156 DEVSEL I/O Device select

157 VDDQ Power IO VDD

158 VSSQ Power IO GND

159 PCISTOP I/O Transaction

stop

160 PCILOCK I/O Exclusive

access

161 PERR I/O Parity error

162 PAR I/O Parity

163 C/BE1 I/O Command/

byte enable

164 AD15 I/O PCI address/

data/port

165 AD14 I/O PCI address/

data/port

166 AD13 I/O PCI address/

data/port

167 AD12 I/O PCI address/

data/port

168 AD11 I/O PCI address/

data/port

169 VDDQ Power IO VDD

170 VSSQ Power IO GND

171 AD10 I/O PCI address/

data/port

172 AD9 I/O PCI address/

data/port

173 AD8 I/O PCI address/

data/port

174 C/BE0 I/O Command/

byte enable

175 VDD Power Internal VDD

176 VSS Power Internal GND

177 AD7 I/O PCI address/

data/port

178 AD6 I/O PCI address/

data/port

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

R01UH0457EJ0301 Rev. 3.01 Page 19 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

179 AD5 I/O PCI address/

data/port

180 AD4 I/O PCI address/

data/port

181 AD3 I/O PCI address/

data/port

182 AD2 I/O PCI address/

data/port

183 VDDQ Power I/O VDD

184 VSSQ Power I/O GND

185 AD1 I/O PCI address/

data/port

186 AD0 I/O PCI address/

data/port

187 IRL0 I Interrupt 0

188 IRL1 I Interrupt 1

189 IRL2 I Interrupt 2

190 IRL3 I Interrupt 3

191 VSSQ Power I/O GND

192 VDDQ Power I/O VDD

193 XTAL2 O RTC crystal

resonator pin

194 EXTAL2 I RTC crystal

resonator pin

195 VDD-RTC Power RTC VDD

196 VSS-RTC Power RTC GND

197 CA*2 I Hardware

standby

198 RESET I Reset RESET

199 TRST I Reset

(H-UDI)

200 MRESET I Manual reset

201 NMI I Nonmaskable

interrupt

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

Page 20 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

202 BACK/

BSREQ

203 BREQ/

BSACK

204 MD6/

IOIS16

205 RDY I Bus ready RDY RDY RDY

206 TXD O SCI data

207 VDDQ Power IO VDD

208 VSSQ Power IO GND

209 VDD Power Internal VDD

210 VSS Power Internal GND

211 MD2/RXD2 I Mode/SCIF

212 RXD I SCI data input

213 TCLK I/O RTC/TMU

214 MD8/RTS2 I/O Mode/SCIF

215 SCK I/O SCIF clock

216 MD1/TXD2 I/O Mode/SCIF

217 MD0/SCK2 I/O Mode/SCIF

218 MD7/CTS2 I/O Mode/SCIF

219 AUDSYNC AUD sync

220 AUDCK AUD clock

221 VDDQ Power IO VDD

222 VSSQ Power IO GND

223 AUDATA0 AUD data

224 AUDATA1 AUD data

O Bus

acknowledge/
bus request

I Bus

request/bus
acknowledge

I Mode/IOIS16

(PCMCIA)

output

data input

clock

data control
(RTS)

data output

clock

data control
(CTS)

MD6 IOIS16

MD2 RXD2 RXD2 RXD2 RXD2 RXD2

MD8 RTS2 RTS2 RTS2 RTS2 RTS2

MD1 TXD2 TXD2 TXD2 TXD2 TXD2

MD0 SCK2 SCK2 SCK2 SCK2 SCK2

MD7 CTS2 CTS2 CTS2 CTS2 CTS2

R01UH0457EJ0301 Rev. 3.01 Page 21 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

225 VDD Power Internal VDD

226 VSS Power Internal GND

227 AUDATA2 AUD data

228 AUDATA3 AUD data

229 Reserved Do not

connect

230 MD3/CE2A I/O Mode/

231 MD4/CE2B I/O Mode/

232 MD5 I Mode MD5

233 VDDQ Power IO VDD

234 VSSQ Power IO GND

235 DACK0 O DMAC0 bus

236 DACK1 O DMAC1 bus

237 DRAK0 O DMAC0

238 DRAK1 O DMAC1

239 VDD Power Internal VDD

240 VSS Power Internal GND

241 STATUS0 O Status

242 STATUS1 O Status

243 DREQ0 I Request from

244 DREQ1 I Request from

245 ASEBRK/

BRKACK

246 TDO O Data out

PCMCIA-CE

PCMCIA-CE

acknowledge

acknowledge

request
acknowledge

request
acknowledge

DMAC0

DMAC1

I/O Pin break/

acknowledge
(H-UDI)

(H-UDI)

MD3 CE2A

MD4 CE2B

Page 22 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX

247 VDDQ Power IO VDD

248 VSSQ Power IO GND

249 VDD-PLL2 Power PLL2 VDD

250 VSS-PLL2 Power PLL2 GND

251 VDD-PLL1 Power PLL1 VDD

252 VSS-PLL1 Power PLL1 GND

253 VDD-CPG Power CPG VDD

254 VSS-CPG Power CPG GND

255 XTAL O Crystal

resonator

256 EXTAL I External input

clock/crystal
resonator

Legend:
I: Input
O: Output
I/O: Input/output
Power: Power supply

Notes: Supply power to all power pins. However, on the SH7751 in hardware standby mode,

supply power to RTC at the minimum.

Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the

on-chip PLL circuits are used.

Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-

chip crystal oscillation circuit is used.

Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-

chip RTC is used.
For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix D.
* I/O attribute is I/O when used as a port.

R01UH0457EJ0301 Rev. 3.01 Page 23 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

1.4.2 Pin Functions (256-Pin BGA)

Table 1.3 Pin Functions

Memory Interface

Pin

No.

Number Pin Name I/O Function

1 B3 TMS I Mode

2 C4 TCK I Clock

3 G3 VDDQ Power IO VDD

4 F2 VSSQ Power IO GND

5 D4 TDI I Data in

6 B1 CS0 O Chip select 0 CS0 CS0

7 C2 CS1 O Chip select 1 CS1 CS1

8 C1 CS4 O Chip select 4 CS4 CS4

9 D3 CS5 O Chip select 5 CS5 CE1A CS5

10 D2 CS6 O Chip select 6 CS6 CE1B CS6

11 D1 BS O Bus start (BS) (BS) (BS) (BS) (BS)

12 E4 WE0/

REG

13 E3 WE1 O D15–D8

14 E2 D0 I/O Data A0

15 G2 VDDQ Power IO VDD

16 L4 VSSQ Power IO GND

17 G4 VDD Power Internal VDD

18 F4 VSS Power Internal GND

19 E1 D1 I/O Data A1

20 F3 D2 I/O Data A2

21 F1 D3 I/O Data A3

22 G1 D4 I/O Data A4

23 H4 D5 I/O Data A5

24 H3 D6 I/O Data A6

25 H2 D7 I/O Data A7

26 H1 D8 I/O Data A8

O D7–D0

(H-UDI)

(H-UDI)

(H-UDI)

select signal

select signal

Reset SRAM DRAM SDRAM PCMCIA MPX

WE0 REG

WE1 WE1

Page 24 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

Pin

No.

Number Pin Name I/O Function

27 J4 D9 I/O Data A9

28 J3 D10 I/O Data A10

29 K3 VDDQ Power IO VDD

30 L3 VSSQ Power IO GND

31 J2 D11 I/O Data A11

32 J1 D12 I/O Data A12

33 K4 D13 I/O Data A13

34 K2 D14 I/O Data A14

35 K1 D15 I/O Data A15

36 L2 CAS0/

DQM0

37 M4 CAS1/

DQM1

38 M3 RD/WR O Read/write RD/WR RD/WR RD/WR RD/WR RD/WR

39 M1 CKIO O Clock output CKIO CKIO CKIO CKIO

40 M2 NC Do not connect

41 P3 VDDQ Power IO VDD

42 L1 VSSQ Power IO GND

43 N3 NC Do not connect

44 P1 RD/

CASS/
FRAME

45 N2 CKE O Clock output

46 N1 RAS O RAS RAS RAS

47 P4 VDD Power Internal VDD

48 R4 VSS Power Internal GND

49 N4 CS2 O Chip select 2 CS2 (CS2) CS2 CS2

50 R3 CS3 O Chip select 3 CS3 (CS3) CS3 CS3

51 R1 A0 O Address

52 T4 A1 O Address

53 T3 A2 O Address

54 T2 A3 O Address

55 P2 VDDQ Power IO VDD

O D7–D0

select signal

O D15–D8

select signal

O Read/CAS/

FRAME

enable

Reset SRAM DRAM SDRAM PCMCIA MPX

CAS0 DQM0

CAS1 DQM1

OE CAS OE FRAME

CKE

R01UH0457EJ0301 Rev. 3.01 Page 25 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

Pin

No.

Number Pin Name I/O Function

56 R2 VSSQ Power IO GND

57 T1 A4 O Address

58 U4 A5 O Address

59 U3 A6 O Address

60 U2 A7 O Address

61 U1 A8 O Address

62 V2 A9 O Address

63 V1 A10 O Address

64 W1 A11 O Address

65 Y1 A12 O Address

66 Y2 A13 O Address

67 V7 VDDQ Power IO VDD

68 V3 VSSQ Power IO GND

69 W3 A14 O Address

70 Y3 A15 O Address

71 V4 A16 O Address

72 W4 A17 O Address

73 Y4 CAS2/

DQM2

74 U5 CAS3/

DQM3

75 V5 D16 I/O Data A16

76 W5 D17 I/O Data A17

77 Y5 D18 I/O Data A18

78 V6 D19 I/O Data A19

79 W7 VDDQ Power IO VDD

80 W2 VSSQ Power IO GND

81 U7 VDD Power Internal VDD

82 U6 VSS Power Internal GND

83 Y6 D20 I/O Data A20

84 Y7 D21 I/O Data A21

85 U8 D22 I/O Data A22

86 V8 D23 I/O Data A23

O D23–D16 select

signal

O D31–D24 select

signal

Reset SRAM DRAM SDRAM PCMCIA MPX

CAS2 DQM2

CAS3 DQM3

Page 26 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

Pin

No.

Number Pin Name I/O Function

87 W8 D24 I/O Data A24

88 Y8 D25 I/O Data A25

89 U9 D26 I/O Data

90 V9 D27 I/O Data

91 W9 D28 I/O Data

92 Y9 D29 I/O Data ACCSIZE0

93 V10 VDDQ Power IO VDD

94 W6 VSSQ Power IO GND

95 W10 D30 I/O Data ACCSIZE1

96 Y10 D31 I/O Data ACCSIZE2

97 U10 VDD Power Internal VDD

98 U11 VSS Power Internal GND

99 V11 A18 O Address

100 Y11 A19 O Address

101 U12 A20 O Address

102 V12 A21 O Address

103 W12 A22 O Address

104 Y12 A23 O Address

105 V14 VDDQ Power IO VDD

106 W11 VSSQ Power IO GND

107 U13 A24 O Address

108 V13 A25 O Address

109 W13 WE2/

ICIORD

110 Y13 WE3/

ICIOWR

111 U14 VDD Power Internal VDD

112 U15 VSS Power Internal GND

113 Y14 SLEEP I Sleep

114 V15 PCIGNT4 O Bus grant (host

115 Y15 PCIGNT3 O Bus grant (host

O D23–D16 select

signal

O D31–D24 select

signal

function)

function)

Reset SRAM DRAM SDRAM PCMCIA MPX

WE2 ICIORD

WE3 ICIOWR

R01UH0457EJ0301 Rev. 3.01 Page 27 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

Pin

No.

Number Pin Name I/O Function

116 U16 PCIGNT2 O Bus grant

117 V16 PCIREQ4 I*1 Bus request

118 W16 PCIREQ3/

MD10

119 W14 VDDQ Power IO VDD

120 W15 VSSQ Power IO GND

121 Y16 PCIREQ2/

MD9

122 U17 IDSEL I Configuration

123 V17 INTA O Interrupt

124 W17 PCIRST O Reset output

125 Y17 PCICLK I PCI input

126 W18 PCIGNT1/

REQOUT

127 Y18 PCIREQ1/

GNTIN

128 Y19 SERR I/O System error

129 Y20 AD31 I/O PCI address/

130 W20 AD30 I/O PCI address/

131 P18 VDDQ Power IO VDD

132 V18 VSSQ Power IO GND

133 V19 AD29 I/O PCI address/

134 V20 AD28 I/O PCI address/

135 U18 AD27 I/O PCI address/

I*1 Bus request

I*1 Bus request

O Bus grant (host

I Bus request

(host function)

(host function)

(host function)/
mode

(host function)/
mode

device select

(async)

clock

function)/
bus request

(host function)/
bus grant

data/port

data/port

data/port

data/port

data/port

Reset SRAM DRAM SDRAM PCMCIA MPX

MD10

MD9

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

Page 28 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

Pin

No.

Number Pin Name I/O Function

136 U20 AD26 I/O PCI address/

137 T17 AD25 I/O PCI address/

138 T18 AD24 I/O PCI address/

139 U19 C/BE3 I/O PCI address/

140 T20 AD23 I/O PCI address/

141 R18 AD22 I/O PCI address/

142 T19 AD21 I/O PCI address/

143 N19 VDDQ Power IO VDD

144 W19 VSSQ Power IO GND

145 P17 VDD Power Internal VDD

146 R17 VSS Power Internal GND

147 R20 AD20 I/O PCI address/

148 P20 AD19 I/O PCI address/

149 P19 AD18 I/O PCI address/

150 N20 AD17 I/O PCI address/

151 N17 AD16 I/O PCI address/

152 N18 C/BE2 I/O Command/

153 M20 PCIFRAME I/O Bus cycle

154 M19 IRDY I/O Initiator ready

155 M18 TRDY I/O Target ready

156 M17 DEVSEL I/O Device select

157 L18 VDDQ Power IO VDD

data/port

data/port

data/port

data/port

data/port

data/port

data/port

data/port

data/port

data/port

data/port

data/port

byte enable

Reset SRAM DRAM SDRAM PCMCIA MPX

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

R01UH0457EJ0301 Rev. 3.01 Page 29 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

Pin

No.

Number Pin Name I/O Function

158 R19 VSSQ Power IO GND

159 L20 PCISTOP I/O Transaction

160 L19 PCILOCK I/O Exclusive

161 L17 PERR I/O Parity error

162 K20 PAR I/O Parity

163 K18 C/BE1 I/O Command/

164 J20 AD15 I/O PCI address/

165 J19 AD14 I/O PCI address/

166 J18 AD13 I/O PCI address/

167 J17 AD12 I/O PCI address/

168 H20 AD11 I/O PCI address/

169 G18 VDDQ Power IO VDD

170 K17 VSSQ Power IO GND

171 H19 AD10 I/O PCI address/

172 G20 AD9 I/O PCI address/

173 H18 AD8 I/O PCI address/

174 H17 C/BE0 I/O Command/

175 G17 VDD Power Internal VDD

176 F17 VSS Power Internal GND

177 F18 AD7 I/O PCI address/

178 F20 AD6 I/O PCI address/

179 E20 AD5 I/O PCI address/

stop

access

byte enable

data/port

data/port

data/port

data/port

data/port

data/port

data/port

data/port

byte enable

data/port

data/port

data/port

Reset SRAM DRAM SDRAM PCMCIA MPX

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

Page 30 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

Pin

No.

Number Pin Name I/O Function

180 E19 AD4 I/O PCI address/

181 E18 AD3 I/O PCI address/

182 D20 AD2 I/O PCI address/

183 G19 VDDQ Power I/O VDD

184 K19 VSSQ Power I/O GND

185 D19 AD1 I/O PCI address/

186 D18 AD0 I/O PCI address/

187 E17 IRL0 I Interrupt 0

188 C20 IRL1 I Interrupt 1

189 C19 IRL2 I Interrupt 2

190 B20 IRL3 I Interrupt 3

191 B18 NC Do not connect

192 D17 VDDQ Power I/O VDD

193 A20 XTAL2 O RTC crystal

194 A19 EXTAL2 I RTC crystal

195 A18 VDD-RTC Power RTC VDD

196 B19 VSS-RTC Power RTC GND

197 B17 CA I Hardware

198 A17 RESET I Reset RESET

199 C16 TRST I Reset (H-UDI)

200 B16 MRESET I Manual reset

201 D16 NMI I Nonmaskable

202 A16 BACK/

BSREQ

data/port

data/port

data/port

data/port

data/port

2

*

resonator pin

resonator pin

standby

interrupt

O Bus

acknowledge/
bus request

Reset SRAM DRAM SDRAM PCMCIA MPX

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

R01UH0457EJ0301 Rev. 3.01 Page 31 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

Pin

No.

Number Pin Name I/O Function

203 B15 BREQ/

BSACK

204 C15 MD6/

IOIS16

205 A15 RDY I Bus ready RDY RDY RDY

206 A14 TXD O SCI data output

207 B14 VDDQ Power IO VDD

208 F19 VSSQ Power IO GND

209 D14 VDD Power Internal VDD

210 D15 VSS Power Internal GND

211 D13 MD2/

RXD2

212 C13 RXD I SCI data input

213 B13 TCLK I/O RTC/TMU clock

214 A13 MD8/

RTS2

215 D12 SCK I/O SCIF clock

216 B11 MD1/

TXD2

217 C12 MD0/

SCK2

218 A12 MD7/

CTS2

219 B12 AUDSYNC AUD sync

220 A11 AUDCK AUD clock

221 C14 VDDQ Power IO VDD

222 C18 VSSQ Power IO GND

223 C10 AUDATA0 AUD data

224 A10 AUDATA1 AUD data

225 D11 VDD Power Internal VDD

226 D10 VSS Power Internal GND

I Bus

request/bus
acknowledge

I Mode/IOIS16

(PCMCIA)

I Mode/SCIF

data input

I/O Mode/SCIF

data control
(RTS)

I/O Mode/SCIF

data output

I/O Mode/SCIF

clock

I/O Mode/SCIF

data control
(CTS)

Reset SRAM DRAM SDRAM PCMCIA MPX

MD6 IOIS16

MD2 RXD2 RXD2 RXD2 RXD2 RXD2

MD8 RTS2 RTS2 RTS2 RTS2 RTS2

MD1 TXD2 TXD2 TXD2 TXD2 TXD2

MD0 SCK2 SCK2 SCK2 SCK2 SCK2

MD7 CTS2 CTS2 CTS2 CTS2 CTS2

Page 32 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

Pin

No.

Number Pin Name I/O Function

227 B9 AUDATA2 AUD data

228 D9 AUDATA3 AUD data

229 C9 NC Do not connect

230 A9 MD3/CE2A I/O Mode/

PCMCIA-CE

231 D8 MD4/CE2B I/O Mode/

232 C8 MD5 I Mode MD5

233 C11 VDDQ Power IO VDD

234 C17 VSSQ Power IO GND

235 B8 DACK0 O DMAC0 bus

236 A8 DACK1 O DMAC1 bus

237 B7 DRAK0 O DMAC0 request

238 A7 DRAK1 O DMAC1 request

239 D7 VDD Power Internal VDD

240 D6 VSS Power Internal GND

241 C6 STATUS0 O Status

242 B6 STATUS1 O Status

243 A6 DREQ0 I Request from

244 C5 DREQ1 I Request from

245 D5 ASEBRK/

BRKACK

246 B4 TDO O Data out

247 C7 VDDQ Power IO VDD

248 B10 VSSQ Power IO GND

249 A5 VDD-PLL2 Power PLL2 VDD

I/O Pin break/

PCMCIA-CE

acknowledge

acknowledge

acknowledge

acknowledge

DMAC0

DMAC1

acknowledge
(H-UDI)

(H-UDI)

Reset SRAM DRAM SDRAM PCMCIA MPX

MD3 CE2A

MD4 CE2B

R01UH0457EJ0301 Rev. 3.01 Page 33 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

Pin

No.

Number Pin Name I/O Function

250 B5 VSS-PLL2 Power PLL2 GND

251 A4 VDD-PLL1 Power PLL1 VDD

252 C3 VSS-PLL1 Power PLL1 GND

253 A3 VDD-CPG Power CPG VDD

254 B2 VSS-CPG Power CPG GND

255 A2 XTAL O Crystal

256 A1 EXTAL I External input

resonator

clock/crystal
resonator

Reset SRAM DRAM SDRAM PCMCIA MPX

Legend:
I: Input
O: Output
I/O: Input/output
Power: Power supply

Notes: Supply power to all power pins. However, on the SH7751 in hardware standby mode,

supply power to RTC at the minimum.

Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the

on-chip PLL circuits are used.

Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-

chip crystal oscillation circuit is used.

Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-

chip RTC is used.

For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix D.

1. I/O attribute is I/O when used as a port.

2. May be connected to V

Q.

SS

Page 34 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

1.4.3 Pin Functions (292-Pin BGA)

Table 1.4 Pin Functions

Memory Interface

Pin

No.

Number Pin Name I/O Function

1 B1 TMS I Mode

(H-UDI)

2 B2 TCK I Clock

3 F4 VDDQ Power IO VDD

4 E4 VSS Power GND

5 C1 TDI I Data in

6 C2 CS0 O Chip select 0 CS0 CS0

7 D1 CS1 O Chip select 1 CS1 CS1

8 D2 CS4 O Chip select 4 CS4 CS4

9 D3 CS5 O Chip select 5 CS5 CE1A CS5

10 E1 CS6 O Chip select 6 CS6 CE1B CS6

11 E2 BS O Bus start (BS) (BS) (BS) (BS) (BS)

12 E3 WE0/

REG

13 F1 WE1 O D15–D8

14 F2 D0 I/O Data A0

15 G3 VDDQ Power IO VDD

16 D4 VSS Power GND

17 G4 VDD Power Internal VDD

18 H4 VSS Power GND

19 F3 D1 I/O Data A1

20 G1 D2 I/O Data A2

21 G2 D3 I/O Data A3

22 H1 D4 I/O Data A4

23 H2 D5 I/O Data A5

24 H3 D6 I/O Data A6

25 J1 D7 I/O Data A7

26 J2 D8 I/O Data A8

O D7–D0

(H-UDI)

(H-UDI)

select signal

select signal

Reset SRAM DRAM SDRAM PCMCIA MPX

WE0 REG

WE1 WE1

R01UH0457EJ0301 Rev. 3.01 Page 35 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

Pin

No.

Number Pin Name I/O Function

27 J3 D9 I/O Data A9

28 K1 D10 I/O Data A10

29 J4 VDDQ Power IO VDD

30 D5 VSS Power GND

31 K2 D11 I/O Data A11

32 K3 D12 I/O Data A12

33 L1 D13 I/O Data A13

34 L2 D14 I/O Data A14

35 L3 D15 I/O Data A15

36 M1 CAS0/

DQM0

37 M2 CAS1/

DQM1

38 M3 RD/WR O Read/write RD/WR RD/WR RD/WR RD/WR RD/WR

39 N1 CKIO O Clock output CKIO CKIO CKIO CKIO CKIO

40 K4 VDD Power Internal VDD

41 R4 VDDQ Power IO VDD

42 L4 VSS Power IO GND

43 M4 VDDQ Power I/O VDD

44 N2 RD/CASS/

FRAME

45 N3 CKE O Clock output

46 P1 RAS O RAS RAS RAS

47 P4 VDD Power Internal VDD

48 N4 VSS Power GND

49 P2 CS2 O Chip select 2 CS2 (CS2) CS2 CS2

50 R1 CS3 O Chip select 3 CS3 (CS3) CS3 CS3

51 R2 A0 O Address

52 R3 A1 O Address

53 T1 A2 O Address

54 T2 A3 O Address

55 P3 VDDQ Power IO VDD

56 T4 VSS Power GND

O D7–D0

select signal

O D15–D8

select signal

O Read/CAS/

FRAME

enable

Reset SRAM DRAM SDRAM PCMCIA MPX

CAS0 DQM0

CAS1 DQM1

OE CAS OE FRAME

CKE

Page 36 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

Pin

No.

Number Pin Name I/O Function

57 T3 A4 O Address

58 U1 A5 O Address

59 U2 A6 O Address

60 U3 A7 O Address

61 V1 A8 O Address

62 V2 A9 O Address

63 V3 A10 O Address

64 W1 A11 O Address

65 W2 A12 O Address

66 Y1 A13 O Address

67 V7 VDDQ Power IO VDD

68 U4 VSS Power GND

69 Y2 A14 O Address

70 Y3 A15 O Address

71 W3 A16 O Address

72 Y4 A17 O Address

73 W4 CAS2/

DQM2

74 V4 CAS3/

DQM3

75 Y5 D16 I/O Data A16

76 W5 D17 I/O Data A17

77 V5 D18 I/O Data A18

78 Y6 D19 I/O Data A19

79 U6 VDDQ Power IO VDD

80 U5 VSS Power GND

81 U7 VDD Power Internal VDD

82 U8 VSS Power GND

83 W6 D20 I/O Data A20

84 V6 D21 I/O Data A21

85 Y7 D22 I/O Data A22

86 W7 D23 I/O Data A23

87 Y8 D24 I/O Data A24

88 W8 D25 I/O Data A25

O D23–D16 select

signal

O D31–D24 select

signal

Reset SRAM DRAM SDRAM PCMCIA MPX

CAS2 DQM2

CAS3 DQM3

R01UH0457EJ0301 Rev. 3.01 Page 37 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

Pin

No.

Number Pin Name I/O Function

89 V8 D26 I/O Data

90 Y9 D27 I/O Data

91 W9 D28 I/O Data

92 V9 D29 I/O Data ACCSIZE0

93 U9 VDDQ Power IO VDD

94 V10 VSS Power GND

95 Y10 D30 I/O Data ACCSIZE1

96 W10 D31 I/O Data ACCSIZE2

97 U10 VDD Power Internal VDD

98 U11 VSS Power GND

99 Y11 A18 O Address

100 W11 A19 O Address

101 V11 A20 O Address

102 Y12 A21 O Address

103 W12 A22 O Address

104 V12 A23 O Address

105 U15 VDDQ Power IO VDD

106 U17 VSS Power GND

107 Y13 A24 O Address

108 W13 A25 O Address

109 V13 WE2/

ICIORD

110 Y14 WE3/

ICIOWR

111 U14 VDD Power Internal VDD

112 U13 VSS Power GND

113 W14 SLEEP I Sleep

114 Y15 PCIGNT4 O Bus grant (host

115 W15 PCIGNT3 O Bus grant (host

116 V15 PCIGNT2 O Bus grant (host

117 Y16 PCIREQ4 I* Bus grant (host

O D23–D16 select

signal

O D31–D24 select

signal

function)

function)

function)

function)

Reset SRAM DRAM SDRAM PCMCIA MPX

WE2 ICIORD

WE3 ICIOWR

Page 38 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

Pin

No.

Number Pin Name I/O Function

118 W16 PCIREQ3/

MD10

119 V14 VDDQ Power IO VDD

120 U16 VSS Power GND

121 V16 PCIREQ2/

MD9

122 Y17 IDSEL I Configuration

123 W17 INTA O Interrupt

124 V17 PCIRST O Reset output

125 Y18 PCICLK I PCI input

126 W18 PCIGNT1/

REQOUT

127 V18 PCIREQ1/

GNTIN

128 Y19 SERR I/O System error

129 Y20 AD31 I/O PCI address/

130 W20 AD30 I/O PCI address/

131 R17 VDDQ Power IO VDD

132 T17 VSS Power GND

133 W19 AD29 I/O PCI address/

134 V20 AD28 I/O PCI address/

135 V19 AD27 I/O PCI address/

136 U20 AD26 I/O PCI address/

137 U19 AD25 I/O PCI address/

I* Bus request

(host function)/
mode

I* Bus request

(host function)/
mode

device select

(async)

clock

O Bus grant (host

function)/
bus request

I Bus grant (host

function)/
bus request

data/port

data/port

data/port

data/port

data/port

data/port

data/port

Reset SRAM DRAM SDRAM PCMCIA MPX

MD10

MD9

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

R01UH0457EJ0301 Rev. 3.01 Page 39 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

Pin

No.

Number Pin Name I/O Function

138 U18 AD24 I/O PCI address/

139 T20 C/BE3 I/O PCI address/

140 T18 AD23 I/O PCI address/

141 T19 AD22 I/O PCI address/

142 R20 AD21 I/O PCI address/

143 P18 VDDQ Power IO VDD

144 U12 VDDQ Power I/O VDD

145 P17 VDD Power Internal VDD

146 N17 VSS Power GND

147 R19 AD20 I/O PCI address/

148 R18 AD19 I/O PCI address/

149 P20 AD18 I/O PCI address/

150 P19 AD17 I/O PCI address/

151 N20 AD16 I/O PCI address/

152 N18 C/BE2 I/O Command/

153 N19 PCIFRAME I/O Bus cycle

154 M20 IRDY I/O Initiator ready

155 M19 TRDY I/O Target ready

156 M18 DEVSEL I/O Device select

157 M17 VDDQ Power IO VDD

158 L17 VDD Power Internal VDD

159 L20 PCISTOP I/O Transaction

160 L19 PCILOCK I/O Exclusive

161 L18 PERR I/O Parity error

data/port

data/port

data/port

data/port

data/port

data/port

data/port

data/port

data/port

data/port

byte enable

stop

access

Reset SRAM DRAM SDRAM PCMCIA MPX

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

Page 40 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

Pin

No.

Number Pin Name I/O Function

162 K20 PAR I/O Parity

163 K19 C/BE1 I/O Command/

164 K18 AD15 I/O PCI address/

165 J20 AD14 I/O PCI address/

166 J19 AD13 I/O PCI address/

167 J18 AD12 I/O PCI address/

168 H20 AD11 I/O PCI address/

169 F17 VDDQ Power IO VDD

170 K17 VSS Power GND

171 H19 AD10 I/O PCI address/

172 H18 AD9 I/O PCI address/

173 G20 AD8 I/O PCI address/

174 G19 C/BE0 I/O Command/

175 G17 VDD Power Internal VDD

176 H17 VSS Power GND

177 F20 AD7 I/O PCI address/

178 F19 AD6 I/O PCI address/

179 F18 AD5 I/O PCI address/

180 E20 AD4 I/O PCI address/

181 E19 AD3 I/O PCI address/

182 E18 AD2 I/O PCI address/

183 G18 VDDQ Power I/O VDD

byte enable

data/port

data/port

data/port

data/port

data/port

data/port

data/port

data/port

byte enable

data/port

data/port

data/port

data/port

data/port

data/port

Reset SRAM DRAM SDRAM PCMCIA MPX

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

R01UH0457EJ0301 Rev. 3.01 Page 41 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

Pin

No.

Number Pin Name I/O Function

184 J17 VDDQ Power I/O VDD

185 D20 AD1 I/O PCI address/

186 D19 AD0 I/O PCI address/

187 D18 IRL0 I Interrupt 0

188 C20 IRL1 I Interrupt 1

189 C19 IRL2 I Interrupt 2

190 B20 IRL3 I Interrupt 3

191 B18 VSS-RTC Power RTC GND

192 E17 VSS Power GND

193 A20 XTAL2 O RTC crystal

194 A19 EXTAL2 I RTC crystal

195 A18 VDD-RTC Power RTC VDD

196 B19 VDDQ Power IO VDD

197 C18 CA I Hardware

198 A17 RESET I Reset RESET

199 B17 TRST I Reset (H-UDI)

200 C17 MRESET I Manual reset

201 A16 NMI I Nonmaskable

202 B16 BACK/

BSREQ

203 C16 BREQ/

BSACK

204 A15 MD6/

IOIS16

205 B15 RDY I Bus ready RDY RDY RDY

206 C15 TXD O SCI data output

207 C14 VDDQ Power IO VDD

208 C11 VSS Power GND

O Bus

I Bus

I Mode/IOIS16

data/port

data/port

resonator pin

resonator pin

standby

interrupt

acknowledge/
bus request

request/bus
acknowledge

(PCMCIA)

Reset SRAM DRAM SDRAM PCMCIA MPX

(Port) (Port) (Port) (Port) (Port)

(Port) (Port) (Port) (Port) (Port)

MD6 IOIS16

Page 42 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

Pin

No.

Number Pin Name I/O Function

209 D14 VDD Power Internal VDD

210 D16 VSS Power GND

211 A14 MD2/RXD2 I Mode/SCIF

212 B14 RXD I SCI data input

213 A13 TCLK I/O RTC/TMU clock

214 B13 MD8/RTS2 I/O Mode/SCIF

215 C13 SCK I/O SCIF clock

216 A12 MD1/TXD2 I/O Mode/SCIF

217 B12 MD0/SCK2 I/O Mode/SCIF

218 C12 MD7/CTS2 I/O Mode/SCIF

219 A11 AUDSYNC AUD Sync

220 B11 AUDCK AUD clock

221 D15 VDDQ Power IO VDD

222 D10 VSS Power GND

223 A10 AUDATA0 AUD data

224 B10 AUDATA1 AUD data

225 D11 VDD Power Internal VDD

226 D17 VSS Power GND

227 C10 AUDATA2 AUD data

228 A9 AUDATA3 AUD data

229 D8 VSS GND

230 B9 MD3/CE2A I/O Mode/

231 C9 MD4/CE2B I/O Mode/

232 A8 MD5 I Mode MD5

233 D12 VDDQ Power IO VDD

234 D9 VDDQ Power I/O VDD

data input

data control
(RTS)

data output

clock

data control
(RTS)

PCMCIA-CE

PCMCIA-CE

Reset SRAM DRAM SDRAM PCMCIA MPX

MD2 RXD2 RXD2 RXD2 RXD2 RXD2

MD8 RTS2 RTS2 RTS2 RTS2 RTS2

MD1 TXD2 TXD2 TXD2 TXD2 TXD2

MD0 SCK2 SCK2 SCK2 SCK2 SCK2

MD7 CTS2 CTS2 CTS2 CTS2 CTS2

MD3 CE2A

MD4 CE2B

R01UH0457EJ0301 Rev. 3.01 Page 43 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Memory Interface

Pin

No.

Number Pin Name I/O Function

235 B8 DACK0 O DMAC0 bus

236 C8 DACK1 O DMAC1 bus

237 A7 DRAK0 O DMAC0 request

238 B7 DRAK1 O DMAC1 request

239 D7 VDD Power Internal VDD

240 D6 VDDQ Power I/O VDD

241 A6 STATUS0 O Status

242 B6 STATUS1 O Status

243 C6 DREQ0 I Request from

244 C5 DREQ1 I Request from

245 B5 ASEBRK/

BRKACK

246 C4 TDO O Data out

247 C7 VDDQ Power IO VDD

248 D13 VSS Power GND

249 A5 VDD-PLL2 Power PLL2 VDD

250 B4 VSS-PLL2 Power PLL2 GND

251 A4 VDD-PLL1 Power PLL1 VDD

252 C3 VSS-PLL1 Power PLL1 GND

253 B3 VDD-CPG Power CPG VDD

254 A3 VSS-CPG Power CPG GND

255 A2 XTAL O Crystal

256 A1 EXTAL I External input

257 H8 VSS Power GND

258 J8 VSS Power GND

259 K8 VSS Power GND

I/O Pin break/

acknowledge

acknowledge

acknowledge

acknowledge

DMAC0

DMAC1

acknowledge
(H-UDI)

(H-UDI)

resonator

clock/crystal
resonator

Reset SRAM DRAM SDRAM PCMCIA MPX

Page 44 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013

SH7751 Group, SH7751R Group Section 1 Overview

Memory Interface

Pin

No.

Number Pin Name I/O Function

260 L8 VSS Power GND

261 M8 VSS Power GND

262 N8 VSS Power GND

263 N9 VSS Power GND

264 N10 VSS Power GND

265 N11 VSS Power GND

266 N12 VSS Power GND

267 N13 VSS Power GND

268 M13 VSS Power GND

269 L13 VSS Power GND

270 K13 VSS Power GND

271 J13 VSS Power GND

272 H13 VSS Power GND

273 H12 VSS Power GND

274 H11 VSS Power GND

275 H10 VSS Power GND

276 H9 VSS Power GND

277 J9 VSS Power GND

278 K9 VSS Power GND

279 L9 VSS Power GND

280 M9 VSS Power GND

281 M10 VSS Power GND

282 M11 VSS Power GND

283 M12 VSS Power GND

284 L12 VSS Power GND

285 K12 VSS Power GND

286 J12 VSS Power GND

287 J11 VSS Power GND

288 J10 VSS Power GND

289 K10 VSS Power GND

290 L10 VSS Power GND

291 L11 VSS Power GND

292 K11 VSS Power GND

Reset SRAM DRAM SDRAM PCMCIA MPX

R01UH0457EJ0301 Rev. 3.01 Page 45 of 1128

Sep 24, 2013

Section 1 Overview SH7751 Group, SH7751R Group

Legend:
I: Input
O: Output
I/O: Input/output
Power: Power supply

Notes: Supply power to all power pins.
Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the

on-chip PLL circuits are used.

Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-

chip crystal oscillation circuit is used.

Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-

chip RTC is used.
For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix D.
* I/O attribute is I/O when used as a port.

Page 46 of 1128 R01UH0457EJ0301 Rev. 3.01

Sep 24, 2013